blob: 7046089457805bea53eb9efdce66a4c13f41f018 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12/*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/pci.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/cache.h>
27#include <linux/slab.h>
28
29
Sam Ravnborg96bde062007-03-26 21:53:30 -080030static void pbus_assign_resources_sorted(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070031{
32 struct pci_dev *dev;
33 struct resource *res;
34 struct resource_list head, *list, *tmp;
35 int idx;
36
Linus Torvalds1da177e2005-04-16 15:20:36 -070037 head.next = NULL;
38 list_for_each_entry(dev, &bus->devices, bus_list) {
39 u16 class = dev->class >> 8;
40
Kenji Kaneshige9bded002006-10-04 02:15:34 -070041 /* Don't touch classless devices or host bridges or ioapics. */
Linus Torvalds1da177e2005-04-16 15:20:36 -070042 if (class == PCI_CLASS_NOT_DEFINED ||
Satoru Takeuchi23186272006-09-12 10:21:44 -070043 class == PCI_CLASS_BRIDGE_HOST)
Linus Torvalds1da177e2005-04-16 15:20:36 -070044 continue;
45
Kenji Kaneshige9bded002006-10-04 02:15:34 -070046 /* Don't touch ioapic devices already enabled by firmware */
Satoru Takeuchi23186272006-09-12 10:21:44 -070047 if (class == PCI_CLASS_SYSTEM_PIC) {
Kenji Kaneshige9bded002006-10-04 02:15:34 -070048 u16 command;
49 pci_read_config_word(dev, PCI_COMMAND, &command);
50 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
Satoru Takeuchi23186272006-09-12 10:21:44 -070051 continue;
52 }
53
Linus Torvalds1da177e2005-04-16 15:20:36 -070054 pdev_sort_resources(dev, &head);
55 }
56
57 for (list = head.next; list;) {
58 res = list->res;
59 idx = res - &list->dev->resource[0];
Rajesh Shah542df5d2005-04-28 00:25:50 -070060 if (pci_assign_resource(list->dev, idx)) {
Ivan Kokshaysky88452562008-03-30 19:50:14 +040061 /* FIXME: get rid of this */
Rajesh Shah542df5d2005-04-28 00:25:50 -070062 res->start = 0;
Ivan Kokshaysky960b8462005-07-07 03:07:56 +040063 res->end = 0;
Rajesh Shah542df5d2005-04-28 00:25:50 -070064 res->flags = 0;
65 }
Linus Torvalds1da177e2005-04-16 15:20:36 -070066 tmp = list;
67 list = list->next;
68 kfree(tmp);
69 }
70}
71
Dominik Brodowskib3743fa2005-09-09 13:03:23 -070072void pci_setup_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -070073{
74 struct pci_dev *bridge = bus->self;
75 struct pci_bus_region region;
76
Bjorn Helgaas80ccba12008-06-13 10:52:11 -060077 dev_info(&bridge->dev, "CardBus bridge, secondary bus %04x:%02x\n",
78 pci_domain_nr(bus), bus->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -070079
80 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
81 if (bus->resource[0]->flags & IORESOURCE_IO) {
82 /*
83 * The IO resource is allocated a range twice as large as it
84 * would normally need. This allows us to set both IO regs.
85 */
Bjorn Helgaas80ccba12008-06-13 10:52:11 -060086 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +110087 (unsigned long)region.start,
88 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
90 region.start);
91 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
92 region.end);
93 }
94
95 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
96 if (bus->resource[1]->flags & IORESOURCE_IO) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -060097 dev_info(&bridge->dev, " IO window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +110098 (unsigned long)region.start,
99 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
101 region.start);
102 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
103 region.end);
104 }
105
106 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
107 if (bus->resource[2]->flags & IORESOURCE_MEM) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600108 dev_info(&bridge->dev, " PREFETCH window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100109 (unsigned long)region.start,
110 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
112 region.start);
113 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
114 region.end);
115 }
116
117 pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
118 if (bus->resource[3]->flags & IORESOURCE_MEM) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600119 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100120 (unsigned long)region.start,
121 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
123 region.start);
124 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
125 region.end);
126 }
127}
Dominik Brodowskib3743fa2005-09-09 13:03:23 -0700128EXPORT_SYMBOL(pci_setup_cardbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129
130/* Initialize bridges with base/limit values we have collected.
131 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
132 requires that if there is no I/O ports or memory behind the
133 bridge, corresponding range must be turned off by writing base
134 value greater than limit to the bridge's base/limit registers.
135
136 Note: care must be taken when updating I/O base/limit registers
137 of bridges which support 32-bit I/O. This update requires two
138 config space writes, so it's quite possible that an I/O window of
139 the bridge will have some undesirable address (e.g. 0) after the
140 first write. Ditto 64-bit prefetchable MMIO. */
Adrian Bunka391f192008-04-18 13:53:57 -0700141static void pci_setup_bridge(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142{
143 struct pci_dev *bridge = bus->self;
144 struct pci_bus_region region;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100145 u32 l, bu, lu, io_upper16;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600147 dev_info(&bridge->dev, "PCI bridge, secondary bus %04x:%02x\n",
148 pci_domain_nr(bus), bus->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149
150 /* Set up the top and bottom of the PCI I/O segment for this bus. */
151 pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
152 if (bus->resource[0]->flags & IORESOURCE_IO) {
153 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
154 l &= 0xffff0000;
155 l |= (region.start >> 8) & 0x00f0;
156 l |= region.end & 0xf000;
157 /* Set up upper 16 bits of I/O base/limit. */
158 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600159 dev_info(&bridge->dev, " IO window: %#04lx-%#04lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100160 (unsigned long)region.start,
161 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700162 }
163 else {
164 /* Clear upper 16 bits of I/O base/limit. */
165 io_upper16 = 0;
166 l = 0x00f0;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600167 dev_info(&bridge->dev, " IO window: disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 }
169 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
170 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
171 /* Update lower 16 bits of I/O base/limit. */
172 pci_write_config_dword(bridge, PCI_IO_BASE, l);
173 /* Update upper 16 bits of I/O base/limit. */
174 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
175
176 /* Set up the top and bottom of the PCI Memory segment
177 for this bus. */
178 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
179 if (bus->resource[1]->flags & IORESOURCE_MEM) {
180 l = (region.start >> 16) & 0xfff0;
181 l |= region.end & 0xfff00000;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600182 dev_info(&bridge->dev, " MEM window: %#08lx-%#08lx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100183 (unsigned long)region.start,
184 (unsigned long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 }
186 else {
187 l = 0x0000fff0;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600188 dev_info(&bridge->dev, " MEM window: disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 }
190 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
191
192 /* Clear out the upper 32 bits of PREF limit.
193 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
194 disables PREF range, which is ok. */
195 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
196
197 /* Set up PREF base/limit. */
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100198 bu = lu = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700199 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
200 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
201 l = (region.start >> 16) & 0xfff0;
202 l |= region.end & 0xfff00000;
Andrew Morton13d36c22008-02-04 23:50:12 -0800203 bu = upper_32_bits(region.start);
204 lu = upper_32_bits(region.end);
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600205 dev_info(&bridge->dev, " PREFETCH window: %#016llx-%#016llx\n",
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100206 (unsigned long long)region.start,
207 (unsigned long long)region.end);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700208 }
209 else {
210 l = 0x0000fff0;
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600211 dev_info(&bridge->dev, " PREFETCH window: disabled\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 }
213 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
214
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100215 /* Set the upper 32 bits of PREF base & limit. */
216 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
217 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218
219 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
220}
221
222/* Check whether the bridge supports optional I/O and
223 prefetchable memory ranges. If not, the respective
224 base/limit registers must be read-only and read as 0. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800225static void pci_bridge_check_ranges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700226{
227 u16 io;
228 u32 pmem;
229 struct pci_dev *bridge = bus->self;
230 struct resource *b_res;
231
232 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
233 b_res[1].flags |= IORESOURCE_MEM;
234
235 pci_read_config_word(bridge, PCI_IO_BASE, &io);
236 if (!io) {
237 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
238 pci_read_config_word(bridge, PCI_IO_BASE, &io);
239 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
240 }
241 if (io)
242 b_res[0].flags |= IORESOURCE_IO;
243 /* DECchip 21050 pass 2 errata: the bridge may miss an address
244 disconnect boundary by one PCI data phase.
245 Workaround: do not use prefetching on this device. */
246 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
247 return;
248 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
249 if (!pmem) {
250 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
251 0xfff0fff0);
252 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
253 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
254 }
255 if (pmem)
256 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
257}
258
259/* Helper function for sizing routines: find first available
260 bus resource of a given type. Note: we intentionally skip
261 the bus resources which have already been assigned (that is,
262 have non-NULL parent resource). */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800263static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700264{
265 int i;
266 struct resource *r;
267 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
268 IORESOURCE_PREFETCH;
269
270 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
271 r = bus->resource[i];
Ivan Kokshaysky299de032005-06-15 18:59:27 +0400272 if (r == &ioport_resource || r == &iomem_resource)
273 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700274 if (r && (r->flags & type_mask) == type && !r->parent)
275 return r;
276 }
277 return NULL;
278}
279
280/* Sizing the IO windows of the PCI-PCI bridge is trivial,
281 since these windows have 4K granularity and the IO ranges
282 of non-bridge PCI devices are limited to 256 bytes.
283 We must be careful with the ISA aliasing though. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800284static void pbus_size_io(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285{
286 struct pci_dev *dev;
287 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
288 unsigned long size = 0, size1 = 0;
289
290 if (!b_res)
291 return;
292
293 list_for_each_entry(dev, &bus->devices, bus_list) {
294 int i;
295
296 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
297 struct resource *r = &dev->resource[i];
298 unsigned long r_size;
299
300 if (r->parent || !(r->flags & IORESOURCE_IO))
301 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800302 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304 if (r_size < 0x400)
305 /* Might be re-aligned for ISA */
306 size += r_size;
307 else
308 size1 += r_size;
309 }
310 }
311/* To be fixed in 2.5: we should have sort of HAVE_ISA
312 flag in the struct pci_bus. */
313#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
314 size = (size & 0xff) + ((size & ~0xffUL) << 2);
315#endif
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700316 size = ALIGN(size + size1, 4096);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 if (!size) {
318 b_res->flags = 0;
319 return;
320 }
321 /* Alignment of the IO window is always 4K */
322 b_res->start = 4096;
323 b_res->end = b_res->start + size - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400324 b_res->flags |= IORESOURCE_STARTALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700325}
326
327/* Calculate the size of the bus and minimal alignment which
328 guarantees that all child resources fit in this size. */
Sam Ravnborg96bde062007-03-26 21:53:30 -0800329static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330{
331 struct pci_dev *dev;
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100332 resource_size_t min_align, align, size;
333 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334 int order, max_order;
335 struct resource *b_res = find_free_bus_resource(bus, type);
336
337 if (!b_res)
338 return 0;
339
340 memset(aligns, 0, sizeof(aligns));
341 max_order = 0;
342 size = 0;
343
344 list_for_each_entry(dev, &bus->devices, bus_list) {
345 int i;
346
347 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
348 struct resource *r = &dev->resource[i];
Benjamin Herrenschmidtc40a22e2007-12-10 17:32:15 +1100349 resource_size_t r_size;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700350
351 if (r->parent || (r->flags & mask) != type)
352 continue;
Zhao, Yu022edd82008-10-13 19:24:28 +0800353 r_size = resource_size(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354 /* For bridges size != alignment */
Linus Torvalds5f17cfc2008-09-04 01:33:59 -0700355 align = resource_alignment(r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700356 order = __ffs(align) - 20;
357 if (order > 11) {
Linus Torvalds5f17cfc2008-09-04 01:33:59 -0700358 dev_warn(&dev->dev, "BAR %d bad alignment %llx: "
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +1100359 "%pR\n", i, (unsigned long long)align, r);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360 r->flags = 0;
361 continue;
362 }
363 size += r_size;
364 if (order < 0)
365 order = 0;
366 /* Exclude ranges with size > align from
367 calculation of the alignment. */
368 if (r_size == align)
369 aligns[order] += align;
370 if (order > max_order)
371 max_order = order;
372 }
373 }
374
375 align = 0;
376 min_align = 0;
377 for (order = 0; order <= max_order; order++) {
Jeremy Fitzhardinge8308c542008-09-11 01:31:50 -0700378 resource_size_t align1 = 1;
379
380 align1 <<= (order + 20);
381
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 if (!align)
383 min_align = align1;
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700384 else if (ALIGN(align + min_align, min_align) < align1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700385 min_align = align1 >> 1;
386 align += aligns[order];
387 }
Milind Arun Choudhary6f6f8c22007-07-09 11:55:51 -0700388 size = ALIGN(size, min_align);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389 if (!size) {
390 b_res->flags = 0;
391 return 1;
392 }
393 b_res->start = min_align;
394 b_res->end = size + min_align - 1;
Ivan Kokshaysky88452562008-03-30 19:50:14 +0400395 b_res->flags |= IORESOURCE_STARTALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 return 1;
397}
398
Adrian Bunk5468ae62008-04-18 13:53:56 -0700399static void pci_bus_size_cardbus(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700400{
401 struct pci_dev *bridge = bus->self;
402 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
403 u16 ctrl;
404
405 /*
406 * Reserve some resources for CardBus. We reserve
407 * a fixed amount of bus space for CardBus bridges.
408 */
Linus Torvalds934b7022008-04-22 18:16:30 -0700409 b_res[0].start = 0;
410 b_res[0].end = pci_cardbus_io_size - 1;
411 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
Linus Torvalds934b7022008-04-22 18:16:30 -0700413 b_res[1].start = 0;
414 b_res[1].end = pci_cardbus_io_size - 1;
415 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416
417 /*
418 * Check whether prefetchable memory is supported
419 * by this bridge.
420 */
421 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
422 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
423 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
424 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
425 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
426 }
427
428 /*
429 * If we have prefetchable memory support, allocate
430 * two regions. Otherwise, allocate one region of
431 * twice the size.
432 */
433 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
Linus Torvalds934b7022008-04-22 18:16:30 -0700434 b_res[2].start = 0;
435 b_res[2].end = pci_cardbus_mem_size - 1;
436 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700437
Linus Torvalds934b7022008-04-22 18:16:30 -0700438 b_res[3].start = 0;
439 b_res[3].end = pci_cardbus_mem_size - 1;
440 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700441 } else {
Linus Torvalds934b7022008-04-22 18:16:30 -0700442 b_res[3].start = 0;
443 b_res[3].end = pci_cardbus_mem_size * 2 - 1;
444 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_SIZEALIGN;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700445 }
446}
447
Sam Ravnborg451124a2008-02-02 22:33:43 +0100448void __ref pci_bus_size_bridges(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449{
450 struct pci_dev *dev;
451 unsigned long mask, prefmask;
452
453 list_for_each_entry(dev, &bus->devices, bus_list) {
454 struct pci_bus *b = dev->subordinate;
455 if (!b)
456 continue;
457
458 switch (dev->class >> 8) {
459 case PCI_CLASS_BRIDGE_CARDBUS:
460 pci_bus_size_cardbus(b);
461 break;
462
463 case PCI_CLASS_BRIDGE_PCI:
464 default:
465 pci_bus_size_bridges(b);
466 break;
467 }
468 }
469
470 /* The root bus? */
471 if (!bus->self)
472 return;
473
474 switch (bus->self->class >> 8) {
475 case PCI_CLASS_BRIDGE_CARDBUS:
476 /* don't size cardbuses yet. */
477 break;
478
479 case PCI_CLASS_BRIDGE_PCI:
480 pci_bridge_check_ranges(bus);
481 default:
482 pbus_size_io(bus);
483 /* If the bridge supports prefetchable range, size it
484 separately. If it doesn't, or its prefetchable window
485 has already been allocated by arch code, try
486 non-prefetchable range for both types of PCI memory
487 resources. */
488 mask = IORESOURCE_MEM;
489 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
490 if (pbus_size_mem(bus, prefmask, prefmask))
491 mask = prefmask; /* Success, size non-prefetch only. */
492 pbus_size_mem(bus, mask, IORESOURCE_MEM);
493 break;
494 }
495}
496EXPORT_SYMBOL(pci_bus_size_bridges);
497
Sam Ravnborg451124a2008-02-02 22:33:43 +0100498void __ref pci_bus_assign_resources(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700499{
500 struct pci_bus *b;
501 struct pci_dev *dev;
502
503 pbus_assign_resources_sorted(bus);
504
Linus Torvalds1da177e2005-04-16 15:20:36 -0700505 list_for_each_entry(dev, &bus->devices, bus_list) {
506 b = dev->subordinate;
507 if (!b)
508 continue;
509
510 pci_bus_assign_resources(b);
511
512 switch (dev->class >> 8) {
513 case PCI_CLASS_BRIDGE_PCI:
514 pci_setup_bridge(b);
515 break;
516
517 case PCI_CLASS_BRIDGE_CARDBUS:
518 pci_setup_cardbus(b);
519 break;
520
521 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600522 dev_info(&dev->dev, "not setting up bridge for bus "
523 "%04x:%02x\n", pci_domain_nr(b), b->number);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 break;
525 }
526 }
527}
528EXPORT_SYMBOL(pci_bus_assign_resources);
529
Yinghai Lu76fbc262008-06-23 20:33:06 +0200530static void pci_bus_dump_res(struct pci_bus *bus)
531{
532 int i;
533
534 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
535 struct resource *res = bus->resource[i];
536 if (!res)
537 continue;
538
Bjorn Helgaasa19f5df2008-12-18 16:34:19 -0700539 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %s %pR\n", i,
540 (res->flags & IORESOURCE_IO) ? "io: " : "mem:", res);
Yinghai Lu76fbc262008-06-23 20:33:06 +0200541 }
542}
543
544static void pci_bus_dump_resources(struct pci_bus *bus)
545{
546 struct pci_bus *b;
547 struct pci_dev *dev;
548
549
550 pci_bus_dump_res(bus);
551
552 list_for_each_entry(dev, &bus->devices, bus_list) {
553 b = dev->subordinate;
554 if (!b)
555 continue;
556
557 pci_bus_dump_resources(b);
558 }
559}
560
Linus Torvalds1da177e2005-04-16 15:20:36 -0700561void __init
562pci_assign_unassigned_resources(void)
563{
564 struct pci_bus *bus;
565
566 /* Depth first, calculate sizes and alignments of all
567 subordinate buses. */
568 list_for_each_entry(bus, &pci_root_buses, node) {
569 pci_bus_size_bridges(bus);
570 }
571 /* Depth last, allocate resources and update the hardware. */
572 list_for_each_entry(bus, &pci_root_buses, node) {
573 pci_bus_assign_resources(bus);
574 pci_enable_bridges(bus);
575 }
Yinghai Lu76fbc262008-06-23 20:33:06 +0200576
577 /* dump the resource on buses */
578 list_for_each_entry(bus, &pci_root_buses, node) {
579 pci_bus_dump_resources(bus);
580 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700581}