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Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
Jesse Barnesd1d70672014-05-28 14:39:03 -070028#include <linux/async.h>
Jesse Barnes79e53942008-11-07 14:24:08 -080029#include <linux/i2c.h>
Damien Lespiau178f7362013-08-06 20:32:18 +010030#include <linux/hdmi.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/i915_drm.h>
Jesse Barnes80824002009-09-10 15:28:06 -070032#include "i915_drv.h"
David Howells760285e2012-10-02 18:01:07 +010033#include <drm/drm_crtc.h>
34#include <drm/drm_crtc_helper.h>
35#include <drm/drm_fb_helper.h>
Ville Syrjäläb1ba1242016-05-02 22:08:23 +030036#include <drm/drm_dp_dual_mode_helper.h>
Dave Airlie0e32b392014-05-02 14:02:48 +100037#include <drm/drm_dp_mst_helper.h>
Gustavo Padovaneeca7782014-09-05 17:04:46 -030038#include <drm/drm_rect.h>
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +020039#include <drm/drm_atomic.h>
Chris Wilson913d8d12010-08-07 11:01:35 +010040
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010041/**
42 * _wait_for - magic (register) wait macro
43 *
44 * Does the right thing for modeset paths when run under kdgb or similar atomic
45 * contexts. Note that it's important that we check the condition again after
46 * having timed out, since the timeout could be due to preemption or similar and
47 * we've never had a chance to check the condition before the timeout.
Tvrtko Ursulin0351b932016-03-03 16:21:27 +000048 *
49 * TODO: When modesetting has fully transitioned to atomic, the below
50 * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
51 * added.
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010052 */
Tvrtko Ursulin3f177622016-03-03 14:36:41 +000053#define _wait_for(COND, US, W) ({ \
54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1; \
Chris Wilson913d8d12010-08-07 11:01:35 +010055 int ret__ = 0; \
Akshay Joshi0206e352011-08-16 15:34:10 -040056 while (!(COND)) { \
Chris Wilson913d8d12010-08-07 11:01:35 +010057 if (time_after(jiffies, timeout__)) { \
Daniel Vetter1d5bfac2013-03-28 00:03:25 +010058 if (!(COND)) \
59 ret__ = -ETIMEDOUT; \
Chris Wilson913d8d12010-08-07 11:01:35 +010060 break; \
61 } \
Ville Syrjälä9848de02015-03-20 21:28:08 +020062 if ((W) && drm_can_sleep()) { \
Tvrtko Ursulin3f177622016-03-03 14:36:41 +000063 usleep_range((W), (W)*2); \
Ben Widawsky0cc27642012-09-01 22:59:48 -070064 } else { \
65 cpu_relax(); \
66 } \
Chris Wilson913d8d12010-08-07 11:01:35 +010067 } \
68 ret__; \
69})
70
Tvrtko Ursulin3f177622016-03-03 14:36:41 +000071#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 1000)
Tvrtko Ursulin3f177622016-03-03 14:36:41 +000072
Tvrtko Ursulin0351b932016-03-03 16:21:27 +000073/* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
74#if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +010075# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
Tvrtko Ursulin0351b932016-03-03 16:21:27 +000076#else
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +010077# define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
Tvrtko Ursulin0351b932016-03-03 16:21:27 +000078#endif
79
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +010080#define _wait_for_atomic(COND, US, ATOMIC) \
81({ \
82 int cpu, ret, timeout = (US) * 1000; \
83 u64 base; \
84 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
Tvrtko Ursulin0351b932016-03-03 16:21:27 +000085 BUILD_BUG_ON((US) > 50000); \
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +010086 if (!(ATOMIC)) { \
87 preempt_disable(); \
88 cpu = smp_processor_id(); \
89 } \
90 base = local_clock(); \
91 for (;;) { \
92 u64 now = local_clock(); \
93 if (!(ATOMIC)) \
94 preempt_enable(); \
95 if (COND) { \
96 ret = 0; \
97 break; \
98 } \
99 if (now - base >= timeout) { \
100 ret = -ETIMEDOUT; \
Tvrtko Ursulin0351b932016-03-03 16:21:27 +0000101 break; \
102 } \
103 cpu_relax(); \
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +0100104 if (!(ATOMIC)) { \
105 preempt_disable(); \
106 if (unlikely(cpu != smp_processor_id())) { \
107 timeout -= now - base; \
108 cpu = smp_processor_id(); \
109 base = local_clock(); \
110 } \
111 } \
Tvrtko Ursulin0351b932016-03-03 16:21:27 +0000112 } \
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +0100113 ret; \
114})
115
116#define wait_for_us(COND, US) \
117({ \
118 int ret__; \
119 BUILD_BUG_ON(!__builtin_constant_p(US)); \
120 if ((US) > 10) \
121 ret__ = _wait_for((COND), (US), 10); \
122 else \
123 ret__ = _wait_for_atomic((COND), (US), 0); \
Tvrtko Ursulin0351b932016-03-03 16:21:27 +0000124 ret__; \
125})
126
Tvrtko Ursulin18f4b842016-06-29 12:27:22 +0100127#define wait_for_atomic(COND, MS) _wait_for_atomic((COND), (MS) * 1000, 1)
128#define wait_for_atomic_us(COND, US) _wait_for_atomic((COND), (US), 1)
Chris Wilson481b6af2010-08-23 17:43:35 +0100129
Jani Nikula49938ac2014-01-10 17:10:20 +0200130#define KHz(x) (1000 * (x))
131#define MHz(x) KHz(1000 * (x))
Chris Wilson021357a2010-09-07 20:54:59 +0100132
Jesse Barnes79e53942008-11-07 14:24:08 -0800133/*
134 * Display related stuff
135 */
136
137/* store information about an Ixxx DVO */
138/* The i830->i865 use multiple DVOs with multiple i2cs */
139/* the i915, i945 have a single sDVO i2c bus - which is different */
140#define MAX_OUTPUTS 6
141/* maximum connectors per crtcs in the mode set */
Jesse Barnes79e53942008-11-07 14:24:08 -0800142
Sagar Kamble4726e0b2014-03-10 17:06:23 +0530143/* Maximum cursor sizes */
144#define GEN2_CURSOR_WIDTH 64
145#define GEN2_CURSOR_HEIGHT 64
Damien Lespiau068be562014-03-28 14:17:49 +0000146#define MAX_CURSOR_WIDTH 256
147#define MAX_CURSOR_HEIGHT 256
Sagar Kamble4726e0b2014-03-10 17:06:23 +0530148
Jesse Barnes79e53942008-11-07 14:24:08 -0800149#define INTEL_I2C_BUS_DVO 1
150#define INTEL_I2C_BUS_SDVO 2
151
152/* these are outputs from the chip - integrated only
153 external chips are via DVO or SDVO output */
Paulo Zanoni6847d712014-10-27 17:47:52 -0200154enum intel_output_type {
155 INTEL_OUTPUT_UNUSED = 0,
156 INTEL_OUTPUT_ANALOG = 1,
157 INTEL_OUTPUT_DVO = 2,
158 INTEL_OUTPUT_SDVO = 3,
159 INTEL_OUTPUT_LVDS = 4,
160 INTEL_OUTPUT_TVOUT = 5,
161 INTEL_OUTPUT_HDMI = 6,
Ville Syrjäläcca05022016-06-22 21:57:06 +0300162 INTEL_OUTPUT_DP = 7,
Paulo Zanoni6847d712014-10-27 17:47:52 -0200163 INTEL_OUTPUT_EDP = 8,
164 INTEL_OUTPUT_DSI = 9,
165 INTEL_OUTPUT_UNKNOWN = 10,
166 INTEL_OUTPUT_DP_MST = 11,
167};
Jesse Barnes79e53942008-11-07 14:24:08 -0800168
169#define INTEL_DVO_CHIP_NONE 0
170#define INTEL_DVO_CHIP_LVDS 1
171#define INTEL_DVO_CHIP_TMDS 2
172#define INTEL_DVO_CHIP_TVOUT 4
173
Shobhit Kumardfba2e22014-04-14 11:18:24 +0530174#define INTEL_DSI_VIDEO_MODE 0
175#define INTEL_DSI_COMMAND_MODE 1
Jani Nikula72ffa332013-08-27 15:12:17 +0300176
Jesse Barnes79e53942008-11-07 14:24:08 -0800177struct intel_framebuffer {
178 struct drm_framebuffer base;
Chris Wilson05394f32010-11-08 19:18:58 +0000179 struct drm_i915_gem_object *obj;
Ville Syrjälä2d7a2152016-02-15 22:54:47 +0200180 struct intel_rotation_info rot_info;
Ville Syrjälä6687c902015-09-15 13:16:41 +0300181
182 /* for each plane in the normal GTT view */
183 struct {
184 unsigned int x, y;
185 } normal[2];
186 /* for each plane in the rotated GTT view */
187 struct {
188 unsigned int x, y;
189 unsigned int pitch; /* pixels */
190 } rotated[2];
Jesse Barnes79e53942008-11-07 14:24:08 -0800191};
192
Chris Wilson37811fc2010-08-25 22:45:57 +0100193struct intel_fbdev {
194 struct drm_fb_helper helper;
Jesse Barnes8bcd4552014-02-07 12:10:38 -0800195 struct intel_framebuffer *fb;
Chris Wilson058d88c2016-08-15 10:49:06 +0100196 struct i915_vma *vma;
Chris Wilson43cee312016-06-21 09:16:54 +0100197 async_cookie_t cookie;
Jesse Barnesd978ef12014-03-07 08:57:51 -0800198 int preferred_bpp;
Chris Wilson37811fc2010-08-25 22:45:57 +0100199};
Jesse Barnes79e53942008-11-07 14:24:08 -0800200
Eric Anholt21d40d32010-03-25 11:11:14 -0700201struct intel_encoder {
Chris Wilson4ef69c72010-09-09 15:14:28 +0100202 struct drm_encoder base;
Daniel Vetter9a935852012-07-05 22:34:27 +0200203
Paulo Zanoni6847d712014-10-27 17:47:52 -0200204 enum intel_output_type type;
Ville Syrjäläbc079e82014-03-03 16:15:28 +0200205 unsigned int cloneable;
Eric Anholt21d40d32010-03-25 11:11:14 -0700206 void (*hot_plug)(struct intel_encoder *);
Daniel Vetter7ae89232013-03-27 00:44:52 +0100207 bool (*compute_config)(struct intel_encoder *,
Maarten Lankhorst0a478c22016-08-09 17:04:05 +0200208 struct intel_crtc_state *,
209 struct drm_connector_state *);
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +0200210 void (*pre_pll_enable)(struct intel_encoder *,
211 struct intel_crtc_state *,
212 struct drm_connector_state *);
213 void (*pre_enable)(struct intel_encoder *,
214 struct intel_crtc_state *,
215 struct drm_connector_state *);
216 void (*enable)(struct intel_encoder *,
217 struct intel_crtc_state *,
218 struct drm_connector_state *);
219 void (*disable)(struct intel_encoder *,
220 struct intel_crtc_state *,
221 struct drm_connector_state *);
222 void (*post_disable)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 void (*post_pll_disable)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
Daniel Vetterf0947c32012-07-02 13:10:34 +0200228 /* Read out the current hw state of this connector, returning true if
229 * the encoder is active. If the encoder is enabled it also set the pipe
230 * it is connected to in the pipe parameter. */
231 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700232 /* Reconstructs the equivalent mode flags for the current hardware
Daniel Vetterfdafa9e2013-06-12 11:47:24 +0200233 * state. This must be called _after_ display->get_pipe_config has
Xiong Zhang63000ef2013-06-28 12:59:06 +0800234 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
235 * be set correctly before calling this function. */
Jesse Barnes045ac3b2013-05-14 17:08:26 -0700236 void (*get_config)(struct intel_encoder *,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200237 struct intel_crtc_state *pipe_config);
Imre Deak07f9cd02014-08-18 14:42:45 +0300238 /*
239 * Called during system suspend after all pending requests for the
240 * encoder are flushed (for example for DP AUX transactions) and
241 * device interrupts are disabled.
242 */
243 void (*suspend)(struct intel_encoder *);
Ma Lingf8aed702009-08-24 13:50:24 +0800244 int crtc_mask;
Egbert Eich1d843f92013-02-25 12:06:49 -0500245 enum hpd_pin hpd_pin;
Jesse Barnes79e53942008-11-07 14:24:08 -0800246};
247
Jani Nikula1d508702012-10-19 14:51:49 +0300248struct intel_panel {
Jani Nikuladd06f902012-10-19 14:51:50 +0300249 struct drm_display_mode *fixed_mode;
Vandana Kannanec9ed192013-12-10 13:37:36 +0530250 struct drm_display_mode *downclock_mode;
Jani Nikula4d891522012-10-26 12:03:59 +0300251 int fitting_mode;
Jani Nikula58c68772013-11-08 16:48:54 +0200252
253 /* backlight */
254 struct {
Jani Nikulac91c9f32013-11-08 16:48:55 +0200255 bool present;
Jani Nikula58c68772013-11-08 16:48:54 +0200256 u32 level;
Jani Nikula6dda7302014-06-24 18:27:40 +0300257 u32 min;
Jani Nikula7bd688c2013-11-08 16:48:56 +0200258 u32 max;
Jani Nikula58c68772013-11-08 16:48:54 +0200259 bool enabled;
Jani Nikula636baeb2013-11-08 16:49:02 +0200260 bool combination_mode; /* gen 2/4 only */
261 bool active_low_pwm;
Shobhit Kumarb029e662015-06-26 14:32:10 +0530262
263 /* PWM chip */
Sunil Kamath022e4e52015-09-30 22:34:57 +0530264 bool util_pin_active_low; /* bxt+ */
265 u8 controller; /* bxt+ only */
Shobhit Kumarb029e662015-06-26 14:32:10 +0530266 struct pwm_device *pwm;
267
Jani Nikula58c68772013-11-08 16:48:54 +0200268 struct backlight_device *device;
Jani Nikulaab656bb2014-08-13 12:10:12 +0300269
Jani Nikula5507fae2015-09-14 14:03:48 +0300270 /* Connector and platform specific backlight functions */
271 int (*setup)(struct intel_connector *connector, enum pipe pipe);
272 uint32_t (*get)(struct intel_connector *connector);
273 void (*set)(struct intel_connector *connector, uint32_t level);
274 void (*disable)(struct intel_connector *connector);
275 void (*enable)(struct intel_connector *connector);
276 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
277 uint32_t hz);
278 void (*power)(struct intel_connector *, bool enable);
279 } backlight;
Jani Nikula1d508702012-10-19 14:51:49 +0300280};
281
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800282struct intel_connector {
283 struct drm_connector base;
Daniel Vetter9a935852012-07-05 22:34:27 +0200284 /*
285 * The fixed encoder this connector is connected to.
286 */
Chris Wilsondf0e9242010-09-09 16:20:55 +0100287 struct intel_encoder *encoder;
Daniel Vetter9a935852012-07-05 22:34:27 +0200288
Daniel Vetterf0947c32012-07-02 13:10:34 +0200289 /* Reads out the current hw, returning true if the connector is enabled
290 * and active (i.e. dpms ON state). */
291 bool (*get_hw_state)(struct intel_connector *);
Jani Nikula1d508702012-10-19 14:51:49 +0300292
293 /* Panel info for eDP and LVDS */
294 struct intel_panel panel;
Jani Nikula9cd300e2012-10-19 14:51:52 +0300295
296 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
297 struct edid *edid;
Chris Wilsonbeb60602014-09-02 20:04:00 +0100298 struct edid *detect_edid;
Egbert Eich821450c2013-04-16 13:36:55 +0200299
300 /* since POLL and HPD connectors may use the same HPD line keep the native
301 state of connector->polled in case hotplug storm detection changes it */
302 u8 polled;
Dave Airlie0e32b392014-05-02 14:02:48 +1000303
304 void *port; /* store this opaque as its illegal to dereference it */
305
306 struct intel_dp *mst_port;
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800307};
308
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300309struct dpll {
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300310 /* given values */
311 int n;
312 int m1, m2;
313 int p1, p2;
314 /* derived values */
315 int dot;
316 int vco;
317 int m;
318 int p;
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +0300319};
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300320
Maarten Lankhorstde419ab2015-06-04 10:21:28 +0200321struct intel_atomic_state {
322 struct drm_atomic_state base;
323
Maarten Lankhorst27c329e2015-06-15 12:33:56 +0200324 unsigned int cdclk;
Maarten Lankhorst565602d2015-12-10 12:33:57 +0100325
Maarten Lankhorst1a617b72015-12-03 14:31:06 +0100326 /*
327 * Calculated device cdclk, can be different from cdclk
328 * only when all crtc's are DPMS off.
329 */
330 unsigned int dev_cdclk;
331
Maarten Lankhorst565602d2015-12-10 12:33:57 +0100332 bool dpll_set, modeset;
333
Matt Roper8b4a7d02016-05-12 07:06:00 -0700334 /*
335 * Does this transaction change the pipes that are active? This mask
336 * tracks which CRTC's have changed their active state at the end of
337 * the transaction (not counting the temporary disable during modesets).
338 * This mask should only be non-zero when intel_state->modeset is true,
339 * but the converse is not necessarily true; simply changing a mode may
340 * not flip the final active status of any CRTC's
341 */
342 unsigned int active_pipe_changes;
343
Maarten Lankhorst565602d2015-12-10 12:33:57 +0100344 unsigned int active_crtcs;
345 unsigned int min_pixclk[I915_MAX_PIPES];
346
Clint Taylorc89e39f2016-05-13 23:41:21 +0300347 /* SKL/KBL Only */
348 unsigned int cdclk_pll_vco;
349
Maarten Lankhorstde419ab2015-06-04 10:21:28 +0200350 struct intel_shared_dpll_config shared_dpll[I915_NUM_PLLS];
Matt Ropered4a6a72016-02-23 17:20:13 -0800351
352 /*
353 * Current watermarks can't be trusted during hardware readout, so
354 * don't bother calculating intermediate watermarks.
355 */
356 bool skip_intermediate_wm;
Matt Roper98d39492016-05-12 07:06:03 -0700357
358 /* Gen9+ only */
Matt Roper734fa012016-05-12 15:11:40 -0700359 struct skl_wm_values wm_results;
Maarten Lankhorstde419ab2015-06-04 10:21:28 +0200360};
361
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300362struct intel_plane_state {
Matt Roper2b875c22014-12-01 15:40:13 -0800363 struct drm_plane_state base;
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300364 struct drm_rect clip;
Matt Roper32b7eee2014-12-24 07:59:06 -0800365
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200366 struct {
367 u32 offset;
368 int x, y;
369 } main;
Ville Syrjälä8d970652016-01-28 16:30:28 +0200370 struct {
371 u32 offset;
372 int x, y;
373 } aux;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200374
Matt Roper32b7eee2014-12-24 07:59:06 -0800375 /*
Chandra Kondurube41e332015-04-07 15:28:36 -0700376 * scaler_id
377 * = -1 : not using a scaler
378 * >= 0 : using a scalers
379 *
380 * plane requiring a scaler:
381 * - During check_plane, its bit is set in
382 * crtc_state->scaler_state.scaler_users by calling helper function
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +0200383 * update_scaler_plane.
Chandra Kondurube41e332015-04-07 15:28:36 -0700384 * - scaler_id indicates the scaler it got assigned.
385 *
386 * plane doesn't require a scaler:
387 * - this can happen when scaling is no more required or plane simply
388 * got disabled.
389 * - During check_plane, corresponding bit is reset in
390 * crtc_state->scaler_state.scaler_users by calling helper function
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +0200391 * update_scaler_plane.
Chandra Kondurube41e332015-04-07 15:28:36 -0700392 */
393 int scaler_id;
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200394
395 struct drm_intel_sprite_colorkey ckey;
Maarten Lankhorst7580d772015-08-18 13:40:06 +0200396
397 /* async flip related structures */
398 struct drm_i915_gem_request *wait_req;
Gustavo Padovaneeca7782014-09-05 17:04:46 -0300399};
400
Damien Lespiau5724dbd2015-01-20 12:51:52 +0000401struct intel_initial_plane_config {
Damien Lespiau2d140302015-02-05 17:22:18 +0000402 struct intel_framebuffer *fb;
Damien Lespiau49af4492015-01-20 12:51:44 +0000403 unsigned int tiling;
Jesse Barnes46f297f2014-03-07 08:57:48 -0800404 int size;
405 u32 base;
406};
407
Chandra Kondurube41e332015-04-07 15:28:36 -0700408#define SKL_MIN_SRC_W 8
409#define SKL_MAX_SRC_W 4096
410#define SKL_MIN_SRC_H 8
Chandra Konduru6156a452015-04-27 13:48:39 -0700411#define SKL_MAX_SRC_H 4096
Chandra Kondurube41e332015-04-07 15:28:36 -0700412#define SKL_MIN_DST_W 8
413#define SKL_MAX_DST_W 4096
414#define SKL_MIN_DST_H 8
Chandra Konduru6156a452015-04-27 13:48:39 -0700415#define SKL_MAX_DST_H 4096
Chandra Kondurube41e332015-04-07 15:28:36 -0700416
417struct intel_scaler {
Chandra Kondurube41e332015-04-07 15:28:36 -0700418 int in_use;
419 uint32_t mode;
420};
421
422struct intel_crtc_scaler_state {
423#define SKL_NUM_SCALERS 2
424 struct intel_scaler scalers[SKL_NUM_SCALERS];
425
426 /*
427 * scaler_users: keeps track of users requesting scalers on this crtc.
428 *
429 * If a bit is set, a user is using a scaler.
430 * Here user can be a plane or crtc as defined below:
431 * bits 0-30 - plane (bit position is index from drm_plane_index)
432 * bit 31 - crtc
433 *
434 * Instead of creating a new index to cover planes and crtc, using
435 * existing drm_plane_index for planes which is well less than 31
436 * planes and bit 31 for crtc. This should be fine to cover all
437 * our platforms.
438 *
439 * intel_atomic_setup_scalers will setup available scalers to users
440 * requesting scalers. It will gracefully fail if request exceeds
441 * avilability.
442 */
443#define SKL_CRTC_INDEX 31
444 unsigned scaler_users;
445
446 /* scaler used by crtc for panel fitting purpose */
447 int scaler_id;
448};
449
Daniel Vetter1ed51de2015-07-15 14:15:51 +0200450/* drm_mode->private_flags */
451#define I915_MODE_FLAG_INHERITED 1
452
Matt Roper4e0963c2015-09-24 15:53:15 -0700453struct intel_pipe_wm {
454 struct intel_wm_level wm[5];
Maarten Lankhorst71f0a622016-03-08 10:57:16 +0100455 struct intel_wm_level raw_wm[5];
Matt Roper4e0963c2015-09-24 15:53:15 -0700456 uint32_t linetime;
457 bool fbc_wm_enabled;
458 bool pipe_enabled;
459 bool sprites_enabled;
460 bool sprites_scaled;
461};
462
463struct skl_pipe_wm {
464 struct skl_wm_level wm[8];
465 struct skl_wm_level trans_wm;
466 uint32_t linetime;
467};
468
Matt Ropere8f1f022016-05-12 07:05:55 -0700469struct intel_crtc_wm_state {
470 union {
471 struct {
472 /*
473 * Intermediate watermarks; these can be
474 * programmed immediately since they satisfy
475 * both the current configuration we're
476 * switching away from and the new
477 * configuration we're switching to.
478 */
479 struct intel_pipe_wm intermediate;
480
481 /*
482 * Optimal watermarks, programmed post-vblank
483 * when this state is committed.
484 */
485 struct intel_pipe_wm optimal;
486 } ilk;
487
488 struct {
489 /* gen9+ only needs 1-step wm programming */
490 struct skl_pipe_wm optimal;
Matt Ropera1de91e2016-05-12 07:05:57 -0700491
492 /* cached plane data rate */
493 unsigned plane_data_rate[I915_MAX_PLANES];
494 unsigned plane_y_data_rate[I915_MAX_PLANES];
Matt Roper86a2100a2016-05-12 07:05:59 -0700495
496 /* minimum block allocation */
497 uint16_t minimum_blocks[I915_MAX_PLANES];
498 uint16_t minimum_y_blocks[I915_MAX_PLANES];
Matt Ropere8f1f022016-05-12 07:05:55 -0700499 } skl;
500 };
501
502 /*
503 * Platforms with two-step watermark programming will need to
504 * update watermark programming post-vblank to switch from the
505 * safe intermediate watermarks to the optimal final
506 * watermarks.
507 */
508 bool need_postvbl_update;
509};
510
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +0200511struct intel_crtc_state {
Ander Conselvan de Oliveira2d112de2015-01-15 14:55:22 +0200512 struct drm_crtc_state base;
513
Daniel Vetterbb760062013-06-06 14:55:52 +0200514 /**
515 * quirks - bitfield with hw state readout quirks
516 *
517 * For various reasons the hw state readout code might not be able to
518 * completely faithfully read out the current state. These cases are
519 * tracked with quirk flags so that fastboot and state checker can act
520 * accordingly.
521 */
Daniel Vetter99535992014-04-13 12:00:33 +0200522#define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
Daniel Vetterbb760062013-06-06 14:55:52 +0200523 unsigned long quirks;
524
Maarten Lankhorstcd202f62016-03-09 10:35:44 +0100525 unsigned fb_bits; /* framebuffers to flip */
Maarten Lankhorstab1d3a02015-11-19 16:07:14 +0100526 bool update_pipe; /* can a fast modeset be performed? */
527 bool disable_cxsr;
Ville Syrjäläcaed3612016-03-09 19:07:25 +0200528 bool update_wm_pre, update_wm_post; /* watermarks are updated */
Maarten Lankhorste8861672016-02-24 11:24:26 +0100529 bool fb_changed; /* fb on any of the planes is changed */
Maarten Lankhorstbfd16b22015-08-27 15:44:05 +0200530
Ville Syrjälä37327ab2013-09-04 18:25:28 +0300531 /* Pipe source size (ie. panel fitter input size)
532 * All planes will be positioned inside this space,
533 * and get clipped at the edges. */
534 int pipe_src_w, pipe_src_h;
535
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100536 /* Whether to set up the PCH/FDI. Note that we never allow sharing
537 * between pch encoders and cpu encoders. */
538 bool has_pch_encoder;
Daniel Vetter50f3b012013-03-27 00:44:56 +0100539
Jesse Barnese43823e2014-11-05 14:26:08 -0800540 /* Are we sending infoframes on the attached port */
541 bool has_infoframe;
542
Daniel Vetter3b117c82013-04-17 20:15:07 +0200543 /* CPU Transcoder for the pipe. Currently this can only differ from the
Jani Nikula4d1de972016-03-18 17:05:42 +0200544 * pipe on Haswell and later (where we have a special eDP transcoder)
545 * and Broxton (where we have special DSI transcoders). */
Daniel Vetter3b117c82013-04-17 20:15:07 +0200546 enum transcoder cpu_transcoder;
547
Daniel Vetter50f3b012013-03-27 00:44:56 +0100548 /*
549 * Use reduced/limited/broadcast rbg range, compressing from the full
550 * range fed into the crtcs.
551 */
552 bool limited_color_range;
553
Ville Syrjälä253c84c2016-06-22 21:57:01 +0300554 /* Bitmask of encoder types (enum intel_output_type)
555 * driven by the pipe.
556 */
557 unsigned int output_types;
558
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200559 /* Whether we should send NULL infoframes. Required for audio. */
560 bool has_hdmi_sink;
561
Daniel Vetter9ed109a2014-04-24 23:54:52 +0200562 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
563 * has_dp_encoder is set. */
564 bool has_audio;
565
Daniel Vetterd8b32242013-04-25 17:54:44 +0200566 /*
567 * Enable dithering, used when the selected pipe bpp doesn't match the
568 * plane bpp.
569 */
Daniel Vetter965e0c42013-03-27 00:44:57 +0100570 bool dither;
Daniel Vetterf47709a2013-03-28 10:42:02 +0100571
572 /* Controls for the clock computation, to override various stages. */
573 bool clock_set;
574
Daniel Vetter09ede542013-04-30 14:01:45 +0200575 /* SDVO TV has a bunch of special case. To make multifunction encoders
576 * work correctly, we need to track this at runtime.*/
577 bool sdvo_tv_clock;
578
Daniel Vettere29c22c2013-02-21 00:00:16 +0100579 /*
580 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
581 * required. This is set in the 2nd loop of calling encoder's
582 * ->compute_config if the first pick doesn't work out.
583 */
584 bool bw_constrained;
585
Daniel Vetterf47709a2013-03-28 10:42:02 +0100586 /* Settings for the intel dpll used on pretty much everything but
587 * haswell. */
Ville Syrjälä80ad9202013-04-19 14:36:51 +0300588 struct dpll dpll;
Daniel Vetterf47709a2013-03-28 10:42:02 +0100589
Ander Conselvan de Oliveira8106ddb2016-03-08 17:46:18 +0200590 /* Selected dpll when shared or NULL. */
591 struct intel_shared_dpll *shared_dpll;
Daniel Vettera43f6e02013-06-07 23:10:32 +0200592
Satheeshakrishna M96b7dfb2014-11-13 14:55:17 +0000593 /*
594 * - PORT_CLK_SEL for DDI ports on HSW/BDW.
595 * - enum skl_dpll on SKL
596 */
Daniel Vetterde7cfc62014-06-25 22:01:54 +0300597 uint32_t ddi_pll_sel;
598
Daniel Vetter66e985c2013-06-05 13:34:20 +0200599 /* Actual register state of the dpll, for shared dpll cross-checking. */
600 struct intel_dpll_hw_state dpll_hw_state;
601
Ville Syrjälä47eacba2016-04-12 22:14:35 +0300602 /* DSI PLL registers */
603 struct {
604 u32 ctrl, div;
605 } dsi_pll;
606
Daniel Vetter965e0c42013-03-27 00:44:57 +0100607 int pipe_bpp;
Daniel Vetter6cf86a52013-04-02 23:38:10 +0200608 struct intel_link_m_n dp_m_n;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200609
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530610 /* m2_n2 for eDP downclock */
611 struct intel_link_m_n dp_m2_n2;
Vandana Kannanf769cd22014-08-05 07:51:22 -0700612 bool has_drrs;
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530613
Daniel Vetterff9a6752013-06-01 17:16:21 +0200614 /*
615 * Frequence the dpll for the port should run at. Differs from the
Ville Syrjälä3c52f4e2013-09-06 23:28:59 +0300616 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
617 * already multiplied by pixel_multiplier.
Daniel Vetterdf92b1e2013-03-28 10:41:58 +0100618 */
Daniel Vetterff9a6752013-06-01 17:16:21 +0200619 int port_clock;
620
Daniel Vetter6cc5f342013-03-27 00:44:53 +0100621 /* Used by SDVO (and if we ever fix it, HDMI). */
622 unsigned pixel_multiplier;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700623
Ville Syrjälä90a6b7b2015-07-06 16:39:15 +0300624 uint8_t lane_count;
625
Imre Deak95a7a2a2016-06-13 16:44:35 +0300626 /*
627 * Used by platforms having DP/HDMI PHY with programmable lane
628 * latency optimization.
629 */
630 uint8_t lane_lat_optim_mask;
631
Jesse Barnes2dd24552013-04-25 12:55:01 -0700632 /* Panel fitter controls for gen2-gen4 + VLV */
Jesse Barnesb074cec2013-04-25 12:55:02 -0700633 struct {
634 u32 control;
635 u32 pgm_ratios;
Daniel Vetter68fc8742013-04-25 22:52:16 +0200636 u32 lvds_border_bits;
Jesse Barnesb074cec2013-04-25 12:55:02 -0700637 } gmch_pfit;
638
639 /* Panel fitter placement and size for Ironlake+ */
640 struct {
641 u32 pos;
642 u32 size;
Chris Wilsonfd4daa92013-08-27 17:04:17 +0100643 bool enabled;
Daniel Vetterfabf6e52014-05-29 14:10:22 +0200644 bool force_thru;
Jesse Barnesb074cec2013-04-25 12:55:02 -0700645 } pch_pfit;
Daniel Vetter33d29b12013-02-13 18:04:45 +0100646
Daniel Vetterca3a0ff2013-02-14 16:54:22 +0100647 /* FDI configuration, only valid if has_pch_encoder is set. */
Daniel Vetter33d29b12013-02-13 18:04:45 +0100648 int fdi_lanes;
Daniel Vetterca3a0ff2013-02-14 16:54:22 +0100649 struct intel_link_m_n fdi_m_n;
Paulo Zanoni42db64e2013-05-31 16:33:22 -0300650
651 bool ips_enabled;
Ville Syrjäläcf532bb2013-09-04 18:30:02 +0300652
Paulo Zanonif51be2e2016-01-19 11:35:50 -0200653 bool enable_fbc;
654
Ville Syrjäläcf532bb2013-09-04 18:30:02 +0300655 bool double_wide;
Dave Airlie0e32b392014-05-02 14:02:48 +1000656
657 bool dp_encoder_is_mst;
658 int pbn;
Chandra Kondurube41e332015-04-07 15:28:36 -0700659
660 struct intel_crtc_scaler_state scaler_state;
Maarten Lankhorst99d736a2015-06-01 12:50:09 +0200661
662 /* w/a for waiting 2 vblanks during crtc enable */
663 enum pipe hsw_workaround_pipe;
Matt Roperd21fbe82015-09-24 15:53:12 -0700664
665 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
666 bool disable_lp_wm;
Matt Roper4e0963c2015-09-24 15:53:15 -0700667
Matt Ropere8f1f022016-05-12 07:05:55 -0700668 struct intel_crtc_wm_state wm;
Lionel Landwerlin05dc6982016-03-16 10:57:15 +0000669
670 /* Gamma mode programmed on the pipe */
671 uint32_t gamma_mode;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100672};
673
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300674struct vlv_wm_state {
675 struct vlv_pipe_wm wm[3];
676 struct vlv_sr_wm sr[3];
677 uint8_t num_active_planes;
678 uint8_t num_levels;
679 uint8_t level;
680 bool cxsr;
681};
682
Jesse Barnes79e53942008-11-07 14:24:08 -0800683struct intel_crtc {
684 struct drm_crtc base;
Jesse Barnes80824002009-09-10 15:28:06 -0700685 enum pipe pipe;
686 enum plane plane;
Jesse Barnes79e53942008-11-07 14:24:08 -0800687 u8 lut_r[256], lut_g[256], lut_b[256];
Daniel Vetter08a48462012-07-02 11:43:47 +0200688 /*
689 * Whether the crtc and the connected output pipeline is active. Implies
690 * that crtc->enabled is set, i.e. the current mode configuration has
691 * some outputs connected to this crtc.
Daniel Vetter08a48462012-07-02 11:43:47 +0200692 */
693 bool active;
Imre Deak6efdf352013-10-16 17:25:52 +0300694 unsigned long enabled_power_domains;
Jesse Barnes652c3932009-08-17 13:31:43 -0700695 bool lowfreq_avail;
Daniel Vetter02e792f2009-09-15 22:57:34 +0200696 struct intel_overlay *overlay;
Daniel Vetter5a21b662016-05-24 17:13:53 +0200697 struct intel_flip_work *flip_work;
Chris Wilsoncda4b7d2010-07-09 08:45:04 +0100698
Chris Wilsonb4a98e52012-11-01 09:26:26 +0000699 atomic_t unpin_work_count;
700
Daniel Vettere506a0c2012-07-05 12:17:29 +0200701 /* Display surface base address adjustement for pageflips. Note that on
702 * gen4+ this only adjusts up to a tile, offsets within a tile are
703 * handled in the hw itself (with the TILEOFF register). */
Ville Syrjälä54ea9da2016-01-20 21:05:25 +0200704 u32 dspaddr_offset;
Paulo Zanoni2db33662015-09-14 15:20:03 -0300705 int adjusted_x;
706 int adjusted_y;
Daniel Vettere506a0c2012-07-05 12:17:29 +0200707
Chris Wilsoncda4b7d2010-07-09 08:45:04 +0100708 uint32_t cursor_addr;
Chris Wilson4b0e3332014-05-30 16:35:26 +0300709 uint32_t cursor_cntl;
Ville Syrjälädc41c152014-08-13 11:57:05 +0300710 uint32_t cursor_size;
Chris Wilson4b0e3332014-05-30 16:35:26 +0300711 uint32_t cursor_base;
Jesse Barnes4b645f12011-10-12 09:51:31 -0700712
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200713 struct intel_crtc_state *config;
Daniel Vetterb8cecdf2013-03-27 00:44:50 +0100714
Daniel Vetter5a21b662016-05-24 17:13:53 +0200715 /* reset counter value when the last flip was submitted */
716 unsigned int reset_counter;
717
Paulo Zanoni86642812013-04-12 17:57:57 -0300718 /* Access to these should be protected by dev_priv->irq_lock. */
719 bool cpu_fifo_underrun_disabled;
720 bool pch_fifo_underrun_disabled;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +0300721
722 /* per-pipe watermark state */
723 struct {
724 /* watermarks currently being used */
Matt Roper4e0963c2015-09-24 15:53:15 -0700725 union {
726 struct intel_pipe_wm ilk;
727 struct skl_pipe_wm skl;
728 } active;
Matt Ropered4a6a72016-02-23 17:20:13 -0800729
Ville Syrjälä852eb002015-06-24 22:00:07 +0300730 /* allow CxSR on this pipe */
731 bool cxsr_allowed;
Ville Syrjälä0b2ae6d2013-10-09 19:17:55 +0300732 } wm;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300733
Ville Syrjälä80715b22014-05-15 20:23:23 +0300734 int scanline_offset;
Matt Roper32b7eee2014-12-24 07:59:06 -0800735
Jesse Barneseb120ef2015-09-15 14:19:32 -0700736 struct {
737 unsigned start_vbl_count;
738 ktime_t start_vbl_time;
739 int min_vbl, max_vbl;
740 int scanline_start;
741 } debug;
Maarten Lankhorst85a62bf2015-09-01 12:15:33 +0200742
Chandra Kondurube41e332015-04-07 15:28:36 -0700743 /* scalers available on this crtc */
744 int num_scalers;
Ville Syrjälä262cd2e2015-06-24 22:00:04 +0300745
746 struct vlv_wm_state wm_state;
Jesse Barnes79e53942008-11-07 14:24:08 -0800747};
748
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300749struct intel_plane_wm_parameters {
750 uint32_t horiz_pixels;
Damien Lespiaued57cb82014-07-15 09:21:24 +0200751 uint32_t vert_pixels;
Chandra Konduru2cd601c2015-04-27 15:47:37 -0700752 /*
753 * For packed pixel formats:
754 * bytes_per_pixel - holds bytes per pixel
755 * For planar pixel formats:
756 * bytes_per_pixel - holds bytes per pixel for uv-plane
757 * y_bytes_per_pixel - holds bytes per pixel for y-plane
758 */
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300759 uint8_t bytes_per_pixel;
Chandra Konduru2cd601c2015-04-27 15:47:37 -0700760 uint8_t y_bytes_per_pixel;
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300761 bool enabled;
762 bool scaled;
Tvrtko Ursulin0fda6562015-02-27 15:12:35 +0000763 u64 tiling;
Tvrtko Ursulin1fc0a8f2015-03-23 11:10:38 +0000764 unsigned int rotation;
Ville Syrjälä6eb1a682015-06-24 22:00:03 +0300765 uint16_t fifo_size;
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300766};
767
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800768struct intel_plane {
769 struct drm_plane base;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700770 int plane;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800771 enum pipe pipe;
Damien Lespiau2d354c32012-10-22 18:19:27 +0100772 bool can_scale;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800773 int max_downscale;
Ville Syrjäläa9ff8712015-06-24 21:59:34 +0300774 uint32_t frontbuffer_bit;
Paulo Zanoni526682e2013-05-24 11:59:18 -0300775
776 /* Since we need to change the watermarks before/after
777 * enabling/disabling the planes, we need to store the parameters here
778 * as the other pieces of the struct may not reflect the values we want
779 * for the watermark calculations. Currently only Haswell uses this.
780 */
Ville Syrjäläc35426d2013-08-07 13:29:50 +0300781 struct intel_plane_wm_parameters wm;
Paulo Zanoni526682e2013-05-24 11:59:18 -0300782
Matt Roper8e7d6882015-01-21 16:35:41 -0800783 /*
784 * NOTE: Do not place new plane state fields here (e.g., when adding
785 * new plane properties). New runtime state should now be placed in
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100786 * the intel_plane_state structure and accessed via plane_state.
Matt Roper8e7d6882015-01-21 16:35:41 -0800787 */
788
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800789 void (*update_plane)(struct drm_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100790 const struct intel_crtc_state *crtc_state,
791 const struct intel_plane_state *plane_state);
Ville Syrjäläb39d53f2013-08-06 22:24:09 +0300792 void (*disable_plane)(struct drm_plane *plane,
Maarten Lankhorst7fabf5e2015-06-15 12:33:47 +0200793 struct drm_crtc *crtc);
Matt Roperc59cb172014-12-01 15:40:16 -0800794 int (*check_plane)(struct drm_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +0200795 struct intel_crtc_state *crtc_state,
Matt Roperc59cb172014-12-01 15:40:16 -0800796 struct intel_plane_state *state);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800797};
798
Eugeni Dodonovb445e3b2012-04-16 22:20:35 -0300799struct intel_watermark_params {
800 unsigned long fifo_size;
801 unsigned long max_wm;
802 unsigned long default_wm;
803 unsigned long guard_size;
804 unsigned long cacheline_size;
805};
806
807struct cxsr_latency {
808 int is_desktop;
809 int is_ddr3;
810 unsigned long fsb_freq;
811 unsigned long mem_freq;
812 unsigned long display_sr;
813 unsigned long display_hpll_disable;
814 unsigned long cursor_sr;
815 unsigned long cursor_hpll_disable;
816};
817
Maarten Lankhorstde419ab2015-06-04 10:21:28 +0200818#define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
Jesse Barnes79e53942008-11-07 14:24:08 -0800819#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +0200820#define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
Zhenyu Wang5daa55e2010-03-30 14:39:28 +0800821#define to_intel_connector(x) container_of(x, struct intel_connector, base)
Chris Wilson4ef69c72010-09-09 15:14:28 +0100822#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
Jesse Barnes79e53942008-11-07 14:24:08 -0800823#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800824#define to_intel_plane(x) container_of(x, struct intel_plane, base)
Matt Roperea2c67b2014-12-23 10:41:52 -0800825#define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
Matt Roper155e6362014-07-07 18:21:47 -0700826#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
Jesse Barnes79e53942008-11-07 14:24:08 -0800827
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300828struct intel_hdmi {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200829 i915_reg_t hdmi_reg;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300830 int ddc_bus;
Ville Syrjäläb1ba1242016-05-02 22:08:23 +0300831 struct {
832 enum drm_dp_dual_mode_type type;
833 int max_tmds_clock;
834 } dp_dual_mode;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +0300835 bool limited_color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200836 bool color_range_auto;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300837 bool has_hdmi_sink;
838 bool has_audio;
839 enum hdmi_force_audio force_audio;
Ville Syrjäläabedc072013-01-17 16:31:31 +0200840 bool rgb_quant_range_selectable;
Vandana Kannan94a11dd2014-06-11 11:06:01 +0530841 enum hdmi_picture_aspect aspect_ratio;
Shashank Sharmad8b4c432015-09-04 18:56:11 +0530842 struct intel_connector *attached_connector;
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300843 void (*write_infoframe)(struct drm_encoder *encoder,
Damien Lespiau178f7362013-08-06 20:32:18 +0100844 enum hdmi_infoframe_type type,
Ville Syrjäläfff63862013-12-10 15:19:08 +0200845 const void *frame, ssize_t len);
Paulo Zanoni687f4d02012-05-28 16:42:48 -0300846 void (*set_infoframes)(struct drm_encoder *encoder,
Daniel Vetter6897b4b2014-04-24 23:54:47 +0200847 bool enable,
Ville Syrjälä7c5f93b2015-09-08 13:40:49 +0300848 const struct drm_display_mode *adjusted_mode);
Ville Syrjäläcda0aaa2015-11-26 18:27:07 +0200849 bool (*infoframe_enabled)(struct drm_encoder *encoder,
850 const struct intel_crtc_state *pipe_config);
Eugeni Dodonovf5bbfca2012-05-09 15:37:30 -0300851};
852
Dave Airlie0e32b392014-05-02 14:02:48 +1000853struct intel_dp_mst_encoder;
Adam Jacksonb091cd92012-09-18 10:58:49 -0400854#define DP_MAX_DOWNSTREAM_PORTS 0x10
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300855
Ramalingam Cfe3cd482015-02-13 15:32:59 +0530856/*
857 * enum link_m_n_set:
858 * When platform provides two set of M_N registers for dp, we can
859 * program them and switch between them incase of DRRS.
860 * But When only one such register is provided, we have to program the
861 * required divider value on that registers itself based on the DRRS state.
862 *
863 * M1_N1 : Program dp_m_n on M1_N1 registers
864 * dp_m2_n2 on M2_N2 registers (If supported)
865 *
866 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
867 * M2_N2 registers are not supported
868 */
869
870enum link_m_n_set {
871 /* Sets the m1_n1 and m2_n2 */
872 M1_N1 = 0,
873 M2_N2
874};
875
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300876struct intel_dp {
Ville Syrjäläf0f59a02015-11-18 15:33:26 +0200877 i915_reg_t output_reg;
878 i915_reg_t aux_ch_ctl_reg;
879 i915_reg_t aux_ch_data_reg[5];
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300880 uint32_t DP;
Ville Syrjälä901c2da2015-08-17 18:05:12 +0300881 int link_rate;
882 uint8_t lane_count;
Shubhangi Shrivastava30d9aa42016-03-30 18:05:25 +0530883 uint8_t sink_count;
Ville Syrjälä64ee2fd2016-07-28 17:50:39 +0300884 bool link_mst;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300885 bool has_audio;
Shubhangi Shrivastava7d23e3c2016-03-30 18:05:23 +0530886 bool detect_done;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300887 enum hdmi_force_audio force_audio;
Ville Syrjälä0f2a2a72015-07-06 15:10:00 +0300888 bool limited_color_range;
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200889 bool color_range_auto;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300890 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
Shobhit Kumar2293bb52013-07-11 18:44:56 -0300891 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
Adam Jacksonb091cd92012-09-18 10:58:49 -0400892 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
Yetunde Adebisi86ee27b2016-04-05 15:10:51 +0100893 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
Ville Syrjälä94ca7192015-03-13 19:40:31 +0200894 /* sink rates as reported by DP_SUPPORTED_LINK_RATES */
895 uint8_t num_sink_rates;
896 int sink_rates[DP_MAX_SUPPORTED_RATES];
Jani Nikula9d1a1032014-03-14 16:51:15 +0200897 struct drm_dp_aux aux;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300898 uint8_t train_set[4];
899 int panel_power_up_delay;
900 int panel_power_down_delay;
901 int panel_power_cycle_delay;
902 int backlight_on_delay;
903 int backlight_off_delay;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300904 struct delayed_work panel_vdd_work;
905 bool want_panel_vdd;
Paulo Zanonidce56b32013-12-19 14:29:40 -0200906 unsigned long last_power_on;
907 unsigned long last_backlight_off;
Abhay Kumard28d4732016-01-22 17:39:04 -0800908 ktime_t panel_power_off_time;
Dave Airlie5d42f822014-08-05 09:04:59 +1000909
Clint Taylor01527b32014-07-07 13:01:46 -0700910 struct notifier_block edp_notifier;
911
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300912 /*
913 * Pipe whose power sequencer is currently locked into
914 * this port. Only relevant on VLV/CHV.
915 */
916 enum pipe pps_pipe;
Imre Deak78597992016-06-16 16:37:20 +0300917 /*
918 * Set if the sequencer may be reset due to a power transition,
919 * requiring a reinitialization. Only relevant on BXT.
920 */
921 bool pps_reset;
Ville Syrjälä36b5f422014-10-16 21:27:30 +0300922 struct edp_power_seq pps_delays;
Ville Syrjäläa4a5d2f2014-09-04 14:54:20 +0300923
Dave Airlie0e32b392014-05-02 14:02:48 +1000924 bool can_mst; /* this port supports mst */
925 bool is_mst;
Ville Syrjälä19e0b4c2016-08-05 19:05:42 +0300926 int active_mst_links;
Dave Airlie0e32b392014-05-02 14:02:48 +1000927 /* connector directly attached - won't be use for modeset in mst world */
Jani Nikuladd06f902012-10-19 14:51:50 +0300928 struct intel_connector *attached_connector;
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000929
Dave Airlie0e32b392014-05-02 14:02:48 +1000930 /* mst connector list */
931 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
932 struct drm_dp_mst_topology_mgr mst_mgr;
933
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000934 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
Damien Lespiau153b1102014-01-21 13:37:15 +0000935 /*
936 * This function returns the value we have to program the AUX_CTL
937 * register with to kick off an AUX transaction.
938 */
939 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
940 bool has_aux_irq,
941 int send_bytes,
942 uint32_t aux_clock_divider);
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +0300943
944 /* This is called before a link training is starterd */
945 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
946
Todd Previtec5d5ab72015-04-15 08:38:38 -0700947 /* Displayport compliance testing */
948 unsigned long compliance_test_type;
Todd Previte559be302015-05-04 07:48:20 -0700949 unsigned long compliance_test_data;
950 bool compliance_test_active;
Shobhit Kumar54d63ca2012-06-29 16:03:35 -0300951};
952
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200953struct intel_digital_port {
954 struct intel_encoder base;
Paulo Zanoni174edf12012-10-26 19:05:50 -0200955 enum port port;
Stéphane Marchesinbcf53de2013-07-12 13:54:41 -0700956 u32 saved_port_bits;
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200957 struct intel_dp dp;
958 struct intel_hdmi hdmi;
Daniel Vetterb2c5c182015-01-23 06:00:31 +0100959 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
Ville Syrjäläb0b33842015-07-08 23:45:55 +0300960 bool release_cl2_override;
Ville Syrjäläccb1a832015-12-08 19:59:38 +0200961 uint8_t max_lanes;
Takashi Iwaicae666c2015-11-12 15:23:41 +0100962 /* for communication with audio component; protected by av_mutex */
963 const struct drm_connector *audio_connector;
Paulo Zanonida63a9f2012-10-26 19:05:46 -0200964};
965
Dave Airlie0e32b392014-05-02 14:02:48 +1000966struct intel_dp_mst_encoder {
967 struct intel_encoder base;
968 enum pipe pipe;
969 struct intel_digital_port *primary;
Dave Airlie0552f762016-03-09 11:14:38 +1000970 struct intel_connector *connector;
Dave Airlie0e32b392014-05-02 14:02:48 +1000971};
972
Ville Syrjälä65d64cc2015-07-08 23:45:53 +0300973static inline enum dpio_channel
Jesse Barnes89b667f2013-04-18 14:51:36 -0700974vlv_dport_to_channel(struct intel_digital_port *dport)
975{
976 switch (dport->port) {
977 case PORT_B:
Chon Ming Lee00fc31b2014-04-09 13:28:15 +0300978 case PORT_D:
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800979 return DPIO_CH0;
Jesse Barnes89b667f2013-04-18 14:51:36 -0700980 case PORT_C:
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800981 return DPIO_CH1;
Jesse Barnes89b667f2013-04-18 14:51:36 -0700982 default:
983 BUG();
984 }
985}
986
Ville Syrjälä65d64cc2015-07-08 23:45:53 +0300987static inline enum dpio_phy
988vlv_dport_to_phy(struct intel_digital_port *dport)
989{
990 switch (dport->port) {
991 case PORT_B:
992 case PORT_C:
993 return DPIO_PHY0;
994 case PORT_D:
995 return DPIO_PHY1;
996 default:
997 BUG();
998 }
999}
1000
1001static inline enum dpio_channel
Chon Ming Leeeb69b0e2014-04-09 13:28:16 +03001002vlv_pipe_to_channel(enum pipe pipe)
1003{
1004 switch (pipe) {
1005 case PIPE_A:
1006 case PIPE_C:
1007 return DPIO_CH0;
1008 case PIPE_B:
1009 return DPIO_CH1;
1010 default:
1011 BUG();
1012 }
1013}
1014
Chris Wilsonf875c152010-09-09 15:44:14 +01001015static inline struct drm_crtc *
1016intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
1017{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001018 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilsonf875c152010-09-09 15:44:14 +01001019 return dev_priv->pipe_to_crtc_mapping[pipe];
1020}
1021
Chris Wilson417ae142011-01-19 15:04:42 +00001022static inline struct drm_crtc *
1023intel_get_crtc_for_plane(struct drm_device *dev, int plane)
1024{
Chris Wilsonfac5e232016-07-04 11:34:36 +01001025 struct drm_i915_private *dev_priv = to_i915(dev);
Chris Wilson417ae142011-01-19 15:04:42 +00001026 return dev_priv->plane_to_crtc_mapping[plane];
1027}
1028
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +02001029struct intel_flip_work {
1030 struct work_struct unpin_work;
1031 struct work_struct mmio_work;
1032
Daniel Vetter5a21b662016-05-24 17:13:53 +02001033 struct drm_crtc *crtc;
1034 struct drm_framebuffer *old_fb;
1035 struct drm_i915_gem_object *pending_flip_obj;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001036 struct drm_pending_vblank_event *event;
Chris Wilsone7d841c2012-12-03 11:36:30 +00001037 atomic_t pending;
Daniel Vetter5a21b662016-05-24 17:13:53 +02001038 u32 flip_count;
1039 u32 gtt_offset;
1040 struct drm_i915_gem_request *flip_queued_req;
Ville Syrjälä66f59c52015-09-14 22:43:46 +03001041 u32 flip_queued_vblank;
Daniel Vetter5a21b662016-05-24 17:13:53 +02001042 u32 flip_ready_vblank;
1043 unsigned int rotation;
Simon Farnsworth4e5359c2010-09-01 17:47:52 +01001044};
1045
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001046struct intel_load_detect_pipe {
Maarten Lankhorstedde3612016-02-17 09:18:35 +01001047 struct drm_atomic_state *restore_state;
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001048};
Daniel Vetterb9805142012-08-31 17:37:33 +02001049
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001050static inline struct intel_encoder *
1051intel_attached_encoder(struct drm_connector *connector)
Chris Wilsondf0e9242010-09-09 16:20:55 +01001052{
1053 return to_intel_connector(connector)->encoder;
1054}
1055
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001056static inline struct intel_digital_port *
1057enc_to_dig_port(struct drm_encoder *encoder)
1058{
1059 return container_of(encoder, struct intel_digital_port, base.base);
1060}
1061
Dave Airlie0e32b392014-05-02 14:02:48 +10001062static inline struct intel_dp_mst_encoder *
1063enc_to_mst(struct drm_encoder *encoder)
1064{
1065 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1066}
1067
Imre Deak9ff8c9b2013-05-08 13:14:02 +03001068static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1069{
1070 return &enc_to_dig_port(encoder)->dp;
1071}
1072
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001073static inline struct intel_digital_port *
1074dp_to_dig_port(struct intel_dp *intel_dp)
1075{
1076 return container_of(intel_dp, struct intel_digital_port, dp);
1077}
1078
1079static inline struct intel_digital_port *
1080hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1081{
1082 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
Paulo Zanoni7739c332012-10-15 15:51:29 -03001083}
1084
Damien Lespiau6af31a62014-03-28 00:18:33 +05301085/*
1086 * Returns the number of planes for this pipe, ie the number of sprites + 1
1087 * (primary plane). This doesn't count the cursor plane then.
1088 */
1089static inline unsigned int intel_num_planes(struct intel_crtc *crtc)
1090{
1091 return INTEL_INFO(crtc->base.dev)->num_sprites[crtc->pipe] + 1;
1092}
Damien Lespiaub0ea7d32012-12-13 16:09:00 +00001093
Daniel Vetter47339cd2014-09-30 10:56:46 +02001094/* intel_fifo_underrun.c */
Daniel Vettera72e4c92014-09-30 10:56:47 +02001095bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
Paulo Zanoni87440422013-09-24 15:48:31 -03001096 enum pipe pipe, bool enable);
Daniel Vettera72e4c92014-09-30 10:56:47 +02001097bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
Paulo Zanoni87440422013-09-24 15:48:31 -03001098 enum transcoder pch_transcoder,
1099 bool enable);
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001100void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1101 enum pipe pipe);
1102void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1103 enum transcoder pch_transcoder);
Ville Syrjäläaca7b682015-10-30 19:22:21 +02001104void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1105void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
Daniel Vetter47339cd2014-09-30 10:56:46 +02001106
1107/* i915_irq.c */
Daniel Vetter480c8032014-07-16 09:49:40 +02001108void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1109void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1110void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1111void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
Chris Wilsondc979972016-05-10 14:10:04 +01001112void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001113void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1114void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
Imre Deak59d02a12014-12-19 19:33:26 +02001115u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask);
Daniel Vetterb9632912014-09-30 10:56:44 +02001116void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1117void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
Jesse Barnes9df7575f2014-06-20 09:29:20 -07001118static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1119{
1120 /*
1121 * We only use drm_irq_uninstall() at unload and VT switch, so
1122 * this is the only thing we need to check.
1123 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02001124 return dev_priv->pm.irqs_enabled;
Jesse Barnes9df7575f2014-06-20 09:29:20 -07001125}
1126
Ville Syrjäläa225f072014-04-29 13:35:45 +03001127int intel_get_crtc_scanline(struct intel_crtc *crtc);
Damien Lespiau4c6c03b2015-03-06 18:50:48 +00001128void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1129 unsigned int pipe_mask);
Ville Syrjäläaae8ba82016-02-19 20:47:30 +02001130void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1131 unsigned int pipe_mask);
Jesse Barnes79e53942008-11-07 14:24:08 -08001132
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001133/* intel_crt.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001134void intel_crt_init(struct drm_device *dev);
Lyude9504a892016-06-21 17:03:42 -04001135void intel_crt_reset(struct drm_encoder *encoder);
Jesse Barnes79e53942008-11-07 14:24:08 -08001136
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001137/* intel_ddi.c */
Ville Syrjäläe404ba82015-08-17 18:46:20 +03001138void intel_ddi_clk_select(struct intel_encoder *encoder,
1139 const struct intel_crtc_state *pipe_config);
Ville Syrjälä32bdc402016-07-12 15:59:33 +03001140void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder);
Paulo Zanoni87440422013-09-24 15:48:31 -03001141void hsw_fdi_link_train(struct drm_crtc *crtc);
1142void intel_ddi_init(struct drm_device *dev, enum port port);
1143enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1144bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
Paulo Zanoni87440422013-09-24 15:48:31 -03001145void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
1146void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1147 enum transcoder cpu_transcoder);
1148void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
1149void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
Ander Conselvan de Oliveira190f68c2015-01-15 14:55:23 +02001150bool intel_ddi_pll_select(struct intel_crtc *crtc,
1151 struct intel_crtc_state *crtc_state);
Paulo Zanoni87440422013-09-24 15:48:31 -03001152void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
Ander Conselvan de Oliveiraad642172015-10-23 13:01:49 +03001153void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
Paulo Zanoni87440422013-09-24 15:48:31 -03001154bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
Maarten Lankhorstfd6bbda2016-08-09 17:04:04 +02001155void intel_ddi_fdi_disable(struct intel_encoder *,
1156 struct intel_crtc_state *,
1157 struct drm_connector_state *);
Paulo Zanoni87440422013-09-24 15:48:31 -03001158void intel_ddi_get_config(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001159 struct intel_crtc_state *pipe_config);
Satheeshakrishna Mbcddf612014-08-22 09:49:10 +05301160struct intel_encoder *
1161intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
Eugeni Dodonov72662e12012-05-09 15:37:31 -03001162
Dave Airlie44905a22014-05-02 13:36:43 +10001163void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder);
Dave Airlie0e32b392014-05-02 14:02:48 +10001164void intel_ddi_clock_get(struct intel_encoder *encoder,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001165 struct intel_crtc_state *pipe_config);
Dave Airlie0e32b392014-05-02 14:02:48 +10001166void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state);
David Weinehallf8896f52015-06-25 11:11:03 +03001167uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001168
Tvrtko Ursulin6761dd32015-03-23 11:10:32 +00001169unsigned int intel_fb_align_height(struct drm_device *dev,
1170 unsigned int height,
1171 uint32_t pixel_format,
1172 uint64_t fb_format_modifier);
Ville Syrjälä7b49f942016-01-12 21:08:32 +02001173u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
1174 uint64_t fb_modifier, uint32_t pixel_format);
Daniel Vetterb680c372014-09-19 18:27:27 +02001175
Jani Nikula7c10a2b2014-10-27 16:26:43 +02001176/* intel_audio.c */
Imre Deak88212942016-03-16 13:38:53 +02001177void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
Jani Nikula69bfe1a2014-10-27 16:26:50 +02001178void intel_audio_codec_enable(struct intel_encoder *encoder);
1179void intel_audio_codec_disable(struct intel_encoder *encoder);
Imre Deak58fddc22015-01-08 17:54:14 +02001180void i915_audio_component_init(struct drm_i915_private *dev_priv);
1181void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
Jani Nikula7c10a2b2014-10-27 16:26:43 +02001182
Daniel Vetterb680c372014-09-19 18:27:27 +02001183/* intel_display.c */
Ville Syrjäläb2045352016-05-13 23:41:27 +03001184void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco);
Ville Syrjälä19ab4ed2016-04-27 17:43:22 +03001185void intel_update_rawclk(struct drm_i915_private *dev_priv);
Ville Syrjäläc30fec62016-03-04 21:43:02 +02001186int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1187 const char *name, u32 reg, int ref_freq);
Matt Roper65a3fea2015-01-21 16:35:42 -08001188extern const struct drm_plane_funcs intel_plane_funcs;
Imre Deak88212942016-03-16 13:38:53 +02001189void intel_init_display_hooks(struct drm_i915_private *dev_priv);
Ville Syrjälä6687c902015-09-15 13:16:41 +03001190unsigned int intel_fb_xy_to_linear(int x, int y,
Ville Syrjälä29490562016-01-20 18:02:50 +02001191 const struct intel_plane_state *state,
1192 int plane);
Ville Syrjälä6687c902015-09-15 13:16:41 +03001193void intel_add_fb_offsets(int *x, int *y,
Ville Syrjälä29490562016-01-20 18:02:50 +02001194 const struct intel_plane_state *state, int plane);
Ville Syrjälä1663b9d2016-02-15 22:54:45 +02001195unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
Daniel Vetterb680c372014-09-19 18:27:27 +02001196bool intel_has_pending_fb_unpin(struct drm_device *dev);
Tvrtko Ursulin7d993732016-04-28 12:57:00 +01001197void intel_mark_busy(struct drm_i915_private *dev_priv);
1198void intel_mark_idle(struct drm_i915_private *dev_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001199void intel_crtc_restore_mode(struct drm_crtc *crtc);
Maarten Lankhorst70e0bd72015-07-13 16:30:29 +02001200int intel_display_suspend(struct drm_device *dev);
Imre Deak8090ba82016-08-10 14:07:33 +03001201void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001202void intel_encoder_destroy(struct drm_encoder *encoder);
Ander Conselvan de Oliveira08d9bc92015-04-10 10:59:10 +03001203int intel_connector_init(struct intel_connector *);
1204struct intel_connector *intel_connector_alloc(void);
Paulo Zanoni87440422013-09-24 15:48:31 -03001205bool intel_connector_get_hw_state(struct intel_connector *connector);
Paulo Zanoni87440422013-09-24 15:48:31 -03001206void intel_connector_attach_encoder(struct intel_connector *connector,
1207 struct intel_encoder *encoder);
Paulo Zanoni87440422013-09-24 15:48:31 -03001208struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1209 struct drm_crtc *crtc);
Jesse Barnes752aa882013-10-31 18:55:49 +02001210enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001211int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1212 struct drm_file *file_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001213enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1214 enum pipe pipe);
Ville Syrjälä2d84d2b2016-06-22 21:57:02 +03001215static inline bool
1216intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1217 enum intel_output_type type)
1218{
1219 return crtc_state->output_types & (1 << type);
1220}
Ville Syrjälä37a56502016-06-22 21:57:04 +03001221static inline bool
1222intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1223{
1224 return crtc_state->output_types &
Ville Syrjäläcca05022016-06-22 21:57:06 +03001225 ((1 << INTEL_OUTPUT_DP) |
Ville Syrjälä37a56502016-06-22 21:57:04 +03001226 (1 << INTEL_OUTPUT_DP_MST) |
1227 (1 << INTEL_OUTPUT_EDP));
1228}
Daniel Vetter4f905cf92014-09-15 14:12:21 +02001229static inline void
1230intel_wait_for_vblank(struct drm_device *dev, int pipe)
1231{
1232 drm_wait_one_vblank(dev, pipe);
1233}
Ville Syrjälä0c241d52015-10-30 19:23:22 +02001234static inline void
1235intel_wait_for_vblank_if_active(struct drm_device *dev, int pipe)
1236{
1237 const struct intel_crtc *crtc =
1238 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
1239
1240 if (crtc->active)
1241 intel_wait_for_vblank(dev, pipe);
1242}
Maarten Lankhorsta2991412016-05-17 15:07:48 +02001243
1244u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1245
Paulo Zanoni87440422013-09-24 15:48:31 -03001246int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001247void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
Ville Syrjälä9b6de0a2015-04-10 18:21:31 +03001248 struct intel_digital_port *dport,
1249 unsigned int expected_mask);
Paulo Zanoni87440422013-09-24 15:48:31 -03001250bool intel_get_load_detect_pipe(struct drm_connector *connector,
1251 struct drm_display_mode *mode,
Rob Clark51fd3712013-11-19 12:10:12 -05001252 struct intel_load_detect_pipe *old,
1253 struct drm_modeset_acquire_ctx *ctx);
Paulo Zanoni87440422013-09-24 15:48:31 -03001254void intel_release_load_detect_pipe(struct drm_connector *connector,
Ander Conselvan de Oliveira49172fe2015-03-20 16:18:02 +02001255 struct intel_load_detect_pipe *old,
1256 struct drm_modeset_acquire_ctx *ctx);
Chris Wilson058d88c2016-08-15 10:49:06 +01001257struct i915_vma *
1258intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
Chris Wilsonfb4b8ce2016-04-28 09:56:35 +01001259void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
Daniel Vettera8bb6812014-02-10 18:00:39 +01001260struct drm_framebuffer *
1261__intel_framebuffer_create(struct drm_device *dev,
Paulo Zanoni87440422013-09-24 15:48:31 -03001262 struct drm_mode_fb_cmd2 *mode_cmd,
1263 struct drm_i915_gem_object *obj);
Daniel Vetter5a21b662016-05-24 17:13:53 +02001264void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe);
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +02001265void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe);
Daniel Vetter5a21b662016-05-24 17:13:53 +02001266void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe);
Matt Roper6beb8c232014-12-01 15:40:14 -08001267int intel_prepare_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +00001268 const struct drm_plane_state *new_state);
Matt Roper38f3ce32014-12-02 07:45:25 -08001269void intel_cleanup_plane_fb(struct drm_plane *plane,
Tvrtko Ursulind136dfe2015-03-03 14:22:31 +00001270 const struct drm_plane_state *old_state);
Matt Ropera98b3432015-01-21 16:35:43 -08001271int intel_plane_atomic_get_property(struct drm_plane *plane,
1272 const struct drm_plane_state *state,
1273 struct drm_property *property,
1274 uint64_t *val);
1275int intel_plane_atomic_set_property(struct drm_plane *plane,
1276 struct drm_plane_state *state,
1277 struct drm_property *property,
1278 uint64_t val);
Maarten Lankhorstda20eab2015-06-15 12:33:44 +02001279int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1280 struct drm_plane_state *plane_state);
Daniel Vetter716c2e52014-06-25 22:02:02 +03001281
Ville Syrjälä832be822016-01-12 21:08:33 +02001282unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
1283 uint64_t fb_modifier, unsigned int cpp);
Tvrtko Ursulin50470bb2015-03-23 11:10:36 +00001284
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00001285static inline bool
1286intel_rotation_90_or_270(unsigned int rotation)
1287{
Joonas Lahtinen31ad61e2016-07-29 08:50:05 +03001288 return rotation & (DRM_ROTATE_90 | DRM_ROTATE_270);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00001289}
1290
Sonika Jindal3b7a5112015-04-10 14:37:29 +05301291void intel_create_rotation_property(struct drm_device *dev,
1292 struct intel_plane *plane);
1293
Ander Conselvan de Oliveira7abd4b32016-03-08 17:46:15 +02001294void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe);
1296
Tvrtko Ursulin3f36b932016-01-19 15:25:17 +00001297int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
1298 const struct dpll *dpll);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001299void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe);
Ville Syrjälä8802e5b2016-02-17 21:41:12 +02001300int lpt_get_iclkip(struct drm_i915_private *dev_priv);
Ville Syrjäläd288f652014-10-28 13:20:22 +02001301
Daniel Vetter716c2e52014-06-25 22:02:02 +03001302/* modesetting asserts */
Daniel Vetterb680c372014-09-19 18:27:27 +02001303void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1304 enum pipe pipe);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001305void assert_pll(struct drm_i915_private *dev_priv,
1306 enum pipe pipe, bool state);
1307#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1308#define assert_pll_disabled(d, p) assert_pll(d, p, false)
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +00001309void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1310#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1311#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001312void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1313 enum pipe pipe, bool state);
1314#define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1315#define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
Paulo Zanoni87440422013-09-24 15:48:31 -03001316void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001317#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1318#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
Ville Syrjälä4f2d9932016-02-15 22:54:44 +02001319u32 intel_compute_tile_offset(int *x, int *y,
Ville Syrjälä29490562016-01-20 18:02:50 +02001320 const struct intel_plane_state *state, int plane);
Chris Wilsonc0336662016-05-06 15:40:21 +01001321void intel_prepare_reset(struct drm_i915_private *dev_priv);
1322void intel_finish_reset(struct drm_i915_private *dev_priv);
Paulo Zanonia14cb6f2014-03-07 20:08:17 -03001323void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1324void hsw_disable_pc8(struct drm_i915_private *dev_priv);
Imre Deak324513c2016-06-13 16:44:36 +03001325void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1326void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
Imre Deak9c8d0b82016-06-13 16:44:34 +03001327void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1328void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
1329bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1330 enum dpio_phy phy);
1331bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1332 enum dpio_phy phy);
Imre Deakda2f41d2016-04-20 20:27:56 +03001333void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
A.Sunil Kamath664326f2014-11-24 13:37:44 +05301334void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1335void bxt_disable_dc9(struct drm_i915_private *dev_priv);
Imre Deakf62c79b2016-04-20 20:27:57 +03001336void gen9_enable_dc5(struct drm_i915_private *dev_priv);
Damien Lespiau5d96d8a2015-05-21 16:37:48 +01001337void skl_init_cdclk(struct drm_i915_private *dev_priv);
1338void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
Clint Taylorc89e39f2016-05-13 23:41:21 +03001339unsigned int skl_cdclk_get_vco(unsigned int freq);
Animesh Manna0a9d2be2015-09-29 11:01:59 +05301340void skl_enable_dc6(struct drm_i915_private *dev_priv);
1341void skl_disable_dc6(struct drm_i915_private *dev_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001342void intel_dp_get_m_n(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001343 struct intel_crtc_state *pipe_config);
Ramalingam Cfe3cd482015-02-13 15:32:59 +05301344void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
Paulo Zanoni87440422013-09-24 15:48:31 -03001345int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
Imre Deak5ab7b0b2015-03-06 03:29:25 +02001346bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
Ander Conselvan de Oliveira9e2c8472016-05-04 12:11:57 +03001347 struct dpll *best_clock);
1348int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
Imre Deakdccbea32015-06-22 23:35:51 +03001349
Paulo Zanoni87440422013-09-24 15:48:31 -03001350bool intel_crtc_active(struct drm_crtc *crtc);
Ville Syrjälä20bc86732013-10-01 18:02:17 +03001351void hsw_enable_ips(struct intel_crtc *crtc);
1352void hsw_disable_ips(struct intel_crtc *crtc);
Imre Deak319be8a2014-03-04 19:22:57 +02001353enum intel_display_power_domain
1354intel_display_port_power_domain(struct intel_encoder *intel_encoder);
Ville Syrjälä25f78f52015-11-16 15:01:04 +01001355enum intel_display_power_domain
1356intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder);
Daniel Vetterf6a83282014-02-11 15:28:57 -08001357void intel_mode_from_pipe_config(struct drm_display_mode *mode,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001358 struct intel_crtc_state *pipe_config);
Maarten Lankhorst86adf9d2015-06-22 09:50:32 +02001359
Maarten Lankhorste435d6e2015-07-13 16:30:15 +02001360int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
Chandra Konduru6156a452015-04-27 13:48:39 -07001361int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001362
Ville Syrjälä6687c902015-09-15 13:16:41 +03001363u32 intel_fb_gtt_offset(struct drm_framebuffer *fb, unsigned int rotation);
Tvrtko Ursulindedf2782015-09-21 10:45:35 +01001364
Chandra Konduru6156a452015-04-27 13:48:39 -07001365u32 skl_plane_ctl_format(uint32_t pixel_format);
1366u32 skl_plane_ctl_tiling(uint64_t fb_modifier);
1367u32 skl_plane_ctl_rotation(unsigned int rotation);
Ville Syrjäläd2196772016-01-28 18:33:11 +02001368u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1369 unsigned int rotation);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +02001370int skl_check_plane_surface(struct intel_plane_state *plane_state);
Tvrtko Ursulin121920f2015-03-23 11:10:37 +00001371
Daniel Vettereb805622015-05-04 14:58:44 +02001372/* intel_csr.c */
Daniel Vetterf4448372015-10-28 23:59:02 +02001373void intel_csr_ucode_init(struct drm_i915_private *);
Imre Deak2abc5252016-03-04 21:57:41 +02001374void intel_csr_load_program(struct drm_i915_private *);
Daniel Vetterf4448372015-10-28 23:59:02 +02001375void intel_csr_ucode_fini(struct drm_i915_private *);
Imre Deakf74ed082016-04-18 14:48:21 +03001376void intel_csr_ucode_suspend(struct drm_i915_private *);
1377void intel_csr_ucode_resume(struct drm_i915_private *);
Daniel Vettereb805622015-05-04 14:58:44 +02001378
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001379/* intel_dp.c */
Chris Wilson457c52d2016-06-01 08:27:50 +01001380bool intel_dp_init(struct drm_device *dev, i915_reg_t output_reg, enum port port);
Paulo Zanoni87440422013-09-24 15:48:31 -03001381bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1382 struct intel_connector *intel_connector);
Ville Syrjälä901c2da2015-08-17 18:05:12 +03001383void intel_dp_set_link_params(struct intel_dp *intel_dp,
1384 const struct intel_crtc_state *pipe_config);
Paulo Zanoni87440422013-09-24 15:48:31 -03001385void intel_dp_start_link_train(struct intel_dp *intel_dp);
Paulo Zanoni87440422013-09-24 15:48:31 -03001386void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1387void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
Imre Deakbf93ba62016-04-18 10:04:21 +03001388void intel_dp_encoder_reset(struct drm_encoder *encoder);
1389void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
Paulo Zanoni87440422013-09-24 15:48:31 -03001390void intel_dp_encoder_destroy(struct drm_encoder *encoder);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02001391int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
Paulo Zanoni87440422013-09-24 15:48:31 -03001392bool intel_dp_compute_config(struct intel_encoder *encoder,
Maarten Lankhorst0a478c22016-08-09 17:04:05 +02001393 struct intel_crtc_state *pipe_config,
1394 struct drm_connector_state *conn_state);
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02001395bool intel_dp_is_edp(struct drm_device *dev, enum port port);
Daniel Vetterb2c5c182015-01-23 06:00:31 +01001396enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1397 bool long_hpd);
Daniel Vetter4be73782014-01-17 14:39:48 +01001398void intel_edp_backlight_on(struct intel_dp *intel_dp);
1399void intel_edp_backlight_off(struct intel_dp *intel_dp);
Jani Nikula24f3e092014-03-17 16:43:36 +02001400void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001401void intel_edp_panel_on(struct intel_dp *intel_dp);
1402void intel_edp_panel_off(struct intel_dp *intel_dp);
Dave Airlie0e32b392014-05-02 14:02:48 +10001403void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
1404void intel_dp_mst_suspend(struct drm_device *dev);
1405void intel_dp_mst_resume(struct drm_device *dev);
Ville Syrjälä50fec212015-03-12 17:10:34 +02001406int intel_dp_max_link_rate(struct intel_dp *intel_dp);
Ville Syrjäläed4e9c12015-03-12 17:10:36 +02001407int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
Dave Airlie0e32b392014-05-02 14:02:48 +10001408void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
Imre Deak78597992016-06-16 16:37:20 +03001409void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001410uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
Matt Roper4a3b8762014-12-23 10:41:51 -08001411void intel_plane_destroy(struct drm_plane *plane);
Maarten Lankhorst85cb48a2016-08-09 17:04:13 +02001412void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1413 struct intel_crtc_state *crtc_state);
1414void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1415 struct intel_crtc_state *crtc_state);
Chris Wilson5748b6a2016-08-04 16:32:38 +01001416void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1417 unsigned int frontbuffer_bits);
1418void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1419 unsigned int frontbuffer_bits);
Sonika Jindal237ed862015-09-15 09:44:20 +05301420bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
Chris Wilson5748b6a2016-08-04 16:32:38 +01001421 struct intel_digital_port *port);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001422
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03001423void
1424intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1425 uint8_t dp_train_pat);
1426void
1427intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1428void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1429uint8_t
1430intel_dp_voltage_max(struct intel_dp *intel_dp);
1431uint8_t
1432intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1433void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1434 uint8_t *link_bw, uint8_t *rate_select);
Ander Conselvan de Oliveirae588fa12015-10-23 13:01:50 +03001435bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
Ander Conselvan de Oliveira94223d02015-10-23 13:01:48 +03001436bool
1437intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1438
Ander Conselvan de Oliveira419b1b72016-04-27 15:44:19 +03001439static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1440{
1441 return ~((1 << lane_count) - 1) & 0xf;
1442}
1443
Yetunde Adebisie7156c82016-04-05 15:10:52 +01001444/* intel_dp_aux_backlight.c */
1445int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1446
Dave Airlie0e32b392014-05-02 14:02:48 +10001447/* intel_dp_mst.c */
1448int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1449void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001450/* intel_dsi.c */
Damien Lespiau4328633d2014-05-28 12:30:56 +01001451void intel_dsi_init(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001452
Jani Nikula90198352016-04-26 16:14:25 +03001453/* intel_dsi_dcs_backlight.c */
1454int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001455
1456/* intel_dvo.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001457void intel_dvo_init(struct drm_device *dev);
Lyude19625e82016-06-21 17:03:44 -04001458/* intel_hotplug.c */
1459void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001460
1461
Daniel Vetter0632fef2013-10-08 17:44:49 +02001462/* legacy fbdev emulation in intel_fbdev.c */
Daniel Vetter06957262015-08-10 13:34:08 +02001463#ifdef CONFIG_DRM_FBDEV_EMULATION
Daniel Vetter4520f532013-10-09 09:18:51 +02001464extern int intel_fbdev_init(struct drm_device *dev);
Ville Syrjäläe00bf692015-11-06 15:08:33 +02001465extern void intel_fbdev_initial_config_async(struct drm_device *dev);
Daniel Vetter4520f532013-10-09 09:18:51 +02001466extern void intel_fbdev_fini(struct drm_device *dev);
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001467extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
Daniel Vetter0632fef2013-10-08 17:44:49 +02001468extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1469extern void intel_fbdev_restore_mode(struct drm_device *dev);
Daniel Vetter4520f532013-10-09 09:18:51 +02001470#else
1471static inline int intel_fbdev_init(struct drm_device *dev)
1472{
1473 return 0;
1474}
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001475
Ville Syrjäläe00bf692015-11-06 15:08:33 +02001476static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +02001477{
1478}
1479
1480static inline void intel_fbdev_fini(struct drm_device *dev)
1481{
1482}
1483
Chris Wilson82e3b8c2014-08-13 13:09:46 +01001484static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
Daniel Vetter4520f532013-10-09 09:18:51 +02001485{
1486}
1487
Daniel Vetter0632fef2013-10-08 17:44:49 +02001488static inline void intel_fbdev_restore_mode(struct drm_device *dev)
Daniel Vetter4520f532013-10-09 09:18:51 +02001489{
1490}
1491#endif
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001492
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001493/* intel_fbc.c */
Paulo Zanonif51be2e2016-01-19 11:35:50 -02001494void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1495 struct drm_atomic_state *state);
Paulo Zanoni0e631ad2015-10-14 17:45:36 -03001496bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001497void intel_fbc_pre_update(struct intel_crtc *crtc,
1498 struct intel_crtc_state *crtc_state,
1499 struct intel_plane_state *plane_state);
Paulo Zanoni1eb52232016-01-19 11:35:44 -02001500void intel_fbc_post_update(struct intel_crtc *crtc);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001501void intel_fbc_init(struct drm_i915_private *dev_priv);
Paulo Zanoni010cf732016-01-19 11:35:48 -02001502void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
Maarten Lankhorstfaf68d92016-06-14 14:24:20 +02001503void intel_fbc_enable(struct intel_crtc *crtc,
1504 struct intel_crtc_state *crtc_state,
1505 struct intel_plane_state *plane_state);
Paulo Zanonic937ab3e52016-01-19 11:35:46 -02001506void intel_fbc_disable(struct intel_crtc *crtc);
1507void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
Paulo Zanonidbef0f12015-02-13 17:23:46 -02001508void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1509 unsigned int frontbuffer_bits,
1510 enum fb_op_origin origin);
1511void intel_fbc_flush(struct drm_i915_private *dev_priv,
Paulo Zanoni6f4551f2015-07-14 16:29:10 -03001512 unsigned int frontbuffer_bits, enum fb_op_origin origin);
Paulo Zanoni7733b492015-07-07 15:26:04 -03001513void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
Rodrigo Vivi7ff0ebc2014-12-08 14:09:10 -02001514
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001515/* intel_hdmi.c */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001516void intel_hdmi_init(struct drm_device *dev, i915_reg_t hdmi_reg, enum port port);
Paulo Zanoni87440422013-09-24 15:48:31 -03001517void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1518 struct intel_connector *intel_connector);
1519struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1520bool intel_hdmi_compute_config(struct intel_encoder *encoder,
Maarten Lankhorst0a478c22016-08-09 17:04:05 +02001521 struct intel_crtc_state *pipe_config,
1522 struct drm_connector_state *conn_state);
Ville Syrjäläb2ccb822016-05-02 22:08:24 +03001523void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001524
1525
1526/* intel_lvds.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001527void intel_lvds_init(struct drm_device *dev);
Imre Deak97a824e12016-06-21 11:51:47 +03001528struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001529bool intel_is_dual_link_lvds(struct drm_device *dev);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001530
1531
1532/* intel_modes.c */
1533int intel_connector_update_modes(struct drm_connector *connector,
Paulo Zanoni87440422013-09-24 15:48:31 -03001534 struct edid *edid);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001535int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
Paulo Zanoni87440422013-09-24 15:48:31 -03001536void intel_attach_force_audio_property(struct drm_connector *connector);
1537void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
Ville Syrjälä7949dd42015-09-25 16:39:30 +03001538void intel_attach_aspect_ratio_property(struct drm_connector *connector);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001539
1540
1541/* intel_overlay.c */
Chris Wilson1ee8da62016-05-12 12:43:23 +01001542void intel_setup_overlay(struct drm_i915_private *dev_priv);
1543void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
Paulo Zanoni87440422013-09-24 15:48:31 -03001544int intel_overlay_switch_off(struct intel_overlay *overlay);
Chris Wilson1ee8da62016-05-12 12:43:23 +01001545int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1546 struct drm_file *file_priv);
1547int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1548 struct drm_file *file_priv);
Ville Syrjälä1362b772014-11-26 17:07:29 +02001549void intel_overlay_reset(struct drm_i915_private *dev_priv);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001550
1551
1552/* intel_panel.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001553int intel_panel_init(struct intel_panel *panel,
Vandana Kannan4b6ed682014-02-11 14:26:36 +05301554 struct drm_display_mode *fixed_mode,
1555 struct drm_display_mode *downclock_mode);
Paulo Zanoni87440422013-09-24 15:48:31 -03001556void intel_panel_fini(struct intel_panel *panel);
1557void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1558 struct drm_display_mode *adjusted_mode);
1559void intel_pch_panel_fitting(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001560 struct intel_crtc_state *pipe_config,
Paulo Zanoni87440422013-09-24 15:48:31 -03001561 int fitting_mode);
1562void intel_gmch_panel_fitting(struct intel_crtc *crtc,
Ander Conselvan de Oliveira5cec2582015-01-15 14:55:21 +02001563 struct intel_crtc_state *pipe_config,
Paulo Zanoni87440422013-09-24 15:48:31 -03001564 int fitting_mode);
Jani Nikula6dda7302014-06-24 18:27:40 +03001565void intel_panel_set_backlight_acpi(struct intel_connector *connector,
1566 u32 level, u32 max);
Chris Wilsonfda9ee92016-06-24 14:00:13 +01001567int intel_panel_setup_backlight(struct drm_connector *connector,
1568 enum pipe pipe);
Jesse Barnes752aa882013-10-31 18:55:49 +02001569void intel_panel_enable_backlight(struct intel_connector *connector);
1570void intel_panel_disable_backlight(struct intel_connector *connector);
Jani Nikuladb31af12013-11-08 16:48:53 +02001571void intel_panel_destroy_backlight(struct drm_connector *connector);
Paulo Zanoni87440422013-09-24 15:48:31 -03001572enum drm_connector_status intel_panel_detect(struct drm_device *dev);
Vandana Kannanec9ed192013-12-10 13:37:36 +05301573extern struct drm_display_mode *intel_find_panel_downclock(
1574 struct drm_device *dev,
1575 struct drm_display_mode *fixed_mode,
1576 struct drm_connector *connector);
Chris Wilsone63d87c2016-06-17 11:40:34 +01001577
1578#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
Chris Wilson1ebaa0b2016-06-24 14:00:15 +01001579int intel_backlight_device_register(struct intel_connector *connector);
Chris Wilsone63d87c2016-06-17 11:40:34 +01001580void intel_backlight_device_unregister(struct intel_connector *connector);
1581#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
Chris Wilson1ebaa0b2016-06-24 14:00:15 +01001582static int intel_backlight_device_register(struct intel_connector *connector)
1583{
1584 return 0;
1585}
Chris Wilsone63d87c2016-06-17 11:40:34 +01001586static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1587{
1588}
1589#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
Ville Syrjälä0962c3c2014-11-07 15:19:46 +02001590
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001591
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001592/* intel_psr.c */
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001593void intel_psr_enable(struct intel_dp *intel_dp);
1594void intel_psr_disable(struct intel_dp *intel_dp);
Chris Wilson5748b6a2016-08-04 16:32:38 +01001595void intel_psr_invalidate(struct drm_i915_private *dev_priv,
Daniel Vetter20c88382015-06-18 10:30:27 +02001596 unsigned frontbuffer_bits);
Chris Wilson5748b6a2016-08-04 16:32:38 +01001597void intel_psr_flush(struct drm_i915_private *dev_priv,
Rodrigo Vivi169de132015-07-08 16:21:31 -07001598 unsigned frontbuffer_bits,
1599 enum fb_op_origin origin);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001600void intel_psr_init(struct drm_device *dev);
Chris Wilson5748b6a2016-08-04 16:32:38 +01001601void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
Daniel Vetter20c88382015-06-18 10:30:27 +02001602 unsigned frontbuffer_bits);
Rodrigo Vivi0bc12bc2014-11-14 08:52:28 -08001603
Daniel Vetter9c065a72014-09-30 10:56:38 +02001604/* intel_runtime_pm.c */
1605int intel_power_domains_init(struct drm_i915_private *);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001606void intel_power_domains_fini(struct drm_i915_private *);
Imre Deak73dfc222015-11-17 17:33:53 +02001607void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1608void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
Imre Deakd7d7c9e2016-04-01 16:02:42 +03001609void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1610void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001611void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
Daniel Stone9895ad02015-11-20 15:55:33 +00001612const char *
1613intel_display_power_domain_str(enum intel_display_power_domain domain);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001614
Daniel Vetterf458ebb2014-09-30 10:56:39 +02001615bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1616 enum intel_display_power_domain domain);
1617bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1618 enum intel_display_power_domain domain);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001619void intel_display_power_get(struct drm_i915_private *dev_priv,
1620 enum intel_display_power_domain domain);
Imre Deak09731282016-02-17 14:17:42 +02001621bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1622 enum intel_display_power_domain domain);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001623void intel_display_power_put(struct drm_i915_private *dev_priv,
1624 enum intel_display_power_domain domain);
Imre Deakda5827c2015-12-15 20:10:33 +02001625
1626static inline void
1627assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1628{
1629 WARN_ONCE(dev_priv->pm.suspended,
1630 "Device suspended during HW access\n");
1631}
1632
1633static inline void
1634assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1635{
1636 assert_rpm_device_not_suspended(dev_priv);
Daniel Vetterbecd9ca2016-01-05 17:54:07 +01001637 /* FIXME: Needs to be converted back to WARN_ONCE, but currently causes
1638 * too much noise. */
1639 if (!atomic_read(&dev_priv->pm.wakeref_count))
1640 DRM_DEBUG_DRIVER("RPM wakelock ref not held during HW access");
Imre Deakda5827c2015-12-15 20:10:33 +02001641}
1642
Imre Deak2b19efe2015-12-15 20:10:37 +02001643static inline int
1644assert_rpm_atomic_begin(struct drm_i915_private *dev_priv)
1645{
1646 int seq = atomic_read(&dev_priv->pm.atomic_seq);
1647
1648 assert_rpm_wakelock_held(dev_priv);
1649
1650 return seq;
1651}
1652
1653static inline void
1654assert_rpm_atomic_end(struct drm_i915_private *dev_priv, int begin_seq)
1655{
1656 WARN_ONCE(atomic_read(&dev_priv->pm.atomic_seq) != begin_seq,
1657 "HW access outside of RPM atomic section\n");
1658}
1659
Imre Deak1f814da2015-12-16 02:52:19 +02001660/**
1661 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1662 * @dev_priv: i915 device instance
1663 *
1664 * This function disable asserts that check if we hold an RPM wakelock
1665 * reference, while keeping the device-not-suspended checks still enabled.
1666 * It's meant to be used only in special circumstances where our rule about
1667 * the wakelock refcount wrt. the device power state doesn't hold. According
1668 * to this rule at any point where we access the HW or want to keep the HW in
1669 * an active state we must hold an RPM wakelock reference acquired via one of
1670 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1671 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1672 * forcewake release timer, and the GPU RPS and hangcheck works. All other
1673 * users should avoid using this function.
1674 *
1675 * Any calls to this function must have a symmetric call to
1676 * enable_rpm_wakeref_asserts().
1677 */
1678static inline void
1679disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1680{
1681 atomic_inc(&dev_priv->pm.wakeref_count);
1682}
1683
1684/**
1685 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1686 * @dev_priv: i915 device instance
1687 *
1688 * This function re-enables the RPM assert checks after disabling them with
1689 * disable_rpm_wakeref_asserts. It's meant to be used only in special
1690 * circumstances otherwise its use should be avoided.
1691 *
1692 * Any calls to this function must have a symmetric call to
1693 * disable_rpm_wakeref_asserts().
1694 */
1695static inline void
1696enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1697{
1698 atomic_dec(&dev_priv->pm.wakeref_count);
1699}
1700
Daniel Vetter9c065a72014-09-30 10:56:38 +02001701void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
Imre Deak09731282016-02-17 14:17:42 +02001702bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
Daniel Vetter9c065a72014-09-30 10:56:38 +02001703void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1704void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1705
Daniel Vetterd9bc89d92014-09-30 10:56:40 +02001706void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1707
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001708void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1709 bool override, unsigned int mask);
Ville Syrjäläb0b33842015-07-08 23:45:55 +03001710bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1711 enum dpio_channel ch, bool override);
Ville Syrjäläe0fce782015-07-08 23:45:54 +03001712
1713
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001714/* intel_pm.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001715void intel_init_clock_gating(struct drm_device *dev);
1716void intel_suspend_hw(struct drm_device *dev);
Damien Lespiau546c81f2014-05-13 15:30:26 +01001717int ilk_wm_max_level(const struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001718void intel_update_watermarks(struct drm_crtc *crtc);
Paulo Zanoni87440422013-09-24 15:48:31 -03001719void intel_init_pm(struct drm_device *dev);
Imre Deakbb400da2016-03-16 13:38:54 +02001720void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
Daniel Vetterf742a552013-12-06 10:17:53 +01001721void intel_pm_setup(struct drm_device *dev);
Paulo Zanoni87440422013-09-24 15:48:31 -03001722void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1723void intel_gpu_ips_teardown(void);
Chris Wilsondc979972016-05-10 14:10:04 +01001724void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
Chris Wilsonb12e0ee2016-07-21 18:28:30 +01001725void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
Chris Wilson54b4f682016-07-21 21:16:19 +01001726void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1727void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1728void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1729void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1730void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001731void gen6_rps_busy(struct drm_i915_private *dev_priv);
1732void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
Daniel Vetter076e29f2013-10-08 19:39:29 +02001733void gen6_rps_idle(struct drm_i915_private *dev_priv);
Chris Wilson1854d5c2015-04-07 16:20:32 +01001734void gen6_rps_boost(struct drm_i915_private *dev_priv,
Chris Wilsone61b9952015-04-27 13:41:24 +01001735 struct intel_rps_client *rps,
1736 unsigned long submitted);
Tvrtko Ursulin91d14252016-05-06 14:48:28 +01001737void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
Ville Syrjälä6eb1a682015-06-24 22:00:03 +03001738void vlv_wm_get_hw_state(struct drm_device *dev);
Ville Syrjälä243e6a42013-10-14 14:55:24 +03001739void ilk_wm_get_hw_state(struct drm_device *dev);
Pradeep Bhat30789992014-11-04 17:06:45 +00001740void skl_wm_get_hw_state(struct drm_device *dev);
Damien Lespiau08db6652014-11-04 17:06:52 +00001741void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1742 struct skl_ddb_allocation *ddb /* out */);
Lyude656d1b82016-08-17 15:55:54 -04001743bool skl_can_enable_sagv(struct drm_atomic_state *state);
1744int skl_enable_sagv(struct drm_i915_private *dev_priv);
1745int skl_disable_sagv(struct drm_i915_private *dev_priv);
Lyude62e0fb82016-08-22 12:50:08 -04001746void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
1747 const struct skl_wm_values *wm);
1748void skl_write_plane_wm(struct intel_crtc *intel_crtc,
1749 const struct skl_wm_values *wm,
1750 int plane);
Ville Syrjälä8cfb3402015-06-03 15:45:11 +03001751uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config);
Matt Ropered4a6a72016-02-23 17:20:13 -08001752bool ilk_disable_lp_wm(struct drm_device *dev);
Chris Wilsondc979972016-05-10 14:10:04 +01001753int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1754static inline int intel_enable_rc6(void)
1755{
1756 return i915.enable_rc6;
1757}
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001758
1759/* intel_sdvo.c */
Ville Syrjäläf0f59a02015-11-18 15:33:26 +02001760bool intel_sdvo_init(struct drm_device *dev,
1761 i915_reg_t reg, enum port port);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001762
1763
1764/* intel_sprite.c */
Ville Syrjälädfd2e9a2016-05-18 11:34:38 +03001765int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1766 int usecs);
Paulo Zanoni87440422013-09-24 15:48:31 -03001767int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
Paulo Zanoni87440422013-09-24 15:48:31 -03001768int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1769 struct drm_file *file_priv);
Maarten Lankhorst34e0adb2015-08-31 13:04:25 +02001770void intel_pipe_update_start(struct intel_crtc *crtc);
Maarten Lankhorst51cbaf02016-05-17 15:07:49 +02001771void intel_pipe_update_end(struct intel_crtc *crtc, struct intel_flip_work *work);
Paulo Zanoni5f1aae62013-09-24 13:52:53 -03001772
1773/* intel_tv.c */
Paulo Zanoni87440422013-09-24 15:48:31 -03001774void intel_tv_init(struct drm_device *dev);
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001775
Matt Roperea2c67b2014-12-23 10:41:52 -08001776/* intel_atomic.c */
Matt Roper2545e4a2015-01-22 16:51:27 -08001777int intel_connector_atomic_get_property(struct drm_connector *connector,
1778 const struct drm_connector_state *state,
1779 struct drm_property *property,
1780 uint64_t *val);
Matt Roper13568372015-01-21 16:35:47 -08001781struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1782void intel_crtc_destroy_state(struct drm_crtc *crtc,
1783 struct drm_crtc_state *state);
Maarten Lankhorstde419ab2015-06-04 10:21:28 +02001784struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1785void intel_atomic_state_clear(struct drm_atomic_state *);
1786struct intel_shared_dpll_config *
1787intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s);
1788
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +02001789static inline struct intel_crtc_state *
1790intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1791 struct intel_crtc *crtc)
1792{
1793 struct drm_crtc_state *crtc_state;
1794 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1795 if (IS_ERR(crtc_state))
Fabian Frederick0b6cc182015-04-25 11:34:29 +02001796 return ERR_CAST(crtc_state);
Ander Conselvan de Oliveira10f81c12015-03-20 16:18:01 +02001797
1798 return to_intel_crtc_state(crtc_state);
1799}
Maarten Lankhorste3bddde2016-03-01 11:07:22 +01001800
1801static inline struct intel_plane_state *
1802intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1803 struct intel_plane *plane)
1804{
1805 struct drm_plane_state *plane_state;
1806
1807 plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1808
1809 return to_intel_plane_state(plane_state);
1810}
1811
Chandra Kondurud03c93d2015-04-09 16:42:46 -07001812int intel_atomic_setup_scalers(struct drm_device *dev,
1813 struct intel_crtc *intel_crtc,
1814 struct intel_crtc_state *crtc_state);
Matt Roper5ee67f12015-01-21 16:35:44 -08001815
1816/* intel_atomic_plane.c */
Matt Roper8e7d6882015-01-21 16:35:41 -08001817struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
Matt Roperea2c67b2014-12-23 10:41:52 -08001818struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1819void intel_plane_destroy_state(struct drm_plane *plane,
1820 struct drm_plane_state *state);
1821extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1822
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +00001823/* intel_color.c */
1824void intel_color_init(struct drm_crtc *crtc);
Lionel Landwerlin82cf4352016-03-16 10:57:16 +00001825int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
Maarten Lankhorstb95c5322016-03-30 17:16:34 +02001826void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1827void intel_color_load_luts(struct drm_crtc_state *crtc_state);
Lionel Landwerlin8563b1e2016-03-16 10:57:14 +00001828
Jesse Barnes79e53942008-11-07 14:24:08 -08001829#endif /* __INTEL_DRV_H__ */