blob: 1d41058bbab2a4227dc663f388e3e026e1ce84b3 [file] [log] [blame]
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001/*
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08002 * Blackfin On-Chip SPI Driver
Wu, Bryana5f6abd2007-05-06 14:50:34 -07003 *
Bryan Wu131b17d2007-12-04 23:45:12 -08004 * Copyright 2004-2007 Analog Devices Inc.
Wu, Bryana5f6abd2007-05-06 14:50:34 -07005 *
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08006 * Enter bugs at http://blackfin.uclinux.org/
Wu, Bryana5f6abd2007-05-06 14:50:34 -07007 *
Mike Frysinger26fdc1f2008-02-06 01:38:21 -08008 * Licensed under the GPL-2 or later.
Wu, Bryana5f6abd2007-05-06 14:50:34 -07009 */
10
11#include <linux/init.h>
12#include <linux/module.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080013#include <linux/delay.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070014#include <linux/device.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080015#include <linux/io.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070016#include <linux/ioport.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080017#include <linux/irq.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070018#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070024
Wu, Bryana5f6abd2007-05-06 14:50:34 -070025#include <asm/dma.h>
Bryan Wu131b17d2007-12-04 23:45:12 -080026#include <asm/portmux.h>
Wu, Bryana5f6abd2007-05-06 14:50:34 -070027#include <asm/bfin5xx_spi.h>
Vitja Makarov8cf58582009-04-06 19:00:31 -070028#include <asm/cacheflush.h>
29
Bryan Wua32c6912007-12-04 23:45:15 -080030#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
Mike Frysinger138f97c2009-04-06 19:00:50 -070032#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
Bryan Wua32c6912007-12-04 23:45:15 -080033#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
Wu, Bryana5f6abd2007-05-06 14:50:34 -070037MODULE_LICENSE("GPL");
38
Bryan Wubb90eb02007-12-04 23:45:18 -080039#define START_STATE ((void *)0)
40#define RUNNING_STATE ((void *)1)
41#define DONE_STATE ((void *)2)
42#define ERROR_STATE ((void *)-1)
43#define QUEUE_RUNNING 0
44#define QUEUE_STOPPED 1
Wu, Bryana5f6abd2007-05-06 14:50:34 -070045
Wolfgang Muees93b61bd2009-04-06 19:00:53 -070046/* Value to send if no TX value is supplied */
47#define SPI_IDLE_TXVAL 0x0000
48
Wu, Bryana5f6abd2007-05-06 14:50:34 -070049struct driver_data {
50 /* Driver model hookup */
51 struct platform_device *pdev;
52
53 /* SPI framework hookup */
54 struct spi_master *master;
55
Bryan Wubb90eb02007-12-04 23:45:18 -080056 /* Regs base of SPI controller */
Bryan Wuf4521262007-12-04 23:45:22 -080057 void __iomem *regs_base;
Bryan Wubb90eb02007-12-04 23:45:18 -080058
Bryan Wu003d9222007-12-04 23:45:22 -080059 /* Pin request list */
60 u16 *pin_req;
61
Wu, Bryana5f6abd2007-05-06 14:50:34 -070062 /* BFIN hookup */
63 struct bfin5xx_spi_master *master_info;
64
65 /* Driver message queue */
66 struct workqueue_struct *workqueue;
67 struct work_struct pump_messages;
68 spinlock_t lock;
69 struct list_head queue;
70 int busy;
71 int run;
72
73 /* Message Transfer pump */
74 struct tasklet_struct pump_transfers;
75
76 /* Current message transfer state info */
77 struct spi_message *cur_msg;
78 struct spi_transfer *cur_transfer;
79 struct chip_data *cur_chip;
80 size_t len_in_bytes;
81 size_t len;
82 void *tx;
83 void *tx_end;
84 void *rx;
85 void *rx_end;
Bryan Wubb90eb02007-12-04 23:45:18 -080086
87 /* DMA stuffs */
88 int dma_channel;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070089 int dma_mapped;
Bryan Wubb90eb02007-12-04 23:45:18 -080090 int dma_requested;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070091 dma_addr_t rx_dma;
92 dma_addr_t tx_dma;
Bryan Wubb90eb02007-12-04 23:45:18 -080093
Wu, Bryana5f6abd2007-05-06 14:50:34 -070094 size_t rx_map_len;
95 size_t tx_map_len;
96 u8 n_bytes;
Bryan Wufad91c82007-12-04 23:45:14 -080097 int cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -070098 void (*write) (struct driver_data *);
99 void (*read) (struct driver_data *);
100 void (*duplex) (struct driver_data *);
101};
102
103struct chip_data {
104 u16 ctl_reg;
105 u16 baud;
106 u16 flag;
107
108 u8 chip_select_num;
109 u8 n_bytes;
Bryan Wu88b40362007-05-21 18:32:16 +0800110 u8 width; /* 0 or 1 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700111 u8 enable_dma;
112 u8 bits_per_word; /* 8 or 16 */
113 u8 cs_change_per_word;
Bryan Wu62310e52007-12-04 23:45:20 -0800114 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
Michael Hennerich42c78b22009-04-06 19:00:51 -0700115 u32 cs_gpio;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700116 u16 idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700117 void (*write) (struct driver_data *);
118 void (*read) (struct driver_data *);
119 void (*duplex) (struct driver_data *);
120};
121
Bryan Wubb90eb02007-12-04 23:45:18 -0800122#define DEFINE_SPI_REG(reg, off) \
123static inline u16 read_##reg(struct driver_data *drv_data) \
124 { return bfin_read16(drv_data->regs_base + off); } \
125static inline void write_##reg(struct driver_data *drv_data, u16 v) \
126 { bfin_write16(drv_data->regs_base + off, v); }
127
128DEFINE_SPI_REG(CTRL, 0x00)
129DEFINE_SPI_REG(FLAG, 0x04)
130DEFINE_SPI_REG(STAT, 0x08)
131DEFINE_SPI_REG(TDBR, 0x0C)
132DEFINE_SPI_REG(RDBR, 0x10)
133DEFINE_SPI_REG(BAUD, 0x14)
134DEFINE_SPI_REG(SHAW, 0x18)
135
Bryan Wu88b40362007-05-21 18:32:16 +0800136static void bfin_spi_enable(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700137{
138 u16 cr;
139
Bryan Wubb90eb02007-12-04 23:45:18 -0800140 cr = read_CTRL(drv_data);
141 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700142}
143
Bryan Wu88b40362007-05-21 18:32:16 +0800144static void bfin_spi_disable(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700145{
146 u16 cr;
147
Bryan Wubb90eb02007-12-04 23:45:18 -0800148 cr = read_CTRL(drv_data);
149 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700150}
151
152/* Caculate the SPI_BAUD register value based on input HZ */
153static u16 hz_to_spi_baud(u32 speed_hz)
154{
155 u_long sclk = get_sclk();
156 u16 spi_baud = (sclk / (2 * speed_hz));
157
158 if ((sclk % (2 * speed_hz)) > 0)
159 spi_baud++;
160
Michael Hennerich7513e002009-04-06 19:00:32 -0700161 if (spi_baud < MIN_SPI_BAUD_VAL)
162 spi_baud = MIN_SPI_BAUD_VAL;
163
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700164 return spi_baud;
165}
166
Mike Frysinger138f97c2009-04-06 19:00:50 -0700167static int bfin_spi_flush(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700168{
169 unsigned long limit = loops_per_jiffy << 1;
170
171 /* wait for stop and clear stat */
Roel Kluinb4bd2ab2009-06-17 16:26:02 -0700172 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
Bryan Wud8c05002007-12-04 23:45:21 -0800173 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700174
Bryan Wubb90eb02007-12-04 23:45:18 -0800175 write_STAT(drv_data, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700176
177 return limit;
178}
179
Bryan Wufad91c82007-12-04 23:45:14 -0800180/* Chip select operation functions for cs_change flag */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700181static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800182{
Michael Hennerich42c78b22009-04-06 19:00:51 -0700183 if (likely(chip->chip_select_num)) {
184 u16 flag = read_FLAG(drv_data);
Bryan Wufad91c82007-12-04 23:45:14 -0800185
Michael Hennerich42c78b22009-04-06 19:00:51 -0700186 flag |= chip->flag;
187 flag &= ~(chip->flag << 8);
Bryan Wufad91c82007-12-04 23:45:14 -0800188
Michael Hennerich42c78b22009-04-06 19:00:51 -0700189 write_FLAG(drv_data, flag);
190 } else {
191 gpio_set_value(chip->cs_gpio, 0);
192 }
Bryan Wufad91c82007-12-04 23:45:14 -0800193}
194
Mike Frysinger138f97c2009-04-06 19:00:50 -0700195static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
Bryan Wufad91c82007-12-04 23:45:14 -0800196{
Michael Hennerich42c78b22009-04-06 19:00:51 -0700197 if (likely(chip->chip_select_num)) {
198 u16 flag = read_FLAG(drv_data);
Bryan Wufad91c82007-12-04 23:45:14 -0800199
Michael Hennerich42c78b22009-04-06 19:00:51 -0700200 flag &= ~chip->flag;
201 flag |= (chip->flag << 8);
Bryan Wufad91c82007-12-04 23:45:14 -0800202
Michael Hennerich42c78b22009-04-06 19:00:51 -0700203 write_FLAG(drv_data, flag);
204 } else {
205 gpio_set_value(chip->cs_gpio, 1);
206 }
Bryan Wu62310e52007-12-04 23:45:20 -0800207
208 /* Move delay here for consistency */
209 if (chip->cs_chg_udelay)
210 udelay(chip->cs_chg_udelay);
Bryan Wufad91c82007-12-04 23:45:14 -0800211}
212
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700213/* stop controller and re-config current chip*/
Mike Frysinger138f97c2009-04-06 19:00:50 -0700214static void bfin_spi_restore_state(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700215{
216 struct chip_data *chip = drv_data->cur_chip;
217
218 /* Clear status and disable clock */
Bryan Wubb90eb02007-12-04 23:45:18 -0800219 write_STAT(drv_data, BIT_STAT_CLR);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700220 bfin_spi_disable(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800221 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700222
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700223 /* Load the registers */
Bryan Wubb90eb02007-12-04 23:45:18 -0800224 write_CTRL(drv_data, chip->ctl_reg);
Bryan Wu092e1fd2007-12-04 23:45:23 -0800225 write_BAUD(drv_data, chip->baud);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800226
227 bfin_spi_enable(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700228 bfin_spi_cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700229}
230
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700231/* used to kick off transfer in rx mode and read unwanted RX data */
232static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700233{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700234 (void) read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700235}
236
Mike Frysinger138f97c2009-04-06 19:00:50 -0700237static void bfin_spi_null_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700238{
239 u8 n_bytes = drv_data->n_bytes;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700240 u16 tx_val = drv_data->cur_chip->idle_tx_val;
241
242 /* clear RXS (we check for RXS inside the loop) */
243 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700244
245 while (drv_data->tx < drv_data->tx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700246 write_TDBR(drv_data, tx_val);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700247 drv_data->tx += n_bytes;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700248 /* wait until transfer finished.
249 checking SPIF or TXS may not guarantee transfer completion */
250 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
251 cpu_relax();
252 /* discard RX data and clear RXS */
253 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700254 }
255}
256
Mike Frysinger138f97c2009-04-06 19:00:50 -0700257static void bfin_spi_null_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700258{
259 u8 n_bytes = drv_data->n_bytes;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700260 u16 tx_val = drv_data->cur_chip->idle_tx_val;
261
262 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700263 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700264
265 while (drv_data->rx < drv_data->rx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700266 write_TDBR(drv_data, tx_val);
267 drv_data->rx += n_bytes;
Bryan Wubb90eb02007-12-04 23:45:18 -0800268 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800269 cpu_relax();
Mike Frysinger138f97c2009-04-06 19:00:50 -0700270 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700271 }
272}
273
Mike Frysinger138f97c2009-04-06 19:00:50 -0700274static void bfin_spi_u8_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700275{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700276 /* clear RXS (we check for RXS inside the loop) */
277 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800278
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700279 while (drv_data->tx < drv_data->tx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700280 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
281 /* wait until transfer finished.
282 checking SPIF or TXS may not guarantee transfer completion */
283 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800284 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700285 /* discard RX data and clear RXS */
286 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700287 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700288}
289
Mike Frysinger138f97c2009-04-06 19:00:50 -0700290static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700291{
292 struct chip_data *chip = drv_data->cur_chip;
293
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700294 /* clear RXS (we check for RXS inside the loop) */
295 bfin_spi_dummy_read(drv_data);
296
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700297 while (drv_data->tx < drv_data->tx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700298 bfin_spi_cs_active(drv_data, chip);
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700299 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
300 /* make sure transfer finished before deactiving CS */
301 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800302 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700303 bfin_spi_dummy_read(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700304 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700305 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700306}
307
Mike Frysinger138f97c2009-04-06 19:00:50 -0700308static void bfin_spi_u8_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700309{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700310 u16 tx_val = drv_data->cur_chip->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700311
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700312 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700313 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800314
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700315 while (drv_data->rx < drv_data->rx_end) {
316 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800317 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800318 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700319 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700320 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700321}
322
Mike Frysinger138f97c2009-04-06 19:00:50 -0700323static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700324{
325 struct chip_data *chip = drv_data->cur_chip;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700326 u16 tx_val = chip->idle_tx_val;
327
328 /* discard old RX data and clear RXS */
329 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700330
Bryan Wue26aa012008-02-06 01:38:18 -0800331 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700332 bfin_spi_cs_active(drv_data, chip);
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700333 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800334 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800335 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700336 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700337 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700338 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700339}
340
Mike Frysinger138f97c2009-04-06 19:00:50 -0700341static void bfin_spi_u8_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700342{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700343 /* discard old RX data and clear RXS */
344 bfin_spi_dummy_read(drv_data);
345
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700346 while (drv_data->rx < drv_data->rx_end) {
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700347 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
Bryan Wubb90eb02007-12-04 23:45:18 -0800348 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800349 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700350 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700351 }
352}
353
Mike Frysinger138f97c2009-04-06 19:00:50 -0700354static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700355{
356 struct chip_data *chip = drv_data->cur_chip;
357
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700358 /* discard old RX data and clear RXS */
359 bfin_spi_dummy_read(drv_data);
360
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700361 while (drv_data->rx < drv_data->rx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700362 bfin_spi_cs_active(drv_data, chip);
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700363 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
Bryan Wubb90eb02007-12-04 23:45:18 -0800364 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800365 cpu_relax();
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700366 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700367 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700368 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700369}
370
Mike Frysinger138f97c2009-04-06 19:00:50 -0700371static void bfin_spi_u16_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700372{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700373 /* clear RXS (we check for RXS inside the loop) */
374 bfin_spi_dummy_read(drv_data);
Bryan Wu88b40362007-05-21 18:32:16 +0800375
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700376 while (drv_data->tx < drv_data->tx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800377 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700378 drv_data->tx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700379 /* wait until transfer finished.
380 checking SPIF or TXS may not guarantee transfer completion */
381 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
382 cpu_relax();
383 /* discard RX data and clear RXS */
384 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700385 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700386}
387
Mike Frysinger138f97c2009-04-06 19:00:50 -0700388static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700389{
390 struct chip_data *chip = drv_data->cur_chip;
391
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700392 /* clear RXS (we check for RXS inside the loop) */
393 bfin_spi_dummy_read(drv_data);
394
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700395 while (drv_data->tx < drv_data->tx_end) {
Mike Frysinger138f97c2009-04-06 19:00:50 -0700396 bfin_spi_cs_active(drv_data, chip);
Bryan Wubb90eb02007-12-04 23:45:18 -0800397 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700398 drv_data->tx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700399 /* make sure transfer finished before deactiving CS */
400 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
401 cpu_relax();
402 bfin_spi_dummy_read(drv_data);
403 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700404 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700405}
406
Mike Frysinger138f97c2009-04-06 19:00:50 -0700407static void bfin_spi_u16_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700408{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700409 u16 tx_val = drv_data->cur_chip->idle_tx_val;
Sonic Zhangcc487e72007-12-04 23:45:17 -0800410
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700411 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700412 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700413
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700414 while (drv_data->rx < drv_data->rx_end) {
415 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800416 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800417 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800418 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700419 drv_data->rx += 2;
420 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700421}
422
Mike Frysinger138f97c2009-04-06 19:00:50 -0700423static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700424{
425 struct chip_data *chip = drv_data->cur_chip;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700426 u16 tx_val = chip->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700427
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700428 /* discard old RX data and clear RXS */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700429 bfin_spi_dummy_read(drv_data);
Sonic Zhangcc487e72007-12-04 23:45:17 -0800430
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700431 while (drv_data->rx < drv_data->rx_end) {
432 bfin_spi_cs_active(drv_data, chip);
433 write_TDBR(drv_data, tx_val);
Bryan Wubb90eb02007-12-04 23:45:18 -0800434 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800435 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800436 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700437 drv_data->rx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700438 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700439 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700440}
441
Mike Frysinger138f97c2009-04-06 19:00:50 -0700442static void bfin_spi_u16_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700443{
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700444 /* discard old RX data and clear RXS */
445 bfin_spi_dummy_read(drv_data);
446
447 while (drv_data->rx < drv_data->rx_end) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800448 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700449 drv_data->tx += 2;
Bryan Wubb90eb02007-12-04 23:45:18 -0800450 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800451 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800452 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700453 drv_data->rx += 2;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700454 }
455}
456
Mike Frysinger138f97c2009-04-06 19:00:50 -0700457static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700458{
459 struct chip_data *chip = drv_data->cur_chip;
460
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700461 /* discard old RX data and clear RXS */
462 bfin_spi_dummy_read(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700463
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700464 while (drv_data->rx < drv_data->rx_end) {
465 bfin_spi_cs_active(drv_data, chip);
Bryan Wubb90eb02007-12-04 23:45:18 -0800466 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700467 drv_data->tx += 2;
Bryan Wubb90eb02007-12-04 23:45:18 -0800468 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800469 cpu_relax();
Bryan Wubb90eb02007-12-04 23:45:18 -0800470 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700471 drv_data->rx += 2;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700472 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700473 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700474}
475
476/* test if ther is more transfer to be done */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700477static void *bfin_spi_next_transfer(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700478{
479 struct spi_message *msg = drv_data->cur_msg;
480 struct spi_transfer *trans = drv_data->cur_transfer;
481
482 /* Move to next transfer */
483 if (trans->transfer_list.next != &msg->transfers) {
484 drv_data->cur_transfer =
485 list_entry(trans->transfer_list.next,
486 struct spi_transfer, transfer_list);
487 return RUNNING_STATE;
488 } else
489 return DONE_STATE;
490}
491
492/*
493 * caller already set message->status;
494 * dma and pio irqs are blocked give finished message back
495 */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700496static void bfin_spi_giveback(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700497{
Bryan Wufad91c82007-12-04 23:45:14 -0800498 struct chip_data *chip = drv_data->cur_chip;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700499 struct spi_transfer *last_transfer;
500 unsigned long flags;
501 struct spi_message *msg;
502
503 spin_lock_irqsave(&drv_data->lock, flags);
504 msg = drv_data->cur_msg;
505 drv_data->cur_msg = NULL;
506 drv_data->cur_transfer = NULL;
507 drv_data->cur_chip = NULL;
508 queue_work(drv_data->workqueue, &drv_data->pump_messages);
509 spin_unlock_irqrestore(&drv_data->lock, flags);
510
511 last_transfer = list_entry(msg->transfers.prev,
512 struct spi_transfer, transfer_list);
513
514 msg->state = NULL;
515
Bryan Wufad91c82007-12-04 23:45:14 -0800516 if (!drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700517 bfin_spi_cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800518
Yi Lib9b2a762009-04-06 19:00:49 -0700519 /* Not stop spi in autobuffer mode */
520 if (drv_data->tx_dma != 0xFFFF)
521 bfin_spi_disable(drv_data);
522
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700523 if (msg->complete)
524 msg->complete(msg->context);
525}
526
Mike Frysinger138f97c2009-04-06 19:00:50 -0700527static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700528{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800529 struct driver_data *drv_data = dev_id;
Bryan Wufad91c82007-12-04 23:45:14 -0800530 struct chip_data *chip = drv_data->cur_chip;
Bryan Wubb90eb02007-12-04 23:45:18 -0800531 struct spi_message *msg = drv_data->cur_msg;
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700532 unsigned long timeout;
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700533 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
Mike Frysinger04b95d22009-04-06 19:00:35 -0700534 u16 spistat = read_STAT(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700535
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700536 dev_dbg(&drv_data->pdev->dev,
537 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
538 dmastat, spistat);
539
Bryan Wubb90eb02007-12-04 23:45:18 -0800540 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700541
Bryan Wud6fe89b2007-06-11 17:34:17 +0800542 /* Wait for DMA to complete */
Bryan Wubb90eb02007-12-04 23:45:18 -0800543 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
Bryan Wud8c05002007-12-04 23:45:21 -0800544 cpu_relax();
Bryan Wud6fe89b2007-06-11 17:34:17 +0800545
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700546 /*
Bryan Wud6fe89b2007-06-11 17:34:17 +0800547 * wait for the last transaction shifted out. HRM states:
548 * at this point there may still be data in the SPI DMA FIFO waiting
549 * to be transmitted ... software needs to poll TXS in the SPI_STAT
550 * register until it goes low for 2 successive reads
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700551 */
552 if (drv_data->tx != NULL) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800553 while ((read_STAT(drv_data) & TXS) ||
554 (read_STAT(drv_data) & TXS))
Bryan Wud8c05002007-12-04 23:45:21 -0800555 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700556 }
557
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700558 dev_dbg(&drv_data->pdev->dev,
559 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
560 dmastat, read_STAT(drv_data));
561
562 timeout = jiffies + HZ;
Bryan Wubb90eb02007-12-04 23:45:18 -0800563 while (!(read_STAT(drv_data) & SPIF))
Mike Frysingeraaaf9392009-04-06 19:00:42 -0700564 if (!time_before(jiffies, timeout)) {
565 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
566 break;
567 } else
568 cpu_relax();
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700569
Mike Frysinger40a29452009-04-06 19:00:38 -0700570 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
Mike Frysinger04b95d22009-04-06 19:00:35 -0700571 msg->state = ERROR_STATE;
572 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
573 } else {
574 msg->actual_length += drv_data->len_in_bytes;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700575
Mike Frysinger04b95d22009-04-06 19:00:35 -0700576 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700577 bfin_spi_cs_deactive(drv_data, chip);
Bryan Wufad91c82007-12-04 23:45:14 -0800578
Mike Frysinger04b95d22009-04-06 19:00:35 -0700579 /* Move to next transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700580 msg->state = bfin_spi_next_transfer(drv_data);
Mike Frysinger04b95d22009-04-06 19:00:35 -0700581 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700582
583 /* Schedule transfer tasklet */
584 tasklet_schedule(&drv_data->pump_transfers);
585
586 /* free the irq handler before next transfer */
Bryan Wu88b40362007-05-21 18:32:16 +0800587 dev_dbg(&drv_data->pdev->dev,
588 "disable dma channel irq%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -0800589 drv_data->dma_channel);
590 dma_disable_irq(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700591
592 return IRQ_HANDLED;
593}
594
Mike Frysinger138f97c2009-04-06 19:00:50 -0700595static void bfin_spi_pump_transfers(unsigned long data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700596{
597 struct driver_data *drv_data = (struct driver_data *)data;
598 struct spi_message *message = NULL;
599 struct spi_transfer *transfer = NULL;
600 struct spi_transfer *previous = NULL;
601 struct chip_data *chip = NULL;
Bryan Wu88b40362007-05-21 18:32:16 +0800602 u8 width;
603 u16 cr, dma_width, dma_config;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700604 u32 tranf_success = 1;
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700605 u8 full_duplex = 0;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700606
607 /* Get current state information */
608 message = drv_data->cur_msg;
609 transfer = drv_data->cur_transfer;
610 chip = drv_data->cur_chip;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800611
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700612 /*
613 * if msg is error or done, report it back using complete() callback
614 */
615
616 /* Handle for abort */
617 if (message->state == ERROR_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700618 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700619 message->status = -EIO;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700620 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700621 return;
622 }
623
624 /* Handle end of message */
625 if (message->state == DONE_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700626 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700627 message->status = 0;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700628 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700629 return;
630 }
631
632 /* Delay if requested at end of transfer */
633 if (message->state == RUNNING_STATE) {
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700634 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700635 previous = list_entry(transfer->transfer_list.prev,
636 struct spi_transfer, transfer_list);
637 if (previous->delay_usecs)
638 udelay(previous->delay_usecs);
639 }
640
641 /* Setup the transfer state based on the type of transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700642 if (bfin_spi_flush(drv_data) == 0) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700643 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
644 message->status = -EIO;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700645 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700646 return;
647 }
648
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700649 if (transfer->len == 0) {
650 /* Move to next transfer of this msg */
651 message->state = bfin_spi_next_transfer(drv_data);
652 /* Schedule next transfer tasklet */
653 tasklet_schedule(&drv_data->pump_transfers);
654 }
655
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700656 if (transfer->tx_buf != NULL) {
657 drv_data->tx = (void *)transfer->tx_buf;
658 drv_data->tx_end = drv_data->tx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800659 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
660 transfer->tx_buf, drv_data->tx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700661 } else {
662 drv_data->tx = NULL;
663 }
664
665 if (transfer->rx_buf != NULL) {
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700666 full_duplex = transfer->tx_buf != NULL;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700667 drv_data->rx = transfer->rx_buf;
668 drv_data->rx_end = drv_data->rx + transfer->len;
Bryan Wu88b40362007-05-21 18:32:16 +0800669 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
670 transfer->rx_buf, drv_data->rx_end);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700671 } else {
672 drv_data->rx = NULL;
673 }
674
675 drv_data->rx_dma = transfer->rx_dma;
676 drv_data->tx_dma = transfer->tx_dma;
677 drv_data->len_in_bytes = transfer->len;
Bryan Wufad91c82007-12-04 23:45:14 -0800678 drv_data->cs_change = transfer->cs_change;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700679
Bryan Wu092e1fd2007-12-04 23:45:23 -0800680 /* Bits per word setup */
681 switch (transfer->bits_per_word) {
682 case 8:
683 drv_data->n_bytes = 1;
684 width = CFG_SPI_WORDSIZE8;
685 drv_data->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700686 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800687 drv_data->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700688 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800689 drv_data->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700690 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800691 break;
692
693 case 16:
694 drv_data->n_bytes = 2;
695 width = CFG_SPI_WORDSIZE16;
696 drv_data->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700697 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800698 drv_data->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700699 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800700 drv_data->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -0700701 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800702 break;
703
704 default:
705 /* No change, the same as default setting */
706 drv_data->n_bytes = chip->n_bytes;
707 width = chip->width;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700708 drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
709 drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader;
710 drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer;
Bryan Wu092e1fd2007-12-04 23:45:23 -0800711 break;
712 }
713 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
714 cr |= (width << 8);
715 write_CTRL(drv_data, cr);
716
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700717 if (width == CFG_SPI_WORDSIZE16) {
718 drv_data->len = (transfer->len) >> 1;
719 } else {
720 drv_data->len = transfer->len;
721 }
Mike Frysinger4fb98ef2008-04-08 17:41:57 -0700722 dev_dbg(&drv_data->pdev->dev,
723 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
Mike Frysinger138f97c2009-04-06 19:00:50 -0700724 drv_data->write, chip->write, bfin_spi_null_writer);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700725
726 /* speed and width has been set on per message */
727 message->state = RUNNING_STATE;
728 dma_config = 0;
729
Bryan Wu092e1fd2007-12-04 23:45:23 -0800730 /* Speed setup (surely valid because already checked) */
731 if (transfer->speed_hz)
732 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
733 else
734 write_BAUD(drv_data, chip->baud);
735
Bryan Wubb90eb02007-12-04 23:45:18 -0800736 write_STAT(drv_data, BIT_STAT_CLR);
737 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
Yi Lib9b2a762009-04-06 19:00:49 -0700738 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700739 bfin_spi_cs_active(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700740
Bryan Wu88b40362007-05-21 18:32:16 +0800741 dev_dbg(&drv_data->pdev->dev,
742 "now pumping a transfer: width is %d, len is %d\n",
743 width, transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700744
745 /*
Vitja Makarov8cf58582009-04-06 19:00:31 -0700746 * Try to map dma buffer and do a dma transfer. If successful use,
747 * different way to r/w according to the enable_dma settings and if
748 * we are not doing a full duplex transfer (since the hardware does
749 * not support full duplex DMA transfers).
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700750 */
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700751 if (!full_duplex && drv_data->cur_chip->enable_dma
752 && drv_data->len > 6) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700753
Mike Frysinger11d6f592009-04-06 19:00:41 -0700754 unsigned long dma_start_addr, flags;
Mike Frysinger7aec3562009-04-06 19:00:36 -0700755
Bryan Wubb90eb02007-12-04 23:45:18 -0800756 disable_dma(drv_data->dma_channel);
757 clear_dma_irqstat(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700758
759 /* config dma channel */
Bryan Wu88b40362007-05-21 18:32:16 +0800760 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
Mike Frysinger7aec3562009-04-06 19:00:36 -0700761 set_dma_x_count(drv_data->dma_channel, drv_data->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700762 if (width == CFG_SPI_WORDSIZE16) {
Bryan Wubb90eb02007-12-04 23:45:18 -0800763 set_dma_x_modify(drv_data->dma_channel, 2);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700764 dma_width = WDSIZE_16;
765 } else {
Bryan Wubb90eb02007-12-04 23:45:18 -0800766 set_dma_x_modify(drv_data->dma_channel, 1);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700767 dma_width = WDSIZE_8;
768 }
769
Sonic Zhang3f479a62007-12-04 23:45:18 -0800770 /* poll for SPI completion before start */
Bryan Wubb90eb02007-12-04 23:45:18 -0800771 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
Bryan Wud8c05002007-12-04 23:45:21 -0800772 cpu_relax();
Sonic Zhang3f479a62007-12-04 23:45:18 -0800773
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700774 /* dirty hack for autobuffer DMA mode */
775 if (drv_data->tx_dma == 0xFFFF) {
Bryan Wu88b40362007-05-21 18:32:16 +0800776 dev_dbg(&drv_data->pdev->dev,
777 "doing autobuffer DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700778
779 /* no irq in autobuffer mode */
780 dma_config =
781 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
Bryan Wubb90eb02007-12-04 23:45:18 -0800782 set_dma_config(drv_data->dma_channel, dma_config);
783 set_dma_start_addr(drv_data->dma_channel,
Bryan Wua32c6912007-12-04 23:45:15 -0800784 (unsigned long)drv_data->tx);
Bryan Wubb90eb02007-12-04 23:45:18 -0800785 enable_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700786
Sonic Zhang07612e52007-12-04 23:45:21 -0800787 /* start SPI transfer */
Mike Frysinger11d6f592009-04-06 19:00:41 -0700788 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
Sonic Zhang07612e52007-12-04 23:45:21 -0800789
790 /* just return here, there can only be one transfer
791 * in this mode
792 */
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700793 message->status = 0;
Mike Frysinger138f97c2009-04-06 19:00:50 -0700794 bfin_spi_giveback(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700795 return;
796 }
797
798 /* In dma mode, rx or tx must be NULL in one transfer */
Mike Frysinger7aec3562009-04-06 19:00:36 -0700799 dma_config = (RESTART | dma_width | DI_EN);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700800 if (drv_data->rx != NULL) {
801 /* set transfer mode, and enable SPI */
Mike Frysingerd24bd1d2009-04-06 19:00:38 -0700802 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
803 drv_data->rx, drv_data->len_in_bytes);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700804
Vitja Makarov8cf58582009-04-06 19:00:31 -0700805 /* invalidate caches, if needed */
Jie Zhang67834fa2009-06-10 06:26:26 +0000806 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
Vitja Makarov8cf58582009-04-06 19:00:31 -0700807 invalidate_dcache_range((unsigned long) drv_data->rx,
808 (unsigned long) (drv_data->rx +
Mike Frysingerace32862009-04-06 19:00:34 -0700809 drv_data->len_in_bytes));
Vitja Makarov8cf58582009-04-06 19:00:31 -0700810
Mike Frysinger7aec3562009-04-06 19:00:36 -0700811 dma_config |= WNR;
812 dma_start_addr = (unsigned long)drv_data->rx;
Mike Frysingerb31e27a2009-04-06 19:00:39 -0700813 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
Sonic Zhang07612e52007-12-04 23:45:21 -0800814
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700815 } else if (drv_data->tx != NULL) {
Bryan Wu88b40362007-05-21 18:32:16 +0800816 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700817
Vitja Makarov8cf58582009-04-06 19:00:31 -0700818 /* flush caches, if needed */
Jie Zhang67834fa2009-06-10 06:26:26 +0000819 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
Vitja Makarov8cf58582009-04-06 19:00:31 -0700820 flush_dcache_range((unsigned long) drv_data->tx,
821 (unsigned long) (drv_data->tx +
Mike Frysingerace32862009-04-06 19:00:34 -0700822 drv_data->len_in_bytes));
Vitja Makarov8cf58582009-04-06 19:00:31 -0700823
Mike Frysinger7aec3562009-04-06 19:00:36 -0700824 dma_start_addr = (unsigned long)drv_data->tx;
Mike Frysingerb31e27a2009-04-06 19:00:39 -0700825 cr |= BIT_CTL_TIMOD_DMA_TX;
Sonic Zhang07612e52007-12-04 23:45:21 -0800826
Mike Frysinger7aec3562009-04-06 19:00:36 -0700827 } else
828 BUG();
829
Mike Frysinger11d6f592009-04-06 19:00:41 -0700830 /* oh man, here there be monsters ... and i dont mean the
831 * fluffy cute ones from pixar, i mean the kind that'll eat
832 * your data, kick your dog, and love it all. do *not* try
833 * and change these lines unless you (1) heavily test DMA
834 * with SPI flashes on a loaded system (e.g. ping floods),
835 * (2) know just how broken the DMA engine interaction with
836 * the SPI peripheral is, and (3) have someone else to blame
837 * when you screw it all up anyways.
838 */
Mike Frysinger7aec3562009-04-06 19:00:36 -0700839 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
Mike Frysinger11d6f592009-04-06 19:00:41 -0700840 set_dma_config(drv_data->dma_channel, dma_config);
841 local_irq_save(flags);
Mike Frysingera963ea82009-04-06 19:00:43 -0700842 SSYNC();
Mike Frysinger11d6f592009-04-06 19:00:41 -0700843 write_CTRL(drv_data, cr);
Mike Frysingera963ea82009-04-06 19:00:43 -0700844 enable_dma(drv_data->dma_channel);
Mike Frysinger11d6f592009-04-06 19:00:41 -0700845 dma_enable_irq(drv_data->dma_channel);
846 local_irq_restore(flags);
Mike Frysinger7aec3562009-04-06 19:00:36 -0700847
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700848 } else {
849 /* IO mode write then read */
Bryan Wu88b40362007-05-21 18:32:16 +0800850 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700851
Wolfgang Muees93b61bd2009-04-06 19:00:53 -0700852 /* we always use SPI_WRITE mode. SPI_READ mode
853 seems to have problems with setting up the
854 output value in TDBR prior to the transfer. */
855 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
856
Vitja Makarov8eeb12e2008-05-01 04:35:03 -0700857 if (full_duplex) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700858 /* full duplex mode */
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
Bryan Wu88b40362007-05-21 18:32:16 +0800861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700863
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700864 drv_data->duplex(drv_data);
865
866 if (drv_data->tx != drv_data->tx_end)
867 tranf_success = 0;
868 } else if (drv_data->tx != NULL) {
869 /* write only half duplex */
Bryan Wu131b17d2007-12-04 23:45:12 -0800870 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800871 "IO write: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700872
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700873 drv_data->write(drv_data);
874
875 if (drv_data->tx != drv_data->tx_end)
876 tranf_success = 0;
877 } else if (drv_data->rx != NULL) {
878 /* read only half duplex */
Bryan Wu131b17d2007-12-04 23:45:12 -0800879 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800880 "IO read: cr is 0x%x\n", cr);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700881
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700882 drv_data->read(drv_data);
883 if (drv_data->rx != drv_data->rx_end)
884 tranf_success = 0;
885 }
886
887 if (!tranf_success) {
Bryan Wu131b17d2007-12-04 23:45:12 -0800888 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800889 "IO write error!\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700890 message->state = ERROR_STATE;
891 } else {
892 /* Update total byte transfered */
Mike Frysingerace32862009-04-06 19:00:34 -0700893 message->actual_length += drv_data->len_in_bytes;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700894 /* Move to next transfer of this msg */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700895 message->state = bfin_spi_next_transfer(drv_data);
Yi Lib9b2a762009-04-06 19:00:49 -0700896 if (drv_data->cs_change)
Mike Frysinger138f97c2009-04-06 19:00:50 -0700897 bfin_spi_cs_deactive(drv_data, chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700898 }
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700899 /* Schedule next transfer tasklet */
900 tasklet_schedule(&drv_data->pump_transfers);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700901 }
902}
903
904/* pop a msg from queue and kick off real transfer */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700905static void bfin_spi_pump_messages(struct work_struct *work)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700906{
Bryan Wu131b17d2007-12-04 23:45:12 -0800907 struct driver_data *drv_data;
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700908 unsigned long flags;
909
Bryan Wu131b17d2007-12-04 23:45:12 -0800910 drv_data = container_of(work, struct driver_data, pump_messages);
911
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700912 /* Lock queue and check for queue work */
913 spin_lock_irqsave(&drv_data->lock, flags);
914 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
915 /* pumper kicked off but no work to do */
916 drv_data->busy = 0;
917 spin_unlock_irqrestore(&drv_data->lock, flags);
918 return;
919 }
920
921 /* Make sure we are not already running a message */
922 if (drv_data->cur_msg) {
923 spin_unlock_irqrestore(&drv_data->lock, flags);
924 return;
925 }
926
927 /* Extract head of queue */
928 drv_data->cur_msg = list_entry(drv_data->queue.next,
929 struct spi_message, queue);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800930
931 /* Setup the SSP using the per chip configuration */
932 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
Mike Frysinger138f97c2009-04-06 19:00:50 -0700933 bfin_spi_restore_state(drv_data);
Bryan Wu5fec5b52007-12-04 23:45:13 -0800934
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700935 list_del_init(&drv_data->cur_msg->queue);
936
937 /* Initial message state */
938 drv_data->cur_msg->state = START_STATE;
939 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
940 struct spi_transfer, transfer_list);
941
Bryan Wu5fec5b52007-12-04 23:45:13 -0800942 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
943 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
944 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
945 drv_data->cur_chip->ctl_reg);
Bryan Wu131b17d2007-12-04 23:45:12 -0800946
947 dev_dbg(&drv_data->pdev->dev,
Bryan Wu88b40362007-05-21 18:32:16 +0800948 "the first transfer len is %d\n",
949 drv_data->cur_transfer->len);
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700950
951 /* Mark as busy and launch transfers */
952 tasklet_schedule(&drv_data->pump_transfers);
953
954 drv_data->busy = 1;
955 spin_unlock_irqrestore(&drv_data->lock, flags);
956}
957
958/*
959 * got a msg to transfer, queue it in drv_data->queue.
960 * And kick off message pumper
961 */
Mike Frysinger138f97c2009-04-06 19:00:50 -0700962static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700963{
964 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
965 unsigned long flags;
966
967 spin_lock_irqsave(&drv_data->lock, flags);
968
969 if (drv_data->run == QUEUE_STOPPED) {
970 spin_unlock_irqrestore(&drv_data->lock, flags);
971 return -ESHUTDOWN;
972 }
973
974 msg->actual_length = 0;
975 msg->status = -EINPROGRESS;
976 msg->state = START_STATE;
977
Bryan Wu88b40362007-05-21 18:32:16 +0800978 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -0700979 list_add_tail(&msg->queue, &drv_data->queue);
980
981 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
982 queue_work(drv_data->workqueue, &drv_data->pump_messages);
983
984 spin_unlock_irqrestore(&drv_data->lock, flags);
985
986 return 0;
987}
988
Sonic Zhang12e17c42007-12-04 23:45:16 -0800989#define MAX_SPI_SSEL 7
990
Mike Frysinger4160bde2009-04-06 19:00:40 -0700991static u16 ssel[][MAX_SPI_SSEL] = {
Sonic Zhang12e17c42007-12-04 23:45:16 -0800992 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
993 P_SPI0_SSEL4, P_SPI0_SSEL5,
994 P_SPI0_SSEL6, P_SPI0_SSEL7},
995
996 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
997 P_SPI1_SSEL4, P_SPI1_SSEL5,
998 P_SPI1_SSEL6, P_SPI1_SSEL7},
999
1000 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1001 P_SPI2_SSEL4, P_SPI2_SSEL5,
1002 P_SPI2_SSEL6, P_SPI2_SSEL7},
1003};
1004
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001005/* first setup for new devices */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001006static int bfin_spi_setup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001007{
1008 struct bfin5xx_spi_chip *chip_info = NULL;
1009 struct chip_data *chip;
1010 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
Michael Hennerich42c78b22009-04-06 19:00:51 -07001011 int ret;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001012
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001013 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1014 return -EINVAL;
1015
1016 /* Only alloc (or use chip_info) on first setup */
1017 chip = spi_get_ctldata(spi);
1018 if (chip == NULL) {
1019 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1020 if (!chip)
1021 return -ENOMEM;
1022
1023 chip->enable_dma = 0;
1024 chip_info = spi->controller_data;
1025 }
1026
1027 /* chip_info isn't always needed */
1028 if (chip_info) {
Mike Frysinger2ed35512007-12-04 23:45:14 -08001029 /* Make sure people stop trying to set fields via ctl_reg
1030 * when they should actually be using common SPI framework.
1031 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1032 * Not sure if a user actually needs/uses any of these,
1033 * but let's assume (for now) they do.
1034 */
1035 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1036 dev_err(&spi->dev, "do not set bits in ctl_reg "
1037 "that the SPI framework manages\n");
1038 return -EINVAL;
1039 }
1040
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001041 chip->enable_dma = chip_info->enable_dma != 0
1042 && drv_data->master_info->enable_dma;
1043 chip->ctl_reg = chip_info->ctl_reg;
1044 chip->bits_per_word = chip_info->bits_per_word;
1045 chip->cs_change_per_word = chip_info->cs_change_per_word;
1046 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
Michael Hennerich42c78b22009-04-06 19:00:51 -07001047 chip->cs_gpio = chip_info->cs_gpio;
Wolfgang Muees93b61bd2009-04-06 19:00:53 -07001048 chip->idle_tx_val = chip_info->idle_tx_val;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001049 }
1050
1051 /* translate common spi framework into our register */
1052 if (spi->mode & SPI_CPOL)
1053 chip->ctl_reg |= CPOL;
1054 if (spi->mode & SPI_CPHA)
1055 chip->ctl_reg |= CPHA;
1056 if (spi->mode & SPI_LSB_FIRST)
1057 chip->ctl_reg |= LSBF;
1058 /* we dont support running in slave mode (yet?) */
1059 chip->ctl_reg |= MSTR;
1060
1061 /*
1062 * if any one SPI chip is registered and wants DMA, request the
1063 * DMA channel for it
1064 */
Bryan Wubb90eb02007-12-04 23:45:18 -08001065 if (chip->enable_dma && !drv_data->dma_requested) {
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001066 /* register dma irq handler */
Mike Frysinger59bfcc62009-04-06 19:00:37 -07001067 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
Bryan Wu88b40362007-05-21 18:32:16 +08001068 dev_dbg(&spi->dev,
1069 "Unable to request BlackFin SPI DMA channel\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001070 return -ENODEV;
1071 }
Bryan Wubb90eb02007-12-04 23:45:18 -08001072 if (set_dma_callback(drv_data->dma_channel,
Mike Frysinger138f97c2009-04-06 19:00:50 -07001073 bfin_spi_dma_irq_handler, drv_data) < 0) {
Bryan Wu88b40362007-05-21 18:32:16 +08001074 dev_dbg(&spi->dev, "Unable to set dma callback\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001075 return -EPERM;
1076 }
Bryan Wubb90eb02007-12-04 23:45:18 -08001077 dma_disable_irq(drv_data->dma_channel);
1078 drv_data->dma_requested = 1;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001079 }
1080
1081 /*
1082 * Notice: for blackfin, the speed_hz is the value of register
1083 * SPI_BAUD, not the real baudrate
1084 */
1085 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
Yi Li2cf36832009-04-06 19:00:44 -07001086 chip->flag = 1 << (spi->chip_select);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001087 chip->chip_select_num = spi->chip_select;
1088
Michael Hennerich42c78b22009-04-06 19:00:51 -07001089 if (chip->chip_select_num == 0) {
1090 ret = gpio_request(chip->cs_gpio, spi->modalias);
1091 if (ret) {
1092 if (drv_data->dma_requested)
1093 free_dma(drv_data->dma_channel);
1094 return ret;
1095 }
1096 gpio_direction_output(chip->cs_gpio, 1);
1097 }
1098
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001099 switch (chip->bits_per_word) {
1100 case 8:
1101 chip->n_bytes = 1;
1102 chip->width = CFG_SPI_WORDSIZE8;
1103 chip->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001104 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001105 chip->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001106 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001107 chip->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001108 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001109 break;
1110
1111 case 16:
1112 chip->n_bytes = 2;
1113 chip->width = CFG_SPI_WORDSIZE16;
1114 chip->read = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001115 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001116 chip->write = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001117 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001118 chip->duplex = chip->cs_change_per_word ?
Mike Frysinger138f97c2009-04-06 19:00:50 -07001119 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001120 break;
1121
1122 default:
1123 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1124 chip->bits_per_word);
Mike Frysinger138f97c2009-04-06 19:00:50 -07001125 if (chip_info)
1126 kfree(chip);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001127 return -ENODEV;
1128 }
1129
Joe Perches898eb712007-10-18 03:06:30 -07001130 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001131 spi->modalias, chip->width, chip->enable_dma);
Bryan Wu88b40362007-05-21 18:32:16 +08001132 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001133 chip->ctl_reg, chip->flag);
1134
1135 spi_set_ctldata(spi, chip);
1136
Sonic Zhang12e17c42007-12-04 23:45:16 -08001137 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1138 if ((chip->chip_select_num > 0)
1139 && (chip->chip_select_num <= spi->master->num_chipselect))
1140 peripheral_request(ssel[spi->master->bus_num]
Bryan Wuaab0d832008-02-06 01:38:17 -08001141 [chip->chip_select_num-1], spi->modalias);
Sonic Zhang12e17c42007-12-04 23:45:16 -08001142
Mike Frysinger138f97c2009-04-06 19:00:50 -07001143 bfin_spi_cs_deactive(drv_data, chip);
Sonic Zhang07612e52007-12-04 23:45:21 -08001144
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001145 return 0;
1146}
1147
1148/*
1149 * callback for spi framework.
1150 * clean driver specific data
1151 */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001152static void bfin_spi_cleanup(struct spi_device *spi)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001153{
Mike Frysinger27bb9e72007-06-11 15:31:30 +08001154 struct chip_data *chip = spi_get_ctldata(spi);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001155
Mike Frysingere7d02e32009-04-06 19:00:51 -07001156 if (!chip)
1157 return;
1158
Sonic Zhang12e17c42007-12-04 23:45:16 -08001159 if ((chip->chip_select_num > 0)
1160 && (chip->chip_select_num <= spi->master->num_chipselect))
1161 peripheral_free(ssel[spi->master->bus_num]
1162 [chip->chip_select_num-1]);
1163
Michael Hennerich42c78b22009-04-06 19:00:51 -07001164 if (chip->chip_select_num == 0)
1165 gpio_free(chip->cs_gpio);
1166
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001167 kfree(chip);
1168}
1169
Mike Frysinger138f97c2009-04-06 19:00:50 -07001170static inline int bfin_spi_init_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001171{
1172 INIT_LIST_HEAD(&drv_data->queue);
1173 spin_lock_init(&drv_data->lock);
1174
1175 drv_data->run = QUEUE_STOPPED;
1176 drv_data->busy = 0;
1177
1178 /* init transfer tasklet */
1179 tasklet_init(&drv_data->pump_transfers,
Mike Frysinger138f97c2009-04-06 19:00:50 -07001180 bfin_spi_pump_transfers, (unsigned long)drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001181
1182 /* init messages workqueue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001183 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
Kay Sievers6c7377a2009-03-24 16:38:21 -07001184 drv_data->workqueue = create_singlethread_workqueue(
1185 dev_name(drv_data->master->dev.parent));
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001186 if (drv_data->workqueue == NULL)
1187 return -EBUSY;
1188
1189 return 0;
1190}
1191
Mike Frysinger138f97c2009-04-06 19:00:50 -07001192static inline int bfin_spi_start_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001193{
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&drv_data->lock, flags);
1197
1198 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1199 spin_unlock_irqrestore(&drv_data->lock, flags);
1200 return -EBUSY;
1201 }
1202
1203 drv_data->run = QUEUE_RUNNING;
1204 drv_data->cur_msg = NULL;
1205 drv_data->cur_transfer = NULL;
1206 drv_data->cur_chip = NULL;
1207 spin_unlock_irqrestore(&drv_data->lock, flags);
1208
1209 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1210
1211 return 0;
1212}
1213
Mike Frysinger138f97c2009-04-06 19:00:50 -07001214static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001215{
1216 unsigned long flags;
1217 unsigned limit = 500;
1218 int status = 0;
1219
1220 spin_lock_irqsave(&drv_data->lock, flags);
1221
1222 /*
1223 * This is a bit lame, but is optimized for the common execution path.
1224 * A wait_queue on the drv_data->busy could be used, but then the common
1225 * execution path (pump_messages) would be required to call wake_up or
1226 * friends on every SPI message. Do this instead
1227 */
1228 drv_data->run = QUEUE_STOPPED;
1229 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1230 spin_unlock_irqrestore(&drv_data->lock, flags);
1231 msleep(10);
1232 spin_lock_irqsave(&drv_data->lock, flags);
1233 }
1234
1235 if (!list_empty(&drv_data->queue) || drv_data->busy)
1236 status = -EBUSY;
1237
1238 spin_unlock_irqrestore(&drv_data->lock, flags);
1239
1240 return status;
1241}
1242
Mike Frysinger138f97c2009-04-06 19:00:50 -07001243static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001244{
1245 int status;
1246
Mike Frysinger138f97c2009-04-06 19:00:50 -07001247 status = bfin_spi_stop_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001248 if (status != 0)
1249 return status;
1250
1251 destroy_workqueue(drv_data->workqueue);
1252
1253 return 0;
1254}
1255
Mike Frysinger138f97c2009-04-06 19:00:50 -07001256static int __init bfin_spi_probe(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001257{
1258 struct device *dev = &pdev->dev;
1259 struct bfin5xx_spi_master *platform_info;
1260 struct spi_master *master;
1261 struct driver_data *drv_data = 0;
Bryan Wua32c6912007-12-04 23:45:15 -08001262 struct resource *res;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001263 int status = 0;
1264
1265 platform_info = dev->platform_data;
1266
1267 /* Allocate master with space for drv_data */
1268 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1269 if (!master) {
1270 dev_err(&pdev->dev, "can not alloc spi_master\n");
1271 return -ENOMEM;
1272 }
Bryan Wu131b17d2007-12-04 23:45:12 -08001273
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001274 drv_data = spi_master_get_devdata(master);
1275 drv_data->master = master;
1276 drv_data->master_info = platform_info;
1277 drv_data->pdev = pdev;
Bryan Wu003d9222007-12-04 23:45:22 -08001278 drv_data->pin_req = platform_info->pin_req;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001279
David Brownelle7db06b2009-06-17 16:26:04 -07001280 /* the spi->mode bits supported by this driver: */
1281 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1282
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001283 master->bus_num = pdev->id;
1284 master->num_chipselect = platform_info->num_chipselect;
Mike Frysinger138f97c2009-04-06 19:00:50 -07001285 master->cleanup = bfin_spi_cleanup;
1286 master->setup = bfin_spi_setup;
1287 master->transfer = bfin_spi_transfer;
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001288
Bryan Wua32c6912007-12-04 23:45:15 -08001289 /* Find and map our resources */
1290 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291 if (res == NULL) {
1292 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1293 status = -ENOENT;
1294 goto out_error_get_res;
1295 }
1296
hartleys74947b82009-12-14 22:33:43 +00001297 drv_data->regs_base = ioremap(res->start, resource_size(res));
Bryan Wuf4521262007-12-04 23:45:22 -08001298 if (drv_data->regs_base == NULL) {
Bryan Wua32c6912007-12-04 23:45:15 -08001299 dev_err(dev, "Cannot map IO\n");
1300 status = -ENXIO;
1301 goto out_error_ioremap;
1302 }
1303
Bryan Wubb90eb02007-12-04 23:45:18 -08001304 drv_data->dma_channel = platform_get_irq(pdev, 0);
1305 if (drv_data->dma_channel < 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001306 dev_err(dev, "No DMA channel specified\n");
1307 status = -ENOENT;
1308 goto out_error_no_dma_ch;
1309 }
1310
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001311 /* Initial and start queue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001312 status = bfin_spi_init_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001313 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001314 dev_err(dev, "problem initializing queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001315 goto out_error_queue_alloc;
1316 }
Bryan Wua32c6912007-12-04 23:45:15 -08001317
Mike Frysinger138f97c2009-04-06 19:00:50 -07001318 status = bfin_spi_start_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001319 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001320 dev_err(dev, "problem starting queue\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001321 goto out_error_queue_alloc;
1322 }
1323
Vitja Makarovf9e522c2008-04-08 17:41:57 -07001324 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1325 if (status != 0) {
1326 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1327 goto out_error_queue_alloc;
1328 }
1329
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001330 /* Register with the SPI framework */
1331 platform_set_drvdata(pdev, drv_data);
1332 status = spi_register_master(master);
1333 if (status != 0) {
Bryan Wua32c6912007-12-04 23:45:15 -08001334 dev_err(dev, "problem registering spi master\n");
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001335 goto out_error_queue_alloc;
1336 }
Bryan Wua32c6912007-12-04 23:45:15 -08001337
Bryan Wuf4521262007-12-04 23:45:22 -08001338 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
Bryan Wubb90eb02007-12-04 23:45:18 -08001339 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1340 drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001341 return status;
1342
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001343out_error_queue_alloc:
Mike Frysinger138f97c2009-04-06 19:00:50 -07001344 bfin_spi_destroy_queue(drv_data);
Bryan Wua32c6912007-12-04 23:45:15 -08001345out_error_no_dma_ch:
Bryan Wubb90eb02007-12-04 23:45:18 -08001346 iounmap((void *) drv_data->regs_base);
Bryan Wua32c6912007-12-04 23:45:15 -08001347out_error_ioremap:
1348out_error_get_res:
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001349 spi_master_put(master);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001350
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001351 return status;
1352}
1353
1354/* stop hardware and remove the driver */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001355static int __devexit bfin_spi_remove(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001356{
1357 struct driver_data *drv_data = platform_get_drvdata(pdev);
1358 int status = 0;
1359
1360 if (!drv_data)
1361 return 0;
1362
1363 /* Remove the queue */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001364 status = bfin_spi_destroy_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001365 if (status != 0)
1366 return status;
1367
1368 /* Disable the SSP at the peripheral and SOC level */
1369 bfin_spi_disable(drv_data);
1370
1371 /* Release DMA */
1372 if (drv_data->master_info->enable_dma) {
Bryan Wubb90eb02007-12-04 23:45:18 -08001373 if (dma_channel_active(drv_data->dma_channel))
1374 free_dma(drv_data->dma_channel);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001375 }
1376
1377 /* Disconnect from the SPI framework */
1378 spi_unregister_master(drv_data->master);
1379
Bryan Wu003d9222007-12-04 23:45:22 -08001380 peripheral_free_list(drv_data->pin_req);
Michael Hennerichcc2f81a2007-12-04 23:45:13 -08001381
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001382 /* Prevent double remove */
1383 platform_set_drvdata(pdev, NULL);
1384
1385 return 0;
1386}
1387
1388#ifdef CONFIG_PM
Mike Frysinger138f97c2009-04-06 19:00:50 -07001389static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001390{
1391 struct driver_data *drv_data = platform_get_drvdata(pdev);
1392 int status = 0;
1393
Mike Frysinger138f97c2009-04-06 19:00:50 -07001394 status = bfin_spi_stop_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001395 if (status != 0)
1396 return status;
1397
1398 /* stop hardware */
1399 bfin_spi_disable(drv_data);
1400
1401 return 0;
1402}
1403
Mike Frysinger138f97c2009-04-06 19:00:50 -07001404static int bfin_spi_resume(struct platform_device *pdev)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001405{
1406 struct driver_data *drv_data = platform_get_drvdata(pdev);
1407 int status = 0;
1408
1409 /* Enable the SPI interface */
1410 bfin_spi_enable(drv_data);
1411
1412 /* Start the queue running */
Mike Frysinger138f97c2009-04-06 19:00:50 -07001413 status = bfin_spi_start_queue(drv_data);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001414 if (status != 0) {
1415 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1416 return status;
1417 }
1418
1419 return 0;
1420}
1421#else
Mike Frysinger138f97c2009-04-06 19:00:50 -07001422#define bfin_spi_suspend NULL
1423#define bfin_spi_resume NULL
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001424#endif /* CONFIG_PM */
1425
Kay Sievers7e38c3c2008-04-10 21:29:20 -07001426MODULE_ALIAS("platform:bfin-spi");
Mike Frysinger138f97c2009-04-06 19:00:50 -07001427static struct platform_driver bfin_spi_driver = {
David Brownellfc3ba952007-08-30 23:56:24 -07001428 .driver = {
Bryan Wua32c6912007-12-04 23:45:15 -08001429 .name = DRV_NAME,
Bryan Wu88b40362007-05-21 18:32:16 +08001430 .owner = THIS_MODULE,
1431 },
Mike Frysinger138f97c2009-04-06 19:00:50 -07001432 .suspend = bfin_spi_suspend,
1433 .resume = bfin_spi_resume,
1434 .remove = __devexit_p(bfin_spi_remove),
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001435};
1436
Mike Frysinger138f97c2009-04-06 19:00:50 -07001437static int __init bfin_spi_init(void)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001438{
Mike Frysinger138f97c2009-04-06 19:00:50 -07001439 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001440}
Mike Frysinger138f97c2009-04-06 19:00:50 -07001441module_init(bfin_spi_init);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001442
Mike Frysinger138f97c2009-04-06 19:00:50 -07001443static void __exit bfin_spi_exit(void)
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001444{
Mike Frysinger138f97c2009-04-06 19:00:50 -07001445 platform_driver_unregister(&bfin_spi_driver);
Wu, Bryana5f6abd2007-05-06 14:50:34 -07001446}
Mike Frysinger138f97c2009-04-06 19:00:50 -07001447module_exit(bfin_spi_exit);