Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2008 Advanced Micro Devices, Inc. |
| 3 | * Copyright 2008 Red Hat Inc. |
| 4 | * Copyright 2009 Jerome Glisse. |
| 5 | * |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 7 | * copy of this software and associated documentation files (the "Software"), |
| 8 | * to deal in the Software without restriction, including without limitation |
| 9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 10 | * and/or sell copies of the Software, and to permit persons to whom the |
| 11 | * Software is furnished to do so, subject to the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice shall be included in |
| 14 | * all copies or substantial portions of the Software. |
| 15 | * |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 22 | * OTHER DEALINGS IN THE SOFTWARE. |
| 23 | * |
| 24 | * Authors: Dave Airlie |
| 25 | * Alex Deucher |
| 26 | * Jerome Glisse |
| 27 | */ |
| 28 | #ifndef __RADEON_H__ |
| 29 | #define __RADEON_H__ |
| 30 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 31 | /* TODO: Here are things that needs to be done : |
| 32 | * - surface allocator & initializer : (bit like scratch reg) should |
| 33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
| 34 | * related to surface |
| 35 | * - WB : write back stuff (do it bit like scratch reg things) |
| 36 | * - Vblank : look at Jesse's rework and what we should do |
| 37 | * - r600/r700: gart & cp |
| 38 | * - cs : clean cs ioctl use bitmap & things like that. |
| 39 | * - power management stuff |
| 40 | * - Barrier in gart code |
| 41 | * - Unmappabled vram ? |
| 42 | * - TESTING, TESTING, TESTING |
| 43 | */ |
| 44 | |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 45 | /* Initialization path: |
| 46 | * We expect that acceleration initialization might fail for various |
| 47 | * reasons even thought we work hard to make it works on most |
| 48 | * configurations. In order to still have a working userspace in such |
| 49 | * situation the init path must succeed up to the memory controller |
| 50 | * initialization point. Failure before this point are considered as |
| 51 | * fatal error. Here is the init callchain : |
| 52 | * radeon_device_init perform common structure, mutex initialization |
| 53 | * asic_init setup the GPU memory layout and perform all |
| 54 | * one time initialization (failure in this |
| 55 | * function are considered fatal) |
| 56 | * asic_startup setup the GPU acceleration, in order to |
| 57 | * follow guideline the first thing this |
| 58 | * function should do is setting the GPU |
| 59 | * memory controller (only MC setup failure |
| 60 | * are considered as fatal) |
| 61 | */ |
| 62 | |
Arun Sharma | 60063497 | 2011-07-26 16:09:06 -0700 | [diff] [blame] | 63 | #include <linux/atomic.h> |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 64 | #include <linux/wait.h> |
| 65 | #include <linux/list.h> |
| 66 | #include <linux/kref.h> |
| 67 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 68 | #include <ttm/ttm_bo_api.h> |
| 69 | #include <ttm/ttm_bo_driver.h> |
| 70 | #include <ttm/ttm_placement.h> |
| 71 | #include <ttm/ttm_module.h> |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 72 | #include <ttm/ttm_execbuf_util.h> |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 73 | |
Dave Airlie | c214271 | 2009-09-22 08:50:10 +1000 | [diff] [blame] | 74 | #include "radeon_family.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 75 | #include "radeon_mode.h" |
| 76 | #include "radeon_reg.h" |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Modules parameters. |
| 80 | */ |
| 81 | extern int radeon_no_wb; |
| 82 | extern int radeon_modeset; |
| 83 | extern int radeon_dynclks; |
| 84 | extern int radeon_r4xx_atom; |
| 85 | extern int radeon_agpmode; |
| 86 | extern int radeon_vram_limit; |
| 87 | extern int radeon_gart_size; |
| 88 | extern int radeon_benchmarking; |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 89 | extern int radeon_testing; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 90 | extern int radeon_connector_table; |
Dave Airlie | 4ce001a | 2009-08-13 16:32:14 +1000 | [diff] [blame] | 91 | extern int radeon_tv; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 92 | extern int radeon_audio; |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 93 | extern int radeon_disp_priority; |
Alex Deucher | e2b0a8e | 2010-03-17 02:07:37 -0400 | [diff] [blame] | 94 | extern int radeon_hw_i2c; |
Alex Deucher | d42dd57 | 2011-01-12 20:05:11 -0500 | [diff] [blame] | 95 | extern int radeon_pcie_gen2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 96 | |
| 97 | /* |
| 98 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
| 99 | * symbol; |
| 100 | */ |
| 101 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 102 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 103 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 104 | #define RADEON_IB_POOL_SIZE 16 |
Michael Witten | c245cb9 | 2011-09-16 20:45:30 +0000 | [diff] [blame] | 105 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 106 | #define RADEONFB_CONN_LIMIT 4 |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 107 | #define RADEON_BIOS_NUM_SCRATCH 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 108 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 109 | /* |
| 110 | * Errata workarounds. |
| 111 | */ |
| 112 | enum radeon_pll_errata { |
| 113 | CHIP_ERRATA_R300_CG = 0x00000001, |
| 114 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
| 115 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
| 116 | }; |
| 117 | |
| 118 | |
| 119 | struct radeon_device; |
| 120 | |
| 121 | |
| 122 | /* |
| 123 | * BIOS. |
| 124 | */ |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 125 | #define ATRM_BIOS_PAGE 4096 |
| 126 | |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 127 | #if defined(CONFIG_VGA_SWITCHEROO) |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 128 | bool radeon_atrm_supported(struct pci_dev *pdev); |
| 129 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
Dave Airlie | 8edb381 | 2010-03-01 21:50:01 +1100 | [diff] [blame] | 130 | #else |
| 131 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
| 132 | { |
| 133 | return false; |
| 134 | } |
| 135 | |
| 136 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
| 137 | return -EINVAL; |
| 138 | } |
| 139 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 140 | bool radeon_get_bios(struct radeon_device *rdev); |
| 141 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 142 | |
| 143 | /* |
| 144 | * Dummy page |
| 145 | */ |
| 146 | struct radeon_dummy_page { |
| 147 | struct page *page; |
| 148 | dma_addr_t addr; |
| 149 | }; |
| 150 | int radeon_dummy_page_init(struct radeon_device *rdev); |
| 151 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
| 152 | |
| 153 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 154 | /* |
| 155 | * Clocks |
| 156 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 157 | struct radeon_clock { |
| 158 | struct radeon_pll p1pll; |
| 159 | struct radeon_pll p2pll; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 160 | struct radeon_pll dcpll; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 161 | struct radeon_pll spll; |
| 162 | struct radeon_pll mpll; |
| 163 | /* 10 Khz units */ |
| 164 | uint32_t default_mclk; |
| 165 | uint32_t default_sclk; |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 166 | uint32_t default_dispclk; |
| 167 | uint32_t dp_extclk; |
Alex Deucher | b20f9be | 2011-06-08 13:01:11 -0400 | [diff] [blame] | 168 | uint32_t max_pixel_clock; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 169 | }; |
| 170 | |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 171 | /* |
| 172 | * Power management |
| 173 | */ |
| 174 | int radeon_pm_init(struct radeon_device *rdev); |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 175 | void radeon_pm_fini(struct radeon_device *rdev); |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 176 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 177 | void radeon_pm_suspend(struct radeon_device *rdev); |
| 178 | void radeon_pm_resume(struct radeon_device *rdev); |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 179 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
| 180 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
Alex Deucher | 8a83ec5 | 2011-04-12 14:49:23 -0400 | [diff] [blame] | 181 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
Alex Deucher | ee4017f | 2011-06-23 12:19:32 -0400 | [diff] [blame] | 182 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage); |
Alex Deucher | f892034 | 2010-06-30 12:02:03 -0400 | [diff] [blame] | 183 | void rs690_pm_info(struct radeon_device *rdev); |
Alex Deucher | 20d391d | 2011-02-01 16:12:34 -0500 | [diff] [blame] | 184 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
| 185 | extern int rv770_get_temp(struct radeon_device *rdev); |
| 186 | extern int evergreen_get_temp(struct radeon_device *rdev); |
| 187 | extern int sumo_get_temp(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 188 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 189 | /* |
| 190 | * Fences. |
| 191 | */ |
| 192 | struct radeon_fence_driver { |
| 193 | uint32_t scratch_reg; |
| 194 | atomic_t seq; |
| 195 | uint32_t last_seq; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 196 | unsigned long last_jiffies; |
| 197 | unsigned long last_timeout; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 198 | wait_queue_head_t queue; |
| 199 | rwlock_t lock; |
| 200 | struct list_head created; |
| 201 | struct list_head emited; |
| 202 | struct list_head signaled; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 203 | bool initialized; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 204 | }; |
| 205 | |
| 206 | struct radeon_fence { |
| 207 | struct radeon_device *rdev; |
| 208 | struct kref kref; |
| 209 | struct list_head list; |
| 210 | /* protected by radeon_fence.lock */ |
| 211 | uint32_t seq; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 212 | bool emited; |
| 213 | bool signaled; |
| 214 | }; |
| 215 | |
| 216 | int radeon_fence_driver_init(struct radeon_device *rdev); |
| 217 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
| 218 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
| 219 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
| 220 | void radeon_fence_process(struct radeon_device *rdev); |
| 221 | bool radeon_fence_signaled(struct radeon_fence *fence); |
| 222 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
| 223 | int radeon_fence_wait_next(struct radeon_device *rdev); |
| 224 | int radeon_fence_wait_last(struct radeon_device *rdev); |
| 225 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
| 226 | void radeon_fence_unref(struct radeon_fence **fence); |
| 227 | |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 228 | /* |
| 229 | * Tiling registers |
| 230 | */ |
| 231 | struct radeon_surface_reg { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 232 | struct radeon_bo *bo; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 233 | }; |
| 234 | |
| 235 | #define RADEON_GEM_MAX_SURFACES 8 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 236 | |
| 237 | /* |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 238 | * TTM. |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 239 | */ |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 240 | struct radeon_mman { |
| 241 | struct ttm_bo_global_ref bo_global_ref; |
Dave Airlie | ba4420c | 2010-03-09 10:56:52 +1000 | [diff] [blame] | 242 | struct drm_global_reference mem_global_ref; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 243 | struct ttm_bo_device bdev; |
Jerome Glisse | 0a0c759 | 2009-12-11 20:36:19 +0100 | [diff] [blame] | 244 | bool mem_global_referenced; |
| 245 | bool initialized; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 246 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 247 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 248 | struct radeon_bo { |
| 249 | /* Protected by gem.mutex */ |
| 250 | struct list_head list; |
| 251 | /* Protected by tbo.reserved */ |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 252 | u32 placements[3]; |
| 253 | struct ttm_placement placement; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 254 | struct ttm_buffer_object tbo; |
| 255 | struct ttm_bo_kmap_obj kmap; |
| 256 | unsigned pin_count; |
| 257 | void *kptr; |
| 258 | u32 tiling_flags; |
| 259 | u32 pitch; |
| 260 | int surface_reg; |
| 261 | /* Constant after initialization */ |
| 262 | struct radeon_device *rdev; |
Daniel Vetter | 441921d | 2011-02-18 17:59:16 +0100 | [diff] [blame] | 263 | struct drm_gem_object gem_base; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 264 | }; |
Daniel Vetter | 7e4d15d | 2011-02-18 17:59:17 +0100 | [diff] [blame] | 265 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 266 | |
| 267 | struct radeon_bo_list { |
Thomas Hellstrom | 147666f | 2010-11-17 12:38:32 +0000 | [diff] [blame] | 268 | struct ttm_validate_buffer tv; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 269 | struct radeon_bo *bo; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 270 | uint64_t gpu_offset; |
| 271 | unsigned rdomain; |
| 272 | unsigned wdomain; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 273 | u32 tiling_flags; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 274 | }; |
| 275 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 276 | /* |
| 277 | * GEM objects. |
| 278 | */ |
| 279 | struct radeon_gem { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 280 | struct mutex mutex; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 281 | struct list_head objects; |
| 282 | }; |
| 283 | |
| 284 | int radeon_gem_init(struct radeon_device *rdev); |
| 285 | void radeon_gem_fini(struct radeon_device *rdev); |
| 286 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 287 | int alignment, int initial_domain, |
| 288 | bool discardable, bool kernel, |
| 289 | struct drm_gem_object **obj); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 290 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
| 291 | uint64_t *gpu_addr); |
| 292 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
| 293 | |
Dave Airlie | ff72145b | 2011-02-07 12:16:14 +1000 | [diff] [blame] | 294 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
| 295 | struct drm_device *dev, |
| 296 | struct drm_mode_create_dumb *args); |
| 297 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
| 298 | struct drm_device *dev, |
| 299 | uint32_t handle, uint64_t *offset_p); |
| 300 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
| 301 | struct drm_device *dev, |
| 302 | uint32_t handle); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * GART structures, functions & helpers |
| 306 | */ |
| 307 | struct radeon_mc; |
| 308 | |
| 309 | struct radeon_gart_table_ram { |
| 310 | volatile uint32_t *ptr; |
| 311 | }; |
| 312 | |
| 313 | struct radeon_gart_table_vram { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 314 | struct radeon_bo *robj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 315 | volatile uint32_t *ptr; |
| 316 | }; |
| 317 | |
| 318 | union radeon_gart_table { |
| 319 | struct radeon_gart_table_ram ram; |
| 320 | struct radeon_gart_table_vram vram; |
| 321 | }; |
| 322 | |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 323 | #define RADEON_GPU_PAGE_SIZE 4096 |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 324 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
Matt Turner | a77f171 | 2009-10-14 00:34:41 -0400 | [diff] [blame] | 325 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 326 | struct radeon_gart { |
| 327 | dma_addr_t table_addr; |
| 328 | unsigned num_gpu_pages; |
| 329 | unsigned num_cpu_pages; |
| 330 | unsigned table_size; |
| 331 | union radeon_gart_table table; |
| 332 | struct page **pages; |
| 333 | dma_addr_t *pages_addr; |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 334 | bool *ttm_alloced; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 335 | bool ready; |
| 336 | }; |
| 337 | |
| 338 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
| 339 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
| 340 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
| 341 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
| 342 | int radeon_gart_init(struct radeon_device *rdev); |
| 343 | void radeon_gart_fini(struct radeon_device *rdev); |
| 344 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
| 345 | int pages); |
| 346 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
Konrad Rzeszutek Wilk | c39d351 | 2010-12-02 11:04:29 -0500 | [diff] [blame] | 347 | int pages, struct page **pagelist, |
| 348 | dma_addr_t *dma_addr); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 349 | |
| 350 | |
| 351 | /* |
| 352 | * GPU MC structures, functions & helpers |
| 353 | */ |
| 354 | struct radeon_mc { |
| 355 | resource_size_t aper_size; |
| 356 | resource_size_t aper_base; |
| 357 | resource_size_t agp_base; |
Dave Airlie | 7a50f01 | 2009-07-21 20:39:30 +1000 | [diff] [blame] | 358 | /* for some chips with <= 32MB we need to lie |
| 359 | * about vram size near mc fb location */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 360 | u64 mc_vram_size; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 361 | u64 visible_vram_size; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 362 | u64 gtt_size; |
| 363 | u64 gtt_start; |
| 364 | u64 gtt_end; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 365 | u64 vram_start; |
| 366 | u64 vram_end; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 367 | unsigned vram_width; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 368 | u64 real_vram_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 369 | int vram_mtrr; |
| 370 | bool vram_is_ddr; |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 371 | bool igp_sideport_enabled; |
Alex Deucher | 8d369bb | 2010-07-15 10:51:10 -0400 | [diff] [blame] | 372 | u64 gtt_base_align; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 373 | }; |
| 374 | |
Alex Deucher | 06b6476 | 2010-01-05 11:27:29 -0500 | [diff] [blame] | 375 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
| 376 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 377 | |
| 378 | /* |
| 379 | * GPU scratch registers structures, functions & helpers |
| 380 | */ |
| 381 | struct radeon_scratch { |
| 382 | unsigned num_reg; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 383 | uint32_t reg_base; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 384 | bool free[32]; |
| 385 | uint32_t reg[32]; |
| 386 | }; |
| 387 | |
| 388 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
| 389 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
| 390 | |
| 391 | |
| 392 | /* |
| 393 | * IRQS. |
| 394 | */ |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 395 | |
| 396 | struct radeon_unpin_work { |
| 397 | struct work_struct work; |
| 398 | struct radeon_device *rdev; |
| 399 | int crtc_id; |
| 400 | struct radeon_fence *fence; |
| 401 | struct drm_pending_vblank_event *event; |
| 402 | struct radeon_bo *old_rbo; |
| 403 | u64 new_crtc_base; |
| 404 | }; |
| 405 | |
| 406 | struct r500_irq_stat_regs { |
| 407 | u32 disp_int; |
| 408 | }; |
| 409 | |
| 410 | struct r600_irq_stat_regs { |
| 411 | u32 disp_int; |
| 412 | u32 disp_int_cont; |
| 413 | u32 disp_int_cont2; |
| 414 | u32 d1grph_int; |
| 415 | u32 d2grph_int; |
| 416 | }; |
| 417 | |
| 418 | struct evergreen_irq_stat_regs { |
| 419 | u32 disp_int; |
| 420 | u32 disp_int_cont; |
| 421 | u32 disp_int_cont2; |
| 422 | u32 disp_int_cont3; |
| 423 | u32 disp_int_cont4; |
| 424 | u32 disp_int_cont5; |
| 425 | u32 d1grph_int; |
| 426 | u32 d2grph_int; |
| 427 | u32 d3grph_int; |
| 428 | u32 d4grph_int; |
| 429 | u32 d5grph_int; |
| 430 | u32 d6grph_int; |
| 431 | }; |
| 432 | |
| 433 | union radeon_irq_stat_regs { |
| 434 | struct r500_irq_stat_regs r500; |
| 435 | struct r600_irq_stat_regs r600; |
| 436 | struct evergreen_irq_stat_regs evergreen; |
| 437 | }; |
| 438 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 439 | struct radeon_irq { |
| 440 | bool installed; |
| 441 | bool sw_int; |
| 442 | /* FIXME: use a define max crtc rather than hardcode it */ |
Alex Deucher | 45f9a39 | 2010-03-24 13:55:51 -0400 | [diff] [blame] | 443 | bool crtc_vblank_int[6]; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 444 | bool pflip[6]; |
Rafał Miłecki | 73a6d3f | 2010-01-08 00:22:47 +0100 | [diff] [blame] | 445 | wait_queue_head_t vblank_queue; |
Alex Deucher | b500f68 | 2009-12-03 13:08:53 -0500 | [diff] [blame] | 446 | /* FIXME: use defines for max hpd/dacs */ |
| 447 | bool hpd[6]; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 448 | bool gui_idle; |
| 449 | bool gui_idle_acked; |
| 450 | wait_queue_head_t idle_queue; |
Christian Koenig | f259493 | 2010-04-10 03:13:16 +0200 | [diff] [blame] | 451 | /* FIXME: use defines for max HDMI blocks */ |
| 452 | bool hdmi[2]; |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 453 | spinlock_t sw_lock; |
| 454 | int sw_refcount; |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 455 | union radeon_irq_stat_regs stat_regs; |
| 456 | spinlock_t pflip_lock[6]; |
| 457 | int pflip_refcount[6]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 458 | }; |
| 459 | |
| 460 | int radeon_irq_kms_init(struct radeon_device *rdev); |
| 461 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
Dave Airlie | 1614f8b | 2009-12-01 16:04:56 +1000 | [diff] [blame] | 462 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
| 463 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 464 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
| 465 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 466 | |
| 467 | /* |
| 468 | * CP & ring. |
| 469 | */ |
| 470 | struct radeon_ib { |
| 471 | struct list_head list; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 472 | unsigned idx; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 473 | uint64_t gpu_addr; |
| 474 | struct radeon_fence *fence; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 475 | uint32_t *ptr; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 476 | uint32_t length_dw; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 477 | bool free; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 478 | }; |
| 479 | |
Dave Airlie | ecb114a | 2009-09-15 11:12:56 +1000 | [diff] [blame] | 480 | /* |
| 481 | * locking - |
| 482 | * mutex protects scheduled_ibs, ready, alloc_bm |
| 483 | */ |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 484 | struct radeon_ib_pool { |
| 485 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 486 | struct radeon_bo *robj; |
Jerome Glisse | 9f93ed3 | 2010-01-28 18:22:31 +0100 | [diff] [blame] | 487 | struct list_head bogus_ib; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 488 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
| 489 | bool ready; |
Jerome Glisse | e821767 | 2010-02-15 21:36:13 +0100 | [diff] [blame] | 490 | unsigned head_id; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 491 | }; |
| 492 | |
| 493 | struct radeon_cp { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 494 | struct radeon_bo *ring_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 495 | volatile uint32_t *ring; |
| 496 | unsigned rptr; |
| 497 | unsigned wptr; |
| 498 | unsigned wptr_old; |
| 499 | unsigned ring_size; |
| 500 | unsigned ring_free_dw; |
| 501 | int count_dw; |
| 502 | uint64_t gpu_addr; |
| 503 | uint32_t align_mask; |
| 504 | uint32_t ptr_mask; |
| 505 | struct mutex mutex; |
| 506 | bool ready; |
| 507 | }; |
| 508 | |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 509 | /* |
| 510 | * R6xx+ IH ring |
| 511 | */ |
| 512 | struct r600_ih { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 513 | struct radeon_bo *ring_obj; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 514 | volatile uint32_t *ring; |
| 515 | unsigned rptr; |
| 516 | unsigned wptr; |
| 517 | unsigned wptr_old; |
| 518 | unsigned ring_size; |
| 519 | uint64_t gpu_addr; |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 520 | uint32_t ptr_mask; |
| 521 | spinlock_t lock; |
| 522 | bool enabled; |
| 523 | }; |
| 524 | |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 525 | struct r600_blit { |
Jerome Glisse | ff82f05 | 2010-01-22 15:19:00 +0100 | [diff] [blame] | 526 | struct mutex mutex; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 527 | struct radeon_bo *shader_obj; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 528 | u64 shader_gpu_addr; |
| 529 | u32 vs_offset, ps_offset; |
| 530 | u32 state_offset; |
| 531 | u32 state_len; |
| 532 | u32 vb_used, vb_total; |
| 533 | struct radeon_ib *vb_ib; |
| 534 | }; |
| 535 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 536 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
| 537 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
| 538 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
| 539 | int radeon_ib_pool_init(struct radeon_device *rdev); |
| 540 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
| 541 | int radeon_ib_test(struct radeon_device *rdev); |
Jerome Glisse | 9f93ed3 | 2010-01-28 18:22:31 +0100 | [diff] [blame] | 542 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 543 | /* Ring access between begin & end cannot sleep */ |
| 544 | void radeon_ring_free_size(struct radeon_device *rdev); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 545 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 546 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
Matthew Garrett | 91700f3 | 2010-04-30 15:24:17 -0400 | [diff] [blame] | 547 | void radeon_ring_commit(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 548 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
| 549 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
| 550 | int radeon_ring_test(struct radeon_device *rdev); |
| 551 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
| 552 | void radeon_ring_fini(struct radeon_device *rdev); |
| 553 | |
| 554 | |
| 555 | /* |
| 556 | * CS. |
| 557 | */ |
| 558 | struct radeon_cs_reloc { |
| 559 | struct drm_gem_object *gobj; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 560 | struct radeon_bo *robj; |
| 561 | struct radeon_bo_list lobj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 562 | uint32_t handle; |
| 563 | uint32_t flags; |
| 564 | }; |
| 565 | |
| 566 | struct radeon_cs_chunk { |
| 567 | uint32_t chunk_id; |
| 568 | uint32_t length_dw; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 569 | int kpage_idx[2]; |
| 570 | uint32_t *kpage[2]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 571 | uint32_t *kdata; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 572 | void __user *user_ptr; |
| 573 | int last_copied_page; |
| 574 | int last_page_index; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 575 | }; |
| 576 | |
| 577 | struct radeon_cs_parser { |
Jerome Glisse | c8c15ff | 2010-01-18 13:01:36 +0100 | [diff] [blame] | 578 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 579 | struct radeon_device *rdev; |
| 580 | struct drm_file *filp; |
| 581 | /* chunks */ |
| 582 | unsigned nchunks; |
| 583 | struct radeon_cs_chunk *chunks; |
| 584 | uint64_t *chunks_array; |
| 585 | /* IB */ |
| 586 | unsigned idx; |
| 587 | /* relocations */ |
| 588 | unsigned nrelocs; |
| 589 | struct radeon_cs_reloc *relocs; |
| 590 | struct radeon_cs_reloc **relocs_ptr; |
| 591 | struct list_head validated; |
| 592 | /* indices of various chunks */ |
| 593 | int chunk_ib_idx; |
| 594 | int chunk_relocs_idx; |
| 595 | struct radeon_ib *ib; |
| 596 | void *track; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 597 | unsigned family; |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 598 | int parser_error; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 599 | }; |
| 600 | |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 601 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
| 602 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 603 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
Dave Airlie | 513bcb4 | 2009-09-23 16:56:27 +1000 | [diff] [blame] | 604 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 605 | struct radeon_cs_packet { |
| 606 | unsigned idx; |
| 607 | unsigned type; |
| 608 | unsigned reg; |
| 609 | unsigned opcode; |
| 610 | int count; |
| 611 | unsigned one_reg_wr; |
| 612 | }; |
| 613 | |
| 614 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
| 615 | struct radeon_cs_packet *pkt, |
| 616 | unsigned idx, unsigned reg); |
| 617 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
| 618 | struct radeon_cs_packet *pkt); |
| 619 | |
| 620 | |
| 621 | /* |
| 622 | * AGP |
| 623 | */ |
| 624 | int radeon_agp_init(struct radeon_device *rdev); |
Dave Airlie | 0ebf171 | 2009-11-05 15:39:10 +1000 | [diff] [blame] | 625 | void radeon_agp_resume(struct radeon_device *rdev); |
Jerome Glisse | 10b0612 | 2010-05-21 18:48:54 +0200 | [diff] [blame] | 626 | void radeon_agp_suspend(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 627 | void radeon_agp_fini(struct radeon_device *rdev); |
| 628 | |
| 629 | |
| 630 | /* |
| 631 | * Writeback |
| 632 | */ |
| 633 | struct radeon_wb { |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 634 | struct radeon_bo *wb_obj; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 635 | volatile uint32_t *wb; |
| 636 | uint64_t gpu_addr; |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 637 | bool enabled; |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 638 | bool use_event; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 639 | }; |
| 640 | |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 641 | #define RADEON_WB_SCRATCH_OFFSET 0 |
| 642 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
Alex Deucher | 0c88a02 | 2011-03-02 20:07:31 -0500 | [diff] [blame] | 643 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
| 644 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 645 | #define R600_WB_IH_WPTR_OFFSET 2048 |
Alex Deucher | d0f8a85 | 2010-09-04 05:04:34 -0400 | [diff] [blame] | 646 | #define R600_WB_EVENT_OFFSET 3072 |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 647 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 648 | /** |
| 649 | * struct radeon_pm - power management datas |
| 650 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
| 651 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
| 652 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
| 653 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
| 654 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
| 655 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
| 656 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
| 657 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
| 658 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 659 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 660 | * @needed_bandwidth: current bandwidth needs |
| 661 | * |
| 662 | * It keeps track of various data needed to take powermanagement decision. |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 663 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 664 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
| 665 | * (type of memory, bus size, efficiency, ...) |
| 666 | */ |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 667 | |
| 668 | enum radeon_pm_method { |
| 669 | PM_METHOD_PROFILE, |
| 670 | PM_METHOD_DYNPM, |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 671 | }; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 672 | |
| 673 | enum radeon_dynpm_state { |
| 674 | DYNPM_STATE_DISABLED, |
| 675 | DYNPM_STATE_MINIMUM, |
| 676 | DYNPM_STATE_PAUSED, |
Rafael J. Wysocki | 3f53eb6 | 2010-06-17 23:02:27 +0000 | [diff] [blame] | 677 | DYNPM_STATE_ACTIVE, |
| 678 | DYNPM_STATE_SUSPENDED, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 679 | }; |
| 680 | enum radeon_dynpm_action { |
| 681 | DYNPM_ACTION_NONE, |
| 682 | DYNPM_ACTION_MINIMUM, |
| 683 | DYNPM_ACTION_DOWNCLOCK, |
| 684 | DYNPM_ACTION_UPCLOCK, |
| 685 | DYNPM_ACTION_DEFAULT |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 686 | }; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 687 | |
| 688 | enum radeon_voltage_type { |
| 689 | VOLTAGE_NONE = 0, |
| 690 | VOLTAGE_GPIO, |
| 691 | VOLTAGE_VDDC, |
| 692 | VOLTAGE_SW |
| 693 | }; |
| 694 | |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 695 | enum radeon_pm_state_type { |
| 696 | POWER_STATE_TYPE_DEFAULT, |
| 697 | POWER_STATE_TYPE_POWERSAVE, |
| 698 | POWER_STATE_TYPE_BATTERY, |
| 699 | POWER_STATE_TYPE_BALANCED, |
| 700 | POWER_STATE_TYPE_PERFORMANCE, |
| 701 | }; |
| 702 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 703 | enum radeon_pm_profile_type { |
| 704 | PM_PROFILE_DEFAULT, |
| 705 | PM_PROFILE_AUTO, |
| 706 | PM_PROFILE_LOW, |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 707 | PM_PROFILE_MID, |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 708 | PM_PROFILE_HIGH, |
| 709 | }; |
| 710 | |
| 711 | #define PM_PROFILE_DEFAULT_IDX 0 |
| 712 | #define PM_PROFILE_LOW_SH_IDX 1 |
Alex Deucher | c9e75b2 | 2010-06-02 17:56:01 -0400 | [diff] [blame] | 713 | #define PM_PROFILE_MID_SH_IDX 2 |
| 714 | #define PM_PROFILE_HIGH_SH_IDX 3 |
| 715 | #define PM_PROFILE_LOW_MH_IDX 4 |
| 716 | #define PM_PROFILE_MID_MH_IDX 5 |
| 717 | #define PM_PROFILE_HIGH_MH_IDX 6 |
| 718 | #define PM_PROFILE_MAX 7 |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 719 | |
| 720 | struct radeon_pm_profile { |
| 721 | int dpms_off_ps_idx; |
| 722 | int dpms_on_ps_idx; |
| 723 | int dpms_off_cm_idx; |
| 724 | int dpms_on_cm_idx; |
Alex Deucher | 516d0e4 | 2009-12-23 14:28:05 -0500 | [diff] [blame] | 725 | }; |
| 726 | |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 727 | enum radeon_int_thermal_type { |
| 728 | THERMAL_TYPE_NONE, |
| 729 | THERMAL_TYPE_RV6XX, |
| 730 | THERMAL_TYPE_RV770, |
| 731 | THERMAL_TYPE_EVERGREEN, |
Alex Deucher | e33df25 | 2010-11-22 17:56:32 -0500 | [diff] [blame] | 732 | THERMAL_TYPE_SUMO, |
Alex Deucher | 4fddba1 | 2011-01-06 21:19:22 -0500 | [diff] [blame] | 733 | THERMAL_TYPE_NI, |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 734 | }; |
| 735 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 736 | struct radeon_voltage { |
| 737 | enum radeon_voltage_type type; |
| 738 | /* gpio voltage */ |
| 739 | struct radeon_gpio_rec gpio; |
| 740 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
| 741 | bool active_high; /* voltage drop is active when bit is high */ |
| 742 | /* VDDC voltage */ |
| 743 | u8 vddc_id; /* index into vddc voltage table */ |
| 744 | u8 vddci_id; /* index into vddci voltage table */ |
| 745 | bool vddci_enabled; |
| 746 | /* r6xx+ sw */ |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 747 | u16 voltage; |
| 748 | /* evergreen+ vddci */ |
| 749 | u16 vddci; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 750 | }; |
| 751 | |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 752 | /* clock mode flags */ |
| 753 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
| 754 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 755 | struct radeon_pm_clock_info { |
| 756 | /* memory clock */ |
| 757 | u32 mclk; |
| 758 | /* engine clock */ |
| 759 | u32 sclk; |
| 760 | /* voltage info */ |
| 761 | struct radeon_voltage voltage; |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 762 | /* standardized clock flags */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 763 | u32 flags; |
| 764 | }; |
| 765 | |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 766 | /* state flags */ |
Alex Deucher | d731117 | 2010-05-03 01:13:14 -0400 | [diff] [blame] | 767 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 768 | |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 769 | struct radeon_power_state { |
Alex Deucher | 0ec0e74 | 2009-12-23 13:21:58 -0500 | [diff] [blame] | 770 | enum radeon_pm_state_type type; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 771 | /* XXX: use a define for num clock modes */ |
| 772 | struct radeon_pm_clock_info clock_info[8]; |
| 773 | /* number of valid clock modes in this power state */ |
| 774 | int num_clock_modes; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 775 | struct radeon_pm_clock_info *default_clock_mode; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 776 | /* standardized state flags */ |
| 777 | u32 flags; |
Alex Deucher | 79daedc | 2010-04-22 14:25:19 -0400 | [diff] [blame] | 778 | u32 misc; /* vbios specific flags */ |
| 779 | u32 misc2; /* vbios specific flags */ |
| 780 | int pcie_lanes; /* pcie lanes */ |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 781 | }; |
| 782 | |
Rafał Miłecki | 2745932 | 2010-02-11 22:16:36 +0000 | [diff] [blame] | 783 | /* |
| 784 | * Some modes are overclocked by very low value, accept them |
| 785 | */ |
| 786 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
| 787 | |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 788 | struct radeon_pm { |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 789 | struct mutex mutex; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 790 | u32 active_crtcs; |
| 791 | int active_crtc_count; |
Rafał Miłecki | c913e23 | 2009-12-22 23:02:16 +0100 | [diff] [blame] | 792 | int req_vblank; |
Rafał Miłecki | 839461d | 2010-03-02 22:06:51 +0100 | [diff] [blame] | 793 | bool vblank_sync; |
Alex Deucher | 2031f77 | 2010-04-22 12:52:11 -0400 | [diff] [blame] | 794 | bool gui_idle; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 795 | fixed20_12 max_bandwidth; |
| 796 | fixed20_12 igp_sideport_mclk; |
| 797 | fixed20_12 igp_system_mclk; |
| 798 | fixed20_12 igp_ht_link_clk; |
| 799 | fixed20_12 igp_ht_link_width; |
| 800 | fixed20_12 k8_bandwidth; |
| 801 | fixed20_12 sideport_bandwidth; |
| 802 | fixed20_12 ht_bandwidth; |
| 803 | fixed20_12 core_bandwidth; |
| 804 | fixed20_12 sclk; |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 805 | fixed20_12 mclk; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 806 | fixed20_12 needed_bandwidth; |
Alex Deucher | 0975b16 | 2011-02-02 18:42:03 -0500 | [diff] [blame] | 807 | struct radeon_power_state *power_state; |
Alex Deucher | 56278a8 | 2009-12-28 13:58:44 -0500 | [diff] [blame] | 808 | /* number of valid power states */ |
| 809 | int num_power_states; |
Alex Deucher | a48b9b4 | 2010-04-22 14:03:55 -0400 | [diff] [blame] | 810 | int current_power_state_index; |
| 811 | int current_clock_mode_index; |
| 812 | int requested_power_state_index; |
| 813 | int requested_clock_mode_index; |
| 814 | int default_power_state_index; |
| 815 | u32 current_sclk; |
| 816 | u32 current_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 817 | u16 current_vddc; |
| 818 | u16 current_vddci; |
Alex Deucher | 9ace9f7 | 2011-01-06 21:19:26 -0500 | [diff] [blame] | 819 | u32 default_sclk; |
| 820 | u32 default_mclk; |
Alex Deucher | 2feea49 | 2011-04-12 14:49:24 -0400 | [diff] [blame] | 821 | u16 default_vddc; |
| 822 | u16 default_vddci; |
Alex Deucher | 29fb52c | 2010-03-11 10:01:17 -0500 | [diff] [blame] | 823 | struct radeon_i2c_chan *i2c_bus; |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 824 | /* selected pm method */ |
| 825 | enum radeon_pm_method pm_method; |
| 826 | /* dynpm power management */ |
| 827 | struct delayed_work dynpm_idle_work; |
| 828 | enum radeon_dynpm_state dynpm_state; |
| 829 | enum radeon_dynpm_action dynpm_planned_action; |
| 830 | unsigned long dynpm_action_timeout; |
| 831 | bool dynpm_can_upclock; |
| 832 | bool dynpm_can_downclock; |
| 833 | /* profile-based power management */ |
| 834 | enum radeon_pm_profile_type profile; |
| 835 | int profile_index; |
| 836 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
Alex Deucher | 21a8122 | 2010-07-02 12:58:16 -0400 | [diff] [blame] | 837 | /* internal thermal controller on rv6xx+ */ |
| 838 | enum radeon_int_thermal_type int_thermal_type; |
| 839 | struct device *int_hwmon_dev; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 840 | }; |
| 841 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 842 | |
| 843 | /* |
| 844 | * Benchmarking |
| 845 | */ |
| 846 | void radeon_benchmark(struct radeon_device *rdev); |
| 847 | |
| 848 | |
| 849 | /* |
Michel Dänzer | ecc0b32 | 2009-07-21 11:23:57 +0200 | [diff] [blame] | 850 | * Testing |
| 851 | */ |
| 852 | void radeon_test_moves(struct radeon_device *rdev); |
| 853 | |
| 854 | |
| 855 | /* |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 856 | * Debugfs |
| 857 | */ |
| 858 | int radeon_debugfs_add_files(struct radeon_device *rdev, |
| 859 | struct drm_info_list *files, |
| 860 | unsigned nfiles); |
| 861 | int radeon_debugfs_fence_init(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 862 | |
| 863 | |
| 864 | /* |
| 865 | * ASIC specific functions. |
| 866 | */ |
| 867 | struct radeon_asic { |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 868 | int (*init)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 869 | void (*fini)(struct radeon_device *rdev); |
| 870 | int (*resume)(struct radeon_device *rdev); |
| 871 | int (*suspend)(struct radeon_device *rdev); |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 872 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 873 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 874 | int (*asic_reset)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 875 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
| 876 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
| 877 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
| 878 | void (*cp_fini)(struct radeon_device *rdev); |
| 879 | void (*cp_disable)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 880 | void (*cp_commit)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 881 | void (*ring_start)(struct radeon_device *rdev); |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 882 | int (*ring_test)(struct radeon_device *rdev); |
| 883 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 884 | int (*irq_set)(struct radeon_device *rdev); |
| 885 | int (*irq_process)(struct radeon_device *rdev); |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 886 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 887 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
| 888 | int (*cs_parse)(struct radeon_cs_parser *p); |
| 889 | int (*copy_blit)(struct radeon_device *rdev, |
| 890 | uint64_t src_offset, |
| 891 | uint64_t dst_offset, |
| 892 | unsigned num_pages, |
| 893 | struct radeon_fence *fence); |
| 894 | int (*copy_dma)(struct radeon_device *rdev, |
| 895 | uint64_t src_offset, |
| 896 | uint64_t dst_offset, |
| 897 | unsigned num_pages, |
| 898 | struct radeon_fence *fence); |
| 899 | int (*copy)(struct radeon_device *rdev, |
| 900 | uint64_t src_offset, |
| 901 | uint64_t dst_offset, |
| 902 | unsigned num_pages, |
| 903 | struct radeon_fence *fence); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 904 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 905 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 906 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 907 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 908 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 909 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
| 910 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 911 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
| 912 | uint32_t tiling_flags, uint32_t pitch, |
| 913 | uint32_t offset, uint32_t obj_size); |
Daniel Vetter | 9479c54 | 2010-03-11 21:19:16 +0000 | [diff] [blame] | 914 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 915 | void (*bandwidth_update)(struct radeon_device *rdev); |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 916 | void (*hpd_init)(struct radeon_device *rdev); |
| 917 | void (*hpd_fini)(struct radeon_device *rdev); |
| 918 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
| 919 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
Jerome Glisse | 062b389 | 2010-02-04 20:36:39 +0100 | [diff] [blame] | 920 | /* ioctl hw specific callback. Some hw might want to perform special |
| 921 | * operation on specific ioctl. For instance on wait idle some hw |
| 922 | * might want to perform and HDP flush through MMIO as it seems that |
| 923 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
| 924 | * through ring. |
| 925 | */ |
| 926 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 927 | bool (*gui_idle)(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 928 | /* power management */ |
Alex Deucher | 49e02b7 | 2010-04-23 17:57:27 -0400 | [diff] [blame] | 929 | void (*pm_misc)(struct radeon_device *rdev); |
| 930 | void (*pm_prepare)(struct radeon_device *rdev); |
| 931 | void (*pm_finish)(struct radeon_device *rdev); |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 932 | void (*pm_init_profile)(struct radeon_device *rdev); |
| 933 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 934 | /* pageflipping */ |
| 935 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
| 936 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
| 937 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 938 | }; |
| 939 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 940 | /* |
| 941 | * Asic structures |
| 942 | */ |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 943 | struct r100_gpu_lockup { |
| 944 | unsigned long last_jiffies; |
| 945 | u32 last_cp_rptr; |
| 946 | }; |
| 947 | |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 948 | struct r100_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 949 | const unsigned *reg_safe_bm; |
| 950 | unsigned reg_safe_bm_size; |
| 951 | u32 hdp_cntl; |
| 952 | struct r100_gpu_lockup lockup; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 953 | }; |
| 954 | |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 955 | struct r300_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 956 | const unsigned *reg_safe_bm; |
| 957 | unsigned reg_safe_bm_size; |
| 958 | u32 resync_scratch; |
| 959 | u32 hdp_cntl; |
| 960 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 961 | }; |
| 962 | |
| 963 | struct r600_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 964 | unsigned max_pipes; |
| 965 | unsigned max_tile_pipes; |
| 966 | unsigned max_simds; |
| 967 | unsigned max_backends; |
| 968 | unsigned max_gprs; |
| 969 | unsigned max_threads; |
| 970 | unsigned max_stack_entries; |
| 971 | unsigned max_hw_contexts; |
| 972 | unsigned max_gs_threads; |
| 973 | unsigned sx_max_export_size; |
| 974 | unsigned sx_max_export_pos_size; |
| 975 | unsigned sx_max_export_smx_size; |
| 976 | unsigned sq_num_cf_insts; |
| 977 | unsigned tiling_nbanks; |
| 978 | unsigned tiling_npipes; |
| 979 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 980 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 981 | unsigned backend_map; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 982 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 983 | }; |
| 984 | |
| 985 | struct rv770_asic { |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 986 | unsigned max_pipes; |
| 987 | unsigned max_tile_pipes; |
| 988 | unsigned max_simds; |
| 989 | unsigned max_backends; |
| 990 | unsigned max_gprs; |
| 991 | unsigned max_threads; |
| 992 | unsigned max_stack_entries; |
| 993 | unsigned max_hw_contexts; |
| 994 | unsigned max_gs_threads; |
| 995 | unsigned sx_max_export_size; |
| 996 | unsigned sx_max_export_pos_size; |
| 997 | unsigned sx_max_export_smx_size; |
| 998 | unsigned sq_num_cf_insts; |
| 999 | unsigned sx_num_of_sets; |
| 1000 | unsigned sc_prim_fifo_size; |
| 1001 | unsigned sc_hiz_tile_fifo_size; |
| 1002 | unsigned sc_earlyz_tile_fifo_fize; |
| 1003 | unsigned tiling_nbanks; |
| 1004 | unsigned tiling_npipes; |
| 1005 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1006 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1007 | unsigned backend_map; |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1008 | struct r100_gpu_lockup lockup; |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1009 | }; |
| 1010 | |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1011 | struct evergreen_asic { |
| 1012 | unsigned num_ses; |
| 1013 | unsigned max_pipes; |
| 1014 | unsigned max_tile_pipes; |
| 1015 | unsigned max_simds; |
| 1016 | unsigned max_backends; |
| 1017 | unsigned max_gprs; |
| 1018 | unsigned max_threads; |
| 1019 | unsigned max_stack_entries; |
| 1020 | unsigned max_hw_contexts; |
| 1021 | unsigned max_gs_threads; |
| 1022 | unsigned sx_max_export_size; |
| 1023 | unsigned sx_max_export_pos_size; |
| 1024 | unsigned sx_max_export_smx_size; |
| 1025 | unsigned sq_num_cf_insts; |
| 1026 | unsigned sx_num_of_sets; |
| 1027 | unsigned sc_prim_fifo_size; |
| 1028 | unsigned sc_hiz_tile_fifo_size; |
| 1029 | unsigned sc_earlyz_tile_fifo_size; |
| 1030 | unsigned tiling_nbanks; |
| 1031 | unsigned tiling_npipes; |
| 1032 | unsigned tiling_group_size; |
Alex Deucher | e7aeeba | 2010-06-04 13:10:12 -0400 | [diff] [blame] | 1033 | unsigned tile_config; |
Alex Deucher | e55b942 | 2011-07-15 19:53:52 +0000 | [diff] [blame] | 1034 | unsigned backend_map; |
Alex Deucher | 17db704 | 2010-12-21 16:05:39 -0500 | [diff] [blame] | 1035 | struct r100_gpu_lockup lockup; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1036 | }; |
| 1037 | |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1038 | struct cayman_asic { |
| 1039 | unsigned max_shader_engines; |
| 1040 | unsigned max_pipes_per_simd; |
| 1041 | unsigned max_tile_pipes; |
| 1042 | unsigned max_simds_per_se; |
| 1043 | unsigned max_backends_per_se; |
| 1044 | unsigned max_texture_channel_caches; |
| 1045 | unsigned max_gprs; |
| 1046 | unsigned max_threads; |
| 1047 | unsigned max_gs_threads; |
| 1048 | unsigned max_stack_entries; |
| 1049 | unsigned sx_num_of_sets; |
| 1050 | unsigned sx_max_export_size; |
| 1051 | unsigned sx_max_export_pos_size; |
| 1052 | unsigned sx_max_export_smx_size; |
| 1053 | unsigned max_hw_contexts; |
| 1054 | unsigned sq_num_cf_insts; |
| 1055 | unsigned sc_prim_fifo_size; |
| 1056 | unsigned sc_hiz_tile_fifo_size; |
| 1057 | unsigned sc_earlyz_tile_fifo_size; |
| 1058 | |
| 1059 | unsigned num_shader_engines; |
| 1060 | unsigned num_shader_pipes_per_simd; |
| 1061 | unsigned num_tile_pipes; |
| 1062 | unsigned num_simds_per_se; |
| 1063 | unsigned num_backends_per_se; |
| 1064 | unsigned backend_disable_mask_per_asic; |
| 1065 | unsigned backend_map; |
| 1066 | unsigned num_texture_channel_caches; |
| 1067 | unsigned mem_max_burst_length_bytes; |
| 1068 | unsigned mem_row_size_in_kb; |
| 1069 | unsigned shader_engine_tile_size; |
| 1070 | unsigned num_gpus; |
| 1071 | unsigned multi_gpu_tile_size; |
| 1072 | |
| 1073 | unsigned tile_config; |
| 1074 | struct r100_gpu_lockup lockup; |
| 1075 | }; |
| 1076 | |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1077 | union radeon_asic_config { |
| 1078 | struct r300_asic r300; |
Dave Airlie | 551ebd8 | 2009-09-01 15:25:57 +1000 | [diff] [blame] | 1079 | struct r100_asic r100; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1080 | struct r600_asic r600; |
| 1081 | struct rv770_asic rv770; |
Alex Deucher | 32fcdbf | 2010-03-24 13:33:47 -0400 | [diff] [blame] | 1082 | struct evergreen_asic evergreen; |
Alex Deucher | fecf1d0 | 2011-03-02 20:07:29 -0500 | [diff] [blame] | 1083 | struct cayman_asic cayman; |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1084 | }; |
| 1085 | |
Daniel Vetter | 0a10c85 | 2010-03-11 21:19:14 +0000 | [diff] [blame] | 1086 | /* |
| 1087 | * asic initizalization from radeon_asic.c |
| 1088 | */ |
| 1089 | void radeon_agp_disable(struct radeon_device *rdev); |
| 1090 | int radeon_asic_init(struct radeon_device *rdev); |
| 1091 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1092 | |
| 1093 | /* |
| 1094 | * IOCTL. |
| 1095 | */ |
| 1096 | int radeon_gem_info_ioctl(struct drm_device *dev, void *data, |
| 1097 | struct drm_file *filp); |
| 1098 | int radeon_gem_create_ioctl(struct drm_device *dev, void *data, |
| 1099 | struct drm_file *filp); |
| 1100 | int radeon_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 1101 | struct drm_file *file_priv); |
| 1102 | int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 1103 | struct drm_file *file_priv); |
| 1104 | int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 1105 | struct drm_file *file_priv); |
| 1106 | int radeon_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 1107 | struct drm_file *file_priv); |
| 1108 | int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1109 | struct drm_file *filp); |
| 1110 | int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1111 | struct drm_file *filp); |
| 1112 | int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 1113 | struct drm_file *filp); |
| 1114 | int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, |
| 1115 | struct drm_file *filp); |
| 1116 | int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1117 | int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
| 1118 | struct drm_file *filp); |
| 1119 | int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, |
| 1120 | struct drm_file *filp); |
Marek Olšák | d3ed740 | 2011-08-07 20:39:04 +0000 | [diff] [blame] | 1121 | int radeon_gem_wait_ioctl(struct drm_device *dev, void *data, |
| 1122 | struct drm_file *filp); |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1123 | |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1124 | /* VRAM scratch page for HDP bug */ |
| 1125 | struct r700_vram_scratch { |
| 1126 | struct radeon_bo *robj; |
| 1127 | volatile uint32_t *ptr; |
| 1128 | }; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1129 | |
| 1130 | /* |
| 1131 | * Core structure, functions and helpers. |
| 1132 | */ |
| 1133 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
| 1134 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
| 1135 | |
| 1136 | struct radeon_device { |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1137 | struct device *dev; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1138 | struct drm_device *ddev; |
| 1139 | struct pci_dev *pdev; |
| 1140 | /* ASIC */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1141 | union radeon_asic_config config; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1142 | enum radeon_family family; |
| 1143 | unsigned long flags; |
| 1144 | int usec_timeout; |
| 1145 | enum radeon_pll_errata pll_errata; |
| 1146 | int num_gb_pipes; |
Alex Deucher | f779b3e | 2009-08-19 19:11:39 -0400 | [diff] [blame] | 1147 | int num_z_pipes; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1148 | int disp_priority; |
| 1149 | /* BIOS */ |
| 1150 | uint8_t *bios; |
| 1151 | bool is_atom_bios; |
| 1152 | uint16_t bios_header_start; |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1153 | struct radeon_bo *stollen_vga_memory; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1154 | /* Register mmio */ |
Dave Airlie | 4c9bc75 | 2009-06-29 18:29:12 +1000 | [diff] [blame] | 1155 | resource_size_t rmmio_base; |
| 1156 | resource_size_t rmmio_size; |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 1157 | void __iomem *rmmio; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1158 | radeon_rreg_t mc_rreg; |
| 1159 | radeon_wreg_t mc_wreg; |
| 1160 | radeon_rreg_t pll_rreg; |
| 1161 | radeon_wreg_t pll_wreg; |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1162 | uint32_t pcie_reg_mask; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1163 | radeon_rreg_t pciep_rreg; |
| 1164 | radeon_wreg_t pciep_wreg; |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1165 | /* io port */ |
| 1166 | void __iomem *rio_mem; |
| 1167 | resource_size_t rio_mem_size; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1168 | struct radeon_clock clock; |
| 1169 | struct radeon_mc mc; |
| 1170 | struct radeon_gart gart; |
| 1171 | struct radeon_mode_info mode_info; |
| 1172 | struct radeon_scratch scratch; |
| 1173 | struct radeon_mman mman; |
| 1174 | struct radeon_fence_driver fence_drv; |
| 1175 | struct radeon_cp cp; |
Alex Deucher | 0c88a02 | 2011-03-02 20:07:31 -0500 | [diff] [blame] | 1176 | /* cayman compute rings */ |
| 1177 | struct radeon_cp cp1; |
| 1178 | struct radeon_cp cp2; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1179 | struct radeon_ib_pool ib_pool; |
| 1180 | struct radeon_irq irq; |
| 1181 | struct radeon_asic *asic; |
| 1182 | struct radeon_gem gem; |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1183 | struct radeon_pm pm; |
Yang Zhao | f657c2a | 2009-09-15 12:21:01 +1000 | [diff] [blame] | 1184 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1185 | struct mutex cs_mutex; |
| 1186 | struct radeon_wb wb; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1187 | struct radeon_dummy_page dummy_page; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1188 | bool gpu_lockup; |
| 1189 | bool shutdown; |
| 1190 | bool suspend; |
Dave Airlie | ad49f50 | 2009-07-10 22:36:26 +1000 | [diff] [blame] | 1191 | bool need_dma32; |
Jerome Glisse | 733289c | 2009-09-16 15:24:21 +0200 | [diff] [blame] | 1192 | bool accel_working; |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1193 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1194 | const struct firmware *me_fw; /* all family ME firmware */ |
| 1195 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1196 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1197 | const struct firmware *mc_fw; /* NI MC firmware */ |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1198 | struct r600_blit r600_blit; |
Alex Deucher | 87cbf8f | 2010-08-27 13:59:54 -0400 | [diff] [blame] | 1199 | struct r700_vram_scratch vram_scratch; |
Alex Deucher | 3e5cb98 | 2009-10-16 12:21:24 -0400 | [diff] [blame] | 1200 | int msi_enabled; /* msi enabled */ |
Alex Deucher | d8f60cf | 2009-12-01 13:43:46 -0500 | [diff] [blame] | 1201 | struct r600_ih ih; /* r6/700 interrupt ring */ |
Alex Deucher | d4877cf | 2009-12-04 16:56:37 -0500 | [diff] [blame] | 1202 | struct work_struct hotplug_work; |
Alex Deucher | 18917b6 | 2010-02-01 16:02:25 -0500 | [diff] [blame] | 1203 | int num_crtc; /* number of crtcs */ |
Alex Deucher | 40bacf1 | 2009-12-23 03:23:21 -0500 | [diff] [blame] | 1204 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
Matthew Garrett | 5876dd2 | 2010-04-26 15:52:20 -0400 | [diff] [blame] | 1205 | struct mutex vram_mutex; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1206 | |
| 1207 | /* audio stuff */ |
Rafał Miłecki | 7eea7e9 | 2010-06-19 12:24:56 +0200 | [diff] [blame] | 1208 | bool audio_enabled; |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1209 | struct timer_list audio_timer; |
| 1210 | int audio_channels; |
| 1211 | int audio_rate; |
| 1212 | int audio_bits_per_sample; |
| 1213 | uint8_t audio_status_bits; |
| 1214 | uint8_t audio_category_code; |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1215 | |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1216 | struct notifier_block acpi_nb; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 1217 | /* only one userspace can use Hyperz features or CMASK at a time */ |
Dave Airlie | ab9e1f5 | 2010-07-13 11:11:11 +1000 | [diff] [blame] | 1218 | struct drm_file *hyperz_filp; |
Marek Olšák | 9eba4a9 | 2011-01-05 05:46:48 +0100 | [diff] [blame] | 1219 | struct drm_file *cmask_filp; |
Alex Deucher | f376b94 | 2010-08-05 21:21:16 -0400 | [diff] [blame] | 1220 | /* i2c buses */ |
| 1221 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1222 | }; |
| 1223 | |
| 1224 | int radeon_device_init(struct radeon_device *rdev, |
| 1225 | struct drm_device *ddev, |
| 1226 | struct pci_dev *pdev, |
| 1227 | uint32_t flags); |
| 1228 | void radeon_device_fini(struct radeon_device *rdev); |
| 1229 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
| 1230 | |
Andi Kleen | 6fcbef7 | 2011-10-13 16:08:42 -0700 | [diff] [blame] | 1231 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
| 1232 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
| 1233 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
| 1234 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1235 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1236 | /* |
| 1237 | * Cast helper |
| 1238 | */ |
| 1239 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1240 | |
| 1241 | /* |
| 1242 | * Registers read & write functions. |
| 1243 | */ |
Benjamin Herrenschmidt | a0533fb | 2011-07-13 06:28:12 +0000 | [diff] [blame] | 1244 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
| 1245 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
| 1246 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
| 1247 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1248 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1249 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1250 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1251 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1252 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
| 1253 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
| 1254 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
| 1255 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
| 1256 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1257 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
| 1258 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
Rafał Miłecki | aa5120d | 2010-02-18 20:24:28 +0000 | [diff] [blame] | 1259 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
| 1260 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1261 | #define WREG32_P(reg, val, mask) \ |
| 1262 | do { \ |
| 1263 | uint32_t tmp_ = RREG32(reg); \ |
| 1264 | tmp_ &= (mask); \ |
| 1265 | tmp_ |= ((val) & ~(mask)); \ |
| 1266 | WREG32(reg, tmp_); \ |
| 1267 | } while (0) |
| 1268 | #define WREG32_PLL_P(reg, val, mask) \ |
| 1269 | do { \ |
| 1270 | uint32_t tmp_ = RREG32_PLL(reg); \ |
| 1271 | tmp_ &= (mask); \ |
| 1272 | tmp_ |= ((val) & ~(mask)); \ |
| 1273 | WREG32_PLL(reg, tmp_); \ |
| 1274 | } while (0) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1275 | #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg))) |
Alex Deucher | 351a52a | 2010-06-30 11:52:50 -0400 | [diff] [blame] | 1276 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
| 1277 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1278 | |
Dave Airlie | de1b289 | 2009-08-12 18:43:14 +1000 | [diff] [blame] | 1279 | /* |
| 1280 | * Indirect registers accessor |
| 1281 | */ |
| 1282 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
| 1283 | { |
| 1284 | uint32_t r; |
| 1285 | |
| 1286 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1287 | r = RREG32(RADEON_PCIE_DATA); |
| 1288 | return r; |
| 1289 | } |
| 1290 | |
| 1291 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
| 1292 | { |
| 1293 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
| 1294 | WREG32(RADEON_PCIE_DATA, (v)); |
| 1295 | } |
| 1296 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1297 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
| 1298 | |
| 1299 | |
| 1300 | /* |
| 1301 | * ASICs helpers. |
| 1302 | */ |
Dave Airlie | b995e43 | 2009-07-14 02:02:32 +1000 | [diff] [blame] | 1303 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
| 1304 | (rdev->pdev->device == 0x5969)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1305 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
| 1306 | (rdev->family == CHIP_RV200) || \ |
| 1307 | (rdev->family == CHIP_RS100) || \ |
| 1308 | (rdev->family == CHIP_RS200) || \ |
| 1309 | (rdev->family == CHIP_RV250) || \ |
| 1310 | (rdev->family == CHIP_RV280) || \ |
| 1311 | (rdev->family == CHIP_RS300)) |
| 1312 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
| 1313 | (rdev->family == CHIP_RV350) || \ |
| 1314 | (rdev->family == CHIP_R350) || \ |
| 1315 | (rdev->family == CHIP_RV380) || \ |
| 1316 | (rdev->family == CHIP_R420) || \ |
| 1317 | (rdev->family == CHIP_R423) || \ |
| 1318 | (rdev->family == CHIP_RV410) || \ |
| 1319 | (rdev->family == CHIP_RS400) || \ |
| 1320 | (rdev->family == CHIP_RS480)) |
Alex Deucher | 3313e3d | 2011-01-06 18:49:34 -0500 | [diff] [blame] | 1321 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
| 1322 | (rdev->ddev->pdev->device == 0x9443) || \ |
| 1323 | (rdev->ddev->pdev->device == 0x944B) || \ |
| 1324 | (rdev->ddev->pdev->device == 0x9506) || \ |
| 1325 | (rdev->ddev->pdev->device == 0x9509) || \ |
| 1326 | (rdev->ddev->pdev->device == 0x950F) || \ |
| 1327 | (rdev->ddev->pdev->device == 0x689C) || \ |
| 1328 | (rdev->ddev->pdev->device == 0x689D)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1329 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
Alex Deucher | 99999aa | 2010-11-16 12:09:41 -0500 | [diff] [blame] | 1330 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
| 1331 | (rdev->family == CHIP_RS690) || \ |
| 1332 | (rdev->family == CHIP_RS740) || \ |
| 1333 | (rdev->family >= CHIP_R600)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1334 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
| 1335 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
Alex Deucher | bcc1c2a | 2010-01-12 17:54:34 -0500 | [diff] [blame] | 1336 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
Alex Deucher | 633b916 | 2011-01-06 21:19:11 -0500 | [diff] [blame] | 1337 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
| 1338 | (rdev->flags & RADEON_IS_IGP)) |
Alex Deucher | 1fe1830 | 2011-01-06 21:19:12 -0500 | [diff] [blame] | 1339 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1340 | |
| 1341 | /* |
| 1342 | * BIOS helpers. |
| 1343 | */ |
| 1344 | #define RBIOS8(i) (rdev->bios[i]) |
| 1345 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
| 1346 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
| 1347 | |
| 1348 | int radeon_combios_init(struct radeon_device *rdev); |
| 1349 | void radeon_combios_fini(struct radeon_device *rdev); |
| 1350 | int radeon_atombios_init(struct radeon_device *rdev); |
| 1351 | void radeon_atombios_fini(struct radeon_device *rdev); |
| 1352 | |
| 1353 | |
| 1354 | /* |
| 1355 | * RING helpers. |
| 1356 | */ |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1357 | |
| 1358 | #if DRM_DEBUG_CODE == 0 |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1359 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
| 1360 | { |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1361 | rdev->cp.ring[rdev->cp.wptr++] = v; |
| 1362 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
| 1363 | rdev->cp.count_dw--; |
| 1364 | rdev->cp.ring_free_dw--; |
| 1365 | } |
Andi Kleen | ce580fa | 2011-10-13 16:08:47 -0700 | [diff] [blame] | 1366 | #else |
| 1367 | /* With debugging this is just too big to inline */ |
| 1368 | void radeon_ring_write(struct radeon_device *rdev, uint32_t v); |
| 1369 | #endif |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1370 | |
| 1371 | /* |
| 1372 | * ASICs macro. |
| 1373 | */ |
Jerome Glisse | 068a117 | 2009-06-17 13:28:30 +0200 | [diff] [blame] | 1374 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1375 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
| 1376 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
| 1377 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1378 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
Dave Airlie | 28d5204 | 2009-09-21 14:33:58 +1000 | [diff] [blame] | 1379 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
Jerome Glisse | 225758d | 2010-03-09 14:45:10 +0000 | [diff] [blame] | 1380 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
Jerome Glisse | a2d07b7 | 2010-03-09 14:45:11 +0000 | [diff] [blame] | 1381 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1382 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
| 1383 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1384 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1385 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
Jerome Glisse | 3ce0a23 | 2009-09-08 10:10:24 +1000 | [diff] [blame] | 1386 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
| 1387 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1388 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
| 1389 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
Michel Dänzer | 7ed220d | 2009-08-13 11:10:51 +0200 | [diff] [blame] | 1390 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1391 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
| 1392 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
| 1393 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
| 1394 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1395 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1396 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
Rafał Miłecki | 7433874 | 2009-11-03 00:53:02 +0100 | [diff] [blame] | 1397 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
Rafał Miłecki | 93e7de7 | 2009-11-04 23:34:10 +0100 | [diff] [blame] | 1398 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
Alex Deucher | c836a41 | 2009-12-23 10:07:50 -0500 | [diff] [blame] | 1399 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1400 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
| 1401 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
Dave Airlie | e024e11 | 2009-06-24 09:48:08 +1000 | [diff] [blame] | 1402 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
| 1403 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
Jerome Glisse | c93bb85 | 2009-07-13 21:04:08 +0200 | [diff] [blame] | 1404 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
Alex Deucher | 429770b | 2009-12-04 15:26:55 -0500 | [diff] [blame] | 1405 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
| 1406 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
| 1407 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
| 1408 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
Alex Deucher | def9ba9 | 2010-04-22 12:39:58 -0400 | [diff] [blame] | 1409 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
Alex Deucher | a424816 | 2010-04-24 14:50:23 -0400 | [diff] [blame] | 1410 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
| 1411 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) |
| 1412 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) |
Alex Deucher | ce8f537 | 2010-05-07 15:10:16 -0400 | [diff] [blame] | 1413 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
| 1414 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) |
Alex Deucher | 6f34be5 | 2010-11-21 10:59:01 -0500 | [diff] [blame] | 1415 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
| 1416 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) |
| 1417 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1418 | |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1419 | /* Common functions */ |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1420 | /* AGP */ |
Jerome Glisse | 90aca4d | 2010-03-09 14:45:12 +0000 | [diff] [blame] | 1421 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
Jerome Glisse | 700a0cc | 2010-01-13 15:16:38 +0100 | [diff] [blame] | 1422 | extern void radeon_agp_disable(struct radeon_device *rdev); |
Jerome Glisse | 4aac047 | 2009-09-14 18:29:49 +0200 | [diff] [blame] | 1423 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
Dave Airlie | 8256856 | 2010-02-05 16:00:07 +1000 | [diff] [blame] | 1424 | extern void radeon_gart_restore(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1425 | extern int radeon_modeset_init(struct radeon_device *rdev); |
| 1426 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
Jerome Glisse | 9f022dd | 2009-09-11 15:35:22 +0200 | [diff] [blame] | 1427 | extern bool radeon_card_posted(struct radeon_device *rdev); |
Alex Deucher | f47299c | 2010-03-16 20:54:38 -0400 | [diff] [blame] | 1428 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
Alex Deucher | f46c012 | 2010-03-31 00:33:27 -0400 | [diff] [blame] | 1429 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
Dave Airlie | 72542d7 | 2009-12-01 14:06:31 +1000 | [diff] [blame] | 1430 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1431 | extern void radeon_scratch_init(struct radeon_device *rdev); |
Alex Deucher | 724c80e | 2010-08-27 18:25:25 -0400 | [diff] [blame] | 1432 | extern void radeon_wb_fini(struct radeon_device *rdev); |
| 1433 | extern int radeon_wb_init(struct radeon_device *rdev); |
| 1434 | extern void radeon_wb_disable(struct radeon_device *rdev); |
Jerome Glisse | 21f9a43 | 2009-09-11 15:55:33 +0200 | [diff] [blame] | 1435 | extern void radeon_surface_init(struct radeon_device *rdev); |
| 1436 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
Jerome Glisse | ca6ffc6 | 2009-10-01 10:20:52 +0200 | [diff] [blame] | 1437 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | d39c3b8 | 2009-09-28 18:34:43 +0200 | [diff] [blame] | 1438 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
Jerome Glisse | 312ea8d | 2009-12-07 15:52:58 +0100 | [diff] [blame] | 1439 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
Jerome Glisse | d03d858 | 2009-12-14 21:02:09 +0100 | [diff] [blame] | 1440 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
Jerome Glisse | d594e46 | 2010-02-17 21:54:29 +0000 | [diff] [blame] | 1441 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
| 1442 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
Dave Airlie | 6a9ee8a | 2010-02-01 15:38:10 +1000 | [diff] [blame] | 1443 | extern int radeon_resume_kms(struct drm_device *dev); |
| 1444 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
Dave Airlie | 5359533 | 2011-03-14 09:47:24 +1000 | [diff] [blame] | 1445 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
Jerome Glisse | 6cf8a3f | 2009-09-10 21:46:48 +0200 | [diff] [blame] | 1446 | |
Daniel Vetter | 3574dda | 2011-02-18 17:59:19 +0100 | [diff] [blame] | 1447 | /* |
| 1448 | * r600 functions used by radeon_encoder.c |
| 1449 | */ |
Rafał Miłecki | 2cd6218c | 2010-03-08 22:14:01 +0000 | [diff] [blame] | 1450 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
| 1451 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
Christian Koenig | dafc3bd | 2009-10-11 23:49:13 +0200 | [diff] [blame] | 1452 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
Alex Deucher | fe251e2 | 2010-03-24 13:36:43 -0400 | [diff] [blame] | 1453 | |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1454 | extern int ni_init_microcode(struct radeon_device *rdev); |
Alex Deucher | 755d819 | 2011-03-02 20:07:34 -0500 | [diff] [blame] | 1455 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
Alex Deucher | 0af62b0 | 2011-01-06 21:19:31 -0500 | [diff] [blame] | 1456 | |
Alberto Milone | d7a2952 | 2010-07-06 11:40:24 -0400 | [diff] [blame] | 1457 | /* radeon_acpi.c */ |
| 1458 | #if defined(CONFIG_ACPI) |
| 1459 | extern int radeon_acpi_init(struct radeon_device *rdev); |
| 1460 | #else |
| 1461 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
| 1462 | #endif |
| 1463 | |
Jerome Glisse | 4c78867 | 2009-11-20 14:29:23 +0100 | [diff] [blame] | 1464 | #include "radeon_object.h" |
| 1465 | |
Jerome Glisse | 771fe6b | 2009-06-05 14:42:42 +0200 | [diff] [blame] | 1466 | #endif |