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Lennert Buytenhek91da11f2008-10-07 13:44:02 +00001/*
Vivien Didelot0d3cd4b2016-06-21 12:28:19 -04002 * Marvell 88e6xxx Ethernet switch single-chip support
3 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +00004 * Copyright (c) 2008 Marvell Semiconductor
5 *
Vivien Didelotb8fee952015-08-13 12:52:19 -04006 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
8 *
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02009 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
10 *
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
Barry Grussling19b2f972013-01-08 16:05:54 +000017#include <linux/delay.h>
Guenter Roeckdefb05b2015-03-26 18:36:38 -070018#include <linux/etherdevice.h>
Andrew Lunndea87022015-08-31 15:56:47 +020019#include <linux/ethtool.h>
Guenter Roeckfacd95b2015-03-26 18:36:35 -070020#include <linux/if_bridge.h>
Barry Grussling19b2f972013-01-08 16:05:54 +000021#include <linux/jiffies.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000022#include <linux/list.h>
Andrew Lunn14c7b3c2016-05-10 23:27:21 +020023#include <linux/mdio.h>
Paul Gortmaker2bbba272012-01-24 10:41:40 +000024#include <linux/module.h>
Vivien Didelotcaac8542016-06-20 13:14:09 -040025#include <linux/of_device.h>
Andrew Lunnb516d452016-06-04 21:17:06 +020026#include <linux/of_mdio.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000027#include <linux/netdevice.h>
Andrew Lunnc8c1b392015-11-20 03:56:24 +010028#include <linux/gpio/consumer.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000029#include <linux/phy.h>
Ben Hutchingsc8f0b862011-11-27 17:06:08 +000030#include <net/dsa.h>
Vivien Didelot1f36faf2015-10-08 11:35:13 -040031#include <net/switchdev.h>
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000032#include "mv88e6xxx.h"
33
Vivien Didelotfad09c72016-06-21 12:28:20 -040034static void assert_reg_lock(struct mv88e6xxx_chip *chip)
Vivien Didelot3996a4f2015-10-30 18:56:45 -040035{
Vivien Didelotfad09c72016-06-21 12:28:20 -040036 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
Vivien Didelot3996a4f2015-10-30 18:56:45 -040038 dump_stack();
39 }
40}
41
Vivien Didelot914b32f2016-06-20 13:14:11 -040042/* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
44 *
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
48 *
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
Lennert Buytenhek91da11f2008-10-07 13:44:02 +000052 */
Vivien Didelot914b32f2016-06-20 13:14:11 -040053
Vivien Didelotfad09c72016-06-21 12:28:20 -040054static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040055 int addr, int reg, u16 *val)
56{
Vivien Didelotfad09c72016-06-21 12:28:20 -040057 if (!chip->smi_ops)
Vivien Didelot914b32f2016-06-20 13:14:11 -040058 return -EOPNOTSUPP;
59
Vivien Didelotfad09c72016-06-21 12:28:20 -040060 return chip->smi_ops->read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040061}
62
Vivien Didelotfad09c72016-06-21 12:28:20 -040063static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040064 int addr, int reg, u16 val)
65{
Vivien Didelotfad09c72016-06-21 12:28:20 -040066 if (!chip->smi_ops)
Vivien Didelot914b32f2016-06-20 13:14:11 -040067 return -EOPNOTSUPP;
68
Vivien Didelotfad09c72016-06-21 12:28:20 -040069 return chip->smi_ops->write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040070}
71
Vivien Didelotfad09c72016-06-21 12:28:20 -040072static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040073 int addr, int reg, u16 *val)
74{
75 int ret;
76
Vivien Didelotfad09c72016-06-21 12:28:20 -040077 ret = mdiobus_read_nested(chip->bus, addr, reg);
Vivien Didelot914b32f2016-06-20 13:14:11 -040078 if (ret < 0)
79 return ret;
80
81 *val = ret & 0xffff;
82
83 return 0;
84}
85
Vivien Didelotfad09c72016-06-21 12:28:20 -040086static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -040087 int addr, int reg, u16 val)
88{
89 int ret;
90
Vivien Didelotfad09c72016-06-21 12:28:20 -040091 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -040092 if (ret < 0)
93 return ret;
94
95 return 0;
96}
97
98static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
101};
102
Vivien Didelotfad09c72016-06-21 12:28:20 -0400103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000104{
105 int ret;
106 int i;
107
108 for (i = 0; i < 16; i++) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000110 if (ret < 0)
111 return ret;
112
Andrew Lunncca8b132015-04-02 04:06:39 +0200113 if ((ret & SMI_CMD_BUSY) == 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000114 return 0;
115 }
116
117 return -ETIMEDOUT;
118}
119
Vivien Didelotfad09c72016-06-21 12:28:20 -0400120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400121 int addr, int reg, u16 *val)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000122{
123 int ret;
124
Barry Grussling3675c8d2013-01-08 16:05:53 +0000125 /* Wait for the bus to become free. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000127 if (ret < 0)
128 return ret;
129
Barry Grussling3675c8d2013-01-08 16:05:53 +0000130 /* Transmit the read command. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
Neil Armstrong6e899e62015-10-22 10:37:53 +0200132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000133 if (ret < 0)
134 return ret;
135
Barry Grussling3675c8d2013-01-08 16:05:53 +0000136 /* Wait for the read command to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000138 if (ret < 0)
139 return ret;
140
Barry Grussling3675c8d2013-01-08 16:05:53 +0000141 /* Read the data. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000143 if (ret < 0)
144 return ret;
145
Vivien Didelot914b32f2016-06-20 13:14:11 -0400146 *val = ret & 0xffff;
147
148 return 0;
149}
150
Vivien Didelotfad09c72016-06-21 12:28:20 -0400151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400152 int addr, int reg, u16 val)
153{
154 int ret;
155
156 /* Wait for the bus to become free. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400158 if (ret < 0)
159 return ret;
160
161 /* Transmit the data to write. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400163 if (ret < 0)
164 return ret;
165
166 /* Transmit the write command. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
169 if (ret < 0)
170 return ret;
171
172 /* Wait for the write command to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400174 if (ret < 0)
175 return ret;
176
177 return 0;
178}
179
180static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
183};
184
Vivien Didelotfad09c72016-06-21 12:28:20 -0400185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400186 int addr, int reg, u16 *val)
187{
188 int err;
189
Vivien Didelotfad09c72016-06-21 12:28:20 -0400190 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400191
Vivien Didelotfad09c72016-06-21 12:28:20 -0400192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400193 if (err)
194 return err;
195
Vivien Didelotfad09c72016-06-21 12:28:20 -0400196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -0400197 addr, reg, *val);
198
199 return 0;
200}
201
Vivien Didelotfad09c72016-06-21 12:28:20 -0400202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
Vivien Didelot914b32f2016-06-20 13:14:11 -0400203 int addr, int reg, u16 val)
204{
205 int err;
206
Vivien Didelotfad09c72016-06-21 12:28:20 -0400207 assert_reg_lock(chip);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400208
Vivien Didelotfad09c72016-06-21 12:28:20 -0400209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400210 if (err)
211 return err;
212
Vivien Didelotfad09c72016-06-21 12:28:20 -0400213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
Vivien Didelot914b32f2016-06-20 13:14:11 -0400214 addr, reg, val);
215
216 return 0;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000217}
218
Vivien Didelotf22ab642016-07-18 20:45:31 -0400219/* Indirect write to single pointer-data register with an Update bit */
220static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
221 u16 update)
222{
223 u16 val;
224 int i, err;
225
226 /* Wait until the previous operation is completed */
227 for (i = 0; i < 16; ++i) {
228 err = mv88e6xxx_read(chip, addr, reg, &val);
229 if (err)
230 return err;
231
232 if (!(val & BIT(15)))
233 break;
234 }
235
236 if (i == 16)
237 return -ETIMEDOUT;
238
239 /* Set the Update bit to trigger a write operation */
240 val = BIT(15) | update;
241
242 return mv88e6xxx_write(chip, addr, reg, val);
243}
244
Vivien Didelotfad09c72016-06-21 12:28:20 -0400245static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000246{
Vivien Didelot914b32f2016-06-20 13:14:11 -0400247 u16 val;
248 int err;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000249
Vivien Didelotfad09c72016-06-21 12:28:20 -0400250 err = mv88e6xxx_read(chip, addr, reg, &val);
Vivien Didelot914b32f2016-06-20 13:14:11 -0400251 if (err)
252 return err;
Vivien Didelot3996a4f2015-10-30 18:56:45 -0400253
Vivien Didelot914b32f2016-06-20 13:14:11 -0400254 return val;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000255}
256
Vivien Didelotfad09c72016-06-21 12:28:20 -0400257static int mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
Guenter Roeck8d6d09e2015-03-26 18:36:31 -0700258{
Guenter Roeck8d6d09e2015-03-26 18:36:31 -0700259 int ret;
260
Vivien Didelotfad09c72016-06-21 12:28:20 -0400261 mutex_lock(&chip->reg_lock);
262 ret = _mv88e6xxx_reg_read(chip, addr, reg);
263 mutex_unlock(&chip->reg_lock);
Guenter Roeck8d6d09e2015-03-26 18:36:31 -0700264
265 return ret;
266}
267
Vivien Didelotfad09c72016-06-21 12:28:20 -0400268static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
Andrew Lunn158bc062016-04-28 21:24:06 -0400269 int reg, u16 val)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000270{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400271 return mv88e6xxx_write(chip, addr, reg, val);
Guenter Roeck8d6d09e2015-03-26 18:36:31 -0700272}
273
Vivien Didelotfad09c72016-06-21 12:28:20 -0400274static int mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
Vivien Didelot57d32312016-06-20 13:13:58 -0400275 int reg, u16 val)
Guenter Roeck8d6d09e2015-03-26 18:36:31 -0700276{
Guenter Roeck8d6d09e2015-03-26 18:36:31 -0700277 int ret;
278
Vivien Didelotfad09c72016-06-21 12:28:20 -0400279 mutex_lock(&chip->reg_lock);
280 ret = _mv88e6xxx_reg_write(chip, addr, reg, val);
281 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000282
283 return ret;
284}
285
Vivien Didelotfad09c72016-06-21 12:28:20 -0400286static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
Andrew Lunn03a4a542016-06-04 21:17:05 +0200287 int addr, int regnum)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000288{
289 if (addr >= 0)
Vivien Didelotfad09c72016-06-21 12:28:20 -0400290 return _mv88e6xxx_reg_read(chip, addr, regnum);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000291 return 0xffff;
292}
293
Vivien Didelotfad09c72016-06-21 12:28:20 -0400294static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
Andrew Lunn03a4a542016-06-04 21:17:05 +0200295 int addr, int regnum, u16 val)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000296{
297 if (addr >= 0)
Vivien Didelotfad09c72016-06-21 12:28:20 -0400298 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000299 return 0;
300}
301
Vivien Didelotfad09c72016-06-21 12:28:20 -0400302static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000303{
304 int ret;
Barry Grussling19b2f972013-01-08 16:05:54 +0000305 unsigned long timeout;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000306
Vivien Didelotfad09c72016-06-21 12:28:20 -0400307 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200308 if (ret < 0)
309 return ret;
310
Vivien Didelotfad09c72016-06-21 12:28:20 -0400311 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
Vivien Didelot8c9983a2016-05-09 13:22:39 -0400312 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200313 if (ret)
314 return ret;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000315
Barry Grussling19b2f972013-01-08 16:05:54 +0000316 timeout = jiffies + 1 * HZ;
317 while (time_before(jiffies, timeout)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400318 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200319 if (ret < 0)
320 return ret;
321
Barry Grussling19b2f972013-01-08 16:05:54 +0000322 usleep_range(1000, 2000);
Andrew Lunncca8b132015-04-02 04:06:39 +0200323 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
324 GLOBAL_STATUS_PPU_POLLING)
Barry Grussling85686582013-01-08 16:05:56 +0000325 return 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000326 }
327
328 return -ETIMEDOUT;
329}
330
Vivien Didelotfad09c72016-06-21 12:28:20 -0400331static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000332{
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200333 int ret, err;
Barry Grussling19b2f972013-01-08 16:05:54 +0000334 unsigned long timeout;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000335
Vivien Didelotfad09c72016-06-21 12:28:20 -0400336 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200337 if (ret < 0)
338 return ret;
339
Vivien Didelotfad09c72016-06-21 12:28:20 -0400340 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
Vivien Didelot762eb672016-06-04 21:16:54 +0200341 ret | GLOBAL_CONTROL_PPU_ENABLE);
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200342 if (err)
343 return err;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000344
Barry Grussling19b2f972013-01-08 16:05:54 +0000345 timeout = jiffies + 1 * HZ;
346 while (time_before(jiffies, timeout)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400347 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
Andrew Lunn48ace4e2016-04-14 23:47:12 +0200348 if (ret < 0)
349 return ret;
350
Barry Grussling19b2f972013-01-08 16:05:54 +0000351 usleep_range(1000, 2000);
Andrew Lunncca8b132015-04-02 04:06:39 +0200352 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
353 GLOBAL_STATUS_PPU_POLLING)
Barry Grussling85686582013-01-08 16:05:56 +0000354 return 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000355 }
356
357 return -ETIMEDOUT;
358}
359
360static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
361{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400362 struct mv88e6xxx_chip *chip;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000363
Vivien Didelotfad09c72016-06-21 12:28:20 -0400364 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
Vivien Didelot762eb672016-06-04 21:16:54 +0200365
Vivien Didelotfad09c72016-06-21 12:28:20 -0400366 mutex_lock(&chip->reg_lock);
Vivien Didelot762eb672016-06-04 21:16:54 +0200367
Vivien Didelotfad09c72016-06-21 12:28:20 -0400368 if (mutex_trylock(&chip->ppu_mutex)) {
369 if (mv88e6xxx_ppu_enable(chip) == 0)
370 chip->ppu_disabled = 0;
371 mutex_unlock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000372 }
Vivien Didelot762eb672016-06-04 21:16:54 +0200373
Vivien Didelotfad09c72016-06-21 12:28:20 -0400374 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000375}
376
377static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
378{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400379 struct mv88e6xxx_chip *chip = (void *)_ps;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000380
Vivien Didelotfad09c72016-06-21 12:28:20 -0400381 schedule_work(&chip->ppu_work);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000382}
383
Vivien Didelotfad09c72016-06-21 12:28:20 -0400384static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000385{
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000386 int ret;
387
Vivien Didelotfad09c72016-06-21 12:28:20 -0400388 mutex_lock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000389
Barry Grussling3675c8d2013-01-08 16:05:53 +0000390 /* If the PHY polling unit is enabled, disable it so that
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000391 * we can access the PHY registers. If it was already
392 * disabled, cancel the timer that is going to re-enable
393 * it.
394 */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400395 if (!chip->ppu_disabled) {
396 ret = mv88e6xxx_ppu_disable(chip);
Barry Grussling85686582013-01-08 16:05:56 +0000397 if (ret < 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400398 mutex_unlock(&chip->ppu_mutex);
Barry Grussling85686582013-01-08 16:05:56 +0000399 return ret;
400 }
Vivien Didelotfad09c72016-06-21 12:28:20 -0400401 chip->ppu_disabled = 1;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000402 } else {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400403 del_timer(&chip->ppu_timer);
Barry Grussling85686582013-01-08 16:05:56 +0000404 ret = 0;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000405 }
406
407 return ret;
408}
409
Vivien Didelotfad09c72016-06-21 12:28:20 -0400410static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000411{
Barry Grussling3675c8d2013-01-08 16:05:53 +0000412 /* Schedule a timer to re-enable the PHY polling unit. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400413 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
414 mutex_unlock(&chip->ppu_mutex);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000415}
416
Vivien Didelotfad09c72016-06-21 12:28:20 -0400417static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000418{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400419 mutex_init(&chip->ppu_mutex);
420 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
421 init_timer(&chip->ppu_timer);
422 chip->ppu_timer.data = (unsigned long)chip;
423 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000424}
425
Vivien Didelotfad09c72016-06-21 12:28:20 -0400426static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
Andrew Lunn03a4a542016-06-04 21:17:05 +0200427 int regnum)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000428{
429 int ret;
430
Vivien Didelotfad09c72016-06-21 12:28:20 -0400431 ret = mv88e6xxx_ppu_access_get(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000432 if (ret >= 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400433 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
434 mv88e6xxx_ppu_access_put(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000435 }
436
437 return ret;
438}
439
Vivien Didelotfad09c72016-06-21 12:28:20 -0400440static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
Andrew Lunn03a4a542016-06-04 21:17:05 +0200441 int regnum, u16 val)
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000442{
443 int ret;
444
Vivien Didelotfad09c72016-06-21 12:28:20 -0400445 ret = mv88e6xxx_ppu_access_get(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000446 if (ret >= 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400447 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
448 mv88e6xxx_ppu_access_put(chip);
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000449 }
450
451 return ret;
452}
Lennert Buytenhek2e5f0322008-10-07 13:45:18 +0000453
Vivien Didelotfad09c72016-06-21 12:28:20 -0400454static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200455{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400456 return chip->info->family == MV88E6XXX_FAMILY_6065;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200457}
458
Vivien Didelotfad09c72016-06-21 12:28:20 -0400459static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200460{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400461 return chip->info->family == MV88E6XXX_FAMILY_6095;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200462}
463
Vivien Didelotfad09c72016-06-21 12:28:20 -0400464static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200465{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400466 return chip->info->family == MV88E6XXX_FAMILY_6097;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200467}
468
Vivien Didelotfad09c72016-06-21 12:28:20 -0400469static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200470{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400471 return chip->info->family == MV88E6XXX_FAMILY_6165;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200472}
473
Vivien Didelotfad09c72016-06-21 12:28:20 -0400474static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200475{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400476 return chip->info->family == MV88E6XXX_FAMILY_6185;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200477}
478
Vivien Didelotfad09c72016-06-21 12:28:20 -0400479static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -0700480{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400481 return chip->info->family == MV88E6XXX_FAMILY_6320;
Aleksey S. Kazantsev7c3d0d62015-07-07 20:38:15 -0700482}
483
Vivien Didelotfad09c72016-06-21 12:28:20 -0400484static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
Andrew Lunn54d792f2015-05-06 01:09:47 +0200485{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400486 return chip->info->family == MV88E6XXX_FAMILY_6351;
Andrew Lunn54d792f2015-05-06 01:09:47 +0200487}
488
Vivien Didelotfad09c72016-06-21 12:28:20 -0400489static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
Andrew Lunnf3a8b6b2015-04-02 04:06:40 +0200490{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400491 return chip->info->family == MV88E6XXX_FAMILY_6352;
Andrew Lunnf3a8b6b2015-04-02 04:06:40 +0200492}
493
Vivien Didelotfad09c72016-06-21 12:28:20 -0400494static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
Vivien Didelotf74df0b2016-03-31 16:53:43 -0400495{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400496 return chip->info->num_databases;
Vivien Didelotf74df0b2016-03-31 16:53:43 -0400497}
498
Vivien Didelotfad09c72016-06-21 12:28:20 -0400499static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
Vivien Didelotb426e5f2016-03-31 16:53:42 -0400500{
501 /* Does the device have dedicated FID registers for ATU and VTU ops? */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400502 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
503 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
Vivien Didelotb426e5f2016-03-31 16:53:42 -0400504 return true;
505
506 return false;
507}
508
Andrew Lunndea87022015-08-31 15:56:47 +0200509/* We expect the switch to perform auto negotiation if there is a real
510 * phy. However, in the case of a fixed link phy, we force the port
511 * settings from the fixed link settings.
512 */
Vivien Didelotf81ec902016-05-09 13:22:58 -0400513static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
514 struct phy_device *phydev)
Andrew Lunndea87022015-08-31 15:56:47 +0200515{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400516 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn49052872015-09-29 01:53:48 +0200517 u32 reg;
518 int ret;
Andrew Lunndea87022015-08-31 15:56:47 +0200519
520 if (!phy_is_pseudo_fixed_link(phydev))
521 return;
522
Vivien Didelotfad09c72016-06-21 12:28:20 -0400523 mutex_lock(&chip->reg_lock);
Andrew Lunndea87022015-08-31 15:56:47 +0200524
Vivien Didelotfad09c72016-06-21 12:28:20 -0400525 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
Andrew Lunndea87022015-08-31 15:56:47 +0200526 if (ret < 0)
527 goto out;
528
529 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
530 PORT_PCS_CTRL_FORCE_LINK |
531 PORT_PCS_CTRL_DUPLEX_FULL |
532 PORT_PCS_CTRL_FORCE_DUPLEX |
533 PORT_PCS_CTRL_UNFORCED);
534
535 reg |= PORT_PCS_CTRL_FORCE_LINK;
536 if (phydev->link)
Vivien Didelot57d32312016-06-20 13:13:58 -0400537 reg |= PORT_PCS_CTRL_LINK_UP;
Andrew Lunndea87022015-08-31 15:56:47 +0200538
Vivien Didelotfad09c72016-06-21 12:28:20 -0400539 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
Andrew Lunndea87022015-08-31 15:56:47 +0200540 goto out;
541
542 switch (phydev->speed) {
543 case SPEED_1000:
544 reg |= PORT_PCS_CTRL_1000;
545 break;
546 case SPEED_100:
547 reg |= PORT_PCS_CTRL_100;
548 break;
549 case SPEED_10:
550 reg |= PORT_PCS_CTRL_10;
551 break;
552 default:
553 pr_info("Unknown speed");
554 goto out;
555 }
556
557 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
558 if (phydev->duplex == DUPLEX_FULL)
559 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
560
Vivien Didelotfad09c72016-06-21 12:28:20 -0400561 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
562 (port >= chip->info->num_ports - 2)) {
Andrew Lunne7e72ac2015-08-31 15:56:51 +0200563 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
564 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
565 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
566 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
567 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
568 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
569 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
570 }
Vivien Didelotfad09c72016-06-21 12:28:20 -0400571 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
Andrew Lunndea87022015-08-31 15:56:47 +0200572
573out:
Vivien Didelotfad09c72016-06-21 12:28:20 -0400574 mutex_unlock(&chip->reg_lock);
Andrew Lunndea87022015-08-31 15:56:47 +0200575}
576
Vivien Didelotfad09c72016-06-21 12:28:20 -0400577static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000578{
579 int ret;
580 int i;
581
582 for (i = 0; i < 10; i++) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400583 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
Andrew Lunncca8b132015-04-02 04:06:39 +0200584 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000585 return 0;
586 }
587
588 return -ETIMEDOUT;
589}
590
Vivien Didelotfad09c72016-06-21 12:28:20 -0400591static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000592{
593 int ret;
594
Vivien Didelotfad09c72016-06-21 12:28:20 -0400595 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
Andrew Lunnf3a8b6b2015-04-02 04:06:40 +0200596 port = (port + 1) << 5;
597
Barry Grussling3675c8d2013-01-08 16:05:53 +0000598 /* Snapshot the hardware statistics counters for this port. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400599 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
Andrew Lunn31888232015-05-06 01:09:54 +0200600 GLOBAL_STATS_OP_CAPTURE_PORT |
601 GLOBAL_STATS_OP_HIST_RX_TX | port);
602 if (ret < 0)
603 return ret;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000604
Barry Grussling3675c8d2013-01-08 16:05:53 +0000605 /* Wait for the snapshotting to complete. */
Vivien Didelotfad09c72016-06-21 12:28:20 -0400606 ret = _mv88e6xxx_stats_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000607 if (ret < 0)
608 return ret;
609
610 return 0;
611}
612
Vivien Didelotfad09c72016-06-21 12:28:20 -0400613static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -0400614 int stat, u32 *val)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000615{
616 u32 _val;
617 int ret;
618
619 *val = 0;
620
Vivien Didelotfad09c72016-06-21 12:28:20 -0400621 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
Andrew Lunn31888232015-05-06 01:09:54 +0200622 GLOBAL_STATS_OP_READ_CAPTURED |
623 GLOBAL_STATS_OP_HIST_RX_TX | stat);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000624 if (ret < 0)
625 return;
626
Vivien Didelotfad09c72016-06-21 12:28:20 -0400627 ret = _mv88e6xxx_stats_wait(chip);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000628 if (ret < 0)
629 return;
630
Vivien Didelotfad09c72016-06-21 12:28:20 -0400631 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000632 if (ret < 0)
633 return;
634
635 _val = ret << 16;
636
Vivien Didelotfad09c72016-06-21 12:28:20 -0400637 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000638 if (ret < 0)
639 return;
640
641 *val = _val | ret;
642}
643
Andrew Lunne413e7e2015-04-02 04:06:38 +0200644static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100645 { "in_good_octets", 8, 0x00, BANK0, },
646 { "in_bad_octets", 4, 0x02, BANK0, },
647 { "in_unicast", 4, 0x04, BANK0, },
648 { "in_broadcasts", 4, 0x06, BANK0, },
649 { "in_multicasts", 4, 0x07, BANK0, },
650 { "in_pause", 4, 0x16, BANK0, },
651 { "in_undersize", 4, 0x18, BANK0, },
652 { "in_fragments", 4, 0x19, BANK0, },
653 { "in_oversize", 4, 0x1a, BANK0, },
654 { "in_jabber", 4, 0x1b, BANK0, },
655 { "in_rx_error", 4, 0x1c, BANK0, },
656 { "in_fcs_error", 4, 0x1d, BANK0, },
657 { "out_octets", 8, 0x0e, BANK0, },
658 { "out_unicast", 4, 0x10, BANK0, },
659 { "out_broadcasts", 4, 0x13, BANK0, },
660 { "out_multicasts", 4, 0x12, BANK0, },
661 { "out_pause", 4, 0x15, BANK0, },
662 { "excessive", 4, 0x11, BANK0, },
663 { "collisions", 4, 0x1e, BANK0, },
664 { "deferred", 4, 0x05, BANK0, },
665 { "single", 4, 0x14, BANK0, },
666 { "multiple", 4, 0x17, BANK0, },
667 { "out_fcs_error", 4, 0x03, BANK0, },
668 { "late", 4, 0x1f, BANK0, },
669 { "hist_64bytes", 4, 0x08, BANK0, },
670 { "hist_65_127bytes", 4, 0x09, BANK0, },
671 { "hist_128_255bytes", 4, 0x0a, BANK0, },
672 { "hist_256_511bytes", 4, 0x0b, BANK0, },
673 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
674 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
675 { "sw_in_discards", 4, 0x10, PORT, },
676 { "sw_in_filtered", 2, 0x12, PORT, },
677 { "sw_out_filtered", 2, 0x13, PORT, },
678 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
682 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
683 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
684 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
685 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
686 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
687 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
688 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
689 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
690 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
691 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
692 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
693 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
694 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
695 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
696 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
697 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
703 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
Andrew Lunne413e7e2015-04-02 04:06:38 +0200704};
705
Vivien Didelotfad09c72016-06-21 12:28:20 -0400706static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100707 struct mv88e6xxx_hw_stat *stat)
Andrew Lunne413e7e2015-04-02 04:06:38 +0200708{
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100709 switch (stat->type) {
710 case BANK0:
Andrew Lunne413e7e2015-04-02 04:06:38 +0200711 return true;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100712 case BANK1:
Vivien Didelotfad09c72016-06-21 12:28:20 -0400713 return mv88e6xxx_6320_family(chip);
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100714 case PORT:
Vivien Didelotfad09c72016-06-21 12:28:20 -0400715 return mv88e6xxx_6095_family(chip) ||
716 mv88e6xxx_6185_family(chip) ||
717 mv88e6xxx_6097_family(chip) ||
718 mv88e6xxx_6165_family(chip) ||
719 mv88e6xxx_6351_family(chip) ||
720 mv88e6xxx_6352_family(chip);
Andrew Lunne413e7e2015-04-02 04:06:38 +0200721 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100722 return false;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000723}
724
Vivien Didelotfad09c72016-06-21 12:28:20 -0400725static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100726 struct mv88e6xxx_hw_stat *s,
Andrew Lunn80c46272015-06-20 18:42:30 +0200727 int port)
728{
Andrew Lunn80c46272015-06-20 18:42:30 +0200729 u32 low;
730 u32 high = 0;
731 int ret;
732 u64 value;
733
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100734 switch (s->type) {
735 case PORT:
Vivien Didelotfad09c72016-06-21 12:28:20 -0400736 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
Andrew Lunn80c46272015-06-20 18:42:30 +0200737 if (ret < 0)
738 return UINT64_MAX;
739
740 low = ret;
741 if (s->sizeof_stat == 4) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400742 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100743 s->reg + 1);
Andrew Lunn80c46272015-06-20 18:42:30 +0200744 if (ret < 0)
745 return UINT64_MAX;
746 high = ret;
747 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100748 break;
749 case BANK0:
750 case BANK1:
Vivien Didelotfad09c72016-06-21 12:28:20 -0400751 _mv88e6xxx_stats_read(chip, s->reg, &low);
Andrew Lunn80c46272015-06-20 18:42:30 +0200752 if (s->sizeof_stat == 8)
Vivien Didelotfad09c72016-06-21 12:28:20 -0400753 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
Andrew Lunn80c46272015-06-20 18:42:30 +0200754 }
755 value = (((u64)high) << 16) | low;
756 return value;
757}
758
Vivien Didelotf81ec902016-05-09 13:22:58 -0400759static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
760 uint8_t *data)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100761{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400762 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100763 struct mv88e6xxx_hw_stat *stat;
764 int i, j;
765
766 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
767 stat = &mv88e6xxx_hw_stats[i];
Vivien Didelotfad09c72016-06-21 12:28:20 -0400768 if (mv88e6xxx_has_stat(chip, stat)) {
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100769 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
770 ETH_GSTRING_LEN);
771 j++;
772 }
773 }
774}
775
Vivien Didelotf81ec902016-05-09 13:22:58 -0400776static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100777{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400778 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100779 struct mv88e6xxx_hw_stat *stat;
780 int i, j;
781
782 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
783 stat = &mv88e6xxx_hw_stats[i];
Vivien Didelotfad09c72016-06-21 12:28:20 -0400784 if (mv88e6xxx_has_stat(chip, stat))
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100785 j++;
786 }
787 return j;
788}
789
Vivien Didelotf81ec902016-05-09 13:22:58 -0400790static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
791 uint64_t *data)
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000792{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400793 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100794 struct mv88e6xxx_hw_stat *stat;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000795 int ret;
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100796 int i, j;
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000797
Vivien Didelotfad09c72016-06-21 12:28:20 -0400798 mutex_lock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000799
Vivien Didelotfad09c72016-06-21 12:28:20 -0400800 ret = _mv88e6xxx_stats_snapshot(chip, port);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000801 if (ret < 0) {
Vivien Didelotfad09c72016-06-21 12:28:20 -0400802 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000803 return;
804 }
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100805 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
806 stat = &mv88e6xxx_hw_stats[i];
Vivien Didelotfad09c72016-06-21 12:28:20 -0400807 if (mv88e6xxx_has_stat(chip, stat)) {
808 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
Andrew Lunnf5e2ed02015-12-23 13:23:17 +0100809 j++;
810 }
811 }
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000812
Vivien Didelotfad09c72016-06-21 12:28:20 -0400813 mutex_unlock(&chip->reg_lock);
Lennert Buytenhek91da11f2008-10-07 13:44:02 +0000814}
Ben Hutchings98e67302011-11-25 14:36:19 +0000815
Vivien Didelotf81ec902016-05-09 13:22:58 -0400816static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700817{
818 return 32 * sizeof(u16);
819}
820
Vivien Didelotf81ec902016-05-09 13:22:58 -0400821static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
822 struct ethtool_regs *regs, void *_p)
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700823{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400824 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700825 u16 *p = _p;
826 int i;
827
828 regs->version = 0;
829
830 memset(p, 0xff, 32 * sizeof(u16));
831
Vivien Didelotfad09c72016-06-21 12:28:20 -0400832 mutex_lock(&chip->reg_lock);
Vivien Didelot23062512016-05-09 13:22:45 -0400833
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700834 for (i = 0; i < 32; i++) {
835 int ret;
836
Vivien Didelotfad09c72016-06-21 12:28:20 -0400837 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700838 if (ret >= 0)
839 p[i] = ret;
840 }
Vivien Didelot23062512016-05-09 13:22:45 -0400841
Vivien Didelotfad09c72016-06-21 12:28:20 -0400842 mutex_unlock(&chip->reg_lock);
Guenter Roecka1ab91f2014-10-29 10:45:05 -0700843}
844
Vivien Didelotfad09c72016-06-21 12:28:20 -0400845static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
Andrew Lunn3898c142015-05-06 01:09:53 +0200846 u16 mask)
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700847{
848 unsigned long timeout = jiffies + HZ / 10;
849
850 while (time_before(jiffies, timeout)) {
851 int ret;
852
Vivien Didelotfad09c72016-06-21 12:28:20 -0400853 ret = _mv88e6xxx_reg_read(chip, reg, offset);
Guenter Roeckfacd95b2015-03-26 18:36:35 -0700854 if (ret < 0)
855 return ret;
856 if (!(ret & mask))
857 return 0;
858
859 usleep_range(1000, 2000);
860 }
861 return -ETIMEDOUT;
862}
863
Vivien Didelotfad09c72016-06-21 12:28:20 -0400864static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg,
Andrew Lunn158bc062016-04-28 21:24:06 -0400865 int offset, u16 mask)
Andrew Lunn3898c142015-05-06 01:09:53 +0200866{
Andrew Lunn3898c142015-05-06 01:09:53 +0200867 int ret;
868
Vivien Didelotfad09c72016-06-21 12:28:20 -0400869 mutex_lock(&chip->reg_lock);
870 ret = _mv88e6xxx_wait(chip, reg, offset, mask);
871 mutex_unlock(&chip->reg_lock);
Andrew Lunn3898c142015-05-06 01:09:53 +0200872
873 return ret;
874}
875
Vivien Didelotfad09c72016-06-21 12:28:20 -0400876static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
Andrew Lunn3898c142015-05-06 01:09:53 +0200877{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400878 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
Andrew Lunn3898c142015-05-06 01:09:53 +0200879 GLOBAL2_SMI_OP_BUSY);
880}
881
Vivien Didelotd24645b2016-05-09 13:22:41 -0400882static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
Andrew Lunn3898c142015-05-06 01:09:53 +0200883{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400884 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn158bc062016-04-28 21:24:06 -0400885
Vivien Didelotfad09c72016-06-21 12:28:20 -0400886 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
Andrew Lunn3898c142015-05-06 01:09:53 +0200887 GLOBAL2_EEPROM_OP_LOAD);
888}
889
Vivien Didelotd24645b2016-05-09 13:22:41 -0400890static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
Andrew Lunn3898c142015-05-06 01:09:53 +0200891{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400892 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn158bc062016-04-28 21:24:06 -0400893
Vivien Didelotfad09c72016-06-21 12:28:20 -0400894 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
Andrew Lunn3898c142015-05-06 01:09:53 +0200895 GLOBAL2_EEPROM_OP_BUSY);
896}
897
Vivien Didelotd24645b2016-05-09 13:22:41 -0400898static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
899{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400900 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotd24645b2016-05-09 13:22:41 -0400901 int ret;
902
Vivien Didelotfad09c72016-06-21 12:28:20 -0400903 mutex_lock(&chip->eeprom_mutex);
Vivien Didelotd24645b2016-05-09 13:22:41 -0400904
Vivien Didelotfad09c72016-06-21 12:28:20 -0400905 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
Vivien Didelotd24645b2016-05-09 13:22:41 -0400906 GLOBAL2_EEPROM_OP_READ |
907 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
908 if (ret < 0)
909 goto error;
910
911 ret = mv88e6xxx_eeprom_busy_wait(ds);
912 if (ret < 0)
913 goto error;
914
Vivien Didelotfad09c72016-06-21 12:28:20 -0400915 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
Vivien Didelotd24645b2016-05-09 13:22:41 -0400916error:
Vivien Didelotfad09c72016-06-21 12:28:20 -0400917 mutex_unlock(&chip->eeprom_mutex);
Vivien Didelotd24645b2016-05-09 13:22:41 -0400918 return ret;
919}
920
Andrew Lunnf8cd8752016-05-10 23:27:25 +0200921static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
922{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400923 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunnf8cd8752016-05-10 23:27:25 +0200924
Vivien Didelotfad09c72016-06-21 12:28:20 -0400925 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
926 return chip->eeprom_len;
Andrew Lunnf8cd8752016-05-10 23:27:25 +0200927
928 return 0;
929}
930
Vivien Didelotf81ec902016-05-09 13:22:58 -0400931static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
932 struct ethtool_eeprom *eeprom, u8 *data)
Vivien Didelotd24645b2016-05-09 13:22:41 -0400933{
Vivien Didelotfad09c72016-06-21 12:28:20 -0400934 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotd24645b2016-05-09 13:22:41 -0400935 int offset;
936 int len;
937 int ret;
938
Vivien Didelotfad09c72016-06-21 12:28:20 -0400939 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
Vivien Didelotd24645b2016-05-09 13:22:41 -0400940 return -EOPNOTSUPP;
941
942 offset = eeprom->offset;
943 len = eeprom->len;
944 eeprom->len = 0;
945
946 eeprom->magic = 0xc3ec4951;
947
948 ret = mv88e6xxx_eeprom_load_wait(ds);
949 if (ret < 0)
950 return ret;
951
952 if (offset & 1) {
953 int word;
954
955 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
956 if (word < 0)
957 return word;
958
959 *data++ = (word >> 8) & 0xff;
960
961 offset++;
962 len--;
963 eeprom->len++;
964 }
965
966 while (len >= 2) {
967 int word;
968
969 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
970 if (word < 0)
971 return word;
972
973 *data++ = word & 0xff;
974 *data++ = (word >> 8) & 0xff;
975
976 offset += 2;
977 len -= 2;
978 eeprom->len += 2;
979 }
980
981 if (len) {
982 int word;
983
984 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
985 if (word < 0)
986 return word;
987
988 *data++ = word & 0xff;
989
990 offset++;
991 len--;
992 eeprom->len++;
993 }
994
995 return 0;
996}
997
998static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
999{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001000 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001001 int ret;
1002
Vivien Didelotfad09c72016-06-21 12:28:20 -04001003 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001004 if (ret < 0)
1005 return ret;
1006
1007 if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
1008 return -EROFS;
1009
1010 return 0;
1011}
1012
1013static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
1014 u16 data)
1015{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001016 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001017 int ret;
1018
Vivien Didelotfad09c72016-06-21 12:28:20 -04001019 mutex_lock(&chip->eeprom_mutex);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001020
Vivien Didelotfad09c72016-06-21 12:28:20 -04001021 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001022 if (ret < 0)
1023 goto error;
1024
Vivien Didelotfad09c72016-06-21 12:28:20 -04001025 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
Vivien Didelotd24645b2016-05-09 13:22:41 -04001026 GLOBAL2_EEPROM_OP_WRITE |
1027 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
1028 if (ret < 0)
1029 goto error;
1030
1031 ret = mv88e6xxx_eeprom_busy_wait(ds);
1032error:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001033 mutex_unlock(&chip->eeprom_mutex);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001034 return ret;
1035}
1036
Vivien Didelotf81ec902016-05-09 13:22:58 -04001037static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
1038 struct ethtool_eeprom *eeprom, u8 *data)
Vivien Didelotd24645b2016-05-09 13:22:41 -04001039{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001040 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotd24645b2016-05-09 13:22:41 -04001041 int offset;
1042 int ret;
1043 int len;
1044
Vivien Didelotfad09c72016-06-21 12:28:20 -04001045 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
Vivien Didelotd24645b2016-05-09 13:22:41 -04001046 return -EOPNOTSUPP;
1047
1048 if (eeprom->magic != 0xc3ec4951)
1049 return -EINVAL;
1050
1051 ret = mv88e6xxx_eeprom_is_readonly(ds);
1052 if (ret)
1053 return ret;
1054
1055 offset = eeprom->offset;
1056 len = eeprom->len;
1057 eeprom->len = 0;
1058
1059 ret = mv88e6xxx_eeprom_load_wait(ds);
1060 if (ret < 0)
1061 return ret;
1062
1063 if (offset & 1) {
1064 int word;
1065
1066 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1067 if (word < 0)
1068 return word;
1069
1070 word = (*data++ << 8) | (word & 0xff);
1071
1072 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1073 if (ret < 0)
1074 return ret;
1075
1076 offset++;
1077 len--;
1078 eeprom->len++;
1079 }
1080
1081 while (len >= 2) {
1082 int word;
1083
1084 word = *data++;
1085 word |= *data++ << 8;
1086
1087 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1088 if (ret < 0)
1089 return ret;
1090
1091 offset += 2;
1092 len -= 2;
1093 eeprom->len += 2;
1094 }
1095
1096 if (len) {
1097 int word;
1098
1099 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1100 if (word < 0)
1101 return word;
1102
1103 word = (word & 0xff00) | *data++;
1104
1105 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1106 if (ret < 0)
1107 return ret;
1108
1109 offset++;
1110 len--;
1111 eeprom->len++;
1112 }
1113
1114 return 0;
1115}
1116
Vivien Didelotfad09c72016-06-21 12:28:20 -04001117static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001118{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001119 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
Andrew Lunncca8b132015-04-02 04:06:39 +02001120 GLOBAL_ATU_OP_BUSY);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001121}
1122
Vivien Didelotfad09c72016-06-21 12:28:20 -04001123static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001124 int addr, int regnum)
Andrew Lunnf3044682015-02-14 19:17:50 +01001125{
1126 int ret;
1127
Vivien Didelotfad09c72016-06-21 12:28:20 -04001128 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
Andrew Lunn3898c142015-05-06 01:09:53 +02001129 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1130 regnum);
Andrew Lunnf3044682015-02-14 19:17:50 +01001131 if (ret < 0)
1132 return ret;
1133
Vivien Didelotfad09c72016-06-21 12:28:20 -04001134 ret = mv88e6xxx_mdio_wait(chip);
Andrew Lunn3898c142015-05-06 01:09:53 +02001135 if (ret < 0)
1136 return ret;
1137
Vivien Didelotfad09c72016-06-21 12:28:20 -04001138 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
Andrew Lunn158bc062016-04-28 21:24:06 -04001139
1140 return ret;
Andrew Lunnf3044682015-02-14 19:17:50 +01001141}
1142
Vivien Didelotfad09c72016-06-21 12:28:20 -04001143static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001144 int addr, int regnum, u16 val)
Andrew Lunnf3044682015-02-14 19:17:50 +01001145{
Andrew Lunn3898c142015-05-06 01:09:53 +02001146 int ret;
Andrew Lunnf3044682015-02-14 19:17:50 +01001147
Vivien Didelotfad09c72016-06-21 12:28:20 -04001148 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
Andrew Lunn3898c142015-05-06 01:09:53 +02001149 if (ret < 0)
1150 return ret;
1151
Vivien Didelotfad09c72016-06-21 12:28:20 -04001152 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
Andrew Lunn3898c142015-05-06 01:09:53 +02001153 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1154 regnum);
1155
Vivien Didelotfad09c72016-06-21 12:28:20 -04001156 return mv88e6xxx_mdio_wait(chip);
Andrew Lunnf3044682015-02-14 19:17:50 +01001157}
1158
Vivien Didelotf81ec902016-05-09 13:22:58 -04001159static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1160 struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001161{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001162 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Guenter Roeck11b3b452015-03-06 22:23:51 -08001163 int reg;
1164
Vivien Didelotfad09c72016-06-21 12:28:20 -04001165 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
Vivien Didelotaadbdb82016-05-09 13:22:44 -04001166 return -EOPNOTSUPP;
1167
Vivien Didelotfad09c72016-06-21 12:28:20 -04001168 mutex_lock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001169
Vivien Didelotfad09c72016-06-21 12:28:20 -04001170 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
Guenter Roeck11b3b452015-03-06 22:23:51 -08001171 if (reg < 0)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001172 goto out;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001173
1174 e->eee_enabled = !!(reg & 0x0200);
1175 e->tx_lpi_enabled = !!(reg & 0x0100);
1176
Vivien Didelotfad09c72016-06-21 12:28:20 -04001177 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
Guenter Roeck11b3b452015-03-06 22:23:51 -08001178 if (reg < 0)
Andrew Lunn2f40c692015-04-02 04:06:37 +02001179 goto out;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001180
Andrew Lunncca8b132015-04-02 04:06:39 +02001181 e->eee_active = !!(reg & PORT_STATUS_EEE);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001182 reg = 0;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001183
Andrew Lunn2f40c692015-04-02 04:06:37 +02001184out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001185 mutex_unlock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001186 return reg;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001187}
1188
Vivien Didelotf81ec902016-05-09 13:22:58 -04001189static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1190 struct phy_device *phydev, struct ethtool_eee *e)
Guenter Roeck11b3b452015-03-06 22:23:51 -08001191{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001192 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001193 int reg;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001194 int ret;
1195
Vivien Didelotfad09c72016-06-21 12:28:20 -04001196 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
Vivien Didelotaadbdb82016-05-09 13:22:44 -04001197 return -EOPNOTSUPP;
1198
Vivien Didelotfad09c72016-06-21 12:28:20 -04001199 mutex_lock(&chip->reg_lock);
Guenter Roeck11b3b452015-03-06 22:23:51 -08001200
Vivien Didelotfad09c72016-06-21 12:28:20 -04001201 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001202 if (ret < 0)
1203 goto out;
1204
1205 reg = ret & ~0x0300;
1206 if (e->eee_enabled)
1207 reg |= 0x0200;
1208 if (e->tx_lpi_enabled)
1209 reg |= 0x0100;
1210
Vivien Didelotfad09c72016-06-21 12:28:20 -04001211 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001212out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001213 mutex_unlock(&chip->reg_lock);
Andrew Lunn2f40c692015-04-02 04:06:37 +02001214
1215 return ret;
Guenter Roeck11b3b452015-03-06 22:23:51 -08001216}
1217
Vivien Didelotfad09c72016-06-21 12:28:20 -04001218static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001219{
1220 int ret;
1221
Vivien Didelotfad09c72016-06-21 12:28:20 -04001222 if (mv88e6xxx_has_fid_reg(chip)) {
1223 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
1224 fid);
Vivien Didelotb426e5f2016-03-31 16:53:42 -04001225 if (ret < 0)
1226 return ret;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001227 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001228 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001229 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
Vivien Didelot11ea8092016-03-31 16:53:44 -04001230 if (ret < 0)
1231 return ret;
1232
Vivien Didelotfad09c72016-06-21 12:28:20 -04001233 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
Vivien Didelot11ea8092016-03-31 16:53:44 -04001234 (ret & 0xfff) |
1235 ((fid << 8) & 0xf000));
1236 if (ret < 0)
1237 return ret;
1238
1239 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1240 cmd |= fid & 0xf;
Vivien Didelotb426e5f2016-03-31 16:53:42 -04001241 }
1242
Vivien Didelotfad09c72016-06-21 12:28:20 -04001243 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001244 if (ret < 0)
1245 return ret;
1246
Vivien Didelotfad09c72016-06-21 12:28:20 -04001247 return _mv88e6xxx_atu_wait(chip);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001248}
1249
Vivien Didelotfad09c72016-06-21 12:28:20 -04001250static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelot37705b72015-09-04 14:34:11 -04001251 struct mv88e6xxx_atu_entry *entry)
1252{
1253 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1254
1255 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1256 unsigned int mask, shift;
1257
1258 if (entry->trunk) {
1259 data |= GLOBAL_ATU_DATA_TRUNK;
1260 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1261 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1262 } else {
1263 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1264 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1265 }
1266
1267 data |= (entry->portv_trunkid << shift) & mask;
1268 }
1269
Vivien Didelotfad09c72016-06-21 12:28:20 -04001270 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
Vivien Didelot37705b72015-09-04 14:34:11 -04001271}
1272
Vivien Didelotfad09c72016-06-21 12:28:20 -04001273static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001274 struct mv88e6xxx_atu_entry *entry,
1275 bool static_too)
1276{
1277 int op;
1278 int err;
1279
Vivien Didelotfad09c72016-06-21 12:28:20 -04001280 err = _mv88e6xxx_atu_wait(chip);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001281 if (err)
1282 return err;
1283
Vivien Didelotfad09c72016-06-21 12:28:20 -04001284 err = _mv88e6xxx_atu_data_write(chip, entry);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001285 if (err)
1286 return err;
1287
1288 if (entry->fid) {
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001289 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1290 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1291 } else {
1292 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1293 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1294 }
1295
Vivien Didelotfad09c72016-06-21 12:28:20 -04001296 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001297}
1298
Vivien Didelotfad09c72016-06-21 12:28:20 -04001299static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001300 u16 fid, bool static_too)
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001301{
1302 struct mv88e6xxx_atu_entry entry = {
1303 .fid = fid,
1304 .state = 0, /* EntryState bits must be 0 */
1305 };
1306
Vivien Didelotfad09c72016-06-21 12:28:20 -04001307 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
Vivien Didelot7fb5e752015-09-04 14:34:12 -04001308}
1309
Vivien Didelotfad09c72016-06-21 12:28:20 -04001310static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
Andrew Lunn158bc062016-04-28 21:24:06 -04001311 int from_port, int to_port, bool static_too)
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001312{
1313 struct mv88e6xxx_atu_entry entry = {
1314 .trunk = false,
1315 .fid = fid,
1316 };
1317
1318 /* EntryState bits must be 0xF */
1319 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1320
1321 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1322 entry.portv_trunkid = (to_port & 0x0f) << 4;
1323 entry.portv_trunkid |= from_port & 0x0f;
1324
Vivien Didelotfad09c72016-06-21 12:28:20 -04001325 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001326}
1327
Vivien Didelotfad09c72016-06-21 12:28:20 -04001328static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
Andrew Lunn158bc062016-04-28 21:24:06 -04001329 int port, bool static_too)
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001330{
1331 /* Destination port 0xF means remove the entries */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001332 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
Vivien Didelot9f4d55d2015-09-04 14:34:15 -04001333}
1334
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001335static const char * const mv88e6xxx_port_state_names[] = {
1336 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1337 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1338 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1339 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1340};
1341
Vivien Didelotfad09c72016-06-21 12:28:20 -04001342static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
Andrew Lunn158bc062016-04-28 21:24:06 -04001343 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001344{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001345 struct dsa_switch *ds = chip->ds;
Geert Uytterhoevenc3ffe6d2015-04-16 20:49:14 +02001346 int reg, ret = 0;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001347 u8 oldstate;
1348
Vivien Didelotfad09c72016-06-21 12:28:20 -04001349 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001350 if (reg < 0)
1351 return reg;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001352
Andrew Lunncca8b132015-04-02 04:06:39 +02001353 oldstate = reg & PORT_CONTROL_STATE_MASK;
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001354
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001355 if (oldstate != state) {
1356 /* Flush forwarding database if we're moving a port
1357 * from Learning or Forwarding state to Disabled or
1358 * Blocking or Listening state.
1359 */
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001360 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
Vivien Didelot57d32312016-06-20 13:13:58 -04001361 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1362 (state == PORT_CONTROL_STATE_DISABLED ||
1363 state == PORT_CONTROL_STATE_BLOCKING)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001364 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001365 if (ret)
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001366 return ret;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001367 }
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001368
Andrew Lunncca8b132015-04-02 04:06:39 +02001369 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001370 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
Andrew Lunncca8b132015-04-02 04:06:39 +02001371 reg);
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001372 if (ret)
1373 return ret;
1374
Andrew Lunnc8b09802016-06-04 21:16:57 +02001375 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
Vivien Didelot2d9deae2016-03-07 18:24:17 -05001376 mv88e6xxx_port_state_names[state],
1377 mv88e6xxx_port_state_names[oldstate]);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001378 }
1379
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001380 return ret;
1381}
1382
Vivien Didelotfad09c72016-06-21 12:28:20 -04001383static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001384{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001385 struct net_device *bridge = chip->ports[port].bridge_dev;
1386 const u16 mask = (1 << chip->info->num_ports) - 1;
1387 struct dsa_switch *ds = chip->ds;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001388 u16 output_ports = 0;
Vivien Didelotede80982015-10-11 18:08:35 -04001389 int reg;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001390 int i;
1391
1392 /* allow CPU port or DSA link(s) to send frames to every port */
1393 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1394 output_ports = mask;
1395 } else {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001396 for (i = 0; i < chip->info->num_ports; ++i) {
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001397 /* allow sending frames to every group member */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001398 if (bridge && chip->ports[i].bridge_dev == bridge)
Vivien Didelotb7666ef2016-02-26 13:16:06 -05001399 output_ports |= BIT(i);
1400
1401 /* allow sending frames to CPU port and DSA link(s) */
1402 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1403 output_ports |= BIT(i);
1404 }
1405 }
1406
1407 /* prevent frames from going back out of the port they came in on */
1408 output_ports &= ~BIT(port);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001409
Vivien Didelotfad09c72016-06-21 12:28:20 -04001410 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
Vivien Didelotede80982015-10-11 18:08:35 -04001411 if (reg < 0)
1412 return reg;
1413
1414 reg &= ~mask;
1415 reg |= output_ports & mask;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001416
Vivien Didelotfad09c72016-06-21 12:28:20 -04001417 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001418}
1419
Vivien Didelotf81ec902016-05-09 13:22:58 -04001420static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1421 u8 state)
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001422{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001423 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001424 int stp_state;
Vivien Didelot553eb542016-05-13 20:38:23 -04001425 int err;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001426
1427 switch (state) {
1428 case BR_STATE_DISABLED:
Andrew Lunncca8b132015-04-02 04:06:39 +02001429 stp_state = PORT_CONTROL_STATE_DISABLED;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001430 break;
1431 case BR_STATE_BLOCKING:
1432 case BR_STATE_LISTENING:
Andrew Lunncca8b132015-04-02 04:06:39 +02001433 stp_state = PORT_CONTROL_STATE_BLOCKING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001434 break;
1435 case BR_STATE_LEARNING:
Andrew Lunncca8b132015-04-02 04:06:39 +02001436 stp_state = PORT_CONTROL_STATE_LEARNING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001437 break;
1438 case BR_STATE_FORWARDING:
1439 default:
Andrew Lunncca8b132015-04-02 04:06:39 +02001440 stp_state = PORT_CONTROL_STATE_FORWARDING;
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001441 break;
1442 }
1443
Vivien Didelotfad09c72016-06-21 12:28:20 -04001444 mutex_lock(&chip->reg_lock);
1445 err = _mv88e6xxx_port_state(chip, port, stp_state);
1446 mutex_unlock(&chip->reg_lock);
Vivien Didelot553eb542016-05-13 20:38:23 -04001447
1448 if (err)
Andrew Lunnc8b09802016-06-04 21:16:57 +02001449 netdev_err(ds->ports[port].netdev,
1450 "failed to update state to %s\n",
Vivien Didelot553eb542016-05-13 20:38:23 -04001451 mv88e6xxx_port_state_names[stp_state]);
Guenter Roeckfacd95b2015-03-26 18:36:35 -07001452}
1453
Vivien Didelotfad09c72016-06-21 12:28:20 -04001454static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
Andrew Lunn158bc062016-04-28 21:24:06 -04001455 u16 *new, u16 *old)
Vivien Didelot76e398a2015-11-01 12:33:55 -05001456{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001457 struct dsa_switch *ds = chip->ds;
Vivien Didelot5da96032016-03-07 18:24:39 -05001458 u16 pvid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001459 int ret;
1460
Vivien Didelotfad09c72016-06-21 12:28:20 -04001461 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
Vivien Didelot76e398a2015-11-01 12:33:55 -05001462 if (ret < 0)
1463 return ret;
1464
Vivien Didelot5da96032016-03-07 18:24:39 -05001465 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1466
1467 if (new) {
1468 ret &= ~PORT_DEFAULT_VLAN_MASK;
1469 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1470
Vivien Didelotfad09c72016-06-21 12:28:20 -04001471 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Vivien Didelot5da96032016-03-07 18:24:39 -05001472 PORT_DEFAULT_VLAN, ret);
1473 if (ret < 0)
1474 return ret;
1475
Andrew Lunnc8b09802016-06-04 21:16:57 +02001476 netdev_dbg(ds->ports[port].netdev,
1477 "DefaultVID %d (was %d)\n", *new, pvid);
Vivien Didelot5da96032016-03-07 18:24:39 -05001478 }
1479
1480 if (old)
1481 *old = pvid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05001482
1483 return 0;
1484}
1485
Vivien Didelotfad09c72016-06-21 12:28:20 -04001486static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001487 int port, u16 *pvid)
Vivien Didelot5da96032016-03-07 18:24:39 -05001488{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001489 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
Vivien Didelot5da96032016-03-07 18:24:39 -05001490}
1491
Vivien Didelotfad09c72016-06-21 12:28:20 -04001492static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001493 int port, u16 pvid)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001494{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001495 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001496}
1497
Vivien Didelotfad09c72016-06-21 12:28:20 -04001498static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
Vivien Didelot6b17e862015-08-13 12:52:18 -04001499{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001500 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
Vivien Didelot6b17e862015-08-13 12:52:18 -04001501 GLOBAL_VTU_OP_BUSY);
1502}
1503
Vivien Didelotfad09c72016-06-21 12:28:20 -04001504static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
Vivien Didelot6b17e862015-08-13 12:52:18 -04001505{
1506 int ret;
1507
Vivien Didelotfad09c72016-06-21 12:28:20 -04001508 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001509 if (ret < 0)
1510 return ret;
1511
Vivien Didelotfad09c72016-06-21 12:28:20 -04001512 return _mv88e6xxx_vtu_wait(chip);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001513}
1514
Vivien Didelotfad09c72016-06-21 12:28:20 -04001515static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
Vivien Didelot6b17e862015-08-13 12:52:18 -04001516{
1517 int ret;
1518
Vivien Didelotfad09c72016-06-21 12:28:20 -04001519 ret = _mv88e6xxx_vtu_wait(chip);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001520 if (ret < 0)
1521 return ret;
1522
Vivien Didelotfad09c72016-06-21 12:28:20 -04001523 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
Vivien Didelot6b17e862015-08-13 12:52:18 -04001524}
1525
Vivien Didelotfad09c72016-06-21 12:28:20 -04001526static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
Vivien Didelotb8fee952015-08-13 12:52:19 -04001527 struct mv88e6xxx_vtu_stu_entry *entry,
1528 unsigned int nibble_offset)
1529{
Vivien Didelotb8fee952015-08-13 12:52:19 -04001530 u16 regs[3];
1531 int i;
1532 int ret;
1533
1534 for (i = 0; i < 3; ++i) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001535 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
Vivien Didelotb8fee952015-08-13 12:52:19 -04001536 GLOBAL_VTU_DATA_0_3 + i);
1537 if (ret < 0)
1538 return ret;
1539
1540 regs[i] = ret;
1541 }
1542
Vivien Didelotfad09c72016-06-21 12:28:20 -04001543 for (i = 0; i < chip->info->num_ports; ++i) {
Vivien Didelotb8fee952015-08-13 12:52:19 -04001544 unsigned int shift = (i % 4) * 4 + nibble_offset;
1545 u16 reg = regs[i / 4];
1546
1547 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1548 }
1549
1550 return 0;
1551}
1552
Vivien Didelotfad09c72016-06-21 12:28:20 -04001553static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001554 struct mv88e6xxx_vtu_stu_entry *entry)
1555{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001556 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001557}
1558
Vivien Didelotfad09c72016-06-21 12:28:20 -04001559static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001560 struct mv88e6xxx_vtu_stu_entry *entry)
1561{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001562 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001563}
1564
Vivien Didelotfad09c72016-06-21 12:28:20 -04001565static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001566 struct mv88e6xxx_vtu_stu_entry *entry,
1567 unsigned int nibble_offset)
1568{
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001569 u16 regs[3] = { 0 };
1570 int i;
1571 int ret;
1572
Vivien Didelotfad09c72016-06-21 12:28:20 -04001573 for (i = 0; i < chip->info->num_ports; ++i) {
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001574 unsigned int shift = (i % 4) * 4 + nibble_offset;
1575 u8 data = entry->data[i];
1576
1577 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1578 }
1579
1580 for (i = 0; i < 3; ++i) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001581 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001582 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1583 if (ret < 0)
1584 return ret;
1585 }
1586
1587 return 0;
1588}
1589
Vivien Didelotfad09c72016-06-21 12:28:20 -04001590static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001591 struct mv88e6xxx_vtu_stu_entry *entry)
1592{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001593 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001594}
1595
Vivien Didelotfad09c72016-06-21 12:28:20 -04001596static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001597 struct mv88e6xxx_vtu_stu_entry *entry)
1598{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001599 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
Vivien Didelot15d7d7d2016-05-10 15:44:28 -04001600}
1601
Vivien Didelotfad09c72016-06-21 12:28:20 -04001602static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
Vivien Didelot36d04ba12015-10-22 09:34:39 -04001603{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001604 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
Vivien Didelot36d04ba12015-10-22 09:34:39 -04001605 vid & GLOBAL_VTU_VID_MASK);
1606}
1607
Vivien Didelotfad09c72016-06-21 12:28:20 -04001608static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
Vivien Didelotb8fee952015-08-13 12:52:19 -04001609 struct mv88e6xxx_vtu_stu_entry *entry)
1610{
1611 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1612 int ret;
1613
Vivien Didelotfad09c72016-06-21 12:28:20 -04001614 ret = _mv88e6xxx_vtu_wait(chip);
Vivien Didelotb8fee952015-08-13 12:52:19 -04001615 if (ret < 0)
1616 return ret;
1617
Vivien Didelotfad09c72016-06-21 12:28:20 -04001618 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
Vivien Didelotb8fee952015-08-13 12:52:19 -04001619 if (ret < 0)
1620 return ret;
1621
Vivien Didelotfad09c72016-06-21 12:28:20 -04001622 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
Vivien Didelotb8fee952015-08-13 12:52:19 -04001623 if (ret < 0)
1624 return ret;
1625
1626 next.vid = ret & GLOBAL_VTU_VID_MASK;
1627 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1628
1629 if (next.valid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001630 ret = mv88e6xxx_vtu_data_read(chip, &next);
Vivien Didelotb8fee952015-08-13 12:52:19 -04001631 if (ret < 0)
1632 return ret;
1633
Vivien Didelotfad09c72016-06-21 12:28:20 -04001634 if (mv88e6xxx_has_fid_reg(chip)) {
1635 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
Vivien Didelotb8fee952015-08-13 12:52:19 -04001636 GLOBAL_VTU_FID);
1637 if (ret < 0)
1638 return ret;
1639
1640 next.fid = ret & GLOBAL_VTU_FID_MASK;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001641 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001642 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1643 * VTU DBNum[3:0] are located in VTU Operation 3:0
1644 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001645 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
Vivien Didelot11ea8092016-03-31 16:53:44 -04001646 GLOBAL_VTU_OP);
1647 if (ret < 0)
1648 return ret;
1649
1650 next.fid = (ret & 0xf00) >> 4;
1651 next.fid |= ret & 0xf;
Vivien Didelot2e7bd5e2016-03-31 16:53:41 -04001652 }
Vivien Didelotb8fee952015-08-13 12:52:19 -04001653
Vivien Didelotfad09c72016-06-21 12:28:20 -04001654 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1655 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
Vivien Didelotb8fee952015-08-13 12:52:19 -04001656 GLOBAL_VTU_SID);
1657 if (ret < 0)
1658 return ret;
1659
1660 next.sid = ret & GLOBAL_VTU_SID_MASK;
1661 }
1662 }
1663
1664 *entry = next;
1665 return 0;
1666}
1667
Vivien Didelotf81ec902016-05-09 13:22:58 -04001668static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1669 struct switchdev_obj_port_vlan *vlan,
1670 int (*cb)(struct switchdev_obj *obj))
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001671{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001672 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001673 struct mv88e6xxx_vtu_stu_entry next;
1674 u16 pvid;
1675 int err;
1676
Vivien Didelotfad09c72016-06-21 12:28:20 -04001677 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04001678 return -EOPNOTSUPP;
1679
Vivien Didelotfad09c72016-06-21 12:28:20 -04001680 mutex_lock(&chip->reg_lock);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001681
Vivien Didelotfad09c72016-06-21 12:28:20 -04001682 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001683 if (err)
1684 goto unlock;
1685
Vivien Didelotfad09c72016-06-21 12:28:20 -04001686 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001687 if (err)
1688 goto unlock;
1689
1690 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001691 err = _mv88e6xxx_vtu_getnext(chip, &next);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001692 if (err)
1693 break;
1694
1695 if (!next.valid)
1696 break;
1697
1698 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1699 continue;
1700
1701 /* reinit and dump this VLAN obj */
Vivien Didelot57d32312016-06-20 13:13:58 -04001702 vlan->vid_begin = next.vid;
1703 vlan->vid_end = next.vid;
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001704 vlan->flags = 0;
1705
1706 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1707 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1708
1709 if (next.vid == pvid)
1710 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1711
1712 err = cb(&vlan->obj);
1713 if (err)
1714 break;
1715 } while (next.vid < GLOBAL_VTU_VID_MASK);
1716
1717unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001718 mutex_unlock(&chip->reg_lock);
Vivien Didelotceff5ef2016-02-23 12:13:55 -05001719
1720 return err;
1721}
1722
Vivien Didelotfad09c72016-06-21 12:28:20 -04001723static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001724 struct mv88e6xxx_vtu_stu_entry *entry)
1725{
Vivien Didelot11ea8092016-03-31 16:53:44 -04001726 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001727 u16 reg = 0;
1728 int ret;
1729
Vivien Didelotfad09c72016-06-21 12:28:20 -04001730 ret = _mv88e6xxx_vtu_wait(chip);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001731 if (ret < 0)
1732 return ret;
1733
1734 if (!entry->valid)
1735 goto loadpurge;
1736
1737 /* Write port member tags */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001738 ret = mv88e6xxx_vtu_data_write(chip, entry);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001739 if (ret < 0)
1740 return ret;
1741
Vivien Didelotfad09c72016-06-21 12:28:20 -04001742 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001743 reg = entry->sid & GLOBAL_VTU_SID_MASK;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001744 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1745 reg);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001746 if (ret < 0)
1747 return ret;
Vivien Didelotb426e5f2016-03-31 16:53:42 -04001748 }
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001749
Vivien Didelotfad09c72016-06-21 12:28:20 -04001750 if (mv88e6xxx_has_fid_reg(chip)) {
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001751 reg = entry->fid & GLOBAL_VTU_FID_MASK;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001752 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1753 reg);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001754 if (ret < 0)
1755 return ret;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001756 } else if (mv88e6xxx_num_databases(chip) == 256) {
Vivien Didelot11ea8092016-03-31 16:53:44 -04001757 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1758 * VTU DBNum[3:0] are located in VTU Operation 3:0
1759 */
1760 op |= (entry->fid & 0xf0) << 8;
1761 op |= entry->fid & 0xf;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001762 }
1763
1764 reg = GLOBAL_VTU_VID_VALID;
1765loadpurge:
1766 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001767 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001768 if (ret < 0)
1769 return ret;
1770
Vivien Didelotfad09c72016-06-21 12:28:20 -04001771 return _mv88e6xxx_vtu_cmd(chip, op);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04001772}
1773
Vivien Didelotfad09c72016-06-21 12:28:20 -04001774static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001775 struct mv88e6xxx_vtu_stu_entry *entry)
1776{
1777 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1778 int ret;
1779
Vivien Didelotfad09c72016-06-21 12:28:20 -04001780 ret = _mv88e6xxx_vtu_wait(chip);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001781 if (ret < 0)
1782 return ret;
1783
Vivien Didelotfad09c72016-06-21 12:28:20 -04001784 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001785 sid & GLOBAL_VTU_SID_MASK);
1786 if (ret < 0)
1787 return ret;
1788
Vivien Didelotfad09c72016-06-21 12:28:20 -04001789 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001790 if (ret < 0)
1791 return ret;
1792
Vivien Didelotfad09c72016-06-21 12:28:20 -04001793 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001794 if (ret < 0)
1795 return ret;
1796
1797 next.sid = ret & GLOBAL_VTU_SID_MASK;
1798
Vivien Didelotfad09c72016-06-21 12:28:20 -04001799 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001800 if (ret < 0)
1801 return ret;
1802
1803 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1804
1805 if (next.valid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001806 ret = mv88e6xxx_stu_data_read(chip, &next);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001807 if (ret < 0)
1808 return ret;
1809 }
1810
1811 *entry = next;
1812 return 0;
1813}
1814
Vivien Didelotfad09c72016-06-21 12:28:20 -04001815static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001816 struct mv88e6xxx_vtu_stu_entry *entry)
1817{
1818 u16 reg = 0;
1819 int ret;
1820
Vivien Didelotfad09c72016-06-21 12:28:20 -04001821 ret = _mv88e6xxx_vtu_wait(chip);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001822 if (ret < 0)
1823 return ret;
1824
1825 if (!entry->valid)
1826 goto loadpurge;
1827
1828 /* Write port states */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001829 ret = mv88e6xxx_stu_data_write(chip, entry);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001830 if (ret < 0)
1831 return ret;
1832
1833 reg = GLOBAL_VTU_VID_VALID;
1834loadpurge:
Vivien Didelotfad09c72016-06-21 12:28:20 -04001835 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001836 if (ret < 0)
1837 return ret;
1838
1839 reg = entry->sid & GLOBAL_VTU_SID_MASK;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001840 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001841 if (ret < 0)
1842 return ret;
1843
Vivien Didelotfad09c72016-06-21 12:28:20 -04001844 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001845}
1846
Vivien Didelotfad09c72016-06-21 12:28:20 -04001847static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
Andrew Lunn158bc062016-04-28 21:24:06 -04001848 u16 *new, u16 *old)
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001849{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001850 struct dsa_switch *ds = chip->ds;
Vivien Didelotf74df0b2016-03-31 16:53:43 -04001851 u16 upper_mask;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001852 u16 fid;
1853 int ret;
1854
Vivien Didelotfad09c72016-06-21 12:28:20 -04001855 if (mv88e6xxx_num_databases(chip) == 4096)
Vivien Didelotf74df0b2016-03-31 16:53:43 -04001856 upper_mask = 0xff;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001857 else if (mv88e6xxx_num_databases(chip) == 256)
Vivien Didelot11ea8092016-03-31 16:53:44 -04001858 upper_mask = 0xf;
Vivien Didelotf74df0b2016-03-31 16:53:43 -04001859 else
1860 return -EOPNOTSUPP;
1861
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001862 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001863 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001864 if (ret < 0)
1865 return ret;
1866
1867 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1868
1869 if (new) {
1870 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1871 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1872
Vivien Didelotfad09c72016-06-21 12:28:20 -04001873 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001874 ret);
1875 if (ret < 0)
1876 return ret;
1877 }
1878
1879 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001880 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001881 if (ret < 0)
1882 return ret;
1883
Vivien Didelotf74df0b2016-03-31 16:53:43 -04001884 fid |= (ret & upper_mask) << 4;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001885
1886 if (new) {
Vivien Didelotf74df0b2016-03-31 16:53:43 -04001887 ret &= ~upper_mask;
1888 ret |= (*new >> 4) & upper_mask;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001889
Vivien Didelotfad09c72016-06-21 12:28:20 -04001890 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001891 ret);
1892 if (ret < 0)
1893 return ret;
1894
Andrew Lunnc8b09802016-06-04 21:16:57 +02001895 netdev_dbg(ds->ports[port].netdev,
1896 "FID %d (was %d)\n", *new, fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001897 }
1898
1899 if (old)
1900 *old = fid;
1901
1902 return 0;
1903}
1904
Vivien Didelotfad09c72016-06-21 12:28:20 -04001905static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001906 int port, u16 *fid)
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001907{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001908 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001909}
1910
Vivien Didelotfad09c72016-06-21 12:28:20 -04001911static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04001912 int port, u16 fid)
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001913{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001914 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001915}
1916
Vivien Didelotfad09c72016-06-21 12:28:20 -04001917static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001918{
1919 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1920 struct mv88e6xxx_vtu_stu_entry vlan;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001921 int i, err;
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001922
1923 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1924
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001925 /* Set every FID bit used by the (un)bridged ports */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001926 for (i = 0; i < chip->info->num_ports; ++i) {
1927 err = _mv88e6xxx_port_fid_get(chip, i, fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05001928 if (err)
1929 return err;
1930
1931 set_bit(*fid, fid_bitmap);
1932 }
1933
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001934 /* Set every FID bit used by the VLAN entries */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001935 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001936 if (err)
1937 return err;
1938
1939 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04001940 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001941 if (err)
1942 return err;
1943
1944 if (!vlan.valid)
1945 break;
1946
1947 set_bit(vlan.fid, fid_bitmap);
1948 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1949
1950 /* The reset value 0x000 is used to indicate that multiple address
1951 * databases are not needed. Return the next positive available.
1952 */
1953 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
Vivien Didelotfad09c72016-06-21 12:28:20 -04001954 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001955 return -ENOSPC;
1956
1957 /* Clear the database */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001958 return _mv88e6xxx_atu_flush(chip, *fid, true);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001959}
1960
Vivien Didelotfad09c72016-06-21 12:28:20 -04001961static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05001962 struct mv88e6xxx_vtu_stu_entry *entry)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001963{
Vivien Didelotfad09c72016-06-21 12:28:20 -04001964 struct dsa_switch *ds = chip->ds;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001965 struct mv88e6xxx_vtu_stu_entry vlan = {
1966 .valid = true,
1967 .vid = vid,
1968 };
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001969 int i, err;
1970
Vivien Didelotfad09c72016-06-21 12:28:20 -04001971 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05001972 if (err)
1973 return err;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001974
Vivien Didelot3d131f02015-11-03 10:52:52 -05001975 /* exclude all ports except the CPU and DSA ports */
Vivien Didelotfad09c72016-06-21 12:28:20 -04001976 for (i = 0; i < chip->info->num_ports; ++i)
Vivien Didelot3d131f02015-11-03 10:52:52 -05001977 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1978 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1979 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001980
Vivien Didelotfad09c72016-06-21 12:28:20 -04001981 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1982 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001983 struct mv88e6xxx_vtu_stu_entry vstp;
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001984
1985 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1986 * implemented, only one STU entry is needed to cover all VTU
1987 * entries. Thus, validate the SID 0.
1988 */
1989 vlan.sid = 0;
Vivien Didelotfad09c72016-06-21 12:28:20 -04001990 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04001991 if (err)
1992 return err;
1993
1994 if (vstp.sid != vlan.sid || !vstp.valid) {
1995 memset(&vstp, 0, sizeof(vstp));
1996 vstp.valid = true;
1997 vstp.sid = vlan.sid;
1998
Vivien Didelotfad09c72016-06-21 12:28:20 -04001999 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002000 if (err)
2001 return err;
2002 }
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002003 }
2004
2005 *entry = vlan;
2006 return 0;
2007}
2008
Vivien Didelotfad09c72016-06-21 12:28:20 -04002009static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05002010 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
2011{
2012 int err;
2013
2014 if (!vid)
2015 return -EINVAL;
2016
Vivien Didelotfad09c72016-06-21 12:28:20 -04002017 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05002018 if (err)
2019 return err;
2020
Vivien Didelotfad09c72016-06-21 12:28:20 -04002021 err = _mv88e6xxx_vtu_getnext(chip, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05002022 if (err)
2023 return err;
2024
2025 if (entry->vid != vid || !entry->valid) {
2026 if (!creat)
2027 return -EOPNOTSUPP;
2028 /* -ENOENT would've been more appropriate, but switchdev expects
2029 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
2030 */
2031
Vivien Didelotfad09c72016-06-21 12:28:20 -04002032 err = _mv88e6xxx_vtu_new(chip, vid, entry);
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05002033 }
2034
2035 return err;
2036}
2037
Vivien Didelotda9c3592016-02-12 12:09:40 -05002038static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2039 u16 vid_begin, u16 vid_end)
2040{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002041 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotda9c3592016-02-12 12:09:40 -05002042 struct mv88e6xxx_vtu_stu_entry vlan;
2043 int i, err;
2044
2045 if (!vid_begin)
2046 return -EOPNOTSUPP;
2047
Vivien Didelotfad09c72016-06-21 12:28:20 -04002048 mutex_lock(&chip->reg_lock);
Vivien Didelotda9c3592016-02-12 12:09:40 -05002049
Vivien Didelotfad09c72016-06-21 12:28:20 -04002050 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
Vivien Didelotda9c3592016-02-12 12:09:40 -05002051 if (err)
2052 goto unlock;
2053
2054 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002055 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelotda9c3592016-02-12 12:09:40 -05002056 if (err)
2057 goto unlock;
2058
2059 if (!vlan.valid)
2060 break;
2061
2062 if (vlan.vid > vid_end)
2063 break;
2064
Vivien Didelotfad09c72016-06-21 12:28:20 -04002065 for (i = 0; i < chip->info->num_ports; ++i) {
Vivien Didelotda9c3592016-02-12 12:09:40 -05002066 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2067 continue;
2068
2069 if (vlan.data[i] ==
2070 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2071 continue;
2072
Vivien Didelotfad09c72016-06-21 12:28:20 -04002073 if (chip->ports[i].bridge_dev ==
2074 chip->ports[port].bridge_dev)
Vivien Didelotda9c3592016-02-12 12:09:40 -05002075 break; /* same bridge, check next VLAN */
2076
Andrew Lunnc8b09802016-06-04 21:16:57 +02002077 netdev_warn(ds->ports[port].netdev,
Vivien Didelotda9c3592016-02-12 12:09:40 -05002078 "hardware VLAN %d already used by %s\n",
2079 vlan.vid,
Vivien Didelotfad09c72016-06-21 12:28:20 -04002080 netdev_name(chip->ports[i].bridge_dev));
Vivien Didelotda9c3592016-02-12 12:09:40 -05002081 err = -EOPNOTSUPP;
2082 goto unlock;
2083 }
2084 } while (vlan.vid < vid_end);
2085
2086unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002087 mutex_unlock(&chip->reg_lock);
Vivien Didelotda9c3592016-02-12 12:09:40 -05002088
2089 return err;
2090}
2091
Vivien Didelot214cdb92016-02-26 13:16:08 -05002092static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2093 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2094 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2095 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2096 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2097};
2098
Vivien Didelotf81ec902016-05-09 13:22:58 -04002099static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2100 bool vlan_filtering)
Vivien Didelot214cdb92016-02-26 13:16:08 -05002101{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002102 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelot214cdb92016-02-26 13:16:08 -05002103 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2104 PORT_CONTROL_2_8021Q_DISABLED;
2105 int ret;
2106
Vivien Didelotfad09c72016-06-21 12:28:20 -04002107 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002108 return -EOPNOTSUPP;
2109
Vivien Didelotfad09c72016-06-21 12:28:20 -04002110 mutex_lock(&chip->reg_lock);
Vivien Didelot214cdb92016-02-26 13:16:08 -05002111
Vivien Didelotfad09c72016-06-21 12:28:20 -04002112 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
Vivien Didelot214cdb92016-02-26 13:16:08 -05002113 if (ret < 0)
2114 goto unlock;
2115
2116 old = ret & PORT_CONTROL_2_8021Q_MASK;
2117
Vivien Didelot5220ef12016-03-07 18:24:52 -05002118 if (new != old) {
2119 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2120 ret |= new & PORT_CONTROL_2_8021Q_MASK;
Vivien Didelot214cdb92016-02-26 13:16:08 -05002121
Vivien Didelotfad09c72016-06-21 12:28:20 -04002122 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
Vivien Didelot5220ef12016-03-07 18:24:52 -05002123 ret);
2124 if (ret < 0)
2125 goto unlock;
Vivien Didelot214cdb92016-02-26 13:16:08 -05002126
Andrew Lunnc8b09802016-06-04 21:16:57 +02002127 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
Vivien Didelot5220ef12016-03-07 18:24:52 -05002128 mv88e6xxx_port_8021q_mode_names[new],
2129 mv88e6xxx_port_8021q_mode_names[old]);
2130 }
2131
2132 ret = 0;
Vivien Didelot214cdb92016-02-26 13:16:08 -05002133unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002134 mutex_unlock(&chip->reg_lock);
Vivien Didelot214cdb92016-02-26 13:16:08 -05002135
2136 return ret;
2137}
2138
Vivien Didelot57d32312016-06-20 13:13:58 -04002139static int
2140mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2141 const struct switchdev_obj_port_vlan *vlan,
2142 struct switchdev_trans *trans)
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002143{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002144 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotda9c3592016-02-12 12:09:40 -05002145 int err;
2146
Vivien Didelotfad09c72016-06-21 12:28:20 -04002147 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002148 return -EOPNOTSUPP;
2149
Vivien Didelotda9c3592016-02-12 12:09:40 -05002150 /* If the requested port doesn't belong to the same bridge as the VLAN
2151 * members, do not support it (yet) and fallback to software VLAN.
2152 */
2153 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2154 vlan->vid_end);
2155 if (err)
2156 return err;
2157
Vivien Didelot76e398a2015-11-01 12:33:55 -05002158 /* We don't need any dynamic resource from the kernel (yet),
2159 * so skip the prepare phase.
2160 */
2161 return 0;
2162}
2163
Vivien Didelotfad09c72016-06-21 12:28:20 -04002164static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
Andrew Lunn158bc062016-04-28 21:24:06 -04002165 u16 vid, bool untagged)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002166{
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002167 struct mv88e6xxx_vtu_stu_entry vlan;
2168 int err;
2169
Vivien Didelotfad09c72016-06-21 12:28:20 -04002170 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
Vivien Didelot36d04ba12015-10-22 09:34:39 -04002171 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002172 return err;
Vivien Didelot36d04ba12015-10-22 09:34:39 -04002173
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002174 vlan.data[port] = untagged ?
2175 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2176 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2177
Vivien Didelotfad09c72016-06-21 12:28:20 -04002178 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002179}
2180
Vivien Didelotf81ec902016-05-09 13:22:58 -04002181static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2182 const struct switchdev_obj_port_vlan *vlan,
2183 struct switchdev_trans *trans)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002184{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002185 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002186 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2187 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2188 u16 vid;
Vivien Didelot76e398a2015-11-01 12:33:55 -05002189
Vivien Didelotfad09c72016-06-21 12:28:20 -04002190 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002191 return;
2192
Vivien Didelotfad09c72016-06-21 12:28:20 -04002193 mutex_lock(&chip->reg_lock);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002194
Vivien Didelot4d5770b2016-04-06 11:55:05 -04002195 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
Vivien Didelotfad09c72016-06-21 12:28:20 -04002196 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
Andrew Lunnc8b09802016-06-04 21:16:57 +02002197 netdev_err(ds->ports[port].netdev,
2198 "failed to add VLAN %d%c\n",
Vivien Didelot4d5770b2016-04-06 11:55:05 -04002199 vid, untagged ? 'u' : 't');
Vivien Didelot76e398a2015-11-01 12:33:55 -05002200
Vivien Didelotfad09c72016-06-21 12:28:20 -04002201 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
Andrew Lunnc8b09802016-06-04 21:16:57 +02002202 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
Vivien Didelot4d5770b2016-04-06 11:55:05 -04002203 vlan->vid_end);
2204
Vivien Didelotfad09c72016-06-21 12:28:20 -04002205 mutex_unlock(&chip->reg_lock);
Vivien Didelot0d3b33e2015-08-13 12:52:22 -04002206}
2207
Vivien Didelotfad09c72016-06-21 12:28:20 -04002208static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04002209 int port, u16 vid)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002210{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002211 struct dsa_switch *ds = chip->ds;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002212 struct mv88e6xxx_vtu_stu_entry vlan;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002213 int i, err;
2214
Vivien Didelotfad09c72016-06-21 12:28:20 -04002215 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot36d04ba12015-10-22 09:34:39 -04002216 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002217 return err;
Vivien Didelot36d04ba12015-10-22 09:34:39 -04002218
Vivien Didelot2fb5ef02016-02-26 13:16:01 -05002219 /* Tell switchdev if this VLAN is handled in software */
2220 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
Vivien Didelot3c06f082016-02-05 14:04:39 -05002221 return -EOPNOTSUPP;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002222
2223 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2224
2225 /* keep the VLAN unless all ports are excluded */
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002226 vlan.valid = false;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002227 for (i = 0; i < chip->info->num_ports; ++i) {
Vivien Didelot3d131f02015-11-03 10:52:52 -05002228 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002229 continue;
2230
2231 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002232 vlan.valid = true;
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002233 break;
2234 }
2235 }
2236
Vivien Didelotfad09c72016-06-21 12:28:20 -04002237 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002238 if (err)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002239 return err;
2240
Vivien Didelotfad09c72016-06-21 12:28:20 -04002241 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002242}
2243
Vivien Didelotf81ec902016-05-09 13:22:58 -04002244static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2245 const struct switchdev_obj_port_vlan *vlan)
Vivien Didelot76e398a2015-11-01 12:33:55 -05002246{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002247 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002248 u16 pvid, vid;
2249 int err = 0;
2250
Vivien Didelotfad09c72016-06-21 12:28:20 -04002251 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
Vivien Didelot54d77b52016-05-09 13:22:47 -04002252 return -EOPNOTSUPP;
2253
Vivien Didelotfad09c72016-06-21 12:28:20 -04002254 mutex_lock(&chip->reg_lock);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002255
Vivien Didelotfad09c72016-06-21 12:28:20 -04002256 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002257 if (err)
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002258 goto unlock;
2259
Vivien Didelot76e398a2015-11-01 12:33:55 -05002260 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002261 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002262 if (err)
2263 goto unlock;
2264
2265 if (vid == pvid) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002266 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
Vivien Didelot76e398a2015-11-01 12:33:55 -05002267 if (err)
2268 goto unlock;
2269 }
2270 }
2271
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002272unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002273 mutex_unlock(&chip->reg_lock);
Vivien Didelot7dad08d2015-08-13 12:52:21 -04002274
2275 return err;
2276}
2277
Vivien Didelotfad09c72016-06-21 12:28:20 -04002278static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
Vivien Didelotc5723ac2015-08-10 09:09:48 -04002279 const unsigned char *addr)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002280{
2281 int i, ret;
2282
2283 for (i = 0; i < 3; i++) {
Andrew Lunncca8b132015-04-02 04:06:39 +02002284 ret = _mv88e6xxx_reg_write(
Vivien Didelotfad09c72016-06-21 12:28:20 -04002285 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
Andrew Lunncca8b132015-04-02 04:06:39 +02002286 (addr[i * 2] << 8) | addr[i * 2 + 1]);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002287 if (ret < 0)
2288 return ret;
2289 }
2290
2291 return 0;
2292}
2293
Vivien Didelotfad09c72016-06-21 12:28:20 -04002294static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04002295 unsigned char *addr)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002296{
2297 int i, ret;
2298
2299 for (i = 0; i < 3; i++) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002300 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
Andrew Lunncca8b132015-04-02 04:06:39 +02002301 GLOBAL_ATU_MAC_01 + i);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002302 if (ret < 0)
2303 return ret;
2304 addr[i * 2] = ret >> 8;
2305 addr[i * 2 + 1] = ret & 0xff;
2306 }
2307
2308 return 0;
2309}
2310
Vivien Didelotfad09c72016-06-21 12:28:20 -04002311static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
Vivien Didelotfd231c82015-08-10 09:09:50 -04002312 struct mv88e6xxx_atu_entry *entry)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002313{
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002314 int ret;
2315
Vivien Didelotfad09c72016-06-21 12:28:20 -04002316 ret = _mv88e6xxx_atu_wait(chip);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002317 if (ret < 0)
2318 return ret;
2319
Vivien Didelotfad09c72016-06-21 12:28:20 -04002320 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002321 if (ret < 0)
2322 return ret;
2323
Vivien Didelotfad09c72016-06-21 12:28:20 -04002324 ret = _mv88e6xxx_atu_data_write(chip, entry);
Vivien Didelotfd231c82015-08-10 09:09:50 -04002325 if (ret < 0)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002326 return ret;
2327
Vivien Didelotfad09c72016-06-21 12:28:20 -04002328 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
Vivien Didelotfd231c82015-08-10 09:09:50 -04002329}
David S. Millercdf09692015-08-11 12:00:37 -07002330
Vivien Didelotfad09c72016-06-21 12:28:20 -04002331static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
Vivien Didelotfd231c82015-08-10 09:09:50 -04002332 const unsigned char *addr, u16 vid,
2333 u8 state)
2334{
2335 struct mv88e6xxx_atu_entry entry = { 0 };
Vivien Didelot3285f9e2016-02-26 13:16:03 -05002336 struct mv88e6xxx_vtu_stu_entry vlan;
2337 int err;
Vivien Didelotfd231c82015-08-10 09:09:50 -04002338
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002339 /* Null VLAN ID corresponds to the port private database */
2340 if (vid == 0)
Vivien Didelotfad09c72016-06-21 12:28:20 -04002341 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002342 else
Vivien Didelotfad09c72016-06-21 12:28:20 -04002343 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
Vivien Didelot3285f9e2016-02-26 13:16:03 -05002344 if (err)
2345 return err;
2346
2347 entry.fid = vlan.fid;
Vivien Didelotfd231c82015-08-10 09:09:50 -04002348 entry.state = state;
2349 ether_addr_copy(entry.mac, addr);
2350 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2351 entry.trunk = false;
2352 entry.portv_trunkid = BIT(port);
2353 }
2354
Vivien Didelotfad09c72016-06-21 12:28:20 -04002355 return _mv88e6xxx_atu_load(chip, &entry);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002356}
2357
Vivien Didelotf81ec902016-05-09 13:22:58 -04002358static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2359 const struct switchdev_obj_port_fdb *fdb,
2360 struct switchdev_trans *trans)
Vivien Didelot146a3202015-10-08 11:35:12 -04002361{
2362 /* We don't need any dynamic resource from the kernel (yet),
2363 * so skip the prepare phase.
2364 */
2365 return 0;
2366}
2367
Vivien Didelotf81ec902016-05-09 13:22:58 -04002368static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2369 const struct switchdev_obj_port_fdb *fdb,
2370 struct switchdev_trans *trans)
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002371{
Vivien Didelot1f36faf2015-10-08 11:35:13 -04002372 int state = is_multicast_ether_addr(fdb->addr) ?
David S. Millercdf09692015-08-11 12:00:37 -07002373 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2374 GLOBAL_ATU_DATA_STATE_UC_STATIC;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002375 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelot6630e232015-08-06 01:44:07 -04002376
Vivien Didelotfad09c72016-06-21 12:28:20 -04002377 mutex_lock(&chip->reg_lock);
2378 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
Andrew Lunnc8b09802016-06-04 21:16:57 +02002379 netdev_err(ds->ports[port].netdev,
2380 "failed to load MAC address\n");
Vivien Didelotfad09c72016-06-21 12:28:20 -04002381 mutex_unlock(&chip->reg_lock);
David S. Millercdf09692015-08-11 12:00:37 -07002382}
2383
Vivien Didelotf81ec902016-05-09 13:22:58 -04002384static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2385 const struct switchdev_obj_port_fdb *fdb)
David S. Millercdf09692015-08-11 12:00:37 -07002386{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002387 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
David S. Millercdf09692015-08-11 12:00:37 -07002388 int ret;
2389
Vivien Didelotfad09c72016-06-21 12:28:20 -04002390 mutex_lock(&chip->reg_lock);
2391 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
David S. Millercdf09692015-08-11 12:00:37 -07002392 GLOBAL_ATU_DATA_STATE_UNUSED);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002393 mutex_unlock(&chip->reg_lock);
David S. Millercdf09692015-08-11 12:00:37 -07002394
2395 return ret;
2396}
2397
Vivien Didelotfad09c72016-06-21 12:28:20 -04002398static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
Vivien Didelot1d194042015-08-10 09:09:51 -04002399 struct mv88e6xxx_atu_entry *entry)
David S. Millercdf09692015-08-11 12:00:37 -07002400{
Vivien Didelot1d194042015-08-10 09:09:51 -04002401 struct mv88e6xxx_atu_entry next = { 0 };
2402 int ret;
2403
2404 next.fid = fid;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002405
Vivien Didelotfad09c72016-06-21 12:28:20 -04002406 ret = _mv88e6xxx_atu_wait(chip);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002407 if (ret < 0)
2408 return ret;
2409
Vivien Didelotfad09c72016-06-21 12:28:20 -04002410 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002411 if (ret < 0)
2412 return ret;
2413
Vivien Didelotfad09c72016-06-21 12:28:20 -04002414 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
Vivien Didelot1d194042015-08-10 09:09:51 -04002415 if (ret < 0)
2416 return ret;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002417
Vivien Didelotfad09c72016-06-21 12:28:20 -04002418 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
Vivien Didelot1d194042015-08-10 09:09:51 -04002419 if (ret < 0)
2420 return ret;
2421
2422 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2423 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2424 unsigned int mask, shift;
2425
2426 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2427 next.trunk = true;
2428 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2429 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2430 } else {
2431 next.trunk = false;
2432 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2433 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2434 }
2435
2436 next.portv_trunkid = (ret & mask) >> shift;
2437 }
2438
2439 *entry = next;
Guenter Roeckdefb05b2015-03-26 18:36:38 -07002440 return 0;
2441}
2442
Vivien Didelotfad09c72016-06-21 12:28:20 -04002443static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
Andrew Lunn158bc062016-04-28 21:24:06 -04002444 u16 fid, u16 vid, int port,
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002445 struct switchdev_obj_port_fdb *fdb,
2446 int (*cb)(struct switchdev_obj *obj))
2447{
2448 struct mv88e6xxx_atu_entry addr = {
2449 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2450 };
2451 int err;
2452
Vivien Didelotfad09c72016-06-21 12:28:20 -04002453 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002454 if (err)
2455 return err;
2456
2457 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002458 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002459 if (err)
2460 break;
2461
2462 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2463 break;
2464
2465 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2466 bool is_static = addr.state ==
2467 (is_multicast_ether_addr(addr.mac) ?
2468 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2469 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2470
2471 fdb->vid = vid;
2472 ether_addr_copy(fdb->addr, addr.mac);
2473 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2474
2475 err = cb(&fdb->obj);
2476 if (err)
2477 break;
2478 }
2479 } while (!is_broadcast_ether_addr(addr.mac));
2480
2481 return err;
2482}
2483
Vivien Didelotf81ec902016-05-09 13:22:58 -04002484static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2485 struct switchdev_obj_port_fdb *fdb,
2486 int (*cb)(struct switchdev_obj *obj))
Vivien Didelotf33475b2015-10-22 09:34:41 -04002487{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002488 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002489 struct mv88e6xxx_vtu_stu_entry vlan = {
2490 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2491 };
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002492 u16 fid;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002493 int err;
2494
Vivien Didelotfad09c72016-06-21 12:28:20 -04002495 mutex_lock(&chip->reg_lock);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002496
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002497 /* Dump port's default Filtering Information Database (VLAN ID 0) */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002498 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002499 if (err)
2500 goto unlock;
2501
Vivien Didelotfad09c72016-06-21 12:28:20 -04002502 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002503 if (err)
2504 goto unlock;
2505
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002506 /* Dump VLANs' Filtering Information Databases */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002507 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002508 if (err)
2509 goto unlock;
2510
2511 do {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002512 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002513 if (err)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002514 break;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002515
2516 if (!vlan.valid)
2517 break;
2518
Vivien Didelotfad09c72016-06-21 12:28:20 -04002519 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2520 port, fdb, cb);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002521 if (err)
Vivien Didelot74b6ba02016-02-26 13:16:02 -05002522 break;
Vivien Didelotf33475b2015-10-22 09:34:41 -04002523 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2524
2525unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002526 mutex_unlock(&chip->reg_lock);
Vivien Didelotf33475b2015-10-22 09:34:41 -04002527
2528 return err;
2529}
2530
Vivien Didelotf81ec902016-05-09 13:22:58 -04002531static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2532 struct net_device *bridge)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002533{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002534 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Colin Ian King1d9619d2016-04-25 23:11:22 +01002535 int i, err = 0;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002536
Vivien Didelotfad09c72016-06-21 12:28:20 -04002537 mutex_lock(&chip->reg_lock);
Vivien Didelot466dfa02016-02-26 13:16:05 -05002538
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002539 /* Assign the bridge and remap each port's VLANTable */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002540 chip->ports[port].bridge_dev = bridge;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002541
Vivien Didelotfad09c72016-06-21 12:28:20 -04002542 for (i = 0; i < chip->info->num_ports; ++i) {
2543 if (chip->ports[i].bridge_dev == bridge) {
2544 err = _mv88e6xxx_port_based_vlan_map(chip, i);
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002545 if (err)
2546 break;
2547 }
2548 }
2549
Vivien Didelotfad09c72016-06-21 12:28:20 -04002550 mutex_unlock(&chip->reg_lock);
Vivien Didelota6692752016-02-12 12:09:39 -05002551
Vivien Didelot466dfa02016-02-26 13:16:05 -05002552 return err;
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002553}
2554
Vivien Didelotf81ec902016-05-09 13:22:58 -04002555static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
Vivien Didelote79a8bc2015-11-04 17:23:40 -05002556{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002557 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2558 struct net_device *bridge = chip->ports[port].bridge_dev;
Vivien Didelot16bfa702016-03-13 16:21:33 -04002559 int i;
Vivien Didelot466dfa02016-02-26 13:16:05 -05002560
Vivien Didelotfad09c72016-06-21 12:28:20 -04002561 mutex_lock(&chip->reg_lock);
Vivien Didelot466dfa02016-02-26 13:16:05 -05002562
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002563 /* Unassign the bridge and remap each port's VLANTable */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002564 chip->ports[port].bridge_dev = NULL;
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002565
Vivien Didelotfad09c72016-06-21 12:28:20 -04002566 for (i = 0; i < chip->info->num_ports; ++i)
2567 if (i == port || chip->ports[i].bridge_dev == bridge)
2568 if (_mv88e6xxx_port_based_vlan_map(chip, i))
Andrew Lunnc8b09802016-06-04 21:16:57 +02002569 netdev_warn(ds->ports[i].netdev,
2570 "failed to remap\n");
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002571
Vivien Didelotfad09c72016-06-21 12:28:20 -04002572 mutex_unlock(&chip->reg_lock);
Vivien Didelot66d9cd02016-02-05 14:07:14 -05002573}
2574
Vivien Didelotfad09c72016-06-21 12:28:20 -04002575static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
Andrew Lunn03a4a542016-06-04 21:17:05 +02002576 int port, int page, int reg, int val)
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002577{
2578 int ret;
2579
Vivien Didelotfad09c72016-06-21 12:28:20 -04002580 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002581 if (ret < 0)
2582 goto restore_page_0;
2583
Vivien Didelotfad09c72016-06-21 12:28:20 -04002584 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002585restore_page_0:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002586 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002587
2588 return ret;
2589}
2590
Vivien Didelotfad09c72016-06-21 12:28:20 -04002591static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
Andrew Lunn03a4a542016-06-04 21:17:05 +02002592 int port, int page, int reg)
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002593{
2594 int ret;
2595
Vivien Didelotfad09c72016-06-21 12:28:20 -04002596 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002597 if (ret < 0)
2598 goto restore_page_0;
2599
Vivien Didelotfad09c72016-06-21 12:28:20 -04002600 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002601restore_page_0:
Vivien Didelotfad09c72016-06-21 12:28:20 -04002602 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00002603
2604 return ret;
2605}
2606
Vivien Didelotfad09c72016-06-21 12:28:20 -04002607static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
Vivien Didelot552238b2016-05-09 13:22:49 -04002608{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002609 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
Vivien Didelot552238b2016-05-09 13:22:49 -04002610 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
Vivien Didelotfad09c72016-06-21 12:28:20 -04002611 struct gpio_desc *gpiod = chip->reset;
Vivien Didelot552238b2016-05-09 13:22:49 -04002612 unsigned long timeout;
2613 int ret;
2614 int i;
2615
2616 /* Set all ports to the disabled state. */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002617 for (i = 0; i < chip->info->num_ports; i++) {
2618 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
Vivien Didelot552238b2016-05-09 13:22:49 -04002619 if (ret < 0)
2620 return ret;
2621
Vivien Didelotfad09c72016-06-21 12:28:20 -04002622 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
Vivien Didelot552238b2016-05-09 13:22:49 -04002623 ret & 0xfffc);
2624 if (ret)
2625 return ret;
2626 }
2627
2628 /* Wait for transmit queues to drain. */
2629 usleep_range(2000, 4000);
2630
2631 /* If there is a gpio connected to the reset pin, toggle it */
2632 if (gpiod) {
2633 gpiod_set_value_cansleep(gpiod, 1);
2634 usleep_range(10000, 20000);
2635 gpiod_set_value_cansleep(gpiod, 0);
2636 usleep_range(10000, 20000);
2637 }
2638
2639 /* Reset the switch. Keep the PPU active if requested. The PPU
2640 * needs to be active to support indirect phy register access
2641 * through global registers 0x18 and 0x19.
2642 */
2643 if (ppu_active)
Vivien Didelotfad09c72016-06-21 12:28:20 -04002644 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
Vivien Didelot552238b2016-05-09 13:22:49 -04002645 else
Vivien Didelotfad09c72016-06-21 12:28:20 -04002646 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
Vivien Didelot552238b2016-05-09 13:22:49 -04002647 if (ret)
2648 return ret;
2649
2650 /* Wait up to one second for reset to complete. */
2651 timeout = jiffies + 1 * HZ;
2652 while (time_before(jiffies, timeout)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002653 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
Vivien Didelot552238b2016-05-09 13:22:49 -04002654 if (ret < 0)
2655 return ret;
2656
2657 if ((ret & is_reset) == is_reset)
2658 break;
2659 usleep_range(1000, 2000);
2660 }
2661 if (time_after(jiffies, timeout))
2662 ret = -ETIMEDOUT;
2663 else
2664 ret = 0;
2665
2666 return ret;
2667}
2668
Vivien Didelotfad09c72016-06-21 12:28:20 -04002669static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002670{
2671 int ret;
2672
Vivien Didelotfad09c72016-06-21 12:28:20 -04002673 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
Andrew Lunn03a4a542016-06-04 21:17:05 +02002674 PAGE_FIBER_SERDES, MII_BMCR);
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002675 if (ret < 0)
2676 return ret;
2677
2678 if (ret & BMCR_PDOWN) {
2679 ret &= ~BMCR_PDOWN;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002680 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
Andrew Lunn03a4a542016-06-04 21:17:05 +02002681 PAGE_FIBER_SERDES, MII_BMCR,
2682 ret);
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002683 }
2684
2685 return ret;
2686}
2687
Vivien Didelotfad09c72016-06-21 12:28:20 -04002688static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
Guenter Roeckd827e882015-03-26 18:36:29 -07002689{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002690 struct dsa_switch *ds = chip->ds;
Vivien Didelotf02bdff2015-10-11 18:08:36 -04002691 int ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002692 u16 reg;
Guenter Roeckd827e882015-03-26 18:36:29 -07002693
Vivien Didelotfad09c72016-06-21 12:28:20 -04002694 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2695 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2696 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2697 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
Andrew Lunn54d792f2015-05-06 01:09:47 +02002698 /* MAC Forcing register: don't force link, speed,
2699 * duplex or flow control state to any particular
2700 * values on physical ports, but force the CPU port
2701 * and all DSA ports to their maximum bandwidth and
2702 * full duplex.
2703 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002704 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
Andrew Lunn60045cb2015-08-17 23:52:51 +02002705 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
Russell King53adc9e2015-09-21 21:42:59 +01002706 reg &= ~PORT_PCS_CTRL_UNFORCED;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002707 reg |= PORT_PCS_CTRL_FORCE_LINK |
2708 PORT_PCS_CTRL_LINK_UP |
2709 PORT_PCS_CTRL_DUPLEX_FULL |
2710 PORT_PCS_CTRL_FORCE_DUPLEX;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002711 if (mv88e6xxx_6065_family(chip))
Andrew Lunn54d792f2015-05-06 01:09:47 +02002712 reg |= PORT_PCS_CTRL_100;
2713 else
2714 reg |= PORT_PCS_CTRL_1000;
2715 } else {
2716 reg |= PORT_PCS_CTRL_UNFORCED;
2717 }
2718
Vivien Didelotfad09c72016-06-21 12:28:20 -04002719 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002720 PORT_PCS_CTRL, reg);
2721 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002722 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002723 }
2724
2725 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2726 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2727 * tunneling, determine priority by looking at 802.1p and IP
2728 * priority fields (IP prio has precedence), and set STP state
2729 * to Forwarding.
2730 *
2731 * If this is the CPU link, use DSA or EDSA tagging depending
2732 * on which tagging mode was configured.
2733 *
2734 * If this is a link to another switch, use DSA tagging mode.
2735 *
2736 * If this is the upstream port for this switch, enable
2737 * forwarding of unknown unicasts and multicasts.
2738 */
2739 reg = 0;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002740 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2741 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2742 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2743 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
Andrew Lunn54d792f2015-05-06 01:09:47 +02002744 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2745 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2746 PORT_CONTROL_STATE_FORWARDING;
2747 if (dsa_is_cpu_port(ds, port)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002748 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
Andrew Lunn54d792f2015-05-06 01:09:47 +02002749 reg |= PORT_CONTROL_DSA_TAG;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002750 if (mv88e6xxx_6352_family(chip) ||
2751 mv88e6xxx_6351_family(chip) ||
2752 mv88e6xxx_6165_family(chip) ||
2753 mv88e6xxx_6097_family(chip) ||
2754 mv88e6xxx_6320_family(chip)) {
Andrew Lunn5377b802016-06-04 21:17:02 +02002755 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2756 PORT_CONTROL_FORWARD_UNKNOWN |
Andrew Lunnc047a1f2015-09-29 01:50:56 +02002757 PORT_CONTROL_FORWARD_UNKNOWN_MC;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002758 }
2759
Vivien Didelotfad09c72016-06-21 12:28:20 -04002760 if (mv88e6xxx_6352_family(chip) ||
2761 mv88e6xxx_6351_family(chip) ||
2762 mv88e6xxx_6165_family(chip) ||
2763 mv88e6xxx_6097_family(chip) ||
2764 mv88e6xxx_6095_family(chip) ||
2765 mv88e6xxx_6065_family(chip) ||
2766 mv88e6xxx_6185_family(chip) ||
2767 mv88e6xxx_6320_family(chip)) {
Vivien Didelot57d32312016-06-20 13:13:58 -04002768 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002769 }
2770 }
Andrew Lunn6083ce72015-08-17 23:52:52 +02002771 if (dsa_is_dsa_port(ds, port)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002772 if (mv88e6xxx_6095_family(chip) ||
2773 mv88e6xxx_6185_family(chip))
Andrew Lunn6083ce72015-08-17 23:52:52 +02002774 reg |= PORT_CONTROL_DSA_TAG;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002775 if (mv88e6xxx_6352_family(chip) ||
2776 mv88e6xxx_6351_family(chip) ||
2777 mv88e6xxx_6165_family(chip) ||
2778 mv88e6xxx_6097_family(chip) ||
2779 mv88e6xxx_6320_family(chip)) {
Andrew Lunn54d792f2015-05-06 01:09:47 +02002780 reg |= PORT_CONTROL_FRAME_MODE_DSA;
Andrew Lunn6083ce72015-08-17 23:52:52 +02002781 }
2782
Andrew Lunn54d792f2015-05-06 01:09:47 +02002783 if (port == dsa_upstream_port(ds))
2784 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2785 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2786 }
2787 if (reg) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002788 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002789 PORT_CONTROL, reg);
2790 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002791 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002792 }
2793
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002794 /* If this port is connected to a SerDes, make sure the SerDes is not
2795 * powered down.
2796 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002797 if (mv88e6xxx_6352_family(chip)) {
2798 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002799 if (ret < 0)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002800 return ret;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002801 ret &= PORT_STATUS_CMODE_MASK;
2802 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2803 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2804 (ret == PORT_STATUS_CMODE_SGMII)) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002805 ret = mv88e6xxx_power_on_serdes(chip);
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002806 if (ret < 0)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002807 return ret;
Patrick Uiterwijk13a7ebb2016-03-30 01:39:41 +00002808 }
2809 }
2810
Vivien Didelot8efdda42015-08-13 12:52:23 -04002811 /* Port Control 2: don't force a good FCS, set the maximum frame size to
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002812 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
Vivien Didelot8efdda42015-08-13 12:52:23 -04002813 * untagged frames on this port, do a destination address lookup on all
2814 * received packets as usual, disable ARP mirroring and don't send a
2815 * copy of all transmitted/received frames on this port to the CPU.
Andrew Lunn54d792f2015-05-06 01:09:47 +02002816 */
2817 reg = 0;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002818 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2819 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2820 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2821 mv88e6xxx_6185_family(chip))
Andrew Lunn54d792f2015-05-06 01:09:47 +02002822 reg = PORT_CONTROL_2_MAP_DA;
2823
Vivien Didelotfad09c72016-06-21 12:28:20 -04002824 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2825 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
Andrew Lunn54d792f2015-05-06 01:09:47 +02002826 reg |= PORT_CONTROL_2_JUMBO_10240;
2827
Vivien Didelotfad09c72016-06-21 12:28:20 -04002828 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
Andrew Lunn54d792f2015-05-06 01:09:47 +02002829 /* Set the upstream port this port should use */
2830 reg |= dsa_upstream_port(ds);
2831 /* enable forwarding of unknown multicast addresses to
2832 * the upstream port
2833 */
2834 if (port == dsa_upstream_port(ds))
2835 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2836 }
2837
Vivien Didelot46fbe5e2016-02-26 13:16:07 -05002838 reg |= PORT_CONTROL_2_8021Q_DISABLED;
Vivien Didelot8efdda42015-08-13 12:52:23 -04002839
Andrew Lunn54d792f2015-05-06 01:09:47 +02002840 if (reg) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04002841 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002842 PORT_CONTROL_2, reg);
2843 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002844 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002845 }
2846
2847 /* Port Association Vector: when learning source addresses
2848 * of packets, add the address to the address database using
2849 * a port bitmap that has only the bit for this port set and
2850 * the other bits clear.
2851 */
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002852 reg = 1 << port;
Vivien Didelot996ecb82016-04-14 14:42:08 -04002853 /* Disable learning for CPU port */
2854 if (dsa_is_cpu_port(ds, port))
Vivien Didelot65fa4022016-04-14 14:42:07 -04002855 reg = 0;
Andrew Lunn4c7ea3c2015-11-03 10:52:36 -05002856
Vivien Didelotfad09c72016-06-21 12:28:20 -04002857 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2858 reg);
Andrew Lunn54d792f2015-05-06 01:09:47 +02002859 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002860 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002861
2862 /* Egress rate control 2: disable egress rate control. */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002863 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
Andrew Lunn54d792f2015-05-06 01:09:47 +02002864 0x0000);
2865 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002866 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002867
Vivien Didelotfad09c72016-06-21 12:28:20 -04002868 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2869 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2870 mv88e6xxx_6320_family(chip)) {
Andrew Lunn54d792f2015-05-06 01:09:47 +02002871 /* Do not limit the period of time that this port can
2872 * be paused for by the remote end or the period of
2873 * time that this port can pause the remote end.
2874 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002875 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002876 PORT_PAUSE_CTRL, 0x0000);
2877 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002878 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002879
2880 /* Port ATU control: disable limiting the number of
2881 * address database entries that this port is allowed
2882 * to use.
2883 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002884 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002885 PORT_ATU_CONTROL, 0x0000);
2886 /* Priority Override: disable DA, SA and VTU priority
2887 * override.
2888 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002889 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002890 PORT_PRI_OVERRIDE, 0x0000);
2891 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002892 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002893
2894 /* Port Ethertype: use the Ethertype DSA Ethertype
2895 * value.
2896 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002897 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002898 PORT_ETH_TYPE, ETH_P_EDSA);
2899 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002900 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002901 /* Tag Remap: use an identity 802.1p prio -> switch
2902 * prio mapping.
2903 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002904 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002905 PORT_TAG_REGMAP_0123, 0x3210);
2906 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002907 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002908
2909 /* Tag Remap 2: use an identity 802.1p prio -> switch
2910 * prio mapping.
2911 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002912 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002913 PORT_TAG_REGMAP_4567, 0x7654);
2914 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002915 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002916 }
2917
Vivien Didelotfad09c72016-06-21 12:28:20 -04002918 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2919 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2920 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2921 mv88e6xxx_6320_family(chip)) {
Andrew Lunn54d792f2015-05-06 01:09:47 +02002922 /* Rate Control: disable ingress rate limiting. */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002923 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
Andrew Lunn54d792f2015-05-06 01:09:47 +02002924 PORT_RATE_CONTROL, 0x0001);
2925 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002926 return ret;
Andrew Lunn54d792f2015-05-06 01:09:47 +02002927 }
2928
Guenter Roeck366f0a02015-03-26 18:36:30 -07002929 /* Port Control 1: disable trunking, disable sending
2930 * learning messages to this port.
Guenter Roeckd827e882015-03-26 18:36:29 -07002931 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002932 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2933 0x0000);
Guenter Roeckd827e882015-03-26 18:36:29 -07002934 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002935 return ret;
Guenter Roeckd827e882015-03-26 18:36:29 -07002936
Vivien Didelot207afda2016-04-14 14:42:09 -04002937 /* Port based VLAN map: give each port the same default address
Vivien Didelotb7666ef2016-02-26 13:16:06 -05002938 * database, and allow bidirectional communication between the
2939 * CPU and DSA port(s), and the other ports.
Guenter Roeckd827e882015-03-26 18:36:29 -07002940 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002941 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002942 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002943 return ret;
Vivien Didelot2db9ce12016-02-26 13:16:04 -05002944
Vivien Didelotfad09c72016-06-21 12:28:20 -04002945 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
Guenter Roeckd827e882015-03-26 18:36:29 -07002946 if (ret)
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002947 return ret;
Guenter Roeckd827e882015-03-26 18:36:29 -07002948
2949 /* Default VLAN ID and priority: don't set a default VLAN
2950 * ID, and set the default packet priority to zero.
2951 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04002952 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
Vivien Didelot47cf1e62015-04-20 17:43:26 -04002953 0x0000);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04002954 if (ret)
2955 return ret;
Guenter Roeckd827e882015-03-26 18:36:29 -07002956
Andrew Lunndbde9e62015-05-06 01:09:48 +02002957 return 0;
2958}
2959
Vivien Didelot3b4caa12016-07-18 20:45:34 -04002960static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2961{
2962 int err;
2963
2964 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2965 (addr[0] << 8) | addr[1]);
2966 if (err)
2967 return err;
2968
2969 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2970 (addr[2] << 8) | addr[3]);
2971 if (err)
2972 return err;
2973
2974 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2975 (addr[4] << 8) | addr[5]);
2976}
2977
Vivien Didelot97299342016-07-18 20:45:30 -04002978static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
Vivien Didelot08a01262016-05-09 13:22:50 -04002979{
Vivien Didelotfad09c72016-06-21 12:28:20 -04002980 struct dsa_switch *ds = chip->ds;
Vivien Didelotb0745e872016-05-09 13:22:53 -04002981 u32 upstream_port = dsa_upstream_port(ds);
Vivien Didelot119477b2016-05-09 13:22:51 -04002982 u16 reg;
Vivien Didelot08a01262016-05-09 13:22:50 -04002983 int err;
Vivien Didelot08a01262016-05-09 13:22:50 -04002984
Vivien Didelot119477b2016-05-09 13:22:51 -04002985 /* Enable the PHY Polling Unit if present, don't discard any packets,
2986 * and mask all interrupt sources.
2987 */
2988 reg = 0;
Vivien Didelotfad09c72016-06-21 12:28:20 -04002989 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2990 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
Vivien Didelot119477b2016-05-09 13:22:51 -04002991 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2992
Vivien Didelotfad09c72016-06-21 12:28:20 -04002993 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
Vivien Didelot119477b2016-05-09 13:22:51 -04002994 if (err)
2995 return err;
2996
Vivien Didelotb0745e872016-05-09 13:22:53 -04002997 /* Configure the upstream port, and configure it as the port to which
2998 * ingress and egress and ARP monitor frames are to be sent.
2999 */
3000 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
3001 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
3002 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003003 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
3004 reg);
Vivien Didelotb0745e872016-05-09 13:22:53 -04003005 if (err)
3006 return err;
3007
Vivien Didelot50484ff2016-05-09 13:22:54 -04003008 /* Disable remote management, and set the switch's DSA device number. */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003009 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
Vivien Didelot50484ff2016-05-09 13:22:54 -04003010 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
3011 (ds->index & 0x1f));
3012 if (err)
3013 return err;
3014
Vivien Didelot08a01262016-05-09 13:22:50 -04003015 /* Set the default address aging time to 5 minutes, and
3016 * enable address learn messages to be sent to all message
3017 * ports.
3018 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003019 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
Vivien Didelot08a01262016-05-09 13:22:50 -04003020 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
3021 if (err)
3022 return err;
3023
Vivien Didelot97299342016-07-18 20:45:30 -04003024 /* Clear all the VTU and STU entries */
3025 err = _mv88e6xxx_vtu_stu_flush(chip);
3026 if (err < 0)
3027 return err;
3028
3029 /* Clear all ATU entries */
3030 err = _mv88e6xxx_atu_flush(chip, 0, true);
3031 if (err)
3032 return err;
3033
Vivien Didelot08a01262016-05-09 13:22:50 -04003034 /* Configure the IP ToS mapping registers. */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003035 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
Vivien Didelot08a01262016-05-09 13:22:50 -04003036 if (err)
3037 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003038 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
Vivien Didelot08a01262016-05-09 13:22:50 -04003039 if (err)
3040 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003041 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
Vivien Didelot08a01262016-05-09 13:22:50 -04003042 if (err)
3043 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003044 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
Vivien Didelot08a01262016-05-09 13:22:50 -04003045 if (err)
3046 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003047 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
Vivien Didelot08a01262016-05-09 13:22:50 -04003048 if (err)
3049 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003050 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
Vivien Didelot08a01262016-05-09 13:22:50 -04003051 if (err)
3052 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003053 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
Vivien Didelot08a01262016-05-09 13:22:50 -04003054 if (err)
3055 return err;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003056 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
Vivien Didelot08a01262016-05-09 13:22:50 -04003057 if (err)
3058 return err;
3059
3060 /* Configure the IEEE 802.1p priority mapping register. */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003061 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
Vivien Didelot08a01262016-05-09 13:22:50 -04003062 if (err)
3063 return err;
3064
Vivien Didelot97299342016-07-18 20:45:30 -04003065 /* Clear the statistics counters for all ports */
3066 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
3067 GLOBAL_STATS_OP_FLUSH_ALL);
3068 if (err)
3069 return err;
3070
3071 /* Wait for the flush to complete. */
3072 err = _mv88e6xxx_stats_wait(chip);
3073 if (err)
3074 return err;
3075
3076 return 0;
3077}
3078
Vivien Didelotf22ab642016-07-18 20:45:31 -04003079static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
3080 int target, int port)
3081{
3082 u16 val = (target << 8) | (port & 0xf);
3083
3084 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
3085}
3086
3087static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
3088{
3089 int target, port;
3090 int err;
3091
3092 /* Initialize the routing port to the 32 possible target devices */
3093 for (target = 0; target < 32; ++target) {
3094 port = 0xf;
3095
3096 if (target < DSA_MAX_SWITCHES) {
3097 port = chip->ds->rtable[target];
3098 if (port == DSA_RTABLE_NONE)
3099 port = 0xf;
3100 }
3101
3102 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
3103 if (err)
3104 break;
3105 }
3106
3107 return err;
3108}
3109
Vivien Didelot51540412016-07-18 20:45:32 -04003110static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
3111 bool hask, u16 mask)
3112{
3113 const u16 port_mask = BIT(chip->info->num_ports) - 1;
3114 u16 val = (num << 12) | (mask & port_mask);
3115
3116 if (hask)
3117 val |= GLOBAL2_TRUNK_MASK_HASK;
3118
3119 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
3120}
3121
3122static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
3123 u16 map)
3124{
3125 const u16 port_mask = BIT(chip->info->num_ports) - 1;
3126 u16 val = (id << 11) | (map & port_mask);
3127
3128 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
3129}
3130
3131static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
3132{
3133 const u16 port_mask = BIT(chip->info->num_ports) - 1;
3134 int i, err;
3135
3136 /* Clear all eight possible Trunk Mask vectors */
3137 for (i = 0; i < 8; ++i) {
3138 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
3139 if (err)
3140 return err;
3141 }
3142
3143 /* Clear all sixteen possible Trunk ID routing vectors */
3144 for (i = 0; i < 16; ++i) {
3145 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
3146 if (err)
3147 return err;
3148 }
3149
3150 return 0;
3151}
3152
Vivien Didelot3b4caa12016-07-18 20:45:34 -04003153/* Indirect write to the Switch MAC/WoL/WoF register */
3154static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
3155 unsigned int pointer, u8 data)
3156{
3157 u16 val = (pointer << 8) | data;
3158
3159 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
3160}
3161
3162static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3163{
3164 int i, err;
3165
3166 for (i = 0; i < 6; i++) {
3167 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
3168 if (err)
3169 break;
3170 }
3171
3172 return err;
3173}
3174
Vivien Didelot97299342016-07-18 20:45:30 -04003175static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3176{
Vivien Didelot47395ed2016-07-18 20:45:33 -04003177 u16 reg;
Vivien Didelot97299342016-07-18 20:45:30 -04003178 int err;
3179 int i;
3180
Vivien Didelot47395ed2016-07-18 20:45:33 -04003181 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3182 /* Consider the frames with reserved multicast destination
3183 * addresses matching 01:80:c2:00:00:2x as MGMT.
3184 */
3185 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3186 0xffff);
3187 if (err)
3188 return err;
3189 }
3190
3191 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3192 /* Consider the frames with reserved multicast destination
3193 * addresses matching 01:80:c2:00:00:0x as MGMT.
3194 */
3195 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3196 0xffff);
3197 if (err)
3198 return err;
3199 }
Vivien Didelot08a01262016-05-09 13:22:50 -04003200
3201 /* Ignore removed tag data on doubly tagged packets, disable
3202 * flow control messages, force flow control priority to the
3203 * highest, and send all special multicast frames to the CPU
3204 * port at the highest priority.
3205 */
Vivien Didelot47395ed2016-07-18 20:45:33 -04003206 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3207 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3208 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3209 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3210 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
Vivien Didelot08a01262016-05-09 13:22:50 -04003211 if (err)
3212 return err;
3213
3214 /* Program the DSA routing table. */
Vivien Didelotf22ab642016-07-18 20:45:31 -04003215 err = mv88e6xxx_g2_set_device_mapping(chip);
3216 if (err)
3217 return err;
Vivien Didelot08a01262016-05-09 13:22:50 -04003218
Vivien Didelot51540412016-07-18 20:45:32 -04003219 /* Clear all trunk masks and mapping. */
3220 err = mv88e6xxx_g2_clear_trunk(chip);
3221 if (err)
3222 return err;
Vivien Didelot08a01262016-05-09 13:22:50 -04003223
Vivien Didelot63ed8802016-07-18 20:45:35 -04003224 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3225 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3226 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3227 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3228 if (err)
3229 return err;
3230 }
3231
Vivien Didelotfad09c72016-06-21 12:28:20 -04003232 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
3233 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
3234 mv88e6xxx_6320_family(chip)) {
Vivien Didelot08a01262016-05-09 13:22:50 -04003235 /* Clear the priority override table. */
3236 for (i = 0; i < 16; i++) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003237 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
Vivien Didelot08a01262016-05-09 13:22:50 -04003238 GLOBAL2_PRIO_OVERRIDE,
3239 0x8000 | (i << 8));
3240 if (err)
3241 return err;
3242 }
3243 }
3244
Vivien Didelotfad09c72016-06-21 12:28:20 -04003245 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
3246 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
3247 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
3248 mv88e6xxx_6320_family(chip)) {
Vivien Didelot08a01262016-05-09 13:22:50 -04003249 /* Disable ingress rate limiting by resetting all
3250 * ingress rate limit registers to their initial
3251 * state.
3252 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003253 for (i = 0; i < chip->info->num_ports; i++) {
3254 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
Vivien Didelot08a01262016-05-09 13:22:50 -04003255 GLOBAL2_INGRESS_OP,
3256 0x9000 | (i << 8));
3257 if (err)
3258 return err;
3259 }
3260 }
3261
Vivien Didelot97299342016-07-18 20:45:30 -04003262 return 0;
Vivien Didelot08a01262016-05-09 13:22:50 -04003263}
3264
Vivien Didelotf81ec902016-05-09 13:22:58 -04003265static int mv88e6xxx_setup(struct dsa_switch *ds)
Guenter Roeckacdaffc2015-03-26 18:36:28 -07003266{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003267 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Vivien Didelot552238b2016-05-09 13:22:49 -04003268 int err;
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04003269 int i;
3270
Vivien Didelotfad09c72016-06-21 12:28:20 -04003271 chip->ds = ds;
3272 ds->slave_mii_bus = chip->mdio_bus;
Vivien Didelot552238b2016-05-09 13:22:49 -04003273
Vivien Didelotfad09c72016-06-21 12:28:20 -04003274 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
3275 mutex_init(&chip->eeprom_mutex);
Vivien Didelotd24645b2016-05-09 13:22:41 -04003276
Vivien Didelotfad09c72016-06-21 12:28:20 -04003277 mutex_lock(&chip->reg_lock);
Vivien Didelot552238b2016-05-09 13:22:49 -04003278
Vivien Didelotfad09c72016-06-21 12:28:20 -04003279 err = mv88e6xxx_switch_reset(chip);
Andrew Lunn48ace4e2016-04-14 23:47:12 +02003280 if (err)
3281 goto unlock;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003282
Vivien Didelot97299342016-07-18 20:45:30 -04003283 /* Setup Switch Port Registers */
3284 for (i = 0; i < chip->info->num_ports; i++) {
3285 err = mv88e6xxx_setup_port(chip, i);
3286 if (err)
3287 goto unlock;
3288 }
3289
3290 /* Setup Switch Global 1 Registers */
3291 err = mv88e6xxx_g1_setup(chip);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04003292 if (err)
3293 goto unlock;
3294
Vivien Didelot97299342016-07-18 20:45:30 -04003295 /* Setup Switch Global 2 Registers */
3296 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3297 err = mv88e6xxx_g2_setup(chip);
Vivien Didelota1a6a4d2016-05-09 13:22:56 -04003298 if (err)
3299 goto unlock;
3300 }
Andrew Lunn54d792f2015-05-06 01:09:47 +02003301
Vivien Didelot6b17e862015-08-13 12:52:18 -04003302unlock:
Vivien Didelotfad09c72016-06-21 12:28:20 -04003303 mutex_unlock(&chip->reg_lock);
Andrew Lunndb687a52015-06-20 21:31:29 +02003304
Andrew Lunn48ace4e2016-04-14 23:47:12 +02003305 return err;
Andrew Lunn54d792f2015-05-06 01:09:47 +02003306}
3307
Vivien Didelot3b4caa12016-07-18 20:45:34 -04003308static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3309{
3310 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3311 int err;
3312
3313 mutex_lock(&chip->reg_lock);
3314
3315 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3316 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3317 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3318 else
3319 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3320
3321 mutex_unlock(&chip->reg_lock);
3322
3323 return err;
3324}
3325
Vivien Didelot57d32312016-06-20 13:13:58 -04003326static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3327 int reg)
Andrew Lunn491435852015-04-02 04:06:35 +02003328{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003329 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn491435852015-04-02 04:06:35 +02003330 int ret;
3331
Vivien Didelotfad09c72016-06-21 12:28:20 -04003332 mutex_lock(&chip->reg_lock);
3333 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3334 mutex_unlock(&chip->reg_lock);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00003335
Andrew Lunn491435852015-04-02 04:06:35 +02003336 return ret;
3337}
3338
Vivien Didelot57d32312016-06-20 13:13:58 -04003339static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3340 int reg, int val)
Andrew Lunn491435852015-04-02 04:06:35 +02003341{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003342 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn491435852015-04-02 04:06:35 +02003343 int ret;
3344
Vivien Didelotfad09c72016-06-21 12:28:20 -04003345 mutex_lock(&chip->reg_lock);
3346 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3347 mutex_unlock(&chip->reg_lock);
Patrick Uiterwijk75baacf2016-03-30 01:39:40 +00003348
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003349 return ret;
3350}
3351
Vivien Didelotfad09c72016-06-21 12:28:20 -04003352static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003353{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003354 if (port >= 0 && port < chip->info->num_ports)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003355 return port;
3356 return -EINVAL;
3357}
3358
Andrew Lunnb516d452016-06-04 21:17:06 +02003359static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003360{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003361 struct mv88e6xxx_chip *chip = bus->priv;
3362 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003363 int ret;
3364
3365 if (addr < 0)
Andrew Lunn158bc062016-04-28 21:24:06 -04003366 return 0xffff;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003367
Vivien Didelotfad09c72016-06-21 12:28:20 -04003368 mutex_lock(&chip->reg_lock);
Vivien Didelot8c9983a2016-05-09 13:22:39 -04003369
Vivien Didelotfad09c72016-06-21 12:28:20 -04003370 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3371 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3372 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3373 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
Vivien Didelot8c9983a2016-05-09 13:22:39 -04003374 else
Vivien Didelotfad09c72016-06-21 12:28:20 -04003375 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
Vivien Didelot8c9983a2016-05-09 13:22:39 -04003376
Vivien Didelotfad09c72016-06-21 12:28:20 -04003377 mutex_unlock(&chip->reg_lock);
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003378 return ret;
3379}
3380
Andrew Lunnb516d452016-06-04 21:17:06 +02003381static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
Andrew Lunn03a4a542016-06-04 21:17:05 +02003382 u16 val)
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003383{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003384 struct mv88e6xxx_chip *chip = bus->priv;
3385 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003386 int ret;
3387
3388 if (addr < 0)
Andrew Lunn158bc062016-04-28 21:24:06 -04003389 return 0xffff;
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003390
Vivien Didelotfad09c72016-06-21 12:28:20 -04003391 mutex_lock(&chip->reg_lock);
Vivien Didelot8c9983a2016-05-09 13:22:39 -04003392
Vivien Didelotfad09c72016-06-21 12:28:20 -04003393 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3394 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3395 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3396 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
Vivien Didelot8c9983a2016-05-09 13:22:39 -04003397 else
Vivien Didelotfad09c72016-06-21 12:28:20 -04003398 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
Vivien Didelot8c9983a2016-05-09 13:22:39 -04003399
Vivien Didelotfad09c72016-06-21 12:28:20 -04003400 mutex_unlock(&chip->reg_lock);
Andrew Lunnfd3a0ee2015-04-02 04:06:36 +02003401 return ret;
3402}
3403
Vivien Didelotfad09c72016-06-21 12:28:20 -04003404static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
Andrew Lunnb516d452016-06-04 21:17:06 +02003405 struct device_node *np)
3406{
3407 static int index;
3408 struct mii_bus *bus;
3409 int err;
3410
Vivien Didelotfad09c72016-06-21 12:28:20 -04003411 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3412 mv88e6xxx_ppu_state_init(chip);
Andrew Lunnb516d452016-06-04 21:17:06 +02003413
3414 if (np)
Vivien Didelotfad09c72016-06-21 12:28:20 -04003415 chip->mdio_np = of_get_child_by_name(np, "mdio");
Andrew Lunnb516d452016-06-04 21:17:06 +02003416
Vivien Didelotfad09c72016-06-21 12:28:20 -04003417 bus = devm_mdiobus_alloc(chip->dev);
Andrew Lunnb516d452016-06-04 21:17:06 +02003418 if (!bus)
3419 return -ENOMEM;
3420
Vivien Didelotfad09c72016-06-21 12:28:20 -04003421 bus->priv = (void *)chip;
Andrew Lunnb516d452016-06-04 21:17:06 +02003422 if (np) {
3423 bus->name = np->full_name;
3424 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3425 } else {
3426 bus->name = "mv88e6xxx SMI";
3427 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3428 }
3429
3430 bus->read = mv88e6xxx_mdio_read;
3431 bus->write = mv88e6xxx_mdio_write;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003432 bus->parent = chip->dev;
Andrew Lunnb516d452016-06-04 21:17:06 +02003433
Vivien Didelotfad09c72016-06-21 12:28:20 -04003434 if (chip->mdio_np)
3435 err = of_mdiobus_register(bus, chip->mdio_np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003436 else
3437 err = mdiobus_register(bus);
3438 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003439 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
Andrew Lunnb516d452016-06-04 21:17:06 +02003440 goto out;
3441 }
Vivien Didelotfad09c72016-06-21 12:28:20 -04003442 chip->mdio_bus = bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003443
3444 return 0;
3445
3446out:
Vivien Didelotfad09c72016-06-21 12:28:20 -04003447 if (chip->mdio_np)
3448 of_node_put(chip->mdio_np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003449
3450 return err;
3451}
3452
Vivien Didelotfad09c72016-06-21 12:28:20 -04003453static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
Andrew Lunnb516d452016-06-04 21:17:06 +02003454
3455{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003456 struct mii_bus *bus = chip->mdio_bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003457
3458 mdiobus_unregister(bus);
3459
Vivien Didelotfad09c72016-06-21 12:28:20 -04003460 if (chip->mdio_np)
3461 of_node_put(chip->mdio_np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003462}
3463
Guenter Roeckc22995c2015-07-25 09:42:28 -07003464#ifdef CONFIG_NET_DSA_HWMON
3465
3466static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3467{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003468 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003469 int ret;
3470 int val;
3471
3472 *temp = 0;
3473
Vivien Didelotfad09c72016-06-21 12:28:20 -04003474 mutex_lock(&chip->reg_lock);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003475
Vivien Didelotfad09c72016-06-21 12:28:20 -04003476 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003477 if (ret < 0)
3478 goto error;
3479
3480 /* Enable temperature sensor */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003481 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003482 if (ret < 0)
3483 goto error;
3484
Vivien Didelotfad09c72016-06-21 12:28:20 -04003485 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
Guenter Roeckc22995c2015-07-25 09:42:28 -07003486 if (ret < 0)
3487 goto error;
3488
3489 /* Wait for temperature to stabilize */
3490 usleep_range(10000, 12000);
3491
Vivien Didelotfad09c72016-06-21 12:28:20 -04003492 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003493 if (val < 0) {
3494 ret = val;
3495 goto error;
3496 }
3497
3498 /* Disable temperature sensor */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003499 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
Guenter Roeckc22995c2015-07-25 09:42:28 -07003500 if (ret < 0)
3501 goto error;
3502
3503 *temp = ((val & 0x1f) - 5) * 5;
3504
3505error:
Vivien Didelotfad09c72016-06-21 12:28:20 -04003506 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3507 mutex_unlock(&chip->reg_lock);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003508 return ret;
3509}
3510
3511static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3512{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003513 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3514 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
Guenter Roeckc22995c2015-07-25 09:42:28 -07003515 int ret;
3516
3517 *temp = 0;
3518
Andrew Lunn03a4a542016-06-04 21:17:05 +02003519 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003520 if (ret < 0)
3521 return ret;
3522
3523 *temp = (ret & 0xff) - 25;
3524
3525 return 0;
3526}
3527
Vivien Didelotf81ec902016-05-09 13:22:58 -04003528static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
Guenter Roeckc22995c2015-07-25 09:42:28 -07003529{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003530 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn158bc062016-04-28 21:24:06 -04003531
Vivien Didelotfad09c72016-06-21 12:28:20 -04003532 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
Vivien Didelot6594f612016-05-09 13:22:42 -04003533 return -EOPNOTSUPP;
3534
Vivien Didelotfad09c72016-06-21 12:28:20 -04003535 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
Guenter Roeckc22995c2015-07-25 09:42:28 -07003536 return mv88e63xx_get_temp(ds, temp);
3537
3538 return mv88e61xx_get_temp(ds, temp);
3539}
3540
Vivien Didelotf81ec902016-05-09 13:22:58 -04003541static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
Guenter Roeckc22995c2015-07-25 09:42:28 -07003542{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003543 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3544 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
Guenter Roeckc22995c2015-07-25 09:42:28 -07003545 int ret;
3546
Vivien Didelotfad09c72016-06-21 12:28:20 -04003547 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
Guenter Roeckc22995c2015-07-25 09:42:28 -07003548 return -EOPNOTSUPP;
3549
3550 *temp = 0;
3551
Andrew Lunn03a4a542016-06-04 21:17:05 +02003552 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003553 if (ret < 0)
3554 return ret;
3555
3556 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3557
3558 return 0;
3559}
3560
Vivien Didelotf81ec902016-05-09 13:22:58 -04003561static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
Guenter Roeckc22995c2015-07-25 09:42:28 -07003562{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003563 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3564 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
Guenter Roeckc22995c2015-07-25 09:42:28 -07003565 int ret;
3566
Vivien Didelotfad09c72016-06-21 12:28:20 -04003567 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
Guenter Roeckc22995c2015-07-25 09:42:28 -07003568 return -EOPNOTSUPP;
3569
Andrew Lunn03a4a542016-06-04 21:17:05 +02003570 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003571 if (ret < 0)
3572 return ret;
3573 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
Andrew Lunn03a4a542016-06-04 21:17:05 +02003574 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3575 (ret & 0xe0ff) | (temp << 8));
Guenter Roeckc22995c2015-07-25 09:42:28 -07003576}
3577
Vivien Didelotf81ec902016-05-09 13:22:58 -04003578static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
Guenter Roeckc22995c2015-07-25 09:42:28 -07003579{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003580 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3581 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
Guenter Roeckc22995c2015-07-25 09:42:28 -07003582 int ret;
3583
Vivien Didelotfad09c72016-06-21 12:28:20 -04003584 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
Guenter Roeckc22995c2015-07-25 09:42:28 -07003585 return -EOPNOTSUPP;
3586
3587 *alarm = false;
3588
Andrew Lunn03a4a542016-06-04 21:17:05 +02003589 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
Guenter Roeckc22995c2015-07-25 09:42:28 -07003590 if (ret < 0)
3591 return ret;
3592
3593 *alarm = !!(ret & 0x40);
3594
3595 return 0;
3596}
3597#endif /* CONFIG_NET_DSA_HWMON */
3598
Vivien Didelotf81ec902016-05-09 13:22:58 -04003599static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3600 [MV88E6085] = {
3601 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3602 .family = MV88E6XXX_FAMILY_6097,
3603 .name = "Marvell 88E6085",
3604 .num_databases = 4096,
3605 .num_ports = 10,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003606 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003607 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3608 },
3609
3610 [MV88E6095] = {
3611 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3612 .family = MV88E6XXX_FAMILY_6095,
3613 .name = "Marvell 88E6095/88E6095F",
3614 .num_databases = 256,
3615 .num_ports = 11,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003616 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003617 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3618 },
3619
3620 [MV88E6123] = {
3621 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3622 .family = MV88E6XXX_FAMILY_6165,
3623 .name = "Marvell 88E6123",
3624 .num_databases = 4096,
3625 .num_ports = 3,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003626 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003627 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3628 },
3629
3630 [MV88E6131] = {
3631 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3632 .family = MV88E6XXX_FAMILY_6185,
3633 .name = "Marvell 88E6131",
3634 .num_databases = 256,
3635 .num_ports = 8,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003636 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003637 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3638 },
3639
3640 [MV88E6161] = {
3641 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3642 .family = MV88E6XXX_FAMILY_6165,
3643 .name = "Marvell 88E6161",
3644 .num_databases = 4096,
3645 .num_ports = 6,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003646 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003647 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3648 },
3649
3650 [MV88E6165] = {
3651 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3652 .family = MV88E6XXX_FAMILY_6165,
3653 .name = "Marvell 88E6165",
3654 .num_databases = 4096,
3655 .num_ports = 6,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003656 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003657 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3658 },
3659
3660 [MV88E6171] = {
3661 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3662 .family = MV88E6XXX_FAMILY_6351,
3663 .name = "Marvell 88E6171",
3664 .num_databases = 4096,
3665 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003666 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003667 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3668 },
3669
3670 [MV88E6172] = {
3671 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3672 .family = MV88E6XXX_FAMILY_6352,
3673 .name = "Marvell 88E6172",
3674 .num_databases = 4096,
3675 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003676 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003677 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3678 },
3679
3680 [MV88E6175] = {
3681 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3682 .family = MV88E6XXX_FAMILY_6351,
3683 .name = "Marvell 88E6175",
3684 .num_databases = 4096,
3685 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003686 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003687 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3688 },
3689
3690 [MV88E6176] = {
3691 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3692 .family = MV88E6XXX_FAMILY_6352,
3693 .name = "Marvell 88E6176",
3694 .num_databases = 4096,
3695 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003696 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003697 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3698 },
3699
3700 [MV88E6185] = {
3701 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3702 .family = MV88E6XXX_FAMILY_6185,
3703 .name = "Marvell 88E6185",
3704 .num_databases = 256,
3705 .num_ports = 10,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003706 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003707 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3708 },
3709
3710 [MV88E6240] = {
3711 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3712 .family = MV88E6XXX_FAMILY_6352,
3713 .name = "Marvell 88E6240",
3714 .num_databases = 4096,
3715 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003716 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003717 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3718 },
3719
3720 [MV88E6320] = {
3721 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3722 .family = MV88E6XXX_FAMILY_6320,
3723 .name = "Marvell 88E6320",
3724 .num_databases = 4096,
3725 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003726 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003727 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3728 },
3729
3730 [MV88E6321] = {
3731 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3732 .family = MV88E6XXX_FAMILY_6320,
3733 .name = "Marvell 88E6321",
3734 .num_databases = 4096,
3735 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003736 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003737 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3738 },
3739
3740 [MV88E6350] = {
3741 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3742 .family = MV88E6XXX_FAMILY_6351,
3743 .name = "Marvell 88E6350",
3744 .num_databases = 4096,
3745 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003746 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003747 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3748 },
3749
3750 [MV88E6351] = {
3751 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3752 .family = MV88E6XXX_FAMILY_6351,
3753 .name = "Marvell 88E6351",
3754 .num_databases = 4096,
3755 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003756 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003757 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3758 },
3759
3760 [MV88E6352] = {
3761 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3762 .family = MV88E6XXX_FAMILY_6352,
3763 .name = "Marvell 88E6352",
3764 .num_databases = 4096,
3765 .num_ports = 7,
Vivien Didelot9dddd472016-06-20 13:14:10 -04003766 .port_base_addr = 0x10,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003767 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3768 },
3769};
3770
Vivien Didelot5f7c0362016-06-20 13:14:04 -04003771static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
Vivien Didelotb9b37712015-10-30 19:39:48 -04003772{
Vivien Didelota439c062016-04-17 13:23:58 -04003773 int i;
Vivien Didelotb9b37712015-10-30 19:39:48 -04003774
Vivien Didelot5f7c0362016-06-20 13:14:04 -04003775 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3776 if (mv88e6xxx_table[i].prod_num == prod_num)
3777 return &mv88e6xxx_table[i];
Vivien Didelotb9b37712015-10-30 19:39:48 -04003778
Vivien Didelotb9b37712015-10-30 19:39:48 -04003779 return NULL;
3780}
3781
Vivien Didelotfad09c72016-06-21 12:28:20 -04003782static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003783{
3784 const struct mv88e6xxx_info *info;
3785 int id, prod_num, rev;
3786
Vivien Didelotfad09c72016-06-21 12:28:20 -04003787 id = mv88e6xxx_reg_read(chip, chip->info->port_base_addr,
3788 PORT_SWITCH_ID);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003789 if (id < 0)
3790 return id;
3791
3792 prod_num = (id & 0xfff0) >> 4;
3793 rev = id & 0x000f;
3794
3795 info = mv88e6xxx_lookup_info(prod_num);
3796 if (!info)
3797 return -ENODEV;
3798
Vivien Didelotcaac8542016-06-20 13:14:09 -04003799 /* Update the compatible info with the probed one */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003800 chip->info = info;
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003801
Vivien Didelotfad09c72016-06-21 12:28:20 -04003802 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3803 chip->info->prod_num, chip->info->name, rev);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003804
3805 return 0;
3806}
3807
Vivien Didelotfad09c72016-06-21 12:28:20 -04003808static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
Vivien Didelot469d7292016-06-20 13:14:06 -04003809{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003810 struct mv88e6xxx_chip *chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04003811
Vivien Didelotfad09c72016-06-21 12:28:20 -04003812 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3813 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04003814 return NULL;
3815
Vivien Didelotfad09c72016-06-21 12:28:20 -04003816 chip->dev = dev;
Vivien Didelot469d7292016-06-20 13:14:06 -04003817
Vivien Didelotfad09c72016-06-21 12:28:20 -04003818 mutex_init(&chip->reg_lock);
Vivien Didelot469d7292016-06-20 13:14:06 -04003819
Vivien Didelotfad09c72016-06-21 12:28:20 -04003820 return chip;
Vivien Didelot469d7292016-06-20 13:14:06 -04003821}
3822
Vivien Didelotfad09c72016-06-21 12:28:20 -04003823static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003824 struct mii_bus *bus, int sw_addr)
3825{
3826 /* ADDR[0] pin is unavailable externally and considered zero */
3827 if (sw_addr & 0x1)
3828 return -EINVAL;
3829
Vivien Didelot914b32f2016-06-20 13:14:11 -04003830 if (sw_addr == 0)
Vivien Didelotfad09c72016-06-21 12:28:20 -04003831 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3832 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3833 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
Vivien Didelot914b32f2016-06-20 13:14:11 -04003834 else
3835 return -EINVAL;
3836
Vivien Didelotfad09c72016-06-21 12:28:20 -04003837 chip->bus = bus;
3838 chip->sw_addr = sw_addr;
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003839
3840 return 0;
3841}
3842
Andrew Lunnfcdce7d2016-05-10 23:27:20 +02003843static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3844 struct device *host_dev, int sw_addr,
3845 void **priv)
Andrew Lunna77d43f2016-04-13 02:40:42 +02003846{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003847 struct mv88e6xxx_chip *chip;
Vivien Didelota439c062016-04-17 13:23:58 -04003848 struct mii_bus *bus;
Andrew Lunnb516d452016-06-04 21:17:06 +02003849 int err;
Andrew Lunna77d43f2016-04-13 02:40:42 +02003850
Vivien Didelota439c062016-04-17 13:23:58 -04003851 bus = dsa_host_dev_to_mii_bus(host_dev);
Andrew Lunnc1569132016-04-13 02:40:45 +02003852 if (!bus)
3853 return NULL;
3854
Vivien Didelotfad09c72016-06-21 12:28:20 -04003855 chip = mv88e6xxx_alloc_chip(dsa_dev);
3856 if (!chip)
Vivien Didelot469d7292016-06-20 13:14:06 -04003857 return NULL;
3858
Vivien Didelotcaac8542016-06-20 13:14:09 -04003859 /* Legacy SMI probing will only support chips similar to 88E6085 */
Vivien Didelotfad09c72016-06-21 12:28:20 -04003860 chip->info = &mv88e6xxx_table[MV88E6085];
Vivien Didelotcaac8542016-06-20 13:14:09 -04003861
Vivien Didelotfad09c72016-06-21 12:28:20 -04003862 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003863 if (err)
3864 goto free;
3865
Vivien Didelotfad09c72016-06-21 12:28:20 -04003866 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003867 if (err)
Vivien Didelot469d7292016-06-20 13:14:06 -04003868 goto free;
Vivien Didelota439c062016-04-17 13:23:58 -04003869
Vivien Didelotfad09c72016-06-21 12:28:20 -04003870 err = mv88e6xxx_mdio_register(chip, NULL);
Andrew Lunnb516d452016-06-04 21:17:06 +02003871 if (err)
Vivien Didelot469d7292016-06-20 13:14:06 -04003872 goto free;
Andrew Lunnb516d452016-06-04 21:17:06 +02003873
Vivien Didelotfad09c72016-06-21 12:28:20 -04003874 *priv = chip;
Vivien Didelota439c062016-04-17 13:23:58 -04003875
Vivien Didelotfad09c72016-06-21 12:28:20 -04003876 return chip->info->name;
Vivien Didelot469d7292016-06-20 13:14:06 -04003877free:
Vivien Didelotfad09c72016-06-21 12:28:20 -04003878 devm_kfree(dsa_dev, chip);
Vivien Didelot469d7292016-06-20 13:14:06 -04003879
3880 return NULL;
Andrew Lunna77d43f2016-04-13 02:40:42 +02003881}
3882
Vivien Didelot57d32312016-06-20 13:13:58 -04003883static struct dsa_switch_driver mv88e6xxx_switch_driver = {
Vivien Didelotf81ec902016-05-09 13:22:58 -04003884 .tag_protocol = DSA_TAG_PROTO_EDSA,
Andrew Lunnfcdce7d2016-05-10 23:27:20 +02003885 .probe = mv88e6xxx_drv_probe,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003886 .setup = mv88e6xxx_setup,
3887 .set_addr = mv88e6xxx_set_addr,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003888 .adjust_link = mv88e6xxx_adjust_link,
3889 .get_strings = mv88e6xxx_get_strings,
3890 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3891 .get_sset_count = mv88e6xxx_get_sset_count,
3892 .set_eee = mv88e6xxx_set_eee,
3893 .get_eee = mv88e6xxx_get_eee,
3894#ifdef CONFIG_NET_DSA_HWMON
3895 .get_temp = mv88e6xxx_get_temp,
3896 .get_temp_limit = mv88e6xxx_get_temp_limit,
3897 .set_temp_limit = mv88e6xxx_set_temp_limit,
3898 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3899#endif
Andrew Lunnf8cd8752016-05-10 23:27:25 +02003900 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
Vivien Didelotf81ec902016-05-09 13:22:58 -04003901 .get_eeprom = mv88e6xxx_get_eeprom,
3902 .set_eeprom = mv88e6xxx_set_eeprom,
3903 .get_regs_len = mv88e6xxx_get_regs_len,
3904 .get_regs = mv88e6xxx_get_regs,
3905 .port_bridge_join = mv88e6xxx_port_bridge_join,
3906 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3907 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3908 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3909 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3910 .port_vlan_add = mv88e6xxx_port_vlan_add,
3911 .port_vlan_del = mv88e6xxx_port_vlan_del,
3912 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3913 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3914 .port_fdb_add = mv88e6xxx_port_fdb_add,
3915 .port_fdb_del = mv88e6xxx_port_fdb_del,
3916 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3917};
3918
Vivien Didelotfad09c72016-06-21 12:28:20 -04003919static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
Vivien Didelotb7e66a52016-06-20 13:14:02 -04003920 struct device_node *np)
3921{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003922 struct device *dev = chip->dev;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04003923 struct dsa_switch *ds;
3924
3925 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3926 if (!ds)
3927 return -ENOMEM;
3928
3929 ds->dev = dev;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003930 ds->priv = chip;
Vivien Didelotb7e66a52016-06-20 13:14:02 -04003931 ds->drv = &mv88e6xxx_switch_driver;
3932
3933 dev_set_drvdata(dev, ds);
3934
3935 return dsa_register_switch(ds, np);
3936}
3937
Vivien Didelotfad09c72016-06-21 12:28:20 -04003938static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
Vivien Didelotb7e66a52016-06-20 13:14:02 -04003939{
Vivien Didelotfad09c72016-06-21 12:28:20 -04003940 dsa_unregister_switch(chip->ds);
Vivien Didelotb7e66a52016-06-20 13:14:02 -04003941}
3942
Vivien Didelot57d32312016-06-20 13:13:58 -04003943static int mv88e6xxx_probe(struct mdio_device *mdiodev)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003944{
3945 struct device *dev = &mdiodev->dev;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02003946 struct device_node *np = dev->of_node;
Vivien Didelotcaac8542016-06-20 13:14:09 -04003947 const struct mv88e6xxx_info *compat_info;
Vivien Didelotfad09c72016-06-21 12:28:20 -04003948 struct mv88e6xxx_chip *chip;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02003949 u32 eeprom_len;
Andrew Lunn52638f72016-05-10 23:27:22 +02003950 int err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003951
Vivien Didelotcaac8542016-06-20 13:14:09 -04003952 compat_info = of_device_get_match_data(dev);
3953 if (!compat_info)
3954 return -EINVAL;
3955
Vivien Didelotfad09c72016-06-21 12:28:20 -04003956 chip = mv88e6xxx_alloc_chip(dev);
3957 if (!chip)
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003958 return -ENOMEM;
3959
Vivien Didelotfad09c72016-06-21 12:28:20 -04003960 chip->info = compat_info;
Vivien Didelotcaac8542016-06-20 13:14:09 -04003961
Vivien Didelotfad09c72016-06-21 12:28:20 -04003962 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
Vivien Didelot4a70c4a2016-06-20 13:14:07 -04003963 if (err)
3964 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003965
Vivien Didelotfad09c72016-06-21 12:28:20 -04003966 err = mv88e6xxx_detect(chip);
Vivien Didelotbc46a3d2016-06-20 13:14:08 -04003967 if (err)
3968 return err;
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003969
Vivien Didelotfad09c72016-06-21 12:28:20 -04003970 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3971 if (IS_ERR(chip->reset))
3972 return PTR_ERR(chip->reset);
Andrew Lunn52638f72016-05-10 23:27:22 +02003973
Vivien Didelotfad09c72016-06-21 12:28:20 -04003974 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM) &&
Andrew Lunnf8cd8752016-05-10 23:27:25 +02003975 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
Vivien Didelotfad09c72016-06-21 12:28:20 -04003976 chip->eeprom_len = eeprom_len;
Andrew Lunnf8cd8752016-05-10 23:27:25 +02003977
Vivien Didelotfad09c72016-06-21 12:28:20 -04003978 err = mv88e6xxx_mdio_register(chip, np);
Andrew Lunnb516d452016-06-04 21:17:06 +02003979 if (err)
3980 return err;
3981
Vivien Didelotfad09c72016-06-21 12:28:20 -04003982 err = mv88e6xxx_register_switch(chip, np);
Andrew Lunn83c0afa2016-06-04 21:17:07 +02003983 if (err) {
Vivien Didelotfad09c72016-06-21 12:28:20 -04003984 mv88e6xxx_mdio_unregister(chip);
Andrew Lunn83c0afa2016-06-04 21:17:07 +02003985 return err;
3986 }
3987
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003988 return 0;
3989}
3990
3991static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3992{
3993 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
Vivien Didelotfad09c72016-06-21 12:28:20 -04003994 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003995
Vivien Didelotfad09c72016-06-21 12:28:20 -04003996 mv88e6xxx_unregister_switch(chip);
3997 mv88e6xxx_mdio_unregister(chip);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02003998}
3999
4000static const struct of_device_id mv88e6xxx_of_match[] = {
Vivien Didelotcaac8542016-06-20 13:14:09 -04004001 {
4002 .compatible = "marvell,mv88e6085",
4003 .data = &mv88e6xxx_table[MV88E6085],
4004 },
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004005 { /* sentinel */ },
4006};
4007
4008MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4009
4010static struct mdio_driver mv88e6xxx_driver = {
4011 .probe = mv88e6xxx_probe,
4012 .remove = mv88e6xxx_remove,
4013 .mdiodrv.driver = {
4014 .name = "mv88e6085",
4015 .of_match_table = mv88e6xxx_of_match,
4016 },
4017};
4018
Ben Hutchings98e67302011-11-25 14:36:19 +00004019static int __init mv88e6xxx_init(void)
4020{
Vivien Didelotf81ec902016-05-09 13:22:58 -04004021 register_switch_driver(&mv88e6xxx_switch_driver);
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004022 return mdio_driver_register(&mv88e6xxx_driver);
Ben Hutchings98e67302011-11-25 14:36:19 +00004023}
4024module_init(mv88e6xxx_init);
4025
4026static void __exit mv88e6xxx_cleanup(void)
4027{
Andrew Lunn14c7b3c2016-05-10 23:27:21 +02004028 mdio_driver_unregister(&mv88e6xxx_driver);
Vivien Didelotf81ec902016-05-09 13:22:58 -04004029 unregister_switch_driver(&mv88e6xxx_switch_driver);
Ben Hutchings98e67302011-11-25 14:36:19 +00004030}
4031module_exit(mv88e6xxx_cleanup);
Ben Hutchings3d825ed2011-11-25 14:37:16 +00004032
4033MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4034MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4035MODULE_LICENSE("GPL");