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Stephen M. Cameronedd16362009-12-08 14:09:11 -08001/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21#ifndef HPSA_H
22#define HPSA_H
23
24#include <scsi/scsicam.h>
25
26#define IO_OK 0
27#define IO_ERROR 1
28
29struct ctlr_info;
30
31struct access_method {
32 void (*submit_command)(struct ctlr_info *h,
33 struct CommandList *c);
34 void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
35 unsigned long (*fifo_full)(struct ctlr_info *h);
Stephen M. Cameron900c5442010-02-04 08:42:35 -060036 bool (*intr_pending)(struct ctlr_info *h);
Stephen M. Cameronedd16362009-12-08 14:09:11 -080037 unsigned long (*command_completed)(struct ctlr_info *h);
38};
39
40struct hpsa_scsi_dev_t {
41 int devtype;
42 int bus, target, lun; /* as presented to the OS */
43 unsigned char scsi3addr[8]; /* as presented to the HW */
44#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
45 unsigned char device_id[16]; /* from inquiry pg. 0x83 */
46 unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
47 unsigned char model[16]; /* bytes 16-31 of inquiry data */
Stephen M. Cameronedd16362009-12-08 14:09:11 -080048 unsigned char raid_level; /* from inquiry page 0xC1 */
49};
50
51struct ctlr_info {
52 int ctlr;
53 char devname[8];
54 char *product_name;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080055 struct pci_dev *pdev;
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -060056 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080057 void __iomem *vaddr;
58 unsigned long paddr;
59 int nr_cmds; /* Number of commands allowed on this controller */
60 struct CfgTable __iomem *cfgtable;
Don Brace303932f2010-02-04 08:42:40 -060061 int max_sg_entries;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080062 int interrupts_enabled;
63 int major;
64 int max_commands;
65 int commands_outstanding;
66 int max_outstanding; /* Debug */
67 int usage_count; /* number of opens all all minor devices */
Don Brace303932f2010-02-04 08:42:40 -060068# define PERF_MODE_INT 0
69# define DOORBELL_INT 1
Stephen M. Cameronedd16362009-12-08 14:09:11 -080070# define SIMPLE_MODE_INT 2
71# define MEMQ_MODE_INT 3
72 unsigned int intr[4];
73 unsigned int msix_vector;
74 unsigned int msi_vector;
Stephen M. Camerona9a3a272011-02-15 15:32:53 -060075 int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
Stephen M. Cameronedd16362009-12-08 14:09:11 -080076 struct access_method access;
77
78 /* queue and queue Info */
Stephen M. Cameron9e0fc762011-02-15 15:32:48 -060079 struct list_head reqQ;
80 struct list_head cmpQ;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080081 unsigned int Qdepth;
82 unsigned int maxQsinceinit;
83 unsigned int maxSG;
84 spinlock_t lock;
Stephen M. Cameron33a2ffc2010-02-25 14:03:27 -060085 int maxsgentries;
86 u8 max_cmd_sg_entries;
87 int chainsize;
88 struct SGDescriptor **cmd_sg_list;
Stephen M. Cameronedd16362009-12-08 14:09:11 -080089
90 /* pointers to command and error info pool */
91 struct CommandList *cmd_pool;
92 dma_addr_t cmd_pool_dhandle;
93 struct ErrorInfo *errinfo_pool;
94 dma_addr_t errinfo_pool_dhandle;
95 unsigned long *cmd_pool_bits;
96 int nr_allocs;
97 int nr_frees;
98 int busy_initializing;
99 int busy_scanning;
Stephen M. Camerona08a8472010-02-04 08:43:16 -0600100 int scan_finished;
101 spinlock_t scan_lock;
102 wait_queue_head_t scan_wait_queue;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800103
104 struct Scsi_Host *scsi_host;
105 spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
106 int ndevices; /* number of used elements in .dev[] array. */
107#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
108 struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
Don Brace303932f2010-02-04 08:42:40 -0600109 /*
110 * Performant mode tables.
111 */
112 u32 trans_support;
113 u32 trans_offset;
114 struct TransTable_struct *transtable;
115 unsigned long transMethod;
116
117 /*
118 * Performant mode completion buffer
119 */
120 u64 *reply_pool;
121 dma_addr_t reply_pool_dhandle;
122 u64 *reply_pool_head;
123 size_t reply_pool_size;
124 unsigned char reply_pool_wraparound;
125 u32 *blockFetchTable;
Stephen M. Cameron339b2b12010-02-04 08:42:50 -0600126 unsigned char *hba_inquiry_data;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800127};
128#define HPSA_ABORT_MSG 0
129#define HPSA_DEVICE_RESET_MSG 1
130#define HPSA_BUS_RESET_MSG 2
131#define HPSA_HOST_RESET_MSG 3
132#define HPSA_MSG_SEND_RETRY_LIMIT 10
Stephen M. Cameron516fda42011-05-03 14:59:15 -0500133#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800134
135/* Maximum time in seconds driver will wait for command completions
136 * when polling before giving up.
137 */
138#define HPSA_MAX_POLL_TIME_SECS (20)
139
140/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
141 * how many times to retry TEST UNIT READY on a device
142 * while waiting for it to become ready before giving up.
143 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
144 * between sending TURs while waiting for a device
145 * to become ready.
146 */
147#define HPSA_TUR_RETRY_LIMIT (20)
148#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
149
150/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
151 * to become ready, in seconds, before giving up on it.
152 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
153 * between polling the board to see if it is ready, in
154 * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
155 * HPSA_BOARD_READY_ITERATIONS are derived from those.
156 */
157#define HPSA_BOARD_READY_WAIT_SECS (120)
Stephen M. Cameron2ed71272011-05-03 14:59:31 -0500158#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800159#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
160#define HPSA_BOARD_READY_POLL_INTERVAL \
161 ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
162#define HPSA_BOARD_READY_ITERATIONS \
163 ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
164 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
Stephen M. Cameronfe5389c2011-01-06 14:48:03 -0600165#define HPSA_BOARD_NOT_READY_ITERATIONS \
166 ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
167 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800168#define HPSA_POST_RESET_PAUSE_MSECS (3000)
169#define HPSA_POST_RESET_NOOP_RETRIES (12)
170
171/* Defining the diffent access_menthods */
172/*
173 * Memory mapped FIFO interface (SMART 53xx cards)
174 */
175#define SA5_DOORBELL 0x20
176#define SA5_REQUEST_PORT_OFFSET 0x40
177#define SA5_REPLY_INTR_MASK_OFFSET 0x34
178#define SA5_REPLY_PORT_OFFSET 0x44
179#define SA5_INTR_STATUS 0x30
180#define SA5_SCRATCHPAD_OFFSET 0xB0
181
182#define SA5_CTCFG_OFFSET 0xB4
183#define SA5_CTMEM_OFFSET 0xB8
184
185#define SA5_INTR_OFF 0x08
186#define SA5B_INTR_OFF 0x04
187#define SA5_INTR_PENDING 0x08
188#define SA5B_INTR_PENDING 0x04
189#define FIFO_EMPTY 0xffffffff
190#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
191
192#define HPSA_ERROR_BIT 0x02
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800193
Don Brace303932f2010-02-04 08:42:40 -0600194/* Performant mode flags */
195#define SA5_PERF_INTR_PENDING 0x04
196#define SA5_PERF_INTR_OFF 0x05
197#define SA5_OUTDB_STATUS_PERF_BIT 0x01
198#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
199#define SA5_OUTDB_CLEAR 0xA0
200#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
201#define SA5_OUTDB_STATUS 0x9C
202
203
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800204#define HPSA_INTR_ON 1
205#define HPSA_INTR_OFF 0
206/*
207 Send the command to the hardware
208*/
209static void SA5_submit_command(struct ctlr_info *h,
210 struct CommandList *c)
211{
Don Brace303932f2010-02-04 08:42:40 -0600212 dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
213 c->Header.Tag.lower);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800214 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
Stephen M. Camerond0be5ec2011-05-03 14:58:49 -0500215 (void) readl(h->vaddr + SA5_REQUEST_PORT_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800216 h->commands_outstanding++;
217 if (h->commands_outstanding > h->max_outstanding)
218 h->max_outstanding = h->commands_outstanding;
219}
220
221/*
222 * This card is the opposite of the other cards.
223 * 0 turns interrupts on...
224 * 0x08 turns them off...
225 */
226static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
227{
228 if (val) { /* Turn interrupts on */
229 h->interrupts_enabled = 1;
230 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500231 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800232 } else { /* Turn them off */
233 h->interrupts_enabled = 0;
234 writel(SA5_INTR_OFF,
235 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500236 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800237 }
238}
Don Brace303932f2010-02-04 08:42:40 -0600239
240static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
241{
242 if (val) { /* turn on interrupts */
243 h->interrupts_enabled = 1;
244 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500245 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Don Brace303932f2010-02-04 08:42:40 -0600246 } else {
247 h->interrupts_enabled = 0;
248 writel(SA5_PERF_INTR_OFF,
249 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Stephen M. Cameron8cd21da2011-05-03 14:58:55 -0500250 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
Don Brace303932f2010-02-04 08:42:40 -0600251 }
252}
253
254static unsigned long SA5_performant_completed(struct ctlr_info *h)
255{
256 unsigned long register_value = FIFO_EMPTY;
257
258 /* flush the controller write of the reply queue by reading
259 * outbound doorbell status register.
260 */
261 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
262 /* msi auto clears the interrupt pending bit. */
263 if (!(h->msi_vector || h->msix_vector)) {
264 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
265 /* Do a read in order to flush the write to the controller
266 * (as per spec.)
267 */
268 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
269 }
270
271 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
272 register_value = *(h->reply_pool_head);
273 (h->reply_pool_head)++;
274 h->commands_outstanding--;
275 } else {
276 register_value = FIFO_EMPTY;
277 }
278 /* Check for wraparound */
279 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
280 h->reply_pool_head = h->reply_pool;
281 h->reply_pool_wraparound ^= 1;
282 }
283
284 return register_value;
285}
286
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800287/*
288 * Returns true if fifo is full.
289 *
290 */
291static unsigned long SA5_fifo_full(struct ctlr_info *h)
292{
293 if (h->commands_outstanding >= h->max_commands)
294 return 1;
295 else
296 return 0;
297
298}
299/*
300 * returns value read from hardware.
301 * returns FIFO_EMPTY if there is nothing to read
302 */
303static unsigned long SA5_completed(struct ctlr_info *h)
304{
305 unsigned long register_value
306 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
307
308 if (register_value != FIFO_EMPTY)
309 h->commands_outstanding--;
310
311#ifdef HPSA_DEBUG
312 if (register_value != FIFO_EMPTY)
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600313 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800314 register_value);
315 else
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600316 dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800317#endif
318
319 return register_value;
320}
321/*
322 * Returns true if an interrupt is pending..
323 */
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600324static bool SA5_intr_pending(struct ctlr_info *h)
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800325{
326 unsigned long register_value =
327 readl(h->vaddr + SA5_INTR_STATUS);
Stephen M. Cameron84ca0be2010-02-04 08:42:30 -0600328 dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
Stephen M. Cameron900c5442010-02-04 08:42:35 -0600329 return register_value & SA5_INTR_PENDING;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800330}
331
Don Brace303932f2010-02-04 08:42:40 -0600332static bool SA5_performant_intr_pending(struct ctlr_info *h)
333{
334 unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
335
336 if (!register_value)
337 return false;
338
339 if (h->msi_vector || h->msix_vector)
340 return true;
341
342 /* Read outbound doorbell to flush */
343 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
344 return register_value & SA5_OUTDB_STATUS_PERF_BIT;
345}
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800346
347static struct access_method SA5_access = {
348 SA5_submit_command,
349 SA5_intr_mask,
350 SA5_fifo_full,
351 SA5_intr_pending,
352 SA5_completed,
353};
354
Don Brace303932f2010-02-04 08:42:40 -0600355static struct access_method SA5_performant_access = {
356 SA5_submit_command,
357 SA5_performant_intr_mask,
358 SA5_fifo_full,
359 SA5_performant_intr_pending,
360 SA5_performant_completed,
361};
362
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800363struct board_type {
Stephen M. Cameron01a02ff2010-02-04 08:41:33 -0600364 u32 board_id;
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800365 char *product_name;
366 struct access_method *access;
367};
368
Stephen M. Cameronedd16362009-12-08 14:09:11 -0800369#endif /* HPSA_H */
370