sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 1 | /* |
| 2 | * OMAP4XXX L3 Interconnect error handling driver header |
| 3 | * |
| 4 | * Copyright (C) 2011 Texas Corporation |
| 5 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
| 6 | * sricharan <r.sricharan@ti.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 |
| 21 | * USA |
| 22 | */ |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 23 | #ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H |
| 24 | #define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H |
| 25 | |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 26 | #define L3_MODULES 3 |
| 27 | #define CLEAR_STDERR_LOG (1 << 31) |
| 28 | #define CUSTOM_ERROR 0x2 |
| 29 | #define STANDARD_ERROR 0x0 |
| 30 | #define INBAND_ERROR 0x0 |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 31 | #define L3_APPLICATION_ERROR 0x0 |
| 32 | #define L3_DEBUG_ERROR 0x1 |
| 33 | |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 34 | /* L3 TARG register offsets */ |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 35 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
| 36 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
| 37 | #define L3_FLAGMUX_REGERR0 0xc |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 38 | |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame^] | 39 | static u32 l3_flagmux[L3_MODULES] = { |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 40 | 0x500, |
| 41 | 0x1000, |
| 42 | 0X0200 |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 43 | }; |
| 44 | |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 45 | /* L3 Target standard Error register offsets */ |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame^] | 46 | static u32 l3_targ_inst_clk1[] = { |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 47 | 0x100, /* DMM1 */ |
| 48 | 0x200, /* DMM2 */ |
| 49 | 0x300, /* ABE */ |
| 50 | 0x400, /* L4CFG */ |
| 51 | 0x600 /* CLK2 PWR DISC */ |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 52 | }; |
| 53 | |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame^] | 54 | static u32 l3_targ_inst_clk2[] = { |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 55 | 0x500, /* CORTEX M3 */ |
| 56 | 0x300, /* DSS */ |
| 57 | 0x100, /* GPMC */ |
| 58 | 0x400, /* ISS */ |
| 59 | 0x700, /* IVAHD */ |
| 60 | 0xD00, /* missing in TRM corresponds to AES1*/ |
| 61 | 0x900, /* L4 PER0*/ |
| 62 | 0x200, /* OCMRAM */ |
| 63 | 0x100, /* missing in TRM corresponds to GPMC sERROR*/ |
| 64 | 0x600, /* SGX */ |
| 65 | 0x800, /* SL2 */ |
| 66 | 0x1600, /* C2C */ |
| 67 | 0x1100, /* missing in TRM corresponds PWR DISC CLK1*/ |
| 68 | 0xF00, /* missing in TRM corrsponds to SHA1*/ |
| 69 | 0xE00, /* missing in TRM corresponds to AES2*/ |
| 70 | 0xC00, /* L4 PER3 */ |
| 71 | 0xA00, /* L4 PER1*/ |
| 72 | 0xB00 /* L4 PER2*/ |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 73 | }; |
| 74 | |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame^] | 75 | static u32 l3_targ_inst_clk3[] = { |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 76 | 0x0100 /* EMUSS */ |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 77 | }; |
| 78 | |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame^] | 79 | static char *l3_targ_inst_name[L3_MODULES][18] = { |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 80 | { |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 81 | "DMM1", |
| 82 | "DMM2", |
| 83 | "ABE", |
| 84 | "L4CFG", |
| 85 | "CLK2 PWR DISC", |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 86 | }, |
| 87 | { |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 88 | "CORTEX M3" , |
| 89 | "DSS ", |
| 90 | "GPMC ", |
| 91 | "ISS ", |
| 92 | "IVAHD ", |
| 93 | "AES1", |
| 94 | "L4 PER0", |
| 95 | "OCMRAM ", |
| 96 | "GPMC sERROR", |
| 97 | "SGX ", |
| 98 | "SL2 ", |
| 99 | "C2C ", |
| 100 | "PWR DISC CLK1", |
| 101 | "SHA1", |
| 102 | "AES2", |
| 103 | "L4 PER3", |
| 104 | "L4 PER1", |
| 105 | "L4 PER2", |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 106 | }, |
| 107 | { |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 108 | "EMUSS", |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 109 | }, |
| 110 | }; |
| 111 | |
sricharan | 6616aac | 2011-08-23 12:58:48 +0530 | [diff] [blame^] | 112 | static u32 *l3_targ[L3_MODULES] = { |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 113 | l3_targ_inst_clk1, |
| 114 | l3_targ_inst_clk2, |
| 115 | l3_targ_inst_clk3, |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 116 | }; |
| 117 | |
| 118 | struct omap4_l3 { |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 119 | struct device *dev; |
| 120 | struct clk *ick; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 121 | |
| 122 | /* memory base */ |
Todd Poynor | 342fd14 | 2011-08-24 19:11:39 +0530 | [diff] [blame] | 123 | void __iomem *l3_base[L3_MODULES]; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 124 | |
sricharan | ed0e352 | 2011-08-24 20:07:45 +0530 | [diff] [blame] | 125 | int debug_irq; |
| 126 | int app_irq; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 127 | }; |
Santosh Shilimkar | 2722e56 | 2011-03-07 20:53:10 +0530 | [diff] [blame] | 128 | #endif |