Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 1 | #ifndef _ASM_X86_CPU_DEBUG_H |
| 2 | #define _ASM_X86_CPU_DEBUG_H |
| 3 | |
| 4 | /* |
| 5 | * CPU x86 architecture debug |
| 6 | * |
| 7 | * Copyright(C) 2009 Jaswinder Singh Rajput |
| 8 | */ |
| 9 | |
| 10 | /* Register flags */ |
| 11 | enum cpu_debug_bit { |
| 12 | /* Model Specific Registers (MSRs) */ |
| 13 | CPU_MC_BIT, /* Machine Check */ |
| 14 | CPU_MONITOR_BIT, /* Monitor */ |
| 15 | CPU_TIME_BIT, /* Time */ |
| 16 | CPU_PMC_BIT, /* Performance Monitor */ |
| 17 | CPU_PLATFORM_BIT, /* Platform */ |
| 18 | CPU_APIC_BIT, /* APIC */ |
| 19 | CPU_POWERON_BIT, /* Power-on */ |
| 20 | CPU_CONTROL_BIT, /* Control */ |
| 21 | CPU_FEATURES_BIT, /* Features control */ |
| 22 | CPU_LBRANCH_BIT, /* Last Branch */ |
| 23 | CPU_BIOS_BIT, /* BIOS */ |
| 24 | CPU_FREQ_BIT, /* Frequency */ |
| 25 | CPU_MTTR_BIT, /* MTRR */ |
| 26 | CPU_PERF_BIT, /* Performance */ |
| 27 | CPU_CACHE_BIT, /* Cache */ |
| 28 | CPU_SYSENTER_BIT, /* Sysenter */ |
| 29 | CPU_THERM_BIT, /* Thermal */ |
| 30 | CPU_MISC_BIT, /* Miscellaneous */ |
| 31 | CPU_DEBUG_BIT, /* Debug */ |
| 32 | CPU_PAT_BIT, /* PAT */ |
| 33 | CPU_VMX_BIT, /* VMX */ |
| 34 | CPU_CALL_BIT, /* System Call */ |
| 35 | CPU_BASE_BIT, /* BASE Address */ |
Jaswinder Singh Rajput | f4c3c4c | 2009-03-13 19:59:26 +0530 | [diff] [blame] | 36 | CPU_VER_BIT, /* Version ID */ |
| 37 | CPU_CONF_BIT, /* Configuration */ |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 38 | CPU_SMM_BIT, /* System mgmt mode */ |
| 39 | CPU_SVM_BIT, /*Secure Virtual Machine*/ |
| 40 | CPU_OSVM_BIT, /* OS-Visible Workaround*/ |
| 41 | /* Standard Registers */ |
| 42 | CPU_TSS_BIT, /* Task Stack Segment */ |
| 43 | CPU_CR_BIT, /* Control Registers */ |
| 44 | CPU_DT_BIT, /* Descriptor Table */ |
| 45 | /* End of Registers flags */ |
| 46 | CPU_REG_ALL_BIT, /* Select all Registers */ |
| 47 | }; |
| 48 | |
| 49 | #define CPU_REG_ALL (~0) /* Select all Registers */ |
| 50 | |
| 51 | #define CPU_MC (1 << CPU_MC_BIT) |
| 52 | #define CPU_MONITOR (1 << CPU_MONITOR_BIT) |
| 53 | #define CPU_TIME (1 << CPU_TIME_BIT) |
| 54 | #define CPU_PMC (1 << CPU_PMC_BIT) |
| 55 | #define CPU_PLATFORM (1 << CPU_PLATFORM_BIT) |
| 56 | #define CPU_APIC (1 << CPU_APIC_BIT) |
| 57 | #define CPU_POWERON (1 << CPU_POWERON_BIT) |
| 58 | #define CPU_CONTROL (1 << CPU_CONTROL_BIT) |
| 59 | #define CPU_FEATURES (1 << CPU_FEATURES_BIT) |
| 60 | #define CPU_LBRANCH (1 << CPU_LBRANCH_BIT) |
| 61 | #define CPU_BIOS (1 << CPU_BIOS_BIT) |
| 62 | #define CPU_FREQ (1 << CPU_FREQ_BIT) |
| 63 | #define CPU_MTRR (1 << CPU_MTTR_BIT) |
| 64 | #define CPU_PERF (1 << CPU_PERF_BIT) |
| 65 | #define CPU_CACHE (1 << CPU_CACHE_BIT) |
| 66 | #define CPU_SYSENTER (1 << CPU_SYSENTER_BIT) |
| 67 | #define CPU_THERM (1 << CPU_THERM_BIT) |
| 68 | #define CPU_MISC (1 << CPU_MISC_BIT) |
| 69 | #define CPU_DEBUG (1 << CPU_DEBUG_BIT) |
| 70 | #define CPU_PAT (1 << CPU_PAT_BIT) |
| 71 | #define CPU_VMX (1 << CPU_VMX_BIT) |
| 72 | #define CPU_CALL (1 << CPU_CALL_BIT) |
| 73 | #define CPU_BASE (1 << CPU_BASE_BIT) |
Jaswinder Singh Rajput | f4c3c4c | 2009-03-13 19:59:26 +0530 | [diff] [blame] | 74 | #define CPU_VER (1 << CPU_VER_BIT) |
| 75 | #define CPU_CONF (1 << CPU_CONF_BIT) |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 76 | #define CPU_SMM (1 << CPU_SMM_BIT) |
| 77 | #define CPU_SVM (1 << CPU_SVM_BIT) |
| 78 | #define CPU_OSVM (1 << CPU_OSVM_BIT) |
| 79 | #define CPU_TSS (1 << CPU_TSS_BIT) |
| 80 | #define CPU_CR (1 << CPU_CR_BIT) |
| 81 | #define CPU_DT (1 << CPU_DT_BIT) |
| 82 | |
| 83 | /* Register file flags */ |
| 84 | enum cpu_file_bit { |
| 85 | CPU_INDEX_BIT, /* index */ |
| 86 | CPU_VALUE_BIT, /* value */ |
| 87 | }; |
| 88 | |
| 89 | #define CPU_FILE_VALUE (1 << CPU_VALUE_BIT) |
| 90 | |
| 91 | /* |
| 92 | * DisplayFamily_DisplayModel Processor Families/Processor Number Series |
| 93 | * -------------------------- ------------------------------------------ |
| 94 | * 05_01, 05_02, 05_04 Pentium, Pentium with MMX |
| 95 | * |
| 96 | * 06_01 Pentium Pro |
| 97 | * 06_03, 06_05 Pentium II Xeon, Pentium II |
| 98 | * 06_07, 06_08, 06_0A, 06_0B Pentium III Xeon, Pentum III |
| 99 | * |
| 100 | * 06_09, 060D Pentium M |
| 101 | * |
| 102 | * 06_0E Core Duo, Core Solo |
| 103 | * |
| 104 | * 06_0F Xeon 3000, 3200, 5100, 5300, 7300 series, |
| 105 | * Core 2 Quad, Core 2 Extreme, Core 2 Duo, |
| 106 | * Pentium dual-core |
| 107 | * 06_17 Xeon 5200, 5400 series, Core 2 Quad Q9650 |
| 108 | * |
| 109 | * 06_1C Atom |
| 110 | * |
| 111 | * 0F_00, 0F_01, 0F_02 Xeon, Xeon MP, Pentium 4 |
| 112 | * 0F_03, 0F_04 Xeon, Xeon MP, Pentium 4, Pentium D |
| 113 | * |
| 114 | * 0F_06 Xeon 7100, 5000 Series, Xeon MP, |
| 115 | * Pentium 4, Pentium D |
| 116 | */ |
| 117 | |
| 118 | /* Register processors bits */ |
| 119 | enum cpu_processor_bit { |
| 120 | CPU_NONE, |
| 121 | /* Intel */ |
| 122 | CPU_INTEL_PENTIUM_BIT, |
| 123 | CPU_INTEL_P6_BIT, |
| 124 | CPU_INTEL_PENTIUM_M_BIT, |
| 125 | CPU_INTEL_CORE_BIT, |
| 126 | CPU_INTEL_CORE2_BIT, |
| 127 | CPU_INTEL_ATOM_BIT, |
| 128 | CPU_INTEL_XEON_P4_BIT, |
| 129 | CPU_INTEL_XEON_MP_BIT, |
Jaswinder Singh Rajput | f4c3c4c | 2009-03-13 19:59:26 +0530 | [diff] [blame] | 130 | /* AMD */ |
| 131 | CPU_AMD_K6_BIT, |
| 132 | CPU_AMD_K7_BIT, |
| 133 | CPU_AMD_K8_BIT, |
| 134 | CPU_AMD_0F_BIT, |
| 135 | CPU_AMD_10_BIT, |
| 136 | CPU_AMD_11_BIT, |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 137 | }; |
| 138 | |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 139 | #define CPU_INTEL_PENTIUM (1 << CPU_INTEL_PENTIUM_BIT) |
| 140 | #define CPU_INTEL_P6 (1 << CPU_INTEL_P6_BIT) |
| 141 | #define CPU_INTEL_PENTIUM_M (1 << CPU_INTEL_PENTIUM_M_BIT) |
| 142 | #define CPU_INTEL_CORE (1 << CPU_INTEL_CORE_BIT) |
| 143 | #define CPU_INTEL_CORE2 (1 << CPU_INTEL_CORE2_BIT) |
| 144 | #define CPU_INTEL_ATOM (1 << CPU_INTEL_ATOM_BIT) |
| 145 | #define CPU_INTEL_XEON_P4 (1 << CPU_INTEL_XEON_P4_BIT) |
| 146 | #define CPU_INTEL_XEON_MP (1 << CPU_INTEL_XEON_MP_BIT) |
| 147 | |
| 148 | #define CPU_INTEL_PX (CPU_INTEL_P6 | CPU_INTEL_PENTIUM_M) |
| 149 | #define CPU_INTEL_COREX (CPU_INTEL_CORE | CPU_INTEL_CORE2) |
| 150 | #define CPU_INTEL_XEON (CPU_INTEL_XEON_P4 | CPU_INTEL_XEON_MP) |
| 151 | #define CPU_CO_AT (CPU_INTEL_CORE | CPU_INTEL_ATOM) |
| 152 | #define CPU_C2_AT (CPU_INTEL_CORE2 | CPU_INTEL_ATOM) |
| 153 | #define CPU_CX_AT (CPU_INTEL_COREX | CPU_INTEL_ATOM) |
| 154 | #define CPU_CX_XE (CPU_INTEL_COREX | CPU_INTEL_XEON) |
| 155 | #define CPU_P6_XE (CPU_INTEL_P6 | CPU_INTEL_XEON) |
| 156 | #define CPU_PM_CO_AT (CPU_INTEL_PENTIUM_M | CPU_CO_AT) |
| 157 | #define CPU_C2_AT_XE (CPU_C2_AT | CPU_INTEL_XEON) |
| 158 | #define CPU_CX_AT_XE (CPU_CX_AT | CPU_INTEL_XEON) |
| 159 | #define CPU_P6_CX_AT (CPU_INTEL_P6 | CPU_CX_AT) |
| 160 | #define CPU_P6_CX_XE (CPU_P6_XE | CPU_INTEL_COREX) |
| 161 | #define CPU_P6_CX_AT_XE (CPU_INTEL_P6 | CPU_CX_AT_XE) |
| 162 | #define CPU_PM_CX_AT_XE (CPU_INTEL_PENTIUM_M | CPU_CX_AT_XE) |
| 163 | #define CPU_PM_CX_AT (CPU_INTEL_PENTIUM_M | CPU_CX_AT) |
| 164 | #define CPU_PM_CX_XE (CPU_INTEL_PENTIUM_M | CPU_CX_XE) |
| 165 | #define CPU_PX_CX_AT (CPU_INTEL_PX | CPU_CX_AT) |
| 166 | #define CPU_PX_CX_AT_XE (CPU_INTEL_PX | CPU_CX_AT_XE) |
| 167 | |
Jaswinder Singh Rajput | f4c3c4c | 2009-03-13 19:59:26 +0530 | [diff] [blame] | 168 | /* Select all supported Intel CPUs */ |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 169 | #define CPU_INTEL_ALL (CPU_INTEL_PENTIUM | CPU_PX_CX_AT_XE) |
| 170 | |
Jaswinder Singh Rajput | f4c3c4c | 2009-03-13 19:59:26 +0530 | [diff] [blame] | 171 | #define CPU_AMD_K6 (1 << CPU_AMD_K6_BIT) |
| 172 | #define CPU_AMD_K7 (1 << CPU_AMD_K7_BIT) |
| 173 | #define CPU_AMD_K8 (1 << CPU_AMD_K8_BIT) |
| 174 | #define CPU_AMD_0F (1 << CPU_AMD_0F_BIT) |
| 175 | #define CPU_AMD_10 (1 << CPU_AMD_10_BIT) |
| 176 | #define CPU_AMD_11 (1 << CPU_AMD_11_BIT) |
| 177 | |
| 178 | #define CPU_K10_PLUS (CPU_AMD_10 | CPU_AMD_11) |
| 179 | #define CPU_K0F_PLUS (CPU_AMD_0F | CPU_K10_PLUS) |
| 180 | #define CPU_K8_PLUS (CPU_AMD_K8 | CPU_K0F_PLUS) |
| 181 | #define CPU_K7_PLUS (CPU_AMD_K7 | CPU_K8_PLUS) |
| 182 | |
| 183 | /* Select all supported AMD CPUs */ |
| 184 | #define CPU_AMD_ALL (CPU_AMD_K6 | CPU_K7_PLUS) |
| 185 | |
| 186 | /* Select all supported CPUs */ |
| 187 | #define CPU_ALL (CPU_INTEL_ALL | CPU_AMD_ALL) |
| 188 | |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 189 | #define MAX_CPU_FILES 512 |
| 190 | |
| 191 | struct cpu_private { |
| 192 | unsigned cpu; |
| 193 | unsigned type; |
| 194 | unsigned reg; |
| 195 | unsigned file; |
| 196 | }; |
| 197 | |
| 198 | struct cpu_debug_base { |
| 199 | char *name; /* Register name */ |
| 200 | unsigned flag; /* Register flag */ |
Jaswinder Singh Rajput | 91219bc | 2009-03-12 02:37:00 +0530 | [diff] [blame] | 201 | unsigned write; /* Register write flag */ |
| 202 | }; |
| 203 | |
| 204 | /* |
| 205 | * Currently it looks similar to cpu_debug_base but once we add more files |
| 206 | * cpu_file_base will go in different direction |
| 207 | */ |
| 208 | struct cpu_file_base { |
| 209 | char *name; /* Register file name */ |
| 210 | unsigned flag; /* Register file flag */ |
| 211 | unsigned write; /* Register write flag */ |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 212 | }; |
| 213 | |
| 214 | struct cpu_cpuX_base { |
| 215 | struct dentry *dentry; /* Register dentry */ |
| 216 | int init; /* Register index file */ |
| 217 | }; |
| 218 | |
Jaswinder Singh Rajput | 9b779ed | 2009-03-10 15:37:51 +0530 | [diff] [blame] | 219 | struct cpu_debug_range { |
| 220 | unsigned min; /* Register range min */ |
| 221 | unsigned max; /* Register range max */ |
| 222 | unsigned flag; /* Supported flags */ |
| 223 | unsigned model; /* Supported models */ |
| 224 | }; |
| 225 | |
| 226 | #endif /* _ASM_X86_CPU_DEBUG_H */ |