Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 1 | /* |
Tony Lindgren | 670c104 | 2006-04-02 17:46:25 +0100 | [diff] [blame^] | 2 | * linux/arch/arm/mach-omap2/sram.S |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 3 | * |
| 4 | * Omap2 specific functions that need to be run in internal SRAM |
| 5 | * |
| 6 | * (C) Copyright 2004 |
| 7 | * Texas Instruments, <www.ti.com> |
| 8 | * Richard Woodruff <r-woodruff2@ti.com> |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | #include <linux/config.h> |
| 26 | #include <linux/linkage.h> |
| 27 | #include <asm/assembler.h> |
| 28 | #include <asm/arch/io.h> |
| 29 | #include <asm/hardware.h> |
| 30 | |
Tony Lindgren | 670c104 | 2006-04-02 17:46:25 +0100 | [diff] [blame^] | 31 | #include "prcm-regs.h" |
Tony Lindgren | 1dbae81 | 2005-11-10 14:26:51 +0000 | [diff] [blame] | 32 | |
| 33 | #define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP24XX_32KSYNCT_BASE + 0x010) |
| 34 | |
| 35 | #define CM_CLKSEL2_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x544) |
| 36 | #define PRCM_VOLTCTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x050) |
| 37 | #define PRCM_CLKCFG_CTRL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x080) |
| 38 | #define CM_CLKEN_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x500) |
| 39 | #define CM_IDLEST_CKGEN_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x520) |
| 40 | #define CM_CLKSEL1_PLL_V IO_ADDRESS(OMAP24XX_PRCM_BASE + 0x540) |
| 41 | |
| 42 | #define SDRC_DLLA_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x060) |
| 43 | #define SDRC_RFR_CTRL_V IO_ADDRESS(OMAP24XX_SDRC_BASE + 0x0a4) |
| 44 | |
| 45 | .text |
| 46 | |
| 47 | ENTRY(sram_ddr_init) |
| 48 | stmfd sp!, {r0 - r12, lr} @ save registers on stack |
| 49 | |
| 50 | mov r12, r2 @ capture CS1 vs CS0 |
| 51 | mov r8, r3 @ capture force parameter |
| 52 | |
| 53 | /* frequency shift down */ |
| 54 | ldr r2, cm_clksel2_pll @ get address of dpllout reg |
| 55 | mov r3, #0x1 @ value for 1x operation |
| 56 | str r3, [r2] @ go to L1-freq operation |
| 57 | |
| 58 | /* voltage shift down */ |
| 59 | mov r9, #0x1 @ set up for L1 voltage call |
| 60 | bl voltage_shift @ go drop voltage |
| 61 | |
| 62 | /* dll lock mode */ |
| 63 | ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl |
| 64 | ldr r10, [r11] @ get current val |
| 65 | cmp r12, #0x1 @ cs1 base (2422 es2.05/1) |
| 66 | addeq r11, r11, #0x8 @ if cs1 base, move to DLLB |
| 67 | mvn r9, #0x4 @ mask to get clear bit2 |
| 68 | and r10, r10, r9 @ clear bit2 for lock mode. |
| 69 | orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) |
| 70 | orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz |
| 71 | str r10, [r11] @ commit to DLLA_CTRL |
| 72 | bl i_dll_wait @ wait for dll to lock |
| 73 | |
| 74 | /* get dll value */ |
| 75 | add r11, r11, #0x4 @ get addr of status reg |
| 76 | ldr r10, [r11] @ get locked value |
| 77 | |
| 78 | /* voltage shift up */ |
| 79 | mov r9, #0x0 @ shift back to L0-voltage |
| 80 | bl voltage_shift @ go raise voltage |
| 81 | |
| 82 | /* frequency shift up */ |
| 83 | mov r3, #0x2 @ value for 2x operation |
| 84 | str r3, [r2] @ go to L0-freq operation |
| 85 | |
| 86 | /* reset entry mode for dllctrl */ |
| 87 | sub r11, r11, #0x4 @ move from status to ctrl |
| 88 | cmp r12, #0x1 @ normalize if cs1 based |
| 89 | subeq r11, r11, #0x8 @ possibly back to DLLA |
| 90 | cmp r8, #0x1 @ if forced unlock exit |
| 91 | orreq r1, r1, #0x4 @ make sure exit with unlocked value |
| 92 | str r1, [r11] @ restore DLLA_CTRL high value |
| 93 | add r11, r11, #0x8 @ move to DLLB_CTRL addr |
| 94 | str r1, [r11] @ set value DLLB_CTRL |
| 95 | bl i_dll_wait @ wait for possible lock |
| 96 | |
| 97 | /* set up for return, DDR should be good */ |
| 98 | str r10, [r0] @ write dll_status and return counter |
| 99 | ldmfd sp!, {r0 - r12, pc} @ restore regs and return |
| 100 | |
| 101 | /* ensure the DLL has relocked */ |
| 102 | i_dll_wait: |
| 103 | mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks |
| 104 | i_dll_delay: |
| 105 | subs r4, r4, #0x1 |
| 106 | bne i_dll_delay |
| 107 | mov pc, lr |
| 108 | |
| 109 | /* |
| 110 | * shift up or down voltage, use R9 as input to tell level. |
| 111 | * wait for it to finish, use 32k sync counter, 1tick=31uS. |
| 112 | */ |
| 113 | voltage_shift: |
| 114 | ldr r4, prcm_voltctrl @ get addr of volt ctrl. |
| 115 | ldr r5, [r4] @ get value. |
| 116 | ldr r6, prcm_mask_val @ get value of mask |
| 117 | and r5, r5, r6 @ apply mask to clear bits |
| 118 | orr r5, r5, r9 @ bulld value for L0/L1-volt operation. |
| 119 | str r5, [r4] @ set up for change. |
| 120 | mov r3, #0x4000 @ get val for force |
| 121 | orr r5, r5, r3 @ build value for force |
| 122 | str r5, [r4] @ Force transition to L1 |
| 123 | |
| 124 | ldr r3, timer_32ksynct_cr @ get addr of counter |
| 125 | ldr r5, [r3] @ get value |
| 126 | add r5, r5, #0x3 @ give it at most 93uS |
| 127 | volt_delay: |
| 128 | ldr r7, [r3] @ get timer value |
| 129 | cmp r5, r7 @ time up? |
| 130 | bhi volt_delay @ not yet->branch |
| 131 | mov pc, lr @ back to caller. |
| 132 | |
| 133 | /* relative load constants */ |
| 134 | cm_clksel2_pll: |
| 135 | .word CM_CLKSEL2_PLL_V |
| 136 | sdrc_dlla_ctrl: |
| 137 | .word SDRC_DLLA_CTRL_V |
| 138 | prcm_voltctrl: |
| 139 | .word PRCM_VOLTCTRL_V |
| 140 | prcm_mask_val: |
| 141 | .word 0xFFFF3FFC |
| 142 | timer_32ksynct_cr: |
| 143 | .word TIMER_32KSYNCT_CR_V |
| 144 | ENTRY(sram_ddr_init_sz) |
| 145 | .word . - sram_ddr_init |
| 146 | |
| 147 | /* |
| 148 | * Reprograms memory timings. |
| 149 | * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] |
| 150 | * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 |
| 151 | */ |
| 152 | ENTRY(sram_reprogram_sdrc) |
| 153 | stmfd sp!, {r0 - r10, lr} @ save registers on stack |
| 154 | mov r3, #0x0 @ clear for mrc call |
| 155 | mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR |
| 156 | nop |
| 157 | nop |
| 158 | ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg |
| 159 | ldr r5, [r6] @ get value |
| 160 | mov r5, r5, lsr #8 @ isolate rfr field and drop burst |
| 161 | |
| 162 | cmp r0, #0x1 @ going to half speed? |
| 163 | movne r9, #0x0 @ if up set flag up for pre up, hi volt |
| 164 | |
| 165 | blne voltage_shift_c @ adjust voltage |
| 166 | |
| 167 | cmp r0, #0x1 @ going to half speed (post branch link) |
| 168 | moveq r5, r5, lsr #1 @ divide by 2 if to half |
| 169 | movne r5, r5, lsl #1 @ mult by 2 if to full |
| 170 | mov r5, r5, lsl #8 @ put rfr field back into place |
| 171 | add r5, r5, #0x1 @ turn on burst of 1 |
| 172 | ldr r4, ddr_cm_clksel2_pll @ get address of out reg |
| 173 | ldr r3, [r4] @ get curr value |
| 174 | orr r3, r3, #0x3 |
| 175 | bic r3, r3, #0x3 @ clear lower bits |
| 176 | orr r3, r3, r0 @ new state value |
| 177 | str r3, [r4] @ set new state (pll/x, x=1 or 2) |
| 178 | nop |
| 179 | nop |
| 180 | |
| 181 | moveq r9, #0x1 @ if speed down, post down, drop volt |
| 182 | bleq voltage_shift_c |
| 183 | |
| 184 | mcr p15, 0, r3, c7, c10, 4 @ memory barrier |
| 185 | str r5, [r6] @ set new RFR_1 value |
| 186 | add r6, r6, #0x30 @ get RFR_2 addr |
| 187 | str r5, [r6] @ set RFR_2 |
| 188 | nop |
| 189 | cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL |
| 190 | bne freq_out @ leave if SDR, no DLL function |
| 191 | |
| 192 | /* With DDR, we need to take care of the DLL for the frequency change */ |
| 193 | ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl |
| 194 | str r1, [r2] @ write out new SDRC_DLLA_CTRL |
| 195 | add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL |
| 196 | str r1, [r2] @ commit to SDRC_DLLB_CTRL |
| 197 | mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks |
| 198 | dll_wait: |
| 199 | subs r1, r1, #0x1 |
| 200 | bne dll_wait |
| 201 | freq_out: |
| 202 | ldmfd sp!, {r0 - r10, pc} @ restore regs and return |
| 203 | |
| 204 | /* |
| 205 | * shift up or down voltage, use R9 as input to tell level. |
| 206 | * wait for it to finish, use 32k sync counter, 1tick=31uS. |
| 207 | */ |
| 208 | voltage_shift_c: |
| 209 | ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl |
| 210 | ldr r8, [r10] @ get value |
| 211 | ldr r7, ddr_prcm_mask_val @ get value of mask |
| 212 | and r8, r8, r7 @ apply mask to clear bits |
| 213 | orr r8, r8, r9 @ bulld value for L0/L1-volt operation. |
| 214 | str r8, [r10] @ set up for change. |
| 215 | mov r7, #0x4000 @ get val for force |
| 216 | orr r8, r8, r7 @ build value for force |
| 217 | str r8, [r10] @ Force transition to L1 |
| 218 | |
| 219 | ldr r10, ddr_timer_32ksynct @ get addr of counter |
| 220 | ldr r8, [r10] @ get value |
| 221 | add r8, r8, #0x2 @ give it at most 62uS (min 31+) |
| 222 | volt_delay_c: |
| 223 | ldr r7, [r10] @ get timer value |
| 224 | cmp r8, r7 @ time up? |
| 225 | bhi volt_delay_c @ not yet->branch |
| 226 | mov pc, lr @ back to caller |
| 227 | |
| 228 | ddr_cm_clksel2_pll: |
| 229 | .word CM_CLKSEL2_PLL_V |
| 230 | ddr_sdrc_dlla_ctrl: |
| 231 | .word SDRC_DLLA_CTRL_V |
| 232 | ddr_sdrc_rfr_ctrl: |
| 233 | .word SDRC_RFR_CTRL_V |
| 234 | ddr_prcm_voltctrl: |
| 235 | .word PRCM_VOLTCTRL_V |
| 236 | ddr_prcm_mask_val: |
| 237 | .word 0xFFFF3FFC |
| 238 | ddr_timer_32ksynct: |
| 239 | .word TIMER_32KSYNCT_CR_V |
| 240 | |
| 241 | ENTRY(sram_reprogram_sdrc_sz) |
| 242 | .word . - sram_reprogram_sdrc |
| 243 | |
| 244 | /* |
| 245 | * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. |
| 246 | */ |
| 247 | ENTRY(sram_set_prcm) |
| 248 | stmfd sp!, {r0-r12, lr} @ regs to stack |
| 249 | adr r4, pbegin @ addr of preload start |
| 250 | adr r8, pend @ addr of preload end |
| 251 | mcrr p15, 1, r8, r4, c12 @ preload into icache |
| 252 | pbegin: |
| 253 | /* move into fast relock bypass */ |
| 254 | ldr r8, pll_ctl @ get addr |
| 255 | ldr r5, [r8] @ get val |
| 256 | mvn r6, #0x3 @ clear mask |
| 257 | and r5, r5, r6 @ clear field |
| 258 | orr r7, r5, #0x2 @ fast relock val |
| 259 | str r7, [r8] @ go to fast relock |
| 260 | ldr r4, pll_stat @ addr of stat |
| 261 | block: |
| 262 | /* wait for bypass */ |
| 263 | ldr r8, [r4] @ stat value |
| 264 | and r8, r8, #0x3 @ mask for stat |
| 265 | cmp r8, #0x1 @ there yet |
| 266 | bne block @ loop if not |
| 267 | |
| 268 | /* set new dpll dividers _after_ in bypass */ |
| 269 | ldr r4, pll_div @ get addr |
| 270 | str r0, [r4] @ set dpll ctrl val |
| 271 | |
| 272 | ldr r4, set_config @ get addr |
| 273 | mov r8, #1 @ valid cfg msk |
| 274 | str r8, [r4] @ make dividers take |
| 275 | |
| 276 | mov r4, #100 @ dead spin a bit |
| 277 | wait_a_bit: |
| 278 | subs r4, r4, #1 @ dec loop |
| 279 | bne wait_a_bit @ delay done? |
| 280 | |
| 281 | /* check if staying in bypass */ |
| 282 | cmp r2, #0x1 @ stay in bypass? |
| 283 | beq pend @ jump over dpll relock |
| 284 | |
| 285 | /* relock DPLL with new vals */ |
| 286 | ldr r5, pll_stat @ get addr |
| 287 | ldr r4, pll_ctl @ get addr |
| 288 | orr r8, r7, #0x3 @ val for lock dpll |
| 289 | str r8, [r4] @ set val |
| 290 | mov r0, #1000 @ dead spin a bit |
| 291 | wait_more: |
| 292 | subs r0, r0, #1 @ dec loop |
| 293 | bne wait_more @ delay done? |
| 294 | wait_lock: |
| 295 | ldr r8, [r5] @ get lock val |
| 296 | and r8, r8, #3 @ isolate field |
| 297 | cmp r8, #2 @ locked? |
| 298 | bne wait_lock @ wait if not |
| 299 | pend: |
| 300 | /* update memory timings & briefly lock dll */ |
| 301 | ldr r4, sdrc_rfr @ get addr |
| 302 | str r1, [r4] @ update refresh timing |
| 303 | ldr r11, dlla_ctrl @ get addr of DLLA ctrl |
| 304 | ldr r10, [r11] @ get current val |
| 305 | mvn r9, #0x4 @ mask to get clear bit2 |
| 306 | and r10, r10, r9 @ clear bit2 for lock mode |
| 307 | orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos) |
| 308 | str r10, [r11] @ commit to DLLA_CTRL |
| 309 | add r11, r11, #0x8 @ move to dllb |
| 310 | str r10, [r11] @ hit DLLB also |
| 311 | |
| 312 | mov r4, #0x800 @ relock time (min 0x400 L3 clocks) |
| 313 | wait_dll_lock: |
| 314 | subs r4, r4, #0x1 |
| 315 | bne wait_dll_lock |
| 316 | nop |
| 317 | ldmfd sp!, {r0-r12, pc} @ restore regs and return |
| 318 | |
| 319 | set_config: |
| 320 | .word PRCM_CLKCFG_CTRL_V |
| 321 | pll_ctl: |
| 322 | .word CM_CLKEN_PLL_V |
| 323 | pll_stat: |
| 324 | .word CM_IDLEST_CKGEN_V |
| 325 | pll_div: |
| 326 | .word CM_CLKSEL1_PLL_V |
| 327 | sdrc_rfr: |
| 328 | .word SDRC_RFR_CTRL_V |
| 329 | dlla_ctrl: |
| 330 | .word SDRC_DLLA_CTRL_V |
| 331 | |
| 332 | ENTRY(sram_set_prcm_sz) |
| 333 | .word . - sram_set_prcm |