Blame - drivers/dma/Kconfig - kernel/msm-4.9

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Chris Leech	c13c826	2006-05-23 17:18:44 -0700	[diff] [blame]	1	#
				2	# DMA engine configuration
				3	#
				4
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	5	menuconfig DMADEVICES
Haavard Skinnemoen	6d4f587	2007-11-28 16:21:43 -0800	[diff] [blame]	6	bool "DMA Engine support"
Dan Williams	04ce9ab	2009-06-03 14:22:28 -0700	[diff] [blame]	7	depends on HAS_DMA
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	8	help
Haavard Skinnemoen	6d4f587	2007-11-28 16:21:43 -0800	[diff] [blame]	9	DMA engines can do asynchronous data transfers without
				10	involving the host CPU. Currently, this framework can be
				11	used to offload memory copies in the network stack and
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	12	RAID operations in the MD driver. This menu only presents
				13	DMA Device drivers supported by the configured arch, it may
				14	be empty in some cases.
Chris Leech	c13c826	2006-05-23 17:18:44 -0700	[diff] [blame]	15
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	16	if DMADEVICES
Chris Leech	db21733	2006-06-17 21:24:58 -0700	[diff] [blame]	17
Chris Leech	0bbd5f4	2006-05-23 17:35:34 -0700	[diff] [blame]	18	comment "DMA Devices"
				19
Dan Williams	138f4c3	2009-09-08 17:42:51 -0700	[diff] [blame]	20	config ASYNC_TX_DISABLE_CHANNEL_SWITCH
				21	bool
				22
Chris Leech	0bbd5f4	2006-05-23 17:35:34 -0700	[diff] [blame]	23	config INTEL_IOATDMA
				24	tristate "Intel I/OAT DMA support"
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	25	depends on PCI && X86
				26	select DMA_ENGINE
				27	select DCA
Dan Williams	138f4c3	2009-09-08 17:42:51 -0700	[diff] [blame]	28	select ASYNC_TX_DISABLE_CHANNEL_SWITCH
Dan Williams	7b3cc2b	2009-11-19 17:10:37 -0700	[diff] [blame]	29	select ASYNC_TX_DISABLE_PQ_VAL_DMA
				30	select ASYNC_TX_DISABLE_XOR_VAL_DMA
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	31	help
				32	Enable support for the Intel(R) I/OAT DMA engine present
				33	in recent Intel Xeon chipsets.
				34
				35	Say Y here if you have such a chipset.
				36
				37	If unsure, say N.
Dan Williams	c211092	2007-01-02 13:52:26 -0700	[diff] [blame]	38
				39	config INTEL_IOP_ADMA
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	40	tristate "Intel IOP ADMA support"
				41	depends on ARCH_IOP32X \|\| ARCH_IOP33X \|\| ARCH_IOP13XX
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	42	select DMA_ENGINE
				43	help
				44	Enable support for the Intel(R) IOP Series RAID engines.
Dan Williams	c211092	2007-01-02 13:52:26 -0700	[diff] [blame]	45
Haavard Skinnemoen	3bfb1d2	2008-07-08 11:59:42 -0700	[diff] [blame]	46	config DW_DMAC
				47	tristate "Synopsys DesignWare AHB DMA support"
				48	depends on AVR32
				49	select DMA_ENGINE
				50	default y if CPU_AT32AP7000
				51	help
				52	Support the Synopsys DesignWare AHB DMA controller. This
				53	can be integrated in chips such as the Atmel AT32ap7000.
				54
Nicolas Ferre	dc78baa	2009-07-03 19:24:33 +0200	[diff] [blame]	55	config AT_HDMAC
				56	tristate "Atmel AHB DMA support"
Yegor Yefremov	cd3abf9	2009-10-23 11:27:59 +0100	[diff] [blame]	57	depends on ARCH_AT91SAM9RL \|\| ARCH_AT91SAM9G45
Nicolas Ferre	dc78baa	2009-07-03 19:24:33 +0200	[diff] [blame]	58	select DMA_ENGINE
				59	help
				60	Support the Atmel AHB DMA controller. This can be integrated in
				61	chips such as the Atmel AT91SAM9RL.
				62
Zhang Wei	173acc7	2008-03-01 07:42:48 -0700	[diff] [blame]	63	config FSL_DMA
Timur Tabi	77cd62e	2008-09-26 17:00:11 -0700	[diff] [blame]	64	tristate "Freescale Elo and Elo Plus DMA support"
				65	depends on FSL_SOC
Zhang Wei	173acc7	2008-03-01 07:42:48 -0700	[diff] [blame]	66	select DMA_ENGINE
				67	---help---
Timur Tabi	77cd62e	2008-09-26 17:00:11 -0700	[diff] [blame]	68	Enable support for the Freescale Elo and Elo Plus DMA controllers.
				69	The Elo is the DMA controller on some 82xx and 83xx parts, and the
				70	Elo Plus is the DMA controller on 85xx and 86xx parts.
Zhang Wei	173acc7	2008-03-01 07:42:48 -0700	[diff] [blame]	71
Saeed Bishara	ff7b047	2008-07-08 11:58:36 -0700	[diff] [blame]	72	config MV_XOR
				73	bool "Marvell XOR engine support"
				74	depends on PLAT_ORION
Saeed Bishara	ff7b047	2008-07-08 11:58:36 -0700	[diff] [blame]	75	select DMA_ENGINE
				76	---help---
				77	Enable support for the Marvell XOR engine.
				78
Guennadi Liakhovetski	5296b56	2009-01-19 15:36:21 -0700	[diff] [blame]	79	config MX3_IPU
				80	bool "MX3x Image Processing Unit support"
				81	depends on ARCH_MX3
				82	select DMA_ENGINE
				83	default y
				84	help
				85	If you plan to use the Image Processing unit in the i.MX3x, say
				86	Y here. If unsure, select Y.
				87
				88	config MX3_IPU_IRQS
				89	int "Number of dynamically mapped interrupts for IPU"
				90	depends on MX3_IPU
				91	range 2 137
				92	default 4
				93	help
				94	Out of 137 interrupt sources on i.MX31 IPU only very few are used.
				95	To avoid bloating the irq_desc[] array we allocate a sufficient
				96	number of IRQ slots and map them dynamically to specific sources.
				97
Atsushi Nemoto	ea76f0b	2009-04-23 00:40:30 +0900	[diff] [blame]	98	config TXX9_DMAC
				99	tristate "Toshiba TXx9 SoC DMA support"
				100	depends on MACH_TX49XX \|\| MACH_TX39XX
				101	select DMA_ENGINE
				102	help
				103	Support the TXx9 SoC internal DMA controller. This can be
				104	integrated in chips such as the Toshiba TX4927/38/39.
				105
Nobuhiro Iwamatsu	d8902ad	2009-09-07 03:26:23 +0000	[diff] [blame]	106	config SH_DMAE
				107	tristate "Renesas SuperH DMAC support"
				108	depends on SUPERH && SH_DMA
				109	depends on !SH_DMA_API
				110	select DMA_ENGINE
				111	help
				112	Enable support for the Renesas SuperH DMA controllers.
				113
Linus Walleij	61f135b	2009-11-19 19:49:17 +0100	[diff] [blame]	114	config COH901318
				115	bool "ST-Ericsson COH901318 DMA support"
				116	select DMA_ENGINE
				117	depends on ARCH_U300
				118	help
				119	Enable support for ST-Ericsson COH 901 318 DMA.
				120
Anatolij Gustschin	12458ea	2009-12-11 21:24:44 -0700	[diff] [blame]	121	config AMCC_PPC440SPE_ADMA
				122	tristate "AMCC PPC440SPe ADMA support"
				123	depends on 440SPe \|\| 440SP
				124	select DMA_ENGINE
				125	select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
				126	help
				127	Enable support for the AMCC PPC440SPe RAID engines.
				128
				129	config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
				130	bool
				131
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	132	config DMA_ENGINE
				133	bool
				134
				135	comment "DMA Clients"
				136	depends on DMA_ENGINE
				137
				138	config NET_DMA
				139	bool "Network: TCP receive copy offload"
				140	depends on DMA_ENGINE && NET
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	141	default (INTEL_IOATDMA \|\| FSL_DMA)
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	142	help
				143	This enables the use of DMA engines in the network stack to
				144	offload receive copy-to-user operations, freeing CPU cycles.
Dan Williams	9c402f4	2008-06-27 01:21:11 -0700	[diff] [blame]	145
				146	Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise
				147	say N.
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	148
Dan Williams	729b5d1	2009-03-25 09:13:25 -0700	[diff] [blame]	149	config ASYNC_TX_DMA
				150	bool "Async_tx: Offload support for the async_tx api"
Dan Williams	9a8de63	2009-09-08 15:06:10 -0700	[diff] [blame]	151	depends on DMA_ENGINE
Dan Williams	729b5d1	2009-03-25 09:13:25 -0700	[diff] [blame]	152	help
				153	This allows the async_tx api to take advantage of offload engines for
				154	memcpy, memset, xor, and raid6 p+q operations. If your platform has
				155	a dma engine that can perform raid operations and you have enabled
				156	MD_RAID456 say Y.
				157
				158	If unsure, say N.
				159
Haavard Skinnemoen	4a776f0	2008-07-08 11:58:45 -0700	[diff] [blame]	160	config DMATEST
				161	tristate "DMA Test client"
				162	depends on DMA_ENGINE
				163	help
				164	Simple DMA test client. Say N unless you're debugging a
				165	DMA Device driver.
				166
Shannon Nelson	2ed6dc3	2007-10-16 01:27:42 -0700	[diff] [blame]	167	endif