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gerrit-public.fairphone.software / kernel / msm-4.9 / 678382be2693ee7d3bfa8dcb893974717ed0e92d / . / drivers / clk / msm / clock-gcc-8952.c
blob: 2e87df12369f4477f1978b84d6359f2c14cc18b2 [file] [log] [blame]
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]1/*
2 * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/err.h>
17#include <linux/ctype.h>
18#include <linux/io.h>
19#include <linux/spinlock.h>
20#include <linux/clk.h>
21#include <linux/regulator/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <soc/qcom/clock-local2.h>
27#include <soc/qcom/clock-pll.h>
28#include <soc/qcom/clock-alpha-pll.h>
29#include <soc/qcom/clock-voter.h>
30#include <soc/qcom/rpm-smd.h>
31#include <soc/qcom/clock-rpm.h>
32
33#include <linux/clk/msm-clock-generic.h>
34#include <linux/regulator/rpm-smd-regulator.h>
35
36#include <dt-bindings/clock/msm-clocks-8952.h>
37#include <dt-bindings/clock/msm-clocks-hwio-8952.h>
38
39#include "clock.h"
40#include "reset.h"
41
42enum {
43 GCC_BASE,
44 APCS_C1_PLL_BASE,
45 APCS_C0_PLL_BASE,
46 APCS_CCI_PLL_BASE,
47 N_BASES,
48};
49
50static void __iomem *virt_bases[N_BASES];
51#define GCC_REG_BASE(x) (void __iomem *)(virt_bases[GCC_BASE] + (x))
52
53static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
54
55/* SMD clocks */
56DEFINE_CLK_RPM_SMD_BRANCH(xo_clk_src, xo_a_clk_src, RPM_MISC_CLK_TYPE,
57 CXO_CLK_SRC_ID, 19200000);
58DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
59DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
60DEFINE_CLK_RPM_SMD(bimc_gpu_clk, bimc_gpu_a_clk, RPM_MEM_CLK_TYPE,
61 BIMC_GPU_CLK_ID, NULL);
62DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
63DEFINE_CLK_RPM_SMD(sysmmnoc_clk, sysmmnoc_a_clk, RPM_BUS_CLK_TYPE,
64 SYSMMNOC_CLK_ID, NULL);
65DEFINE_CLK_RPM_SMD(ipa_clk, ipa_a_clk, RPM_IPA_CLK_TYPE, IPA_CLK_ID, NULL);
66DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE, QDSS_CLK_ID);
67
68/* SMD_XO_BUFFER */
69DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk1, bb_clk1_a, BB_CLK1_ID);
70DEFINE_CLK_RPM_SMD_XO_BUFFER(bb_clk2, bb_clk2_a, BB_CLK2_ID);
71DEFINE_CLK_RPM_SMD_XO_BUFFER(rf_clk2, rf_clk2_a, RF_CLK2_ID);
72DEFINE_CLK_RPM_SMD_XO_BUFFER(div_clk2, div_clk2_a, DIV_CLK2_ID);
73
74DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk1_pin, bb_clk1_a_pin, BB_CLK1_ID);
75DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(bb_clk2_pin, bb_clk2_a_pin, BB_CLK2_ID);
76
77/* Voter clocks */
78static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
79static DEFINE_CLK_VOTER(snoc_msmbus_clk, &snoc_clk.c, LONG_MAX);
80static DEFINE_CLK_VOTER(sysmmnoc_msmbus_clk, &sysmmnoc_clk.c, LONG_MAX);
81static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
82
83static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
84static DEFINE_CLK_VOTER(snoc_msmbus_a_clk, &snoc_a_clk.c, LONG_MAX);
85static DEFINE_CLK_VOTER(sysmmnoc_msmbus_a_clk, &sysmmnoc_a_clk.c, LONG_MAX);
86static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
87static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
88
89static DEFINE_CLK_VOTER(pnoc_usb_a_clk, &pnoc_a_clk.c, LONG_MAX);
90static DEFINE_CLK_VOTER(snoc_usb_a_clk, &snoc_a_clk.c, LONG_MAX);
91static DEFINE_CLK_VOTER(bimc_usb_a_clk, &bimc_a_clk.c, LONG_MAX);
92
93static DEFINE_CLK_VOTER(pnoc_usb_clk, &pnoc_clk.c, LONG_MAX);
94static DEFINE_CLK_VOTER(snoc_usb_clk, &snoc_clk.c, LONG_MAX);
95static DEFINE_CLK_VOTER(bimc_usb_clk, &bimc_clk.c, LONG_MAX);
96
97static DEFINE_CLK_VOTER(snoc_wcnss_a_clk, &snoc_a_clk.c, LONG_MAX);
98static DEFINE_CLK_VOTER(bimc_wcnss_a_clk, &bimc_a_clk.c, LONG_MAX);
99
100/* Branch Voter clocks */
101static DEFINE_CLK_BRANCH_VOTER(xo_gcc, &xo_clk_src.c);
102static DEFINE_CLK_BRANCH_VOTER(xo_otg_clk, &xo_clk_src.c);
103static DEFINE_CLK_BRANCH_VOTER(xo_lpm_clk, &xo_clk_src.c);
104static DEFINE_CLK_BRANCH_VOTER(xo_pil_pronto_clk, &xo_clk_src.c);
105static DEFINE_CLK_BRANCH_VOTER(xo_pil_mss_clk, &xo_clk_src.c);
106static DEFINE_CLK_BRANCH_VOTER(xo_wlan_clk, &xo_clk_src.c);
107static DEFINE_CLK_BRANCH_VOTER(xo_pil_lpass_clk, &xo_clk_src.c);
108
109DEFINE_CLK_DUMMY(wcnss_m_clk, 0);
110
111enum vdd_sr2_pll_levels {
112 VDD_SR2_PLL_OFF,
113 VDD_SR2_PLL_SVS,
114 VDD_SR2_PLL_NOM,
115 VDD_SR2_PLL_TUR,
116 VDD_SR2_PLL_SUPER_TUR,
117 VDD_SR2_PLL_NUM,
118};
119
120static int vdd_sr2_levels[] = {
121 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_SR2_PLL_OFF */
122 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_SR2_PLL_SVS */
123 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_SR2_PLL_NOM */
124 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_SR2_PLL_TUR */
125 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_SR2_PLL_SUPER_TUR */
126};
127
128static DEFINE_VDD_REGULATORS(vdd_sr2_pll, VDD_SR2_PLL_NUM, 2,
129 vdd_sr2_levels, NULL);
130
131enum vdd_hf_pll_levels {
132 VDD_HF_PLL_OFF,
133 VDD_HF_PLL_SVS,
134 VDD_HF_PLL_NOM,
135 VDD_HF_PLL_TUR,
136 VDD_HF_PLL_SUPER_TUR,
137 VDD_HF_PLL_NUM,
138};
139
140static int vdd_hf_levels[] = {
141 0, RPM_REGULATOR_LEVEL_NONE, /* VDD_HF_PLL_OFF */
142 1800000, RPM_REGULATOR_LEVEL_SVS, /* VDD_HF_PLL_SVS */
143 1800000, RPM_REGULATOR_LEVEL_NOM, /* VDD_HF_PLL_NOM */
144 1800000, RPM_REGULATOR_LEVEL_TURBO, /* VDD_HF_PLL_TUR */
145 1800000, RPM_REGULATOR_LEVEL_BINNING, /* VDD_HF_PLL_SUPER_TUR */
146};
147static DEFINE_VDD_REGULATORS(vdd_hf_pll, VDD_HF_PLL_NUM, 2,
148 vdd_hf_levels, NULL);
149
150static struct pll_freq_tbl apcs_cci_pll_freq[] = {
151 F_APCS_PLL(307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
152 F_APCS_PLL(600000000, 31, 0x1, 0x4, 0x0, 0x0, 0x0),
153};
154
155static struct pll_clk a53ss_cci_pll = {
156 .mode_reg = (void __iomem *)APCS_CCI_PLL_MODE,
157 .l_reg = (void __iomem *)APCS_CCI_PLL_L_VAL,
158 .m_reg = (void __iomem *)APCS_CCI_PLL_M_VAL,
159 .n_reg = (void __iomem *)APCS_CCI_PLL_N_VAL,
160 .config_reg = (void __iomem *)APCS_CCI_PLL_USER_CTL,
161 .status_reg = (void __iomem *)APCS_CCI_PLL_STATUS,
162 .freq_tbl = apcs_cci_pll_freq,
163 .masks = {
164 .vco_mask = BM(29, 28),
165 .pre_div_mask = BIT(12),
166 .post_div_mask = BM(9, 8),
167 .mn_en_mask = BIT(24),
168 .main_output_mask = BIT(0),
169 },
170 .base = &virt_bases[APCS_CCI_PLL_BASE],
171 .spm_ctrl = {
172 .offset = 0x40,
173 .event_bit = 0x0,
174 },
175 .c = {
176 .parent = &xo_a_clk_src.c,
177 .dbg_name = "a53ss_cci_pll",
178 .ops = &clk_ops_sr2_pll,
179 .vdd_class = &vdd_sr2_pll,
180 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
181 [VDD_SR2_PLL_SVS] = 1000000000,
182 [VDD_SR2_PLL_NOM] = 1900000000,
183 },
184 .num_fmax = VDD_SR2_PLL_NUM,
185 CLK_INIT(a53ss_cci_pll.c),
186 },
187};
188
189static struct pll_freq_tbl apcs_c0_pll_freq[] = {
190 F_APCS_PLL( 249600000, 13, 0x0, 0x1, 0x0, 0x0, 0x0),
191 F_APCS_PLL( 307200000, 16, 0x0, 0x1, 0x0, 0x0, 0x0),
192 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
193 F_APCS_PLL( 384000000, 20, 0x0, 0x1, 0x0, 0x0, 0x0),
194 F_APCS_PLL( 460800000, 24, 0x0, 0x1, 0x0, 0x0, 0x0),
195 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
196 F_APCS_PLL( 518400000, 27, 0x0, 0x1, 0x0, 0x0, 0x0),
197 F_APCS_PLL( 768000000, 40, 0x0, 0x1, 0x0, 0x0, 0x0),
198 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
199 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
200 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
201 F_APCS_PLL( 902400000, 47, 0x0, 0x1, 0x0, 0x0, 0x0),
202 F_APCS_PLL( 921600000, 48, 0x0, 0x1, 0x0, 0x0, 0x0),
203 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
204 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]205 F_APCS_PLL(1171200000, 61, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]206 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]207 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
208 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]209};
210
211static struct pll_clk a53ss_c0_pll = {
212 .mode_reg = (void __iomem *)APCS_C0_PLL_MODE,
213 .l_reg = (void __iomem *)APCS_C0_PLL_L_VAL,
214 .m_reg = (void __iomem *)APCS_C0_PLL_M_VAL,
215 .n_reg = (void __iomem *)APCS_C0_PLL_N_VAL,
216 .config_reg = (void __iomem *)APCS_C0_PLL_USER_CTL,
217 .status_reg = (void __iomem *)APCS_C0_PLL_STATUS,
218 .freq_tbl = apcs_c0_pll_freq,
219 .masks = {
220 .vco_mask = BM(29, 28),
221 .pre_div_mask = BIT(12),
222 .post_div_mask = BM(9, 8),
223 .mn_en_mask = BIT(24),
224 .main_output_mask = BIT(0),
225 },
226 .base = &virt_bases[APCS_C0_PLL_BASE],
227 .spm_ctrl = {
228 .offset = 0x50,
229 .event_bit = 0x4,
230 },
231 .c = {
232 .parent = &xo_a_clk_src.c,
233 .dbg_name = "a53ss_c0_pll",
234 .ops = &clk_ops_sr2_pll,
235 .vdd_class = &vdd_sr2_pll,
236 .fmax = (unsigned long [VDD_SR2_PLL_NUM]) {
237 [VDD_SR2_PLL_SVS] = 1000000000,
238 [VDD_SR2_PLL_NOM] = 1900000000,
239 },
240 .num_fmax = VDD_SR2_PLL_NUM,
241 CLK_INIT(a53ss_c0_pll.c),
242 },
243};
244
245static struct pll_freq_tbl apcs_c1_pll_freq[] = {
246 F_APCS_PLL( 345600000, 18, 0x0, 0x1, 0x0, 0x0, 0x0),
247 F_APCS_PLL( 422400000, 22, 0x0, 0x1, 0x0, 0x0, 0x0),
248 F_APCS_PLL( 499200000, 26, 0x0, 0x1, 0x0, 0x0, 0x0),
249 F_APCS_PLL( 652800000, 34, 0x0, 0x1, 0x0, 0x0, 0x0),
250 F_APCS_PLL( 729600000, 38, 0x0, 0x1, 0x0, 0x0, 0x0),
251 F_APCS_PLL( 806400000, 42, 0x0, 0x1, 0x0, 0x0, 0x0),
252 F_APCS_PLL( 844800000, 44, 0x0, 0x1, 0x0, 0x0, 0x0),
253 F_APCS_PLL( 883200000, 46, 0x0, 0x1, 0x0, 0x0, 0x0),
254 F_APCS_PLL( 960000000, 50, 0x0, 0x1, 0x0, 0x0, 0x0),
255 F_APCS_PLL( 998400000, 52, 0x0, 0x1, 0x0, 0x0, 0x0),
256 F_APCS_PLL(1036800000, 54, 0x0, 0x1, 0x0, 0x0, 0x0),
257 F_APCS_PLL(1094400000, 57, 0x0, 0x1, 0x0, 0x0, 0x0),
258 F_APCS_PLL(1113600000, 58, 0x0, 0x1, 0x0, 0x0, 0x0),
259 F_APCS_PLL(1190400000, 62, 0x0, 0x1, 0x0, 0x0, 0x0),
260 F_APCS_PLL(1209600000, 63, 0x0, 0x1, 0x0, 0x0, 0x0),
261 F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
262 F_APCS_PLL(1267200000, 66, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]263 F_APCS_PLL(1305600000, 68, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]264 F_APCS_PLL(1344000000, 70, 0x0, 0x1, 0x0, 0x0, 0x0),
265 F_APCS_PLL(1401000000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
266 F_APCS_PLL(1420800000, 74, 0x0, 0x1, 0x0, 0x0, 0x0),
267 F_APCS_PLL(1440000000, 75, 0x0, 0x1, 0x0, 0x0, 0x0),
268 F_APCS_PLL(1459200000, 76, 0x0, 0x1, 0x0, 0x0, 0x0),
269 F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
270 F_APCS_PLL(1516800000, 79, 0x0, 0x1, 0x0, 0x0, 0x0),
271 F_APCS_PLL(1536000000, 80, 0x0, 0x1, 0x0, 0x0, 0x0),
272 F_APCS_PLL(1651200000, 86, 0x0, 0x1, 0x0, 0x0, 0x0),
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]273 F_APCS_PLL(1708800000, 89, 0x0, 0x1, 0x0, 0x0, 0x0),
274 F_APCS_PLL(1804800000, 94, 0x0, 0x1, 0x0, 0x0, 0x0),
275 F_APCS_PLL(1958400000, 102, 0x0, 0x1, 0x0, 0x0, 0x0),
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]276};
277
278static struct pll_clk a53ss_c1_pll = {
279 .mode_reg = (void __iomem *)APCS_C1_PLL_MODE,
280 .l_reg = (void __iomem *)APCS_C1_PLL_L_VAL,
281 .m_reg = (void __iomem *)APCS_C1_PLL_M_VAL,
282 .n_reg = (void __iomem *)APCS_C1_PLL_N_VAL,
283 .config_reg = (void __iomem *)APCS_C1_PLL_USER_CTL,
284 .status_reg = (void __iomem *)APCS_C1_PLL_STATUS,
285 .freq_tbl = apcs_c1_pll_freq,
286 .masks = {
287 .vco_mask = BM(29, 28),
288 .pre_div_mask = BIT(12),
289 .post_div_mask = BM(9, 8),
290 .mn_en_mask = BIT(24),
291 .main_output_mask = BIT(0),
292 },
293 .base = &virt_bases[APCS_C1_PLL_BASE],
294 .spm_ctrl = {
295 .offset = 0x50,
296 .event_bit = 0x4,
297 },
298 .c = {
299 .parent = &xo_a_clk_src.c,
300 .dbg_name = "a53ss_c1_pll",
301 .ops = &clk_ops_sr2_pll,
302 .vdd_class = &vdd_hf_pll,
303 .fmax = (unsigned long [VDD_HF_PLL_NUM]) {
304 [VDD_HF_PLL_SVS] = 1000000000,
305 [VDD_HF_PLL_NOM] = 2000000000,
306 },
307 .num_fmax = VDD_HF_PLL_NUM,
308 CLK_INIT(a53ss_c1_pll.c),
309 },
310};
311
312static struct pll_vote_clk gpll0_sleep_clk_src = {
313 .en_reg = (void __iomem *)APCS_CLOCK_SLEEP_ENA_VOTE,
314 .en_mask = BIT(23),
315 .status_reg = (void __iomem *)GPLL0_MODE,
316 .status_mask = BIT(30),
317 .base = &virt_bases[GCC_BASE],
318 .c = {
319 .parent = &xo_clk_src.c,
320 .rate = 800000000,
321 .dbg_name = "gpll0_sleep_clk_src",
322 .ops = &clk_ops_pll_sleep_vote,
323 CLK_INIT(gpll0_sleep_clk_src.c),
324 },
325};
326
327static unsigned int soft_vote_gpll0;
328
329/* PLL_ACTIVE_FLAG bit of GCC_GPLL0_MODE register
330 * gets set from PLL voting FSM.It indicates when
331 * FSM has enabled the PLL and PLL should be locked.
332 */
333static struct pll_vote_clk gpll0_clk_src_8952 = {
334 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
335 .en_mask = BIT(0),
336 .status_reg = (void __iomem *)GPLL0_STATUS,
337 .status_mask = BIT(17),
338 .soft_vote = &soft_vote_gpll0,
339 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
340 .base = &virt_bases[GCC_BASE],
341 .c = {
342 .parent = &xo_clk_src.c,
343 .rate = 800000000,
344 .dbg_name = "gpll0_clk_src_8952",
345 .ops = &clk_ops_pll_acpu_vote,
346 CLK_INIT(gpll0_clk_src_8952.c),
347 },
348};
349
350static struct pll_vote_clk gpll0_clk_src_8937 = {
351 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
352 .en_mask = BIT(0),
353 .status_reg = (void __iomem *)GPLL0_MODE,
354 .status_mask = BIT(30),
355 .soft_vote = &soft_vote_gpll0,
356 .soft_vote_mask = PLL_SOFT_VOTE_PRIMARY,
357 .base = &virt_bases[GCC_BASE],
358 .c = {
359 .parent = &gpll0_sleep_clk_src.c,
360 .rate = 800000000,
361 .dbg_name = "gpll0_clk_src_8937",
362 .ops = &clk_ops_pll_acpu_vote,
363 CLK_INIT(gpll0_clk_src_8937.c),
364 },
365};
366
367DEFINE_EXT_CLK(gpll0_clk_src, NULL);
368DEFINE_EXT_CLK(gpll0_ao_clk_src, NULL);
369DEFINE_EXT_CLK(gpll0_out_aux_clk_src, &gpll0_clk_src.c);
370DEFINE_EXT_CLK(gpll0_out_main_clk_src, &gpll0_clk_src.c);
371DEFINE_EXT_CLK(ext_pclk0_clk_src, NULL);
372DEFINE_EXT_CLK(ext_byte0_clk_src, NULL);
373DEFINE_EXT_CLK(ext_pclk1_clk_src, NULL);
374DEFINE_EXT_CLK(ext_byte1_clk_src, NULL);
375
376/* Don't vote for xo if using this clock to allow xo shutdown */
377static struct pll_vote_clk gpll0_ao_clk_src_8952 = {
378 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
379 .en_mask = BIT(0),
380 .status_reg = (void __iomem *)GPLL0_STATUS,
381 .status_mask = BIT(17),
382 .soft_vote = &soft_vote_gpll0,
383 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
384 .base = &virt_bases[GCC_BASE],
385 .c = {
386 .parent = &xo_a_clk_src.c,
387 .rate = 800000000,
388 .dbg_name = "gpll0_ao_clk_src_8952",
389 .ops = &clk_ops_pll_acpu_vote,
390 CLK_INIT(gpll0_ao_clk_src_8952.c),
391 },
392};
393
394static struct pll_vote_clk gpll0_ao_clk_src_8937 = {
395 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
396 .en_mask = BIT(0),
397 .status_reg = (void __iomem *)GPLL0_MODE,
398 .status_mask = BIT(30),
399 .soft_vote = &soft_vote_gpll0,
400 .soft_vote_mask = PLL_SOFT_VOTE_ACPU,
401 .base = &virt_bases[GCC_BASE],
402 .c = {
403 .parent = &xo_a_clk_src.c,
404 .rate = 800000000,
405 .dbg_name = "gpll0_ao_clk_src_8937",
406 .ops = &clk_ops_pll_acpu_vote,
407 CLK_INIT(gpll0_ao_clk_src_8937.c),
408 },
409};
410
411static struct pll_vote_clk gpll6_clk_src = {
412 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
413 .en_mask = BIT(7),
414 .status_reg = (void __iomem *)GPLL6_STATUS,
415 .status_mask = BIT(17),
416 .base = &virt_bases[GCC_BASE],
417 .c = {
418 .parent = &xo_clk_src.c,
419 .rate = 1080000000,
420 .dbg_name = "gpll6_clk_src",
421 .ops = &clk_ops_pll_vote,
422 CLK_INIT(gpll6_clk_src.c),
423 },
424};
425
426DEFINE_EXT_CLK(gpll6_aux_clk_src, &gpll6_clk_src.c);
427DEFINE_EXT_CLK(gpll6_out_main_clk_src, &gpll6_clk_src.c);
428
429static struct alpha_pll_masks pll_masks_p = {
430 .lock_mask = BIT(31),
431 .active_mask = BIT(30),
432 .vco_mask = BM(21, 20) >> 20,
433 .vco_shift = 20,
434 .alpha_en_mask = BIT(24),
435 .output_mask = 0xf,
436 .update_mask = BIT(22),
437 .post_div_mask = BM(11, 8),
438 .test_ctl_lo_mask = BM(31, 0),
439 .test_ctl_hi_mask = BM(31, 0),
440};
441
442/* Slewing plls won't allow to change vco_sel.
443 * Hence will have only one vco table entry
444 */
445static struct alpha_pll_vco_tbl p_vco[] = {
446 VCO(0, 700000000, 1400000000),
447};
448
449/* Slewing plls won't allow to change vco_sel.
450 * Hence will have only one vco table entry
451 */
452static struct alpha_pll_vco_tbl p_vco_8937[] = {
453 VCO(1, 525000000, 1066000000),
454};
455
456static struct alpha_pll_clk gpll3_clk_src = {
457 .masks = &pll_masks_p,
458 .base = &virt_bases[GCC_BASE],
459 .offset = GPLL3_MODE,
460 .vco_tbl = p_vco,
461 .num_vco = ARRAY_SIZE(p_vco),
462 .enable_config = 1,
463 /*
464 * gpll3 is dedicated to oxili and has a fuse implementation for
465 * post divider to limit frequency. HW with fuse blown has a divider
466 * value set to 2. So lets stick to divide by 2 in software to avoid
467 * conflicts.
468 */
469 .post_div_config = 1 << 8,
470 .slew = true,
471 .config_ctl_val = 0x4001055b,
472 .test_ctl_hi_val = 0x40000600,
473 .c = {
474 .rate = 1050000000,
475 .parent = &xo_clk_src.c,
476 .dbg_name = "gpll3_clk_src",
477 .ops = &clk_ops_dyna_alpha_pll,
478 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
479 CLK_INIT(gpll3_clk_src.c),
480 },
481};
482
483static struct pll_vote_clk gpll4_clk_src = {
484 .en_reg = (void __iomem *)APCS_GPLL_ENA_VOTE,
485 .en_mask = BIT(5),
486 .status_reg = (void __iomem *)GPLL4_MODE,
487 .status_mask = BIT(30),
488 .base = &virt_bases[GCC_BASE],
489 .c = {
490 .rate = 1152000000,
491 .parent = &xo_clk_src.c,
492 .dbg_name = "gpll4_clk_src",
493 .ops = &clk_ops_pll_vote,
494 VDD_DIG_FMAX_MAP1(NOMINAL, 1400000000),
495 CLK_INIT(gpll4_clk_src.c),
496 },
497};
498DEFINE_EXT_CLK(gpll4_out_clk_src, &gpll4_clk_src.c);
499
500static struct clk_freq_tbl ftbl_gcc_camss_top_ahb_clk[] = {
501 F( 40000000, gpll0, 10, 1, 2),
502 F( 61540000, gpll0, 13, 0, 0),
503 F( 80000000, gpll0, 10, 0, 0),
504 F_END
505};
506
507static struct rcg_clk camss_top_ahb_clk_src = {
508 .cmd_rcgr_reg = CAMSS_TOP_AHB_CMD_RCGR,
509 .set_rate = set_rate_mnd,
510 .freq_tbl = ftbl_gcc_camss_top_ahb_clk,
511 .current_freq = &rcg_dummy_freq,
512 .base = &virt_bases[GCC_BASE],
513 .c = {
514 .dbg_name = "camss_top_ahb_clk_src",
515 .ops = &clk_ops_rcg_mnd,
516 VDD_DIG_FMAX_MAP3(LOWER, 40000000, LOW, 61540000,
517 NOMINAL, 80000000),
518 CLK_INIT(camss_top_ahb_clk_src.c),
519 },
520};
521
522static struct clk_freq_tbl ftbl_gcc_apss_ahb_clk[] = {
523 F( 19200000, xo_a, 1, 0, 0),
524 F( 50000000, gpll0, 16, 0, 0),
525 F( 100000000, gpll0, 8, 0, 0),
526 F( 133330000, gpll0, 6, 0, 0),
527 F_END
528};
529
530static struct rcg_clk apss_ahb_clk_src = {
531 .cmd_rcgr_reg = APSS_AHB_CMD_RCGR,
532 .set_rate = set_rate_hid,
533 .freq_tbl = ftbl_gcc_apss_ahb_clk,
534 .current_freq = &rcg_dummy_freq,
535 .base = &virt_bases[GCC_BASE],
536 .c = {
537 .dbg_name = "apss_ahb_clk_src",
538 .ops = &clk_ops_rcg,
539 CLK_INIT(apss_ahb_clk_src.c),
540 },
541};
542
543static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk[] = {
544 F( 100000000, gpll0, 8, 0, 0),
545 F( 160000000, gpll0, 5, 0, 0),
546 F( 200000000, gpll0, 4, 0, 0),
547 F_END
548};
549
550static struct clk_freq_tbl ftbl_gcc_camss_csi0_2_clk_8937[] = {
551 F( 100000000, gpll0, 8, 0, 0),
552 F( 160000000, gpll0, 5, 0, 0),
553 F( 200000000, gpll0, 4, 0, 0),
554 F( 266670000, gpll0, 3, 0, 0),
555 F_END
556};
557
558
559static struct rcg_clk csi0_clk_src = {
560 .cmd_rcgr_reg = CSI0_CMD_RCGR,
561 .set_rate = set_rate_hid,
562 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
563 .current_freq = &rcg_dummy_freq,
564 .base = &virt_bases[GCC_BASE],
565 .c = {
566 .dbg_name = "csi0_clk_src",
567 .ops = &clk_ops_rcg,
568 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
569 NOMINAL, 200000000),
570 CLK_INIT(csi0_clk_src.c),
571 },
572};
573
574static struct rcg_clk csi1_clk_src = {
575 .cmd_rcgr_reg = CSI1_CMD_RCGR,
576 .set_rate = set_rate_hid,
577 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
578 .current_freq = &rcg_dummy_freq,
579 .base = &virt_bases[GCC_BASE],
580 .c = {
581 .dbg_name = "csi1_clk_src",
582 .ops = &clk_ops_rcg,
583 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
584 NOMINAL, 200000000),
585 CLK_INIT(csi1_clk_src.c),
586 },
587};
588
589static struct rcg_clk csi2_clk_src = {
590 .cmd_rcgr_reg = CSI2_CMD_RCGR,
591 .set_rate = set_rate_hid,
592 .freq_tbl = ftbl_gcc_camss_csi0_2_clk,
593 .current_freq = &rcg_dummy_freq,
594 .base = &virt_bases[GCC_BASE],
595 .c = {
596 .dbg_name = "csi2_clk_src",
597 .ops = &clk_ops_rcg,
598 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
599 NOMINAL, 200000000),
600 CLK_INIT(csi2_clk_src.c),
601 },
602};
603
604static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
605 F( 133330000, gpll0, 6, 0, 0),
606 F( 180000000, gpll6, 6, 0, 0),
607 F( 228570000, gpll0, 3.5, 0, 0),
608 F( 266670000, gpll0, 3, 0, 0),
609 F( 308570000, gpll6, 3.5, 0, 0),
610 F_END
611};
612
613static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8937[] = {
614 F( 166150000, gpll6, 6.5, 0, 0),
615 F( 240000000, gpll6, 4.5, 0, 0),
616 F( 308570000, gpll6, 3.5, 0, 0),
617 F( 320000000, gpll0, 2.5, 0, 0),
618 F( 360000000, gpll6, 3, 0, 0),
619 F_END
620};
621
622static struct clk_freq_tbl ftbl_gcc_venus0_vcodec0_clk_8917[] = {
623 F( 160000000, gpll0, 5, 0, 0),
624 F( 200000000, gpll0, 4, 0, 0),
625 F( 270000000, gpll6, 4, 0, 0),
626 F( 308570000, gpll6, 3.5, 0, 0),
627 F( 329140000, gpll4_out, 3.5, 0, 0),
628 F( 360000000, gpll6, 3, 0, 0),
629 F_END
630};
631
632static struct rcg_clk vcodec0_clk_src = {
633 .cmd_rcgr_reg = VCODEC0_CMD_RCGR,
634 .set_rate = set_rate_mnd,
635 .freq_tbl = ftbl_gcc_venus0_vcodec0_clk,
636 .current_freq = &rcg_dummy_freq,
637 .base = &virt_bases[GCC_BASE],
638 .c = {
639 .dbg_name = "vcodec0_clk_src",
640 .ops = &clk_ops_rcg_mnd,
641 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
642 NOMINAL, 228570000, NOM_PLUS, 266670000,
643 HIGH, 308570000),
644 CLK_INIT(vcodec0_clk_src.c),
645 },
646};
647
648static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk[] = {
649 F( 50000000, gpll0, 16, 0, 0),
650 F( 80000000, gpll0, 10, 0, 0),
651 F( 100000000, gpll0, 8, 0, 0),
652 F( 133330000, gpll0, 6, 0, 0),
653 F( 160000000, gpll0, 5, 0, 0),
654 F( 177780000, gpll0, 4.5, 0, 0),
655 F( 200000000, gpll0, 4, 0, 0),
656 F( 266670000, gpll0, 3, 0, 0),
657 F( 308570000, gpll6, 3.5, 0, 0),
658 F( 320000000, gpll0, 2.5, 0, 0),
659 F( 360000000, gpll6, 3, 0, 0),
660 F_END
661};
662
663static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8937[] = {
664 F( 50000000, gpll0, 16, 0, 0),
665 F( 80000000, gpll0, 10, 0, 0),
666 F( 100000000, gpll0, 8, 0, 0),
667 F( 133333333, gpll0, 6, 0, 0),
668 F( 160000000, gpll0, 5, 0, 0),
669 F( 177780000, gpll0, 4.5, 0, 0),
670 F( 200000000, gpll0, 4, 0, 0),
671 F( 266670000, gpll0, 3, 0, 0),
672 F( 308570000, gpll6, 3.5, 0, 0),
673 F( 320000000, gpll0, 2.5, 0, 0),
674 F( 360000000, gpll6, 3, 0, 0),
675 F( 400000000, gpll0, 2, 0, 0),
676 F( 432000000, gpll6, 2.5, 0, 0),
677 F_END
678};
679
680static struct clk_freq_tbl ftbl_gcc_camss_vfe0_1_clk_8917[] = {
681 F( 50000000, gpll0, 16, 0, 0),
682 F( 80000000, gpll0, 10, 0, 0),
683 F( 100000000, gpll0, 8, 0, 0),
684 F( 133333333, gpll0, 6, 0, 0),
685 F( 160000000, gpll0, 5, 0, 0),
686 F( 177780000, gpll0, 4.5, 0, 0),
687 F( 200000000, gpll0, 4, 0, 0),
688 F( 266670000, gpll0, 3, 0, 0),
689 F( 308570000, gpll6, 3.5, 0, 0),
690 F( 320000000, gpll0, 2.5, 0, 0),
691 F( 329140000, gpll4_out, 3.5, 0, 0),
692 F( 360000000, gpll6, 3, 0, 0),
693 F_END
694};
695
696static struct rcg_clk vfe0_clk_src = {
697 .cmd_rcgr_reg = VFE0_CMD_RCGR,
698 .set_rate = set_rate_hid,
699 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
700 .current_freq = &rcg_dummy_freq,
701 .base = &virt_bases[GCC_BASE],
702 .c = {
703 .dbg_name = "vfe0_clk_src",
704 .ops = &clk_ops_rcg,
705 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
706 NOMINAL, 308570000, NOM_PLUS, 320000000,
707 HIGH, 360000000),
708 CLK_INIT(vfe0_clk_src.c),
709 },
710};
711
712static struct rcg_clk vfe1_clk_src = {
713 .cmd_rcgr_reg = VFE1_CMD_RCGR,
714 .set_rate = set_rate_hid,
715 .freq_tbl = ftbl_gcc_camss_vfe0_1_clk,
716 .current_freq = &rcg_dummy_freq,
717 .base = &virt_bases[GCC_BASE],
718 .c = {
719 .dbg_name = "vfe1_clk_src",
720 .ops = &clk_ops_rcg,
721 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 266670000,
722 NOMINAL, 308570000, NOM_PLUS, 320000000,
723 HIGH, 360000000),
724 CLK_INIT(vfe1_clk_src.c),
725 },
726};
727
728static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
729 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
730 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
731 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
732 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
733 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
734 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
735 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
736 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
737 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
738 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
739 F_SLEW( 465000000, 930000000, gpll3, 1, 0, 0),
740 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
741 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
742 F_END
743};
744
745static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937[] = {
746 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
747 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
748 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
749 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
750 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
751 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
752 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
753 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
754 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
755 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
756 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
757 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
758 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
759 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
760 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
761 F_END
762};
763
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]764static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_sdm439[] = {
765 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
766 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
767 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
768 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
769 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
770 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
771 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
772 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
773 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
774 F_SLEW( 259200000, 1296000000, gpll3, 2.5, 0, 0),
775 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
776 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
777 F_SLEW( 355200000, 710400000, gpll3, 1, 0, 0),
778 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
779 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
780 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
781 F_SLEW( 510000000, 1020000000, gpll3, 1, 0, 0),
782 F_SLEW( 560000000, 1120000000, gpll3, 1, 0, 0),
783 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
784 F_END
785};
786
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]787static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8937_475MHz[] = {
788 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
789 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
790 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
791 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
792 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
793 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
794 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
795 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
796 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
797 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
798 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
799 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
800 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
801 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
802 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
803 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
804 F_END
805};
806
807static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8940_500MHz[] = {
808 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
809 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
810 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
811 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
812 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
813 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
814 F_SLEW( 216000000, FIXED_CLK_SRC, gpll6_aux, 5, 0, 0),
815 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
816 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
817 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
818 F_SLEW( 300000000, 600000000, gpll3, 1, 0, 0),
819 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
820 F_SLEW( 375000000, 750000000, gpll3, 1, 0, 0),
821 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
822 F_SLEW( 450000000, 900000000, gpll3, 1, 0, 0),
823 F_SLEW( 475000000, 950000000, gpll3, 1, 0, 0),
824 F_SLEW( 500000000, 1000000000, gpll3, 1, 0, 0),
825 F_END
826};
827
828static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917[] = {
829 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
830 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
831 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
832 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
833 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
834 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
835 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
836 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
837 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
838 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
839 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
840 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
841 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
842 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
843 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
844 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
845 F_END
846};
847
848static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk_8917_650MHz[] = {
849 F_SLEW( 19200000, FIXED_CLK_SRC, xo, 1, 0, 0),
850 F_SLEW( 50000000, FIXED_CLK_SRC, gpll0, 16, 0, 0),
851 F_SLEW( 80000000, FIXED_CLK_SRC, gpll0, 10, 0, 0),
852 F_SLEW( 100000000, FIXED_CLK_SRC, gpll0, 8, 0, 0),
853 F_SLEW( 160000000, FIXED_CLK_SRC, gpll0, 5, 0, 0),
854 F_SLEW( 200000000, FIXED_CLK_SRC, gpll0, 4, 0, 0),
855 F_SLEW( 228570000, FIXED_CLK_SRC, gpll0, 3.5, 0, 0),
856 F_SLEW( 240000000, FIXED_CLK_SRC, gpll6_aux, 4.5, 0, 0),
857 F_SLEW( 266670000, FIXED_CLK_SRC, gpll0, 3, 0, 0),
858 F_SLEW( 270000000, FIXED_CLK_SRC, gpll6_aux, 4, 0, 0),
859 F_SLEW( 320000000, FIXED_CLK_SRC, gpll0, 2.5, 0, 0),
860 F_SLEW( 400000000, FIXED_CLK_SRC, gpll0, 2, 0, 0),
861 F_SLEW( 484800000, 969600000, gpll3, 1, 0, 0),
862 F_SLEW( 523200000, 1046400000, gpll3, 1, 0, 0),
863 F_SLEW( 550000000, 1100000000, gpll3, 1, 0, 0),
864 F_SLEW( 598000000, 1196000000, gpll3, 1, 0, 0),
865 F_SLEW( 650000000, 1300000000, gpll3, 1, 0, 0),
866 F_END
867};
868
869static struct rcg_clk gfx3d_clk_src = {
870 .cmd_rcgr_reg = GFX3D_CMD_RCGR,
871 .set_rate = set_rate_hid,
872 .freq_tbl = ftbl_gcc_oxili_gfx3d_clk,
873 .current_freq = &rcg_dummy_freq,
874 .base = &virt_bases[GCC_BASE],
875 .c = {
876 .dbg_name = "gfx3d_clk_src",
877 .ops = &clk_ops_rcg,
878 VDD_DIG_FMAX_MAP5(LOWER, 240000000, LOW, 400000000,
879 NOMINAL, 465000000, NOM_PLUS, 500000000,
880 HIGH, 550000000),
881 CLK_INIT(gfx3d_clk_src.c),
882 },
883};
884
885static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk[] = {
886 F( 19200000, xo, 1, 0, 0),
887 F( 50000000, gpll0, 16, 0, 0),
888 F_END
889};
890
891static struct rcg_clk blsp1_qup1_i2c_apps_clk_src = {
892 .cmd_rcgr_reg = BLSP1_QUP1_I2C_APPS_CMD_RCGR,
893 .set_rate = set_rate_hid,
894 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
895 .current_freq = &rcg_dummy_freq,
896 .base = &virt_bases[GCC_BASE],
897 .c = {
898 .dbg_name = "blsp1_qup1_i2c_apps_clk_src",
899 .ops = &clk_ops_rcg,
900 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
901 CLK_INIT(blsp1_qup1_i2c_apps_clk_src.c),
902 },
903};
904
905static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk[] = {
906 F( 960000, xo, 10, 1, 2),
907 F( 4800000, xo, 4, 0, 0),
908 F( 9600000, xo, 2, 0, 0),
909 F( 16000000, gpll0, 10, 1, 5),
910 F( 19200000, xo, 1, 0, 0),
911 F( 25000000, gpll0, 16, 1, 2),
912 F( 50000000, gpll0, 16, 0, 0),
913 F_END
914};
915
916static struct clk_freq_tbl ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917[] = {
917 F( 960000, xo, 10, 1, 2),
918 F( 4800000, xo, 4, 0, 0),
919 F( 9600000, xo, 2, 0, 0),
920 F( 16000000, gpll0, 10, 1, 5),
921 F( 19200000, xo, 1, 0, 0),
922 F( 25000000, gpll0, 16, 1, 2),
923 F( 40000000, gpll0, 10, 1, 2),
924 F( 50000000, gpll0, 16, 0, 0),
925 F_END
926};
927
928static struct rcg_clk blsp1_qup1_spi_apps_clk_src = {
929 .cmd_rcgr_reg = BLSP1_QUP1_SPI_APPS_CMD_RCGR,
930 .set_rate = set_rate_mnd,
931 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
932 .current_freq = &rcg_dummy_freq,
933 .base = &virt_bases[GCC_BASE],
934 .c = {
935 .dbg_name = "blsp1_qup1_spi_apps_clk_src",
936 .ops = &clk_ops_rcg_mnd,
937 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
938 CLK_INIT(blsp1_qup1_spi_apps_clk_src.c),
939 },
940};
941
942static struct rcg_clk blsp1_qup2_i2c_apps_clk_src = {
943 .cmd_rcgr_reg = BLSP1_QUP2_I2C_APPS_CMD_RCGR,
944 .set_rate = set_rate_hid,
945 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
946 .current_freq = &rcg_dummy_freq,
947 .base = &virt_bases[GCC_BASE],
948 .c = {
949 .dbg_name = "blsp1_qup2_i2c_apps_clk_src",
950 .ops = &clk_ops_rcg,
951 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
952 CLK_INIT(blsp1_qup2_i2c_apps_clk_src.c),
953 },
954};
955
956static struct rcg_clk blsp1_qup2_spi_apps_clk_src = {
957 .cmd_rcgr_reg = BLSP1_QUP2_SPI_APPS_CMD_RCGR,
958 .set_rate = set_rate_mnd,
959 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
960 .current_freq = &rcg_dummy_freq,
961 .base = &virt_bases[GCC_BASE],
962 .c = {
963 .dbg_name = "blsp1_qup2_spi_apps_clk_src",
964 .ops = &clk_ops_rcg_mnd,
965 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
966 CLK_INIT(blsp1_qup2_spi_apps_clk_src.c),
967 },
968};
969
970static struct rcg_clk blsp1_qup3_i2c_apps_clk_src = {
971 .cmd_rcgr_reg = BLSP1_QUP3_I2C_APPS_CMD_RCGR,
972 .set_rate = set_rate_hid,
973 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
974 .current_freq = &rcg_dummy_freq,
975 .base = &virt_bases[GCC_BASE],
976 .c = {
977 .dbg_name = "blsp1_qup3_i2c_apps_clk_src",
978 .ops = &clk_ops_rcg,
979 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
980 CLK_INIT(blsp1_qup3_i2c_apps_clk_src.c),
981 },
982};
983
984static struct rcg_clk blsp1_qup3_spi_apps_clk_src = {
985 .cmd_rcgr_reg = BLSP1_QUP3_SPI_APPS_CMD_RCGR,
986 .set_rate = set_rate_mnd,
987 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
988 .current_freq = &rcg_dummy_freq,
989 .base = &virt_bases[GCC_BASE],
990 .c = {
991 .dbg_name = "blsp1_qup3_spi_apps_clk_src",
992 .ops = &clk_ops_rcg_mnd,
993 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
994 CLK_INIT(blsp1_qup3_spi_apps_clk_src.c),
995 },
996};
997
998static struct rcg_clk blsp1_qup4_i2c_apps_clk_src = {
999 .cmd_rcgr_reg = BLSP1_QUP4_I2C_APPS_CMD_RCGR,
1000 .set_rate = set_rate_hid,
1001 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1002 .current_freq = &rcg_dummy_freq,
1003 .base = &virt_bases[GCC_BASE],
1004 .c = {
1005 .dbg_name = "blsp1_qup4_i2c_apps_clk_src",
1006 .ops = &clk_ops_rcg,
1007 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1008 CLK_INIT(blsp1_qup4_i2c_apps_clk_src.c),
1009 },
1010};
1011
1012static struct rcg_clk blsp1_qup4_spi_apps_clk_src = {
1013 .cmd_rcgr_reg = BLSP1_QUP4_SPI_APPS_CMD_RCGR,
1014 .set_rate = set_rate_mnd,
1015 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1016 .current_freq = &rcg_dummy_freq,
1017 .base = &virt_bases[GCC_BASE],
1018 .c = {
1019 .dbg_name = "blsp1_qup4_spi_apps_clk_src",
1020 .ops = &clk_ops_rcg_mnd,
1021 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1022 CLK_INIT(blsp1_qup4_spi_apps_clk_src.c),
1023 },
1024};
1025
1026static struct clk_freq_tbl ftbl_gcc_blsp1_2_uart1_2_apps_clk[] = {
1027 F( 3686400, gpll0, 1, 72, 15625),
1028 F( 7372800, gpll0, 1, 144, 15625),
1029 F( 14745600, gpll0, 1, 288, 15625),
1030 F( 16000000, gpll0, 10, 1, 5),
1031 F( 19200000, xo, 1, 0, 0),
1032 F( 24000000, gpll0, 1, 3, 100),
1033 F( 25000000, gpll0, 16, 1, 2),
1034 F( 32000000, gpll0, 1, 1, 25),
1035 F( 40000000, gpll0, 1, 1, 20),
1036 F( 46400000, gpll0, 1, 29, 500),
1037 F( 48000000, gpll0, 1, 3, 50),
1038 F( 51200000, gpll0, 1, 8, 125),
1039 F( 56000000, gpll0, 1, 7, 100),
1040 F( 58982400, gpll0, 1, 1152, 15625),
1041 F( 60000000, gpll0, 1, 3, 40),
1042 F( 64000000, gpll0, 1, 2, 25),
1043 F_END
1044};
1045
1046static struct rcg_clk blsp1_uart1_apps_clk_src = {
1047 .cmd_rcgr_reg = BLSP1_UART1_APPS_CMD_RCGR,
1048 .set_rate = set_rate_mnd,
1049 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1050 .current_freq = &rcg_dummy_freq,
1051 .base = &virt_bases[GCC_BASE],
1052 .c = {
1053 .dbg_name = "blsp1_uart1_apps_clk_src",
1054 .ops = &clk_ops_rcg_mnd,
1055 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1056 CLK_INIT(blsp1_uart1_apps_clk_src.c),
1057 },
1058};
1059
1060static struct rcg_clk blsp1_uart2_apps_clk_src = {
1061 .cmd_rcgr_reg = BLSP1_UART2_APPS_CMD_RCGR,
1062 .set_rate = set_rate_mnd,
1063 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1064 .current_freq = &rcg_dummy_freq,
1065 .base = &virt_bases[GCC_BASE],
1066 .c = {
1067 .dbg_name = "blsp1_uart2_apps_clk_src",
1068 .ops = &clk_ops_rcg_mnd,
1069 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1070 CLK_INIT(blsp1_uart2_apps_clk_src.c),
1071 },
1072};
1073
1074static struct rcg_clk blsp2_qup1_i2c_apps_clk_src = {
1075 .cmd_rcgr_reg = BLSP2_QUP1_I2C_APPS_CMD_RCGR,
1076 .set_rate = set_rate_hid,
1077 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1078 .current_freq = &rcg_dummy_freq,
1079 .base = &virt_bases[GCC_BASE],
1080 .c = {
1081 .dbg_name = "blsp2_qup1_i2c_apps_clk_src",
1082 .ops = &clk_ops_rcg,
1083 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1084 CLK_INIT(blsp2_qup1_i2c_apps_clk_src.c),
1085 },
1086};
1087
1088static struct rcg_clk blsp2_qup1_spi_apps_clk_src = {
1089 .cmd_rcgr_reg = BLSP2_QUP1_SPI_APPS_CMD_RCGR,
1090 .set_rate = set_rate_mnd,
1091 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1092 .current_freq = &rcg_dummy_freq,
1093 .base = &virt_bases[GCC_BASE],
1094 .c = {
1095 .dbg_name = "blsp2_qup1_spi_apps_clk_src",
1096 .ops = &clk_ops_rcg_mnd,
1097 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1098 CLK_INIT(blsp2_qup1_spi_apps_clk_src.c),
1099 },
1100};
1101
1102static struct rcg_clk blsp2_qup2_i2c_apps_clk_src = {
1103 .cmd_rcgr_reg = BLSP2_QUP2_I2C_APPS_CMD_RCGR,
1104 .set_rate = set_rate_hid,
1105 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1106 .current_freq = &rcg_dummy_freq,
1107 .base = &virt_bases[GCC_BASE],
1108 .c = {
1109 .dbg_name = "blsp2_qup2_i2c_apps_clk_src",
1110 .ops = &clk_ops_rcg,
1111 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1112 CLK_INIT(blsp2_qup2_i2c_apps_clk_src.c),
1113 },
1114};
1115
1116static struct rcg_clk blsp2_qup2_spi_apps_clk_src = {
1117 .cmd_rcgr_reg = BLSP2_QUP2_SPI_APPS_CMD_RCGR,
1118 .set_rate = set_rate_mnd,
1119 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1120 .current_freq = &rcg_dummy_freq,
1121 .base = &virt_bases[GCC_BASE],
1122 .c = {
1123 .dbg_name = "blsp2_qup2_spi_apps_clk_src",
1124 .ops = &clk_ops_rcg_mnd,
1125 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1126 CLK_INIT(blsp2_qup2_spi_apps_clk_src.c),
1127 },
1128};
1129
1130static struct rcg_clk blsp2_qup3_i2c_apps_clk_src = {
1131 .cmd_rcgr_reg = BLSP2_QUP3_I2C_APPS_CMD_RCGR,
1132 .set_rate = set_rate_hid,
1133 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1134 .current_freq = &rcg_dummy_freq,
1135 .base = &virt_bases[GCC_BASE],
1136 .c = {
1137 .dbg_name = "blsp2_qup3_i2c_apps_clk_src",
1138 .ops = &clk_ops_rcg,
1139 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1140 CLK_INIT(blsp2_qup3_i2c_apps_clk_src.c),
1141 },
1142};
1143
1144static struct rcg_clk blsp2_qup3_spi_apps_clk_src = {
1145 .cmd_rcgr_reg = BLSP2_QUP3_SPI_APPS_CMD_RCGR,
1146 .set_rate = set_rate_mnd,
1147 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1148 .current_freq = &rcg_dummy_freq,
1149 .base = &virt_bases[GCC_BASE],
1150 .c = {
1151 .dbg_name = "blsp2_qup3_spi_apps_clk_src",
1152 .ops = &clk_ops_rcg_mnd,
1153 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1154 CLK_INIT(blsp2_qup3_spi_apps_clk_src.c),
1155 },
1156};
1157
1158static struct rcg_clk blsp2_qup4_i2c_apps_clk_src = {
1159 .cmd_rcgr_reg = BLSP2_QUP4_I2C_APPS_CMD_RCGR,
1160 .set_rate = set_rate_hid,
1161 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_i2c_apps_clk,
1162 .current_freq = &rcg_dummy_freq,
1163 .base = &virt_bases[GCC_BASE],
1164 .c = {
1165 .dbg_name = "blsp2_qup4_i2c_apps_clk_src",
1166 .ops = &clk_ops_rcg,
1167 VDD_DIG_FMAX_MAP1(LOWER, 50000000),
1168 CLK_INIT(blsp2_qup4_i2c_apps_clk_src.c),
1169 },
1170};
1171
1172static struct rcg_clk blsp2_qup4_spi_apps_clk_src = {
1173 .cmd_rcgr_reg = BLSP2_QUP4_SPI_APPS_CMD_RCGR,
1174 .set_rate = set_rate_mnd,
1175 .freq_tbl = ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk,
1176 .current_freq = &rcg_dummy_freq,
1177 .base = &virt_bases[GCC_BASE],
1178 .c = {
1179 .dbg_name = "blsp2_qup4_spi_apps_clk_src",
1180 .ops = &clk_ops_rcg_mnd,
1181 VDD_DIG_FMAX_MAP2(LOWER, 25000000, NOMINAL, 50000000),
1182 CLK_INIT(blsp2_qup4_spi_apps_clk_src.c),
1183 },
1184};
1185
1186static struct rcg_clk blsp2_uart1_apps_clk_src = {
1187 .cmd_rcgr_reg = BLSP2_UART1_APPS_CMD_RCGR,
1188 .set_rate = set_rate_mnd,
1189 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1190 .current_freq = &rcg_dummy_freq,
1191 .base = &virt_bases[GCC_BASE],
1192 .c = {
1193 .dbg_name = "blsp2_uart1_apps_clk_src",
1194 .ops = &clk_ops_rcg_mnd,
1195 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1196 CLK_INIT(blsp2_uart1_apps_clk_src.c),
1197 },
1198};
1199
1200static struct rcg_clk blsp2_uart2_apps_clk_src = {
1201 .cmd_rcgr_reg = BLSP2_UART2_APPS_CMD_RCGR,
1202 .set_rate = set_rate_mnd,
1203 .freq_tbl = ftbl_gcc_blsp1_2_uart1_2_apps_clk,
1204 .current_freq = &rcg_dummy_freq,
1205 .base = &virt_bases[GCC_BASE],
1206 .c = {
1207 .dbg_name = "blsp2_uart2_apps_clk_src",
1208 .ops = &clk_ops_rcg_mnd,
1209 VDD_DIG_FMAX_MAP2(LOWER, 32000000, NOMINAL, 64000000),
1210 CLK_INIT(blsp2_uart2_apps_clk_src.c),
1211 },
1212};
1213
1214static struct clk_freq_tbl ftbl_gcc_camss_cci_clk[] = {
1215 F( 19200000, xo, 1, 0, 0),
1216 F( 37500000, gpll0_out_aux, 1, 3, 64),
1217 F_END
1218};
1219
1220static struct rcg_clk cci_clk_src = {
1221 .cmd_rcgr_reg = CCI_CMD_RCGR,
1222 .set_rate = set_rate_mnd,
1223 .freq_tbl = ftbl_gcc_camss_cci_clk,
1224 .current_freq = &rcg_dummy_freq,
1225 .base = &virt_bases[GCC_BASE],
1226 .c = {
1227 .dbg_name = "cci_clk_src",
1228 .ops = &clk_ops_rcg_mnd,
1229 VDD_DIG_FMAX_MAP2(LOWER, 19200000, LOW, 37500000),
1230 CLK_INIT(cci_clk_src.c),
1231 },
1232};
1233
1234static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1235 F( 133330000, gpll0, 6, 0, 0),
1236 F( 180000000, gpll6, 6, 0, 0),
1237 F( 266670000, gpll0, 3, 0, 0),
1238 F( 308570000, gpll6, 3.5, 0, 0),
1239 F( 320000000, gpll0, 2.5, 0, 0),
1240 F_END
1241};
1242
1243static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8937[] = {
1244 F( 133333333, gpll0, 6, 0, 0),
1245 F( 160000000, gpll0, 5, 0, 0),
1246 F( 200000000, gpll0, 4, 0, 0),
1247 F( 266666667, gpll0, 3, 0, 0),
1248 F( 308570000, gpll6, 3.5, 0, 0),
1249 F( 320000000, gpll0, 2.5, 0, 0),
1250 F( 360000000, gpll6, 3, 0, 0),
1251 F_END
1252};
1253
1254static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk_8917[] = {
1255 F( 133330000, gpll0, 6, 0, 0),
1256 F( 160000000, gpll0, 5, 0, 0),
1257 F( 266670000, gpll0, 3, 0, 0),
1258 F( 308570000, gpll6, 3.5, 0, 0),
1259 F( 320000000, gpll0, 2.5, 0, 0),
1260 F( 360000000, gpll6, 3, 0, 0),
1261 F_END
1262};
1263
1264static struct rcg_clk cpp_clk_src = {
1265 .cmd_rcgr_reg = CPP_CMD_RCGR,
1266 .set_rate = set_rate_hid,
1267 .freq_tbl = ftbl_gcc_camss_cpp_clk,
1268 .current_freq = &rcg_dummy_freq,
1269 .base = &virt_bases[GCC_BASE],
1270 .c = {
1271 .dbg_name = "cpp_clk_src",
1272 .ops = &clk_ops_rcg,
1273 VDD_DIG_FMAX_MAP5(LOWER, 133330000, LOW, 180000000,
1274 NOMINAL, 266670000, NOM_PLUS, 308570000,
1275 HIGH, 320000000),
1276 CLK_INIT(cpp_clk_src.c),
1277 },
1278};
1279
1280static struct clk_freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
1281 F( 100000000, gpll0, 8, 0, 0),
1282 F( 160000000, gpll0, 5, 0, 0),
1283 F( 200000000, gpll0, 4, 0, 0),
1284 F_END
1285};
1286
1287static struct rcg_clk camss_gp0_clk_src = {
1288 .cmd_rcgr_reg = MM_GP0_CMD_RCGR,
1289 .set_rate = set_rate_mnd,
1290 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1291 .current_freq = &rcg_dummy_freq,
1292 .base = &virt_bases[GCC_BASE],
1293 .c = {
1294 .dbg_name = "camss_gp0_clk_src",
1295 .ops = &clk_ops_rcg_mnd,
1296 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1297 NOMINAL, 200000000),
1298 CLK_INIT(camss_gp0_clk_src.c),
1299 },
1300};
1301
1302static struct rcg_clk camss_gp1_clk_src = {
1303 .cmd_rcgr_reg = MM_GP1_CMD_RCGR,
1304 .set_rate = set_rate_mnd,
1305 .freq_tbl = ftbl_gcc_camss_gp0_1_clk,
1306 .current_freq = &rcg_dummy_freq,
1307 .base = &virt_bases[GCC_BASE],
1308 .c = {
1309 .dbg_name = "camss_gp1_clk_src",
1310 .ops = &clk_ops_rcg_mnd,
1311 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1312 NOMINAL, 200000000),
1313 CLK_INIT(camss_gp1_clk_src.c),
1314 },
1315};
1316
1317static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk[] = {
1318 F( 133330000, gpll0, 6, 0, 0),
1319 F( 266670000, gpll0, 3, 0, 0),
1320 F( 320000000, gpll0, 2.5, 0, 0),
1321 F_END
1322};
1323
1324static struct clk_freq_tbl ftbl_gcc_camss_jpeg0_clk_8937[] = {
1325 F( 133333333, gpll0, 6, 0, 0),
1326 F( 200000000, gpll0, 4, 0, 0),
1327 F( 266666667, gpll0, 3, 0, 0),
1328 F( 308570000, gpll6, 3.5, 0, 0),
1329 F( 320000000, gpll0, 2.5, 0, 0),
1330 F_END
1331};
1332
1333static struct rcg_clk jpeg0_clk_src = {
1334 .cmd_rcgr_reg = JPEG0_CMD_RCGR,
1335 .set_rate = set_rate_hid,
1336 .freq_tbl = ftbl_gcc_camss_jpeg0_clk,
1337 .current_freq = &rcg_dummy_freq,
1338 .base = &virt_bases[GCC_BASE],
1339 .c = {
1340 .dbg_name = "jpeg0_clk_src",
1341 .ops = &clk_ops_rcg,
1342 VDD_DIG_FMAX_MAP3(LOWER, 133330000, NOMINAL, 266670000,
1343 HIGH, 320000000),
1344 CLK_INIT(jpeg0_clk_src.c),
1345 },
1346};
1347
1348static struct clk_freq_tbl ftbl_gcc_camss_mclk0_2_clk[] = {
1349 F( 19200000, xo, 1, 0, 0),
1350 F( 24000000, gpll6, 1, 1, 45),
1351 F( 66670000, gpll0, 12, 0, 0),
1352 F_END
1353};
1354
1355static struct rcg_clk mclk0_clk_src = {
1356 .cmd_rcgr_reg = MCLK0_CMD_RCGR,
1357 .set_rate = set_rate_mnd,
1358 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1359 .current_freq = &rcg_dummy_freq,
1360 .base = &virt_bases[GCC_BASE],
1361 .c = {
1362 .dbg_name = "mclk0_clk_src",
1363 .ops = &clk_ops_rcg_mnd,
1364 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1365 CLK_INIT(mclk0_clk_src.c),
1366 },
1367};
1368
1369static struct rcg_clk mclk1_clk_src = {
1370 .cmd_rcgr_reg = MCLK1_CMD_RCGR,
1371 .set_rate = set_rate_mnd,
1372 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1373 .current_freq = &rcg_dummy_freq,
1374 .base = &virt_bases[GCC_BASE],
1375 .c = {
1376 .dbg_name = "mclk1_clk_src",
1377 .ops = &clk_ops_rcg_mnd,
1378 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1379 CLK_INIT(mclk1_clk_src.c),
1380 },
1381};
1382
1383static struct rcg_clk mclk2_clk_src = {
1384 .cmd_rcgr_reg = MCLK2_CMD_RCGR,
1385 .set_rate = set_rate_mnd,
1386 .freq_tbl = ftbl_gcc_camss_mclk0_2_clk,
1387 .current_freq = &rcg_dummy_freq,
1388 .base = &virt_bases[GCC_BASE],
1389 .c = {
1390 .dbg_name = "mclk2_clk_src",
1391 .ops = &clk_ops_rcg_mnd,
1392 VDD_DIG_FMAX_MAP1(LOWER, 66670000),
1393 CLK_INIT(mclk2_clk_src.c),
1394 },
1395};
1396
1397static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk[] = {
1398 F( 100000000, gpll0, 8, 0, 0),
1399 F( 160000000, gpll0, 5, 0, 0),
1400 F( 200000000, gpll0, 4, 0, 0),
1401 F_END
1402};
1403
1404static struct clk_freq_tbl ftbl_gcc_camss_csi0_1phytimer_clk_8917[] = {
1405 F( 100000000, gpll0, 8, 0, 0),
1406 F( 160000000, gpll0, 5, 0, 0),
1407 F( 200000000, gpll0, 4, 0, 0),
1408 F( 266670000, gpll0, 3, 0, 0),
1409 F_END
1410};
1411
1412static struct rcg_clk csi0phytimer_clk_src = {
1413 .cmd_rcgr_reg = CSI0PHYTIMER_CMD_RCGR,
1414 .set_rate = set_rate_hid,
1415 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1416 .current_freq = &rcg_dummy_freq,
1417 .base = &virt_bases[GCC_BASE],
1418 .c = {
1419 .dbg_name = "csi0phytimer_clk_src",
1420 .ops = &clk_ops_rcg,
1421 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1422 NOMINAL, 200000000),
1423 CLK_INIT(csi0phytimer_clk_src.c),
1424 },
1425};
1426
1427static struct rcg_clk csi1phytimer_clk_src = {
1428 .cmd_rcgr_reg = CSI1PHYTIMER_CMD_RCGR,
1429 .set_rate = set_rate_hid,
1430 .freq_tbl = ftbl_gcc_camss_csi0_1phytimer_clk,
1431 .current_freq = &rcg_dummy_freq,
1432 .base = &virt_bases[GCC_BASE],
1433 .c = {
1434 .dbg_name = "csi1phytimer_clk_src",
1435 .ops = &clk_ops_rcg,
1436 VDD_DIG_FMAX_MAP3(LOWER, 100000000, LOW, 160000000,
1437 NOMINAL, 200000000),
1438 CLK_INIT(csi1phytimer_clk_src.c),
1439 },
1440};
1441
1442static struct clk_freq_tbl ftbl_gcc_crypto_clk[] = {
1443 F( 50000000, gpll0, 16, 0, 0),
1444 F( 80000000, gpll0, 10, 0, 0),
1445 F( 100000000, gpll0, 8, 0, 0),
1446 F( 160000000, gpll0, 5, 0, 0),
1447 F_END
1448};
1449
1450static struct rcg_clk crypto_clk_src = {
1451 .cmd_rcgr_reg = CRYPTO_CMD_RCGR,
1452 .set_rate = set_rate_hid,
1453 .freq_tbl = ftbl_gcc_crypto_clk,
1454 .current_freq = &rcg_dummy_freq,
1455 .base = &virt_bases[GCC_BASE],
1456 .c = {
1457 .dbg_name = "crypto_clk_src",
1458 .ops = &clk_ops_rcg,
1459 VDD_DIG_FMAX_MAP2(LOWER, 80000000, NOMINAL, 160000000),
1460 CLK_INIT(crypto_clk_src.c),
1461 },
1462};
1463
1464static struct clk_freq_tbl ftbl_gcc_gp1_3_clk[] = {
1465 F( 19200000, xo, 1, 0, 0),
1466 F_END
1467};
1468
1469static struct rcg_clk gp1_clk_src = {
1470 .cmd_rcgr_reg = GP1_CMD_RCGR,
1471 .set_rate = set_rate_mnd,
1472 .freq_tbl = ftbl_gcc_gp1_3_clk,
1473 .current_freq = &rcg_dummy_freq,
1474 .base = &virt_bases[GCC_BASE],
1475 .c = {
1476 .dbg_name = "gp1_clk_src",
1477 .ops = &clk_ops_rcg_mnd,
1478 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1479 CLK_INIT(gp1_clk_src.c),
1480 },
1481};
1482
1483static struct rcg_clk gp2_clk_src = {
1484 .cmd_rcgr_reg = GP2_CMD_RCGR,
1485 .set_rate = set_rate_mnd,
1486 .freq_tbl = ftbl_gcc_gp1_3_clk,
1487 .current_freq = &rcg_dummy_freq,
1488 .base = &virt_bases[GCC_BASE],
1489 .c = {
1490 .dbg_name = "gp2_clk_src",
1491 .ops = &clk_ops_rcg_mnd,
1492 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1493 CLK_INIT(gp2_clk_src.c),
1494 },
1495};
1496
1497static struct rcg_clk gp3_clk_src = {
1498 .cmd_rcgr_reg = GP3_CMD_RCGR,
1499 .set_rate = set_rate_mnd,
1500 .freq_tbl = ftbl_gcc_gp1_3_clk,
1501 .current_freq = &rcg_dummy_freq,
1502 .base = &virt_bases[GCC_BASE],
1503 .c = {
1504 .dbg_name = "gp3_clk_src",
1505 .ops = &clk_ops_rcg_mnd,
1506 VDD_DIG_FMAX_MAP1(LOW, 19200000),
1507 CLK_INIT(gp3_clk_src.c),
1508 },
1509};
1510
1511static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk[] = {
1512 {
1513 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1514 | BVAL(4, 0, 0),
1515 .src_clk = &ext_byte0_clk_src.c,
1516 .freq_hz = 0,
1517 },
1518 F_END
1519};
1520
1521static struct clk_freq_tbl ftbl_gcc_mdss_byte0_clk_8937[] = {
1522 {
1523 .div_src_val = BVAL(10, 8, xo_source_val)
1524 | BVAL(4, 0, 0),
1525 .src_clk = &xo_clk_src.c,
1526 .freq_hz = 0,
1527 },
1528 {
1529 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1530 | BVAL(4, 0, 0),
1531 .src_clk = &ext_byte0_clk_src.c,
1532 .freq_hz = 0,
1533 },
1534 {
1535 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1536 | BVAL(4, 0, 0),
1537 .src_clk = &ext_byte1_clk_src.c,
1538 .freq_hz = 0,
1539 },
1540 F_END
1541};
1542
1543static struct rcg_clk byte0_clk_src = {
1544 .cmd_rcgr_reg = BYTE0_CMD_RCGR,
1545 .set_rate = set_rate_hid,
1546 .current_freq = ftbl_gcc_mdss_byte0_clk,
1547 .freq_tbl = ftbl_gcc_mdss_byte0_clk,
1548 .base = &virt_bases[GCC_BASE],
1549 .c = {
1550 .dbg_name = "byte0_clk_src",
1551 .ops = &clk_ops_byte_multiparent,
1552 .flags = CLKFLAG_NO_RATE_CACHE,
1553 VDD_DIG_FMAX_MAP2(LOWER, 120000000, NOMINAL, 187500000),
1554 CLK_INIT(byte0_clk_src.c),
1555 },
1556};
1557
1558static struct clk_freq_tbl ftbl_gcc_mdss_byte1_clk[] = {
1559 {
1560 .div_src_val = BVAL(10, 8, xo_source_val)
1561 | BVAL(4, 0, 0),
1562 .src_clk = &xo_clk_src.c,
1563 .freq_hz = 0,
1564 },
1565 {
1566 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1567 | BVAL(4, 0, 0),
1568 .src_clk = &ext_byte1_clk_src.c,
1569 .freq_hz = 0,
1570 },
1571 {
1572 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1573 | BVAL(4, 0, 0),
1574 .src_clk = &ext_byte0_clk_src.c,
1575 .freq_hz = 0,
1576 },
1577 F_END
1578};
1579
1580static struct rcg_clk byte1_clk_src = {
1581 .cmd_rcgr_reg = BYTE1_CMD_RCGR,
1582 .set_rate = set_rate_hid,
1583 .current_freq = ftbl_gcc_mdss_byte1_clk,
1584 .freq_tbl = ftbl_gcc_mdss_byte1_clk,
1585 .base = &virt_bases[GCC_BASE],
1586 .c = {
1587 .dbg_name = "byte1_clk_src",
1588 .ops = &clk_ops_byte_multiparent,
1589 .flags = CLKFLAG_NO_RATE_CACHE,
1590 VDD_DIG_FMAX_MAP2(LOWER, 125000000, NOMINAL, 187500000),
1591 CLK_INIT(byte1_clk_src.c),
1592 },
1593};
1594
1595static struct clk_freq_tbl ftbl_gcc_mdss_esc0_clk[] = {
1596 F( 19200000, xo, 1, 0, 0),
1597 F_END
1598};
1599
1600static struct rcg_clk esc0_clk_src = {
1601 .cmd_rcgr_reg = ESC0_CMD_RCGR,
1602 .set_rate = set_rate_hid,
1603 .freq_tbl = ftbl_gcc_mdss_esc0_clk,
1604 .current_freq = &rcg_dummy_freq,
1605 .base = &virt_bases[GCC_BASE],
1606 .c = {
1607 .dbg_name = "esc0_clk_src",
1608 .ops = &clk_ops_rcg,
1609 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1610 CLK_INIT(esc0_clk_src.c),
1611 },
1612};
1613
1614static struct clk_freq_tbl ftbl_esc1_clk_src[] = {
1615 F( 19200000, xo, 1, 0, 0),
1616 F_END
1617};
1618
1619static struct rcg_clk esc1_clk_src = {
1620 .cmd_rcgr_reg = ESC1_CMD_RCGR,
1621 .set_rate = set_rate_hid,
1622 .freq_tbl = ftbl_esc1_clk_src,
1623 .current_freq = &rcg_dummy_freq,
1624 .base = &virt_bases[GCC_BASE],
1625 .c = {
1626 .dbg_name = "esc1_clk_src",
1627 .ops = &clk_ops_rcg,
1628 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1629 CLK_INIT(esc1_clk_src.c),
1630 },
1631};
1632
1633static struct clk_freq_tbl ftbl_gcc_mdss_mdp_clk[] = {
1634 F( 50000000, gpll0, 16, 0, 0),
1635 F( 80000000, gpll0, 10, 0, 0),
1636 F( 100000000, gpll0, 8, 0, 0),
1637 F( 145450000, gpll0, 5.5, 0, 0),
1638 F( 160000000, gpll0, 5, 0, 0),
1639 F( 177780000, gpll0, 4.5, 0, 0),
1640 F( 200000000, gpll0, 4, 0, 0),
1641 F( 266670000, gpll0, 3, 0, 0),
1642 F( 320000000, gpll0, 2.5, 0, 0),
1643 F_END
1644};
1645
1646static struct rcg_clk mdp_clk_src = {
1647 .cmd_rcgr_reg = MDP_CMD_RCGR,
1648 .set_rate = set_rate_hid,
1649 .freq_tbl = ftbl_gcc_mdss_mdp_clk,
1650 .current_freq = &rcg_dummy_freq,
1651 .base = &virt_bases[GCC_BASE],
1652 .c = {
1653 .dbg_name = "mdp_clk_src",
1654 .ops = &clk_ops_rcg,
1655 VDD_DIG_FMAX_MAP3(LOWER, 160000000, NOMINAL, 266670000,
1656 HIGH, 320000000),
1657 CLK_INIT(mdp_clk_src.c),
1658 },
1659};
1660
1661static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk[] = {
1662 {
1663 .div_src_val = BVAL(10, 8, dsi0_phypll_source_val)
1664 | BVAL(4, 0, 0),
1665 .src_clk = &ext_pclk0_clk_src.c,
1666 .freq_hz = 0,
1667 },
1668 F_END
1669};
1670
1671static struct clk_freq_tbl ftbl_gcc_mdss_pclk0_clk_8937[] = {
1672 {
1673 .div_src_val = BVAL(10, 8, xo_source_val)
1674 | BVAL(4, 0, 0),
1675 .src_clk = &xo_clk_src.c,
1676 .freq_hz = 0,
1677 },
1678 {
1679 .div_src_val = BVAL(10, 8, dsi0_0phypll_source_val)
1680 | BVAL(4, 0, 0),
1681 .src_clk = &ext_pclk0_clk_src.c,
1682 .freq_hz = 0,
1683 },
1684 {
1685 .div_src_val = BVAL(10, 8, dsi1_0phypll_source_val)
1686 | BVAL(4, 0, 0),
1687 .src_clk = &ext_pclk1_clk_src.c,
1688 .freq_hz = 0,
1689 },
1690 F_END
1691};
1692
1693static struct rcg_clk pclk0_clk_src = {
1694 .cmd_rcgr_reg = PCLK0_CMD_RCGR,
1695 .set_rate = set_rate_mnd,
1696 .current_freq = ftbl_gcc_mdss_pclk0_clk,
1697 .freq_tbl = ftbl_gcc_mdss_pclk0_clk,
1698 .base = &virt_bases[GCC_BASE],
1699 .c = {
1700 .dbg_name = "pclk0_clk_src",
1701 .ops = &clk_ops_pixel_multiparent,
1702 VDD_DIG_FMAX_MAP2(LOWER, 160000000, NOMINAL, 250000000),
1703 .flags = CLKFLAG_NO_RATE_CACHE,
1704 CLK_INIT(pclk0_clk_src.c),
1705 },
1706};
1707
1708static struct clk_freq_tbl ftbl_gcc_mdss_pclk1_clk[] = {
1709 {
1710 .div_src_val = BVAL(10, 8, xo_source_val)
1711 | BVAL(4, 0, 0),
1712 .src_clk = &xo_clk_src.c,
1713 .freq_hz = 0,
1714 },
1715 {
1716 .div_src_val = BVAL(10, 8, dsi1_1phypll_source_val)
1717 | BVAL(4, 0, 0),
1718 .src_clk = &ext_pclk1_clk_src.c,
1719 .freq_hz = 0,
1720 },
1721 {
1722 .div_src_val = BVAL(10, 8, dsi0_1phypll_source_val)
1723 | BVAL(4, 0, 0),
1724 .src_clk = &ext_pclk0_clk_src.c,
1725 .freq_hz = 0,
1726 },
1727 F_END
1728};
1729
1730static struct rcg_clk pclk1_clk_src = {
1731 .cmd_rcgr_reg = PCLK1_CMD_RCGR,
1732 .set_rate = set_rate_mnd,
1733 .current_freq = ftbl_gcc_mdss_pclk1_clk,
1734 .freq_tbl = ftbl_gcc_mdss_pclk1_clk,
1735 .base = &virt_bases[GCC_BASE],
1736 .c = {
1737 .dbg_name = "pclk1_clk_src",
1738 .ops = &clk_ops_pixel_multiparent,
1739 .flags = CLKFLAG_NO_RATE_CACHE,
1740 VDD_DIG_FMAX_MAP2(LOWER, 166670000, NOMINAL, 250000000),
1741 CLK_INIT(pclk1_clk_src.c),
1742 },
1743};
1744
1745static struct clk_freq_tbl ftbl_gcc_mdss_vsync_clk[] = {
1746 F( 19200000, xo, 1, 0, 0),
1747 F_END
1748};
1749
1750static struct rcg_clk vsync_clk_src = {
1751 .cmd_rcgr_reg = VSYNC_CMD_RCGR,
1752 .set_rate = set_rate_hid,
1753 .freq_tbl = ftbl_gcc_mdss_vsync_clk,
1754 .current_freq = &rcg_dummy_freq,
1755 .base = &virt_bases[GCC_BASE],
1756 .c = {
1757 .dbg_name = "vsync_clk_src",
1758 .ops = &clk_ops_rcg,
1759 VDD_DIG_FMAX_MAP1(LOWER, 19200000),
1760 CLK_INIT(vsync_clk_src.c),
1761 },
1762};
1763
1764static struct clk_freq_tbl ftbl_gcc_pdm2_clk[] = {
1765 F( 64000000, gpll0, 12.5, 0, 0),
1766 F_END
1767};
1768
1769static struct rcg_clk pdm2_clk_src = {
1770 .cmd_rcgr_reg = PDM2_CMD_RCGR,
1771 .set_rate = set_rate_hid,
1772 .freq_tbl = ftbl_gcc_pdm2_clk,
1773 .current_freq = &rcg_dummy_freq,
1774 .base = &virt_bases[GCC_BASE],
1775 .c = {
1776 .dbg_name = "pdm2_clk_src",
1777 .ops = &clk_ops_rcg,
1778 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1779 CLK_INIT(pdm2_clk_src.c),
1780 },
1781};
1782
1783static struct clk_freq_tbl ftbl_gcc_sdcc1_apps_clk[] = {
1784 F( 144000, xo, 16, 3, 25),
1785 F( 400000, xo, 12, 1, 4),
1786 F( 20000000, gpll0, 10, 1, 4),
1787 F( 25000000, gpll0, 16, 1, 2),
1788 F( 50000000, gpll0, 16, 0, 0),
1789 F( 100000000, gpll0, 8, 0, 0),
1790 F( 177770000, gpll0, 4.5, 0, 0),
1791 F( 192000000, gpll4, 6, 0, 0),
1792 F( 200000000, gpll0, 4, 0, 0),
1793 F( 384000000, gpll4, 3, 0, 0),
1794 F_END
1795};
1796
1797static struct rcg_clk sdcc1_apps_clk_src = {
1798 .cmd_rcgr_reg = SDCC1_APPS_CMD_RCGR,
1799 .set_rate = set_rate_mnd,
1800 .freq_tbl = ftbl_gcc_sdcc1_apps_clk,
1801 .current_freq = &rcg_dummy_freq,
1802 .base = &virt_bases[GCC_BASE],
1803 .c = {
1804 .dbg_name = "sdcc1_apps_clk_src",
1805 .ops = &clk_ops_rcg_mnd,
1806 VDD_DIG_FMAX_MAP2(LOWER, 50000000, NOMINAL, 384000000),
1807 CLK_INIT(sdcc1_apps_clk_src.c),
1808 },
1809};
1810
1811static struct clk_freq_tbl ftbl_gcc_sdcc1_ice_core_clk[] = {
1812 F( 100000000, gpll0_out_main, 8, 0, 0),
1813 F( 200000000, gpll0_out_main, 4, 0, 0),
1814 F_END
1815};
1816
1817static struct rcg_clk sdcc1_ice_core_clk_src = {
1818 .cmd_rcgr_reg = SDCC1_ICE_CORE_CMD_RCGR,
1819 .set_rate = set_rate_mnd,
1820 .freq_tbl = ftbl_gcc_sdcc1_ice_core_clk,
1821 .current_freq = &rcg_dummy_freq,
1822 .base = &virt_bases[GCC_BASE],
1823 .c = {
1824 .dbg_name = "sdcc1_ice_core_clk_src",
1825 .ops = &clk_ops_rcg_mnd,
1826 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1827 CLK_INIT(sdcc1_ice_core_clk_src.c),
1828 },
1829};
1830
1831static struct clk_freq_tbl ftbl_gcc_sdcc2_apps_clk[] = {
1832 F( 144000, xo, 16, 3, 25),
1833 F( 400000, xo, 12, 1, 4),
1834 F( 20000000, gpll0, 10, 1, 4),
1835 F( 25000000, gpll0, 16, 1, 2),
1836 F( 50000000, gpll0, 16, 0, 0),
1837 F( 100000000, gpll0, 8, 0, 0),
1838 F( 177770000, gpll0, 4.5, 0, 0),
1839 F( 200000000, gpll0, 4, 0, 0),
1840 F_END
1841};
1842
1843static struct rcg_clk sdcc2_apps_clk_src = {
1844 .cmd_rcgr_reg = SDCC2_APPS_CMD_RCGR,
1845 .set_rate = set_rate_mnd,
1846 .freq_tbl = ftbl_gcc_sdcc2_apps_clk,
1847 .current_freq = &rcg_dummy_freq,
1848 .base = &virt_bases[GCC_BASE],
1849 .c = {
1850 .dbg_name = "sdcc2_apps_clk_src",
1851 .ops = &clk_ops_rcg_mnd,
1852 VDD_DIG_FMAX_MAP2(LOWER, 100000000, NOMINAL, 200000000),
1853 CLK_INIT(sdcc2_apps_clk_src.c),
1854 },
1855};
1856
1857static struct clk_freq_tbl ftbl_gcc_usb_fs_ic_clk[] = {
1858 F( 60000000, gpll6_out_main, 9, 1, 2),
1859 F_END
1860};
1861
1862static struct rcg_clk usb_fs_ic_clk_src = {
1863 .cmd_rcgr_reg = USB_FS_IC_CMD_RCGR,
1864 .set_rate = set_rate_mnd,
1865 .freq_tbl = ftbl_gcc_usb_fs_ic_clk,
1866 .current_freq = &rcg_dummy_freq,
1867 .base = &virt_bases[GCC_BASE],
1868 .c = {
1869 .dbg_name = "usb_fs_ic_clk_src",
1870 .ops = &clk_ops_rcg_mnd,
1871 VDD_DIG_FMAX_MAP1(LOWER, 60000000),
1872 CLK_INIT(usb_fs_ic_clk_src.c),
1873 },
1874};
1875
1876static struct clk_freq_tbl ftbl_gcc_usb_fs_system_clk[] = {
1877 F( 64000000, gpll0_out_aux, 12.5, 0, 0),
1878 F_END
1879};
1880
1881static struct rcg_clk usb_fs_system_clk_src = {
1882 .cmd_rcgr_reg = USB_FS_SYSTEM_CMD_RCGR,
1883 .set_rate = set_rate_mnd,
1884 .freq_tbl = ftbl_gcc_usb_fs_system_clk,
1885 .current_freq = &rcg_dummy_freq,
1886 .base = &virt_bases[GCC_BASE],
1887 .c = {
1888 .dbg_name = "usb_fs_system_clk_src",
1889 .ops = &clk_ops_rcg_mnd,
1890 VDD_DIG_FMAX_MAP1(LOWER, 64000000),
1891 CLK_INIT(usb_fs_system_clk_src.c),
1892 },
1893};
1894
1895static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1896 F( 57140000, gpll0, 14, 0, 0),
1897 F( 100000000, gpll0, 8, 0, 0),
1898 F( 133330000, gpll0, 6, 0, 0),
1899 F( 177780000, gpll0, 4.5, 0, 0),
1900 F_END
1901};
1902
1903static struct clk_freq_tbl ftbl_gcc_usb_hs_system_clk_8917[] = {
1904 F( 80000000, gpll0, 10, 0, 0),
1905 F( 100000000, gpll0, 8, 0, 0),
1906 F( 133330000, gpll0, 6, 0, 0),
1907 F( 177780000, gpll0, 4.5, 0, 0),
1908 F_END
1909};
1910
1911static struct rcg_clk usb_hs_system_clk_src = {
1912 .cmd_rcgr_reg = USB_HS_SYSTEM_CMD_RCGR,
1913 .set_rate = set_rate_hid,
1914 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
1915 .current_freq = &rcg_dummy_freq,
1916 .base = &virt_bases[GCC_BASE],
1917 .c = {
1918 .dbg_name = "usb_hs_system_clk_src",
1919 .ops = &clk_ops_rcg,
1920 VDD_DIG_FMAX_MAP3(LOWER, 57140000, NOMINAL, 133330000,
1921 HIGH, 177780000),
1922 CLK_INIT(usb_hs_system_clk_src.c),
1923 },
1924};
1925
1926static struct branch_clk gcc_bimc_gpu_clk = {
1927 .cbcr_reg = BIMC_GPU_CBCR,
1928 .has_sibling = 1,
1929 .base = &virt_bases[GCC_BASE],
1930 .c = {
1931 .dbg_name = "gcc_bimc_gpu_clk",
1932 .ops = &clk_ops_branch,
1933 CLK_INIT(gcc_bimc_gpu_clk.c),
1934 },
1935};
1936
1937static struct branch_clk gcc_dcc_clk = {
1938 .cbcr_reg = DCC_CBCR,
1939 .has_sibling = 1,
1940 .base = &virt_bases[GCC_BASE],
1941 .c = {
1942 .dbg_name = "gcc_dcc_clk",
1943 .ops = &clk_ops_branch,
1944 CLK_INIT(gcc_dcc_clk.c),
1945 },
1946};
1947
1948static struct local_vote_clk gcc_blsp1_ahb_clk = {
1949 .cbcr_reg = BLSP1_AHB_CBCR,
1950 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
1951 .en_mask = BIT(10),
1952 .base = &virt_bases[GCC_BASE],
1953 .c = {
1954 .dbg_name = "gcc_blsp1_ahb_clk",
1955 .ops = &clk_ops_vote,
1956 CLK_INIT(gcc_blsp1_ahb_clk.c),
1957 },
1958};
1959
1960static struct branch_clk gcc_blsp1_qup1_i2c_apps_clk = {
1961 .cbcr_reg = BLSP1_QUP1_I2C_APPS_CBCR,
1962 .has_sibling = 0,
1963 .base = &virt_bases[GCC_BASE],
1964 .c = {
1965 .dbg_name = "gcc_blsp1_qup1_i2c_apps_clk",
1966 .parent = &blsp1_qup1_i2c_apps_clk_src.c,
1967 .ops = &clk_ops_branch,
1968 CLK_INIT(gcc_blsp1_qup1_i2c_apps_clk.c),
1969 },
1970};
1971
1972static struct branch_clk gcc_blsp1_qup1_spi_apps_clk = {
1973 .cbcr_reg = BLSP1_QUP1_SPI_APPS_CBCR,
1974 .has_sibling = 0,
1975 .base = &virt_bases[GCC_BASE],
1976 .c = {
1977 .dbg_name = "gcc_blsp1_qup1_spi_apps_clk",
1978 .parent = &blsp1_qup1_spi_apps_clk_src.c,
1979 .ops = &clk_ops_branch,
1980 CLK_INIT(gcc_blsp1_qup1_spi_apps_clk.c),
1981 },
1982};
1983
1984static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
1985 .cbcr_reg = BLSP1_QUP2_I2C_APPS_CBCR,
1986 .has_sibling = 0,
1987 .base = &virt_bases[GCC_BASE],
1988 .c = {
1989 .dbg_name = "gcc_blsp1_qup2_i2c_apps_clk",
1990 .parent = &blsp1_qup2_i2c_apps_clk_src.c,
1991 .ops = &clk_ops_branch,
1992 CLK_INIT(gcc_blsp1_qup2_i2c_apps_clk.c),
1993 },
1994};
1995
1996static struct branch_clk gcc_blsp1_qup2_spi_apps_clk = {
1997 .cbcr_reg = BLSP1_QUP2_SPI_APPS_CBCR,
1998 .has_sibling = 0,
1999 .base = &virt_bases[GCC_BASE],
2000 .c = {
2001 .dbg_name = "gcc_blsp1_qup2_spi_apps_clk",
2002 .parent = &blsp1_qup2_spi_apps_clk_src.c,
2003 .ops = &clk_ops_branch,
2004 CLK_INIT(gcc_blsp1_qup2_spi_apps_clk.c),
2005 },
2006};
2007
2008static struct branch_clk gcc_blsp1_qup3_i2c_apps_clk = {
2009 .cbcr_reg = BLSP1_QUP3_I2C_APPS_CBCR,
2010 .has_sibling = 0,
2011 .base = &virt_bases[GCC_BASE],
2012 .c = {
2013 .dbg_name = "gcc_blsp1_qup3_i2c_apps_clk",
2014 .parent = &blsp1_qup3_i2c_apps_clk_src.c,
2015 .ops = &clk_ops_branch,
2016 CLK_INIT(gcc_blsp1_qup3_i2c_apps_clk.c),
2017 },
2018};
2019
2020static struct branch_clk gcc_blsp1_qup3_spi_apps_clk = {
2021 .cbcr_reg = BLSP1_QUP3_SPI_APPS_CBCR,
2022 .has_sibling = 0,
2023 .base = &virt_bases[GCC_BASE],
2024 .c = {
2025 .dbg_name = "gcc_blsp1_qup3_spi_apps_clk",
2026 .parent = &blsp1_qup3_spi_apps_clk_src.c,
2027 .ops = &clk_ops_branch,
2028 CLK_INIT(gcc_blsp1_qup3_spi_apps_clk.c),
2029 },
2030};
2031
2032static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
2033 .cbcr_reg = BLSP1_QUP4_I2C_APPS_CBCR,
2034 .has_sibling = 0,
2035 .base = &virt_bases[GCC_BASE],
2036 .c = {
2037 .dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
2038 .parent = &blsp1_qup4_i2c_apps_clk_src.c,
2039 .ops = &clk_ops_branch,
2040 CLK_INIT(gcc_blsp1_qup4_i2c_apps_clk.c),
2041 },
2042};
2043
2044static struct branch_clk gcc_blsp1_qup4_spi_apps_clk = {
2045 .cbcr_reg = BLSP1_QUP4_SPI_APPS_CBCR,
2046 .has_sibling = 0,
2047 .base = &virt_bases[GCC_BASE],
2048 .c = {
2049 .dbg_name = "gcc_blsp1_qup4_spi_apps_clk",
2050 .parent = &blsp1_qup4_spi_apps_clk_src.c,
2051 .ops = &clk_ops_branch,
2052 CLK_INIT(gcc_blsp1_qup4_spi_apps_clk.c),
2053 },
2054};
2055
2056static struct branch_clk gcc_blsp1_uart1_apps_clk = {
2057 .cbcr_reg = BLSP1_UART1_APPS_CBCR,
2058 .has_sibling = 0,
2059 .base = &virt_bases[GCC_BASE],
2060 .c = {
2061 .dbg_name = "gcc_blsp1_uart1_apps_clk",
2062 .parent = &blsp1_uart1_apps_clk_src.c,
2063 .ops = &clk_ops_branch,
2064 CLK_INIT(gcc_blsp1_uart1_apps_clk.c),
2065 },
2066};
2067
2068static struct branch_clk gcc_blsp1_uart2_apps_clk = {
2069 .cbcr_reg = BLSP1_UART2_APPS_CBCR,
2070 .has_sibling = 0,
2071 .base = &virt_bases[GCC_BASE],
2072 .c = {
2073 .dbg_name = "gcc_blsp1_uart2_apps_clk",
2074 .parent = &blsp1_uart2_apps_clk_src.c,
2075 .ops = &clk_ops_branch,
2076 CLK_INIT(gcc_blsp1_uart2_apps_clk.c),
2077 },
2078};
2079
2080static struct local_vote_clk gcc_blsp2_ahb_clk = {
2081 .cbcr_reg = BLSP2_AHB_CBCR,
2082 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2083 .en_mask = BIT(20),
2084 .base = &virt_bases[GCC_BASE],
2085 .c = {
2086 .dbg_name = "gcc_blsp2_ahb_clk",
2087 .ops = &clk_ops_vote,
2088 CLK_INIT(gcc_blsp2_ahb_clk.c),
2089 },
2090};
2091
2092static struct branch_clk gcc_blsp2_qup1_i2c_apps_clk = {
2093 .cbcr_reg = BLSP2_QUP1_I2C_APPS_CBCR,
2094 .has_sibling = 0,
2095 .base = &virt_bases[GCC_BASE],
2096 .c = {
2097 .dbg_name = "gcc_blsp2_qup1_i2c_apps_clk",
2098 .parent = &blsp2_qup1_i2c_apps_clk_src.c,
2099 .ops = &clk_ops_branch,
2100 CLK_INIT(gcc_blsp2_qup1_i2c_apps_clk.c),
2101 },
2102};
2103
2104static struct branch_clk gcc_blsp2_qup1_spi_apps_clk = {
2105 .cbcr_reg = BLSP2_QUP1_SPI_APPS_CBCR,
2106 .has_sibling = 0,
2107 .base = &virt_bases[GCC_BASE],
2108 .c = {
2109 .dbg_name = "gcc_blsp2_qup1_spi_apps_clk",
2110 .parent = &blsp2_qup1_spi_apps_clk_src.c,
2111 .ops = &clk_ops_branch,
2112 CLK_INIT(gcc_blsp2_qup1_spi_apps_clk.c),
2113 },
2114};
2115
2116static struct branch_clk gcc_blsp2_qup2_i2c_apps_clk = {
2117 .cbcr_reg = BLSP2_QUP2_I2C_APPS_CBCR,
2118 .has_sibling = 0,
2119 .base = &virt_bases[GCC_BASE],
2120 .c = {
2121 .dbg_name = "gcc_blsp2_qup2_i2c_apps_clk",
2122 .parent = &blsp2_qup2_i2c_apps_clk_src.c,
2123 .ops = &clk_ops_branch,
2124 CLK_INIT(gcc_blsp2_qup2_i2c_apps_clk.c),
2125 },
2126};
2127
2128static struct branch_clk gcc_blsp2_qup2_spi_apps_clk = {
2129 .cbcr_reg = BLSP2_QUP2_SPI_APPS_CBCR,
2130 .has_sibling = 0,
2131 .base = &virt_bases[GCC_BASE],
2132 .c = {
2133 .dbg_name = "gcc_blsp2_qup2_spi_apps_clk",
2134 .parent = &blsp2_qup2_spi_apps_clk_src.c,
2135 .ops = &clk_ops_branch,
2136 CLK_INIT(gcc_blsp2_qup2_spi_apps_clk.c),
2137 },
2138};
2139
2140static struct branch_clk gcc_blsp2_qup3_i2c_apps_clk = {
2141 .cbcr_reg = BLSP2_QUP3_I2C_APPS_CBCR,
2142 .has_sibling = 0,
2143 .base = &virt_bases[GCC_BASE],
2144 .c = {
2145 .dbg_name = "gcc_blsp2_qup3_i2c_apps_clk",
2146 .parent = &blsp2_qup3_i2c_apps_clk_src.c,
2147 .ops = &clk_ops_branch,
2148 CLK_INIT(gcc_blsp2_qup3_i2c_apps_clk.c),
2149 },
2150};
2151
2152static struct branch_clk gcc_blsp2_qup3_spi_apps_clk = {
2153 .cbcr_reg = BLSP2_QUP3_SPI_APPS_CBCR,
2154 .has_sibling = 0,
2155 .base = &virt_bases[GCC_BASE],
2156 .c = {
2157 .dbg_name = "gcc_blsp2_qup3_spi_apps_clk",
2158 .parent = &blsp2_qup3_spi_apps_clk_src.c,
2159 .ops = &clk_ops_branch,
2160 CLK_INIT(gcc_blsp2_qup3_spi_apps_clk.c),
2161 },
2162};
2163
2164static struct branch_clk gcc_blsp2_qup4_i2c_apps_clk = {
2165 .cbcr_reg = BLSP2_QUP4_I2C_APPS_CBCR,
2166 .has_sibling = 0,
2167 .base = &virt_bases[GCC_BASE],
2168 .c = {
2169 .dbg_name = "gcc_blsp2_qup4_i2c_apps_clk",
2170 .parent = &blsp2_qup4_i2c_apps_clk_src.c,
2171 .ops = &clk_ops_branch,
2172 CLK_INIT(gcc_blsp2_qup4_i2c_apps_clk.c),
2173 },
2174};
2175
2176static struct branch_clk gcc_blsp2_qup4_spi_apps_clk = {
2177 .cbcr_reg = BLSP2_QUP4_SPI_APPS_CBCR,
2178 .has_sibling = 0,
2179 .base = &virt_bases[GCC_BASE],
2180 .c = {
2181 .dbg_name = "gcc_blsp2_qup4_spi_apps_clk",
2182 .parent = &blsp2_qup4_spi_apps_clk_src.c,
2183 .ops = &clk_ops_branch,
2184 CLK_INIT(gcc_blsp2_qup4_spi_apps_clk.c),
2185 },
2186};
2187
2188static struct branch_clk gcc_blsp2_uart1_apps_clk = {
2189 .cbcr_reg = BLSP2_UART1_APPS_CBCR,
2190 .has_sibling = 0,
2191 .base = &virt_bases[GCC_BASE],
2192 .c = {
2193 .dbg_name = "gcc_blsp2_uart1_apps_clk",
2194 .parent = &blsp2_uart1_apps_clk_src.c,
2195 .ops = &clk_ops_branch,
2196 CLK_INIT(gcc_blsp2_uart1_apps_clk.c),
2197 },
2198};
2199
2200static struct branch_clk gcc_blsp2_uart2_apps_clk = {
2201 .cbcr_reg = BLSP2_UART2_APPS_CBCR,
2202 .has_sibling = 0,
2203 .base = &virt_bases[GCC_BASE],
2204 .c = {
2205 .dbg_name = "gcc_blsp2_uart2_apps_clk",
2206 .parent = &blsp2_uart2_apps_clk_src.c,
2207 .ops = &clk_ops_branch,
2208 CLK_INIT(gcc_blsp2_uart2_apps_clk.c),
2209 },
2210};
2211
2212static struct local_vote_clk gcc_boot_rom_ahb_clk = {
2213 .cbcr_reg = BOOT_ROM_AHB_CBCR,
2214 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2215 .en_mask = BIT(7),
2216 .base = &virt_bases[GCC_BASE],
2217 .c = {
2218 .dbg_name = "gcc_boot_rom_ahb_clk",
2219 .ops = &clk_ops_vote,
2220 CLK_INIT(gcc_boot_rom_ahb_clk.c),
2221 },
2222};
2223
2224static struct branch_clk gcc_camss_cci_ahb_clk = {
2225 .cbcr_reg = CAMSS_CCI_AHB_CBCR,
2226 .has_sibling = 1,
2227 .base = &virt_bases[GCC_BASE],
2228 .c = {
2229 .dbg_name = "gcc_camss_cci_ahb_clk",
2230 .parent = &camss_top_ahb_clk_src.c,
2231 .ops = &clk_ops_branch,
2232 CLK_INIT(gcc_camss_cci_ahb_clk.c),
2233 },
2234};
2235
2236static struct branch_clk gcc_camss_cci_clk = {
2237 .cbcr_reg = CAMSS_CCI_CBCR,
2238 .has_sibling = 0,
2239 .base = &virt_bases[GCC_BASE],
2240 .c = {
2241 .dbg_name = "gcc_camss_cci_clk",
2242 .parent = &cci_clk_src.c,
2243 .ops = &clk_ops_branch,
2244 CLK_INIT(gcc_camss_cci_clk.c),
2245 },
2246};
2247
2248static struct branch_clk gcc_camss_cpp_ahb_clk = {
2249 .cbcr_reg = CAMSS_CPP_AHB_CBCR,
2250 .has_sibling = 1,
2251 .base = &virt_bases[GCC_BASE],
2252 .c = {
2253 .dbg_name = "gcc_camss_cpp_ahb_clk",
2254 .parent = &camss_top_ahb_clk_src.c,
2255 .ops = &clk_ops_branch,
2256 CLK_INIT(gcc_camss_cpp_ahb_clk.c),
2257 },
2258};
2259
2260static struct branch_clk gcc_camss_cpp_axi_clk = {
2261 .cbcr_reg = CAMSS_CPP_AXI_CBCR,
2262 .has_sibling = 1,
2263 .base = &virt_bases[GCC_BASE],
2264 .c = {
2265 .dbg_name = "gcc_camss_cpp_axi_clk",
2266 .ops = &clk_ops_branch,
2267 CLK_INIT(gcc_camss_cpp_axi_clk.c),
2268 },
2269};
2270
2271static struct branch_clk gcc_camss_cpp_clk = {
2272 .cbcr_reg = CAMSS_CPP_CBCR,
2273 .has_sibling = 0,
2274 .base = &virt_bases[GCC_BASE],
2275 .c = {
2276 .dbg_name = "gcc_camss_cpp_clk",
2277 .parent = &cpp_clk_src.c,
2278 .ops = &clk_ops_branch,
2279 CLK_INIT(gcc_camss_cpp_clk.c),
2280 },
2281};
2282
2283static struct branch_clk gcc_camss_csi0_ahb_clk = {
2284 .cbcr_reg = CAMSS_CSI0_AHB_CBCR,
2285 .has_sibling = 1,
2286 .base = &virt_bases[GCC_BASE],
2287 .c = {
2288 .dbg_name = "gcc_camss_csi0_ahb_clk",
2289 .parent = &camss_top_ahb_clk_src.c,
2290 .ops = &clk_ops_branch,
2291 CLK_INIT(gcc_camss_csi0_ahb_clk.c),
2292 },
2293};
2294
2295static struct branch_clk gcc_camss_csi0_clk = {
2296 .cbcr_reg = CAMSS_CSI0_CBCR,
2297 .has_sibling = 1,
2298 .base = &virt_bases[GCC_BASE],
2299 .c = {
2300 .dbg_name = "gcc_camss_csi0_clk",
2301 .parent = &csi0_clk_src.c,
2302 .ops = &clk_ops_branch,
2303 CLK_INIT(gcc_camss_csi0_clk.c),
2304 },
2305};
2306
2307static struct branch_clk gcc_camss_csi0phy_clk = {
2308 .cbcr_reg = CAMSS_CSI0PHY_CBCR,
2309 .has_sibling = 1,
2310 .base = &virt_bases[GCC_BASE],
2311 .c = {
2312 .dbg_name = "gcc_camss_csi0phy_clk",
2313 .parent = &csi0_clk_src.c,
2314 .ops = &clk_ops_branch,
2315 CLK_INIT(gcc_camss_csi0phy_clk.c),
2316 },
2317};
2318
2319static struct branch_clk gcc_camss_csi0pix_clk = {
2320 .cbcr_reg = CAMSS_CSI0PIX_CBCR,
2321 .has_sibling = 1,
2322 .base = &virt_bases[GCC_BASE],
2323 .c = {
2324 .dbg_name = "gcc_camss_csi0pix_clk",
2325 .parent = &csi0_clk_src.c,
2326 .ops = &clk_ops_branch,
2327 CLK_INIT(gcc_camss_csi0pix_clk.c),
2328 },
2329};
2330
2331static struct branch_clk gcc_camss_csi0rdi_clk = {
2332 .cbcr_reg = CAMSS_CSI0RDI_CBCR,
2333 .has_sibling = 1,
2334 .base = &virt_bases[GCC_BASE],
2335 .c = {
2336 .dbg_name = "gcc_camss_csi0rdi_clk",
2337 .parent = &csi0_clk_src.c,
2338 .ops = &clk_ops_branch,
2339 CLK_INIT(gcc_camss_csi0rdi_clk.c),
2340 },
2341};
2342
2343static struct branch_clk gcc_camss_csi1_ahb_clk = {
2344 .cbcr_reg = CAMSS_CSI1_AHB_CBCR,
2345 .has_sibling = 1,
2346 .base = &virt_bases[GCC_BASE],
2347 .c = {
2348 .dbg_name = "gcc_camss_csi1_ahb_clk",
2349 .parent = &camss_top_ahb_clk_src.c,
2350 .ops = &clk_ops_branch,
2351 CLK_INIT(gcc_camss_csi1_ahb_clk.c),
2352 },
2353};
2354
2355static struct branch_clk gcc_camss_csi1_clk = {
2356 .cbcr_reg = CAMSS_CSI1_CBCR,
2357 .has_sibling = 1,
2358 .base = &virt_bases[GCC_BASE],
2359 .c = {
2360 .dbg_name = "gcc_camss_csi1_clk",
2361 .parent = &csi1_clk_src.c,
2362 .ops = &clk_ops_branch,
2363 CLK_INIT(gcc_camss_csi1_clk.c),
2364 },
2365};
2366
2367static struct branch_clk gcc_camss_csi1phy_clk = {
2368 .cbcr_reg = CAMSS_CSI1PHY_CBCR,
2369 .has_sibling = 1,
2370 .base = &virt_bases[GCC_BASE],
2371 .c = {
2372 .dbg_name = "gcc_camss_csi1phy_clk",
2373 .parent = &csi1_clk_src.c,
2374 .ops = &clk_ops_branch,
2375 CLK_INIT(gcc_camss_csi1phy_clk.c),
2376 },
2377};
2378
2379static struct branch_clk gcc_camss_csi1pix_clk = {
2380 .cbcr_reg = CAMSS_CSI1PIX_CBCR,
2381 .has_sibling = 1,
2382 .base = &virt_bases[GCC_BASE],
2383 .c = {
2384 .dbg_name = "gcc_camss_csi1pix_clk",
2385 .parent = &csi1_clk_src.c,
2386 .ops = &clk_ops_branch,
2387 CLK_INIT(gcc_camss_csi1pix_clk.c),
2388 },
2389};
2390
2391static struct branch_clk gcc_camss_csi1rdi_clk = {
2392 .cbcr_reg = CAMSS_CSI1RDI_CBCR,
2393 .has_sibling = 1,
2394 .base = &virt_bases[GCC_BASE],
2395 .c = {
2396 .dbg_name = "gcc_camss_csi1rdi_clk",
2397 .parent = &csi1_clk_src.c,
2398 .ops = &clk_ops_branch,
2399 CLK_INIT(gcc_camss_csi1rdi_clk.c),
2400 },
2401};
2402
2403static struct branch_clk gcc_camss_csi2_ahb_clk = {
2404 .cbcr_reg = CAMSS_CSI2_AHB_CBCR,
2405 .has_sibling = 1,
2406 .base = &virt_bases[GCC_BASE],
2407 .c = {
2408 .dbg_name = "gcc_camss_csi2_ahb_clk",
2409 .parent = &camss_top_ahb_clk_src.c,
2410 .ops = &clk_ops_branch,
2411 CLK_INIT(gcc_camss_csi2_ahb_clk.c),
2412 },
2413};
2414
2415static struct branch_clk gcc_camss_csi2_clk = {
2416 .cbcr_reg = CAMSS_CSI2_CBCR,
2417 .has_sibling = 1,
2418 .base = &virt_bases[GCC_BASE],
2419 .c = {
2420 .dbg_name = "gcc_camss_csi2_clk",
2421 .parent = &csi2_clk_src.c,
2422 .ops = &clk_ops_branch,
2423 CLK_INIT(gcc_camss_csi2_clk.c),
2424 },
2425};
2426
2427static struct branch_clk gcc_camss_csi2phy_clk = {
2428 .cbcr_reg = CAMSS_CSI2PHY_CBCR,
2429 .has_sibling = 1,
2430 .base = &virt_bases[GCC_BASE],
2431 .c = {
2432 .dbg_name = "gcc_camss_csi2phy_clk",
2433 .parent = &csi2_clk_src.c,
2434 .ops = &clk_ops_branch,
2435 CLK_INIT(gcc_camss_csi2phy_clk.c),
2436 },
2437};
2438
2439static struct branch_clk gcc_camss_csi2pix_clk = {
2440 .cbcr_reg = CAMSS_CSI2PIX_CBCR,
2441 .has_sibling = 1,
2442 .base = &virt_bases[GCC_BASE],
2443 .c = {
2444 .dbg_name = "gcc_camss_csi2pix_clk",
2445 .parent = &csi2_clk_src.c,
2446 .ops = &clk_ops_branch,
2447 CLK_INIT(gcc_camss_csi2pix_clk.c),
2448 },
2449};
2450
2451static struct branch_clk gcc_camss_csi2rdi_clk = {
2452 .cbcr_reg = CAMSS_CSI2RDI_CBCR,
2453 .has_sibling = 1,
2454 .base = &virt_bases[GCC_BASE],
2455 .c = {
2456 .dbg_name = "gcc_camss_csi2rdi_clk",
2457 .parent = &csi2_clk_src.c,
2458 .ops = &clk_ops_branch,
2459 CLK_INIT(gcc_camss_csi2rdi_clk.c),
2460 },
2461};
2462
2463static struct branch_clk gcc_camss_csi_vfe0_clk = {
2464 .cbcr_reg = CAMSS_CSI_VFE0_CBCR,
2465 .has_sibling = 1,
2466 .base = &virt_bases[GCC_BASE],
2467 .c = {
2468 .dbg_name = "gcc_camss_csi_vfe0_clk",
2469 .parent = &vfe0_clk_src.c,
2470 .ops = &clk_ops_branch,
2471 CLK_INIT(gcc_camss_csi_vfe0_clk.c),
2472 },
2473};
2474
2475static struct branch_clk gcc_camss_csi_vfe1_clk = {
2476 .cbcr_reg = CAMSS_CSI_VFE1_CBCR,
2477 .has_sibling = 1,
2478 .base = &virt_bases[GCC_BASE],
2479 .c = {
2480 .dbg_name = "gcc_camss_csi_vfe1_clk",
2481 .parent = &vfe1_clk_src.c,
2482 .ops = &clk_ops_branch,
2483 CLK_INIT(gcc_camss_csi_vfe1_clk.c),
2484 },
2485};
2486
2487static struct branch_clk gcc_camss_gp0_clk = {
2488 .cbcr_reg = CAMSS_GP0_CBCR,
2489 .has_sibling = 0,
2490 .base = &virt_bases[GCC_BASE],
2491 .c = {
2492 .dbg_name = "gcc_camss_gp0_clk",
2493 .parent = &camss_gp0_clk_src.c,
2494 .ops = &clk_ops_branch,
2495 CLK_INIT(gcc_camss_gp0_clk.c),
2496 },
2497};
2498
2499static struct branch_clk gcc_camss_gp1_clk = {
2500 .cbcr_reg = CAMSS_GP1_CBCR,
2501 .has_sibling = 0,
2502 .base = &virt_bases[GCC_BASE],
2503 .c = {
2504 .dbg_name = "gcc_camss_gp1_clk",
2505 .parent = &camss_gp1_clk_src.c,
2506 .ops = &clk_ops_branch,
2507 CLK_INIT(gcc_camss_gp1_clk.c),
2508 },
2509};
2510
2511static struct branch_clk gcc_camss_ispif_ahb_clk = {
2512 .cbcr_reg = CAMSS_ISPIF_AHB_CBCR,
2513 .has_sibling = 0,
2514 .base = &virt_bases[GCC_BASE],
2515 .c = {
2516 .dbg_name = "gcc_camss_ispif_ahb_clk",
2517 .parent = &camss_top_ahb_clk_src.c,
2518 .ops = &clk_ops_branch,
2519 CLK_INIT(gcc_camss_ispif_ahb_clk.c),
2520 },
2521};
2522
2523static struct branch_clk gcc_camss_jpeg0_clk = {
2524 .cbcr_reg = CAMSS_JPEG0_CBCR,
2525 .has_sibling = 0,
2526 .base = &virt_bases[GCC_BASE],
2527 .c = {
2528 .dbg_name = "gcc_camss_jpeg0_clk",
2529 .parent = &jpeg0_clk_src.c,
2530 .ops = &clk_ops_branch,
2531 CLK_INIT(gcc_camss_jpeg0_clk.c),
2532 },
2533};
2534
2535static struct branch_clk gcc_camss_jpeg_ahb_clk = {
2536 .cbcr_reg = CAMSS_JPEG_AHB_CBCR,
2537 .has_sibling = 1,
2538 .base = &virt_bases[GCC_BASE],
2539 .c = {
2540 .dbg_name = "gcc_camss_jpeg_ahb_clk",
2541 .parent = &camss_top_ahb_clk_src.c,
2542 .ops = &clk_ops_branch,
2543 CLK_INIT(gcc_camss_jpeg_ahb_clk.c),
2544 },
2545};
2546
2547static struct branch_clk gcc_camss_jpeg_axi_clk = {
2548 .cbcr_reg = CAMSS_JPEG_AXI_CBCR,
2549 .has_sibling = 1,
2550 .base = &virt_bases[GCC_BASE],
2551 .c = {
2552 .dbg_name = "gcc_camss_jpeg_axi_clk",
2553 .ops = &clk_ops_branch,
2554 CLK_INIT(gcc_camss_jpeg_axi_clk.c),
2555 },
2556};
2557
2558static struct branch_clk gcc_camss_mclk0_clk = {
2559 .cbcr_reg = CAMSS_MCLK0_CBCR,
2560 .has_sibling = 0,
2561 .base = &virt_bases[GCC_BASE],
2562 .c = {
2563 .dbg_name = "gcc_camss_mclk0_clk",
2564 .parent = &mclk0_clk_src.c,
2565 .ops = &clk_ops_branch,
2566 CLK_INIT(gcc_camss_mclk0_clk.c),
2567 },
2568};
2569
2570static struct branch_clk gcc_camss_mclk1_clk = {
2571 .cbcr_reg = CAMSS_MCLK1_CBCR,
2572 .has_sibling = 0,
2573 .base = &virt_bases[GCC_BASE],
2574 .c = {
2575 .dbg_name = "gcc_camss_mclk1_clk",
2576 .parent = &mclk1_clk_src.c,
2577 .ops = &clk_ops_branch,
2578 CLK_INIT(gcc_camss_mclk1_clk.c),
2579 },
2580};
2581
2582static struct branch_clk gcc_camss_mclk2_clk = {
2583 .cbcr_reg = CAMSS_MCLK2_CBCR,
2584 .has_sibling = 0,
2585 .base = &virt_bases[GCC_BASE],
2586 .c = {
2587 .dbg_name = "gcc_camss_mclk2_clk",
2588 .parent = &mclk2_clk_src.c,
2589 .ops = &clk_ops_branch,
2590 CLK_INIT(gcc_camss_mclk2_clk.c),
2591 },
2592};
2593
2594static struct branch_clk gcc_camss_micro_ahb_clk = {
2595 .cbcr_reg = CAMSS_MICRO_AHB_CBCR,
2596 .bcr_reg = CAMSS_MICRO_BCR,
2597 .has_sibling = 1,
2598 .base = &virt_bases[GCC_BASE],
2599 .c = {
2600 .dbg_name = "gcc_camss_micro_ahb_clk",
2601 .parent = &camss_top_ahb_clk_src.c,
2602 .ops = &clk_ops_branch,
2603 CLK_INIT(gcc_camss_micro_ahb_clk.c),
2604 },
2605};
2606
2607static struct branch_clk gcc_camss_csi0phytimer_clk = {
2608 .cbcr_reg = CAMSS_CSI0PHYTIMER_CBCR,
2609 .has_sibling = 0,
2610 .base = &virt_bases[GCC_BASE],
2611 .c = {
2612 .dbg_name = "gcc_camss_csi0phytimer_clk",
2613 .parent = &csi0phytimer_clk_src.c,
2614 .ops = &clk_ops_branch,
2615 CLK_INIT(gcc_camss_csi0phytimer_clk.c),
2616 },
2617};
2618
2619static struct branch_clk gcc_camss_csi1phytimer_clk = {
2620 .cbcr_reg = CAMSS_CSI1PHYTIMER_CBCR,
2621 .has_sibling = 0,
2622 .base = &virt_bases[GCC_BASE],
2623 .c = {
2624 .dbg_name = "gcc_camss_csi1phytimer_clk",
2625 .parent = &csi1phytimer_clk_src.c,
2626 .ops = &clk_ops_branch,
2627 CLK_INIT(gcc_camss_csi1phytimer_clk.c),
2628 },
2629};
2630
2631static struct branch_clk gcc_camss_ahb_clk = {
2632 .cbcr_reg = CAMSS_AHB_CBCR,
2633 .has_sibling = 1,
2634 .base = &virt_bases[GCC_BASE],
2635 .c = {
2636 .dbg_name = "gcc_camss_ahb_clk",
2637 .ops = &clk_ops_branch,
2638 CLK_INIT(gcc_camss_ahb_clk.c),
2639 },
2640};
2641
2642static struct branch_clk gcc_camss_top_ahb_clk = {
2643 .cbcr_reg = CAMSS_TOP_AHB_CBCR,
2644 .has_sibling = 1,
2645 .base = &virt_bases[GCC_BASE],
2646 .c = {
2647 .dbg_name = "gcc_camss_top_ahb_clk",
2648 .parent = &camss_top_ahb_clk_src.c,
2649 .ops = &clk_ops_branch,
2650 CLK_INIT(gcc_camss_top_ahb_clk.c),
2651 },
2652};
2653
2654static struct branch_clk gcc_camss_vfe0_clk = {
2655 .cbcr_reg = CAMSS_VFE0_CBCR,
2656 .has_sibling = 1,
2657 .base = &virt_bases[GCC_BASE],
2658 .c = {
2659 .dbg_name = "gcc_camss_vfe0_clk",
2660 .parent = &vfe0_clk_src.c,
2661 .ops = &clk_ops_branch,
2662 CLK_INIT(gcc_camss_vfe0_clk.c),
2663 },
2664};
2665
2666static struct branch_clk gcc_camss_vfe_ahb_clk = {
2667 .cbcr_reg = CAMSS_VFE_AHB_CBCR,
2668 .has_sibling = 1,
2669 .base = &virt_bases[GCC_BASE],
2670 .c = {
2671 .dbg_name = "gcc_camss_vfe_ahb_clk",
2672 .ops = &clk_ops_branch,
2673 CLK_INIT(gcc_camss_vfe_ahb_clk.c),
2674 },
2675};
2676
2677static struct branch_clk gcc_camss_vfe_axi_clk = {
2678 .cbcr_reg = CAMSS_VFE_AXI_CBCR,
2679 .has_sibling = 1,
2680 .base = &virt_bases[GCC_BASE],
2681 .c = {
2682 .dbg_name = "gcc_camss_vfe_axi_clk",
2683 .ops = &clk_ops_branch,
2684 CLK_INIT(gcc_camss_vfe_axi_clk.c),
2685 },
2686};
2687
2688static struct branch_clk gcc_camss_vfe1_ahb_clk = {
2689 .cbcr_reg = CAMSS_VFE1_AHB_CBCR,
2690 .has_sibling = 1,
2691 .base = &virt_bases[GCC_BASE],
2692 .c = {
2693 .dbg_name = "gcc_camss_vfe1_ahb_clk",
2694 .parent = &camss_top_ahb_clk_src.c,
2695 .ops = &clk_ops_branch,
2696 CLK_INIT(gcc_camss_vfe1_ahb_clk.c),
2697 },
2698};
2699
2700static struct branch_clk gcc_camss_vfe1_axi_clk = {
2701 .cbcr_reg = CAMSS_VFE1_AXI_CBCR,
2702 .has_sibling = 1,
2703 .base = &virt_bases[GCC_BASE],
2704 .c = {
2705 .dbg_name = "gcc_camss_vfe1_axi_clk",
2706 .ops = &clk_ops_branch,
2707 CLK_INIT(gcc_camss_vfe1_axi_clk.c),
2708 },
2709};
2710
2711static struct branch_clk gcc_camss_vfe1_clk = {
2712 .cbcr_reg = CAMSS_VFE1_CBCR,
2713 .has_sibling = 1,
2714 .base = &virt_bases[GCC_BASE],
2715 .c = {
2716 .dbg_name = "gcc_camss_vfe1_clk",
2717 .parent = &vfe1_clk_src.c,
2718 .ops = &clk_ops_branch,
2719 CLK_INIT(gcc_camss_vfe1_clk.c),
2720 },
2721};
2722
2723static struct local_vote_clk gcc_crypto_ahb_clk = {
2724 .cbcr_reg = CRYPTO_AHB_CBCR,
2725 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2726 .en_mask = BIT(0),
2727 .base = &virt_bases[GCC_BASE],
2728 .c = {
2729 .dbg_name = "gcc_crypto_ahb_clk",
2730 .parent = &crypto_clk_src.c,
2731 .ops = &clk_ops_vote,
2732 CLK_INIT(gcc_crypto_ahb_clk.c),
2733 },
2734};
2735
2736static struct local_vote_clk gcc_crypto_axi_clk = {
2737 .cbcr_reg = CRYPTO_AXI_CBCR,
2738 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2739 .en_mask = BIT(1),
2740 .base = &virt_bases[GCC_BASE],
2741 .c = {
2742 .dbg_name = "gcc_crypto_axi_clk",
2743 .ops = &clk_ops_vote,
2744 CLK_INIT(gcc_crypto_axi_clk.c),
2745 },
2746};
2747
2748static struct local_vote_clk gcc_crypto_clk = {
2749 .cbcr_reg = CRYPTO_CBCR,
2750 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
2751 .en_mask = BIT(2),
2752 .base = &virt_bases[GCC_BASE],
2753 .c = {
2754 .dbg_name = "gcc_crypto_clk",
2755 .parent = &crypto_clk_src.c,
2756 .ops = &clk_ops_vote,
2757 CLK_INIT(gcc_crypto_clk.c),
2758 },
2759};
2760
2761static struct gate_clk gcc_oxili_gmem_clk = {
2762 .en_reg = OXILI_GMEM_CBCR,
2763 .en_mask = BIT(0),
2764 .delay_us = 50,
2765 .base = &virt_bases[GCC_BASE],
2766 .c = {
2767 .dbg_name = "gcc_oxili_gmem_clk",
2768 .parent = &gfx3d_clk_src.c,
2769 .ops = &clk_ops_gate,
2770 CLK_INIT(gcc_oxili_gmem_clk.c),
2771 },
2772};
2773
2774static struct branch_clk gcc_gp1_clk = {
2775 .cbcr_reg = GP1_CBCR,
2776 .has_sibling = 0,
2777 .base = &virt_bases[GCC_BASE],
2778 .c = {
2779 .dbg_name = "gcc_gp1_clk",
2780 .parent = &gp1_clk_src.c,
2781 .ops = &clk_ops_branch,
2782 CLK_INIT(gcc_gp1_clk.c),
2783 },
2784};
2785
2786static struct branch_clk gcc_gp2_clk = {
2787 .cbcr_reg = GP2_CBCR,
2788 .has_sibling = 0,
2789 .base = &virt_bases[GCC_BASE],
2790 .c = {
2791 .dbg_name = "gcc_gp2_clk",
2792 .parent = &gp2_clk_src.c,
2793 .ops = &clk_ops_branch,
2794 CLK_INIT(gcc_gp2_clk.c),
2795 },
2796};
2797
2798static struct branch_clk gcc_gp3_clk = {
2799 .cbcr_reg = GP3_CBCR,
2800 .has_sibling = 0,
2801 .base = &virt_bases[GCC_BASE],
2802 .c = {
2803 .dbg_name = "gcc_gp3_clk",
2804 .parent = &gp3_clk_src.c,
2805 .ops = &clk_ops_branch,
2806 CLK_INIT(gcc_gp3_clk.c),
2807 },
2808};
2809
2810static struct branch_clk gcc_mdss_ahb_clk = {
2811 .cbcr_reg = MDSS_AHB_CBCR,
2812 .has_sibling = 1,
2813 .base = &virt_bases[GCC_BASE],
2814 .c = {
2815 .dbg_name = "gcc_mdss_ahb_clk",
2816 .ops = &clk_ops_branch,
2817 CLK_INIT(gcc_mdss_ahb_clk.c),
2818 },
2819};
2820
2821static struct branch_clk gcc_mdss_axi_clk = {
2822 .cbcr_reg = MDSS_AXI_CBCR,
2823 .has_sibling = 1,
2824 .base = &virt_bases[GCC_BASE],
2825 .c = {
2826 .dbg_name = "gcc_mdss_axi_clk",
2827 .ops = &clk_ops_branch,
2828 CLK_INIT(gcc_mdss_axi_clk.c),
2829 },
2830};
2831
2832static struct branch_clk gcc_mdss_byte0_clk = {
2833 .cbcr_reg = MDSS_BYTE0_CBCR,
2834 .has_sibling = 0,
2835 .base = &virt_bases[GCC_BASE],
2836 .c = {
2837 .dbg_name = "gcc_mdss_byte0_clk",
2838 .parent = &byte0_clk_src.c,
2839 .ops = &clk_ops_branch,
2840 .flags = CLKFLAG_NO_RATE_CACHE,
2841 CLK_INIT(gcc_mdss_byte0_clk.c),
2842 },
2843};
2844
2845static struct branch_clk gcc_mdss_byte1_clk = {
2846 .cbcr_reg = MDSS_BYTE1_CBCR,
2847 .has_sibling = 0,
2848 .base = &virt_bases[GCC_BASE],
2849 .c = {
2850 .dbg_name = "gcc_mdss_byte1_clk",
2851 .parent = &byte1_clk_src.c,
2852 .ops = &clk_ops_branch,
2853 .flags = CLKFLAG_NO_RATE_CACHE,
2854 CLK_INIT(gcc_mdss_byte1_clk.c),
2855 },
2856};
2857
2858static struct branch_clk gcc_mdss_esc0_clk = {
2859 .cbcr_reg = MDSS_ESC0_CBCR,
2860 .has_sibling = 0,
2861 .base = &virt_bases[GCC_BASE],
2862 .c = {
2863 .dbg_name = "gcc_mdss_esc0_clk",
2864 .parent = &esc0_clk_src.c,
2865 .ops = &clk_ops_branch,
2866 CLK_INIT(gcc_mdss_esc0_clk.c),
2867 },
2868};
2869
2870static struct branch_clk gcc_mdss_esc1_clk = {
2871 .cbcr_reg = MDSS_ESC1_CBCR,
2872 .has_sibling = 0,
2873 .base = &virt_bases[GCC_BASE],
2874 .c = {
2875 .dbg_name = "gcc_mdss_esc1_clk",
2876 .parent = &esc1_clk_src.c,
2877 .ops = &clk_ops_branch,
2878 CLK_INIT(gcc_mdss_esc1_clk.c),
2879 },
2880};
2881
2882static struct branch_clk gcc_mdss_mdp_clk = {
2883 .cbcr_reg = MDSS_MDP_CBCR,
2884 .has_sibling = 0,
2885 .base = &virt_bases[GCC_BASE],
2886 .c = {
2887 .dbg_name = "gcc_mdss_mdp_clk",
2888 .parent = &mdp_clk_src.c,
2889 .ops = &clk_ops_branch,
2890 CLK_INIT(gcc_mdss_mdp_clk.c),
2891 },
2892};
2893
2894static DEFINE_CLK_VOTER(mdss_mdp_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2895static DEFINE_CLK_VOTER(mdss_rotator_vote_clk, &gcc_mdss_mdp_clk.c, 0);
2896
2897static struct branch_clk gcc_mdss_pclk0_clk = {
2898 .cbcr_reg = MDSS_PCLK0_CBCR,
2899 .has_sibling = 0,
2900 .base = &virt_bases[GCC_BASE],
2901 .c = {
2902 .dbg_name = "gcc_mdss_pclk0_clk",
2903 .parent = &pclk0_clk_src.c,
2904 .ops = &clk_ops_branch,
2905 .flags = CLKFLAG_NO_RATE_CACHE,
2906 CLK_INIT(gcc_mdss_pclk0_clk.c),
2907 },
2908};
2909
2910static struct branch_clk gcc_mdss_pclk1_clk = {
2911 .cbcr_reg = MDSS_PCLK1_CBCR,
2912 .has_sibling = 0,
2913 .base = &virt_bases[GCC_BASE],
2914 .c = {
2915 .dbg_name = "gcc_mdss_pclk1_clk",
2916 .parent = &pclk1_clk_src.c,
2917 .ops = &clk_ops_branch,
2918 .flags = CLKFLAG_NO_RATE_CACHE,
2919 CLK_INIT(gcc_mdss_pclk1_clk.c),
2920 },
2921};
2922
2923static struct branch_clk gcc_mdss_vsync_clk = {
2924 .cbcr_reg = MDSS_VSYNC_CBCR,
2925 .has_sibling = 0,
2926 .base = &virt_bases[GCC_BASE],
2927 .c = {
2928 .dbg_name = "gcc_mdss_vsync_clk",
2929 .parent = &vsync_clk_src.c,
2930 .ops = &clk_ops_branch,
2931 CLK_INIT(gcc_mdss_vsync_clk.c),
2932 },
2933};
2934
2935static struct branch_clk gcc_mss_cfg_ahb_clk = {
2936 .cbcr_reg = MSS_CFG_AHB_CBCR,
2937 .has_sibling = 1,
2938 .base = &virt_bases[GCC_BASE],
2939 .c = {
2940 .dbg_name = "gcc_mss_cfg_ahb_clk",
2941 .ops = &clk_ops_branch,
2942 CLK_INIT(gcc_mss_cfg_ahb_clk.c),
2943 },
2944};
2945
2946static struct branch_clk gcc_mss_q6_bimc_axi_clk = {
2947 .cbcr_reg = MSS_Q6_BIMC_AXI_CBCR,
2948 .has_sibling = 1,
2949 .base = &virt_bases[GCC_BASE],
2950 .c = {
2951 .dbg_name = "gcc_mss_q6_bimc_axi_clk",
2952 .ops = &clk_ops_branch,
2953 CLK_INIT(gcc_mss_q6_bimc_axi_clk.c),
2954 },
2955};
2956
2957static struct local_vote_clk gcc_apss_tcu_clk;
2958static struct branch_clk gcc_bimc_gfx_clk = {
2959 .cbcr_reg = BIMC_GFX_CBCR,
2960 .has_sibling = 1,
2961 .base = &virt_bases[GCC_BASE],
2962 .c = {
2963 .dbg_name = "gcc_bimc_gfx_clk",
2964 .ops = &clk_ops_branch,
2965 CLK_INIT(gcc_bimc_gfx_clk.c),
2966 .depends = &gcc_apss_tcu_clk.c,
2967 },
2968};
2969
2970static struct branch_clk gcc_oxili_ahb_clk = {
2971 .cbcr_reg = OXILI_AHB_CBCR,
2972 .has_sibling = 1,
2973 .base = &virt_bases[GCC_BASE],
2974 .c = {
2975 .dbg_name = "gcc_oxili_ahb_clk",
2976 .ops = &clk_ops_branch,
2977 CLK_INIT(gcc_oxili_ahb_clk.c),
2978 },
2979};
2980
2981static struct branch_clk gcc_oxili_gfx3d_clk = {
2982 .cbcr_reg = OXILI_GFX3D_CBCR,
2983 .has_sibling = 0,
2984 .base = &virt_bases[GCC_BASE],
2985 .c = {
2986 .dbg_name = "gcc_oxili_gfx3d_clk",
2987 .parent = &gfx3d_clk_src.c,
2988 .ops = &clk_ops_branch,
2989 CLK_INIT(gcc_oxili_gfx3d_clk.c),
2990 },
2991};
2992
2993static struct branch_clk gcc_oxili_timer_clk = {
2994 .cbcr_reg = OXILI_TIMER_CBCR,
2995 .has_sibling = 0,
2996 .base = &virt_bases[GCC_BASE],
2997 .c = {
2998 .dbg_name = "gcc_oxili_timer_clk",
2999 .parent = &xo_clk_src.c,
3000 .ops = &clk_ops_branch,
3001 CLK_INIT(gcc_oxili_timer_clk.c),
3002 },
3003};
3004
3005static struct branch_clk gcc_oxili_aon_clk = {
3006 .cbcr_reg = OXILI_AON_CBCR,
3007 .has_sibling = 0,
3008 .base = &virt_bases[GCC_BASE],
3009 .c = {
3010 .dbg_name = "gcc_oxili_aon_clk",
3011 .parent = &gfx3d_clk_src.c,
3012 .ops = &clk_ops_branch,
3013 CLK_INIT(gcc_oxili_aon_clk.c),
3014 },
3015};
3016
3017static struct branch_clk gcc_pdm2_clk = {
3018 .cbcr_reg = PDM2_CBCR,
3019 .has_sibling = 0,
3020 .base = &virt_bases[GCC_BASE],
3021 .c = {
3022 .dbg_name = "gcc_pdm2_clk",
3023 .parent = &pdm2_clk_src.c,
3024 .ops = &clk_ops_branch,
3025 CLK_INIT(gcc_pdm2_clk.c),
3026 },
3027};
3028
3029static struct branch_clk gcc_pdm_ahb_clk = {
3030 .cbcr_reg = PDM_AHB_CBCR,
3031 .has_sibling = 1,
3032 .base = &virt_bases[GCC_BASE],
3033 .c = {
3034 .dbg_name = "gcc_pdm_ahb_clk",
3035 .ops = &clk_ops_branch,
3036 CLK_INIT(gcc_pdm_ahb_clk.c),
3037 },
3038};
3039
3040static struct local_vote_clk gcc_prng_ahb_clk = {
3041 .cbcr_reg = PRNG_AHB_CBCR,
3042 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3043 .en_mask = BIT(8),
3044 .base = &virt_bases[GCC_BASE],
3045 .c = {
3046 .dbg_name = "gcc_prng_ahb_clk",
3047 .ops = &clk_ops_vote,
3048 CLK_INIT(gcc_prng_ahb_clk.c),
3049 },
3050};
3051
3052static struct local_vote_clk gcc_qdss_dap_clk = {
3053 .cbcr_reg = QDSS_DAP_CBCR,
3054 .vote_reg = APCS_CLOCK_BRANCH_ENA_VOTE,
3055 .en_mask = BIT(21),
3056 .base = &virt_bases[GCC_BASE],
3057 .c = {
3058 .dbg_name = "gcc_qdss_dap_clk",
3059 .ops = &clk_ops_vote,
3060 CLK_INIT(gcc_qdss_dap_clk.c),
3061 },
3062};
3063
3064static struct branch_clk gcc_sdcc1_ahb_clk = {
3065 .cbcr_reg = SDCC1_AHB_CBCR,
3066 .has_sibling = 1,
3067 .base = &virt_bases[GCC_BASE],
3068 .c = {
3069 .dbg_name = "gcc_sdcc1_ahb_clk",
3070 .ops = &clk_ops_branch,
3071 CLK_INIT(gcc_sdcc1_ahb_clk.c),
3072 },
3073};
3074
3075static struct branch_clk gcc_sdcc1_apps_clk = {
3076 .cbcr_reg = SDCC1_APPS_CBCR,
3077 .has_sibling = 0,
3078 .base = &virt_bases[GCC_BASE],
3079 .c = {
3080 .dbg_name = "gcc_sdcc1_apps_clk",
3081 .parent = &sdcc1_apps_clk_src.c,
3082 .ops = &clk_ops_branch,
3083 CLK_INIT(gcc_sdcc1_apps_clk.c),
3084 },
3085};
3086
3087static struct branch_clk gcc_sdcc1_ice_core_clk = {
3088 .cbcr_reg = SDCC1_ICE_CORE_CBCR,
3089 .has_sibling = 0,
3090 .base = &virt_bases[GCC_BASE],
3091 .c = {
3092 .dbg_name = "gcc_sdcc1_ice_core_clk",
3093 .parent = &sdcc1_ice_core_clk_src.c,
3094 .ops = &clk_ops_branch,
3095 CLK_INIT(gcc_sdcc1_ice_core_clk.c),
3096 }
3097};
3098
3099static struct branch_clk gcc_sdcc2_ahb_clk = {
3100 .cbcr_reg = SDCC2_AHB_CBCR,
3101 .has_sibling = 1,
3102 .base = &virt_bases[GCC_BASE],
3103 .c = {
3104 .dbg_name = "gcc_sdcc2_ahb_clk",
3105 .ops = &clk_ops_branch,
3106 CLK_INIT(gcc_sdcc2_ahb_clk.c),
3107 },
3108};
3109
3110static struct branch_clk gcc_sdcc2_apps_clk = {
3111 .cbcr_reg = SDCC2_APPS_CBCR,
3112 .has_sibling = 0,
3113 .base = &virt_bases[GCC_BASE],
3114 .c = {
3115 .dbg_name = "gcc_sdcc2_apps_clk",
3116 .parent = &sdcc2_apps_clk_src.c,
3117 .ops = &clk_ops_branch,
3118 CLK_INIT(gcc_sdcc2_apps_clk.c),
3119 },
3120};
3121
3122static struct local_vote_clk gcc_cpp_tbu_clk = {
3123 .cbcr_reg = CPP_TBU_CBCR,
3124 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3125 .en_mask = BIT(14),
3126 .base = &virt_bases[GCC_BASE],
3127 .c = {
3128 .dbg_name = "gcc_cpp_tbu_clk",
3129 .ops = &clk_ops_vote,
3130 CLK_INIT(gcc_cpp_tbu_clk.c),
3131 },
3132};
3133
3134static struct local_vote_clk gcc_gfx_tbu_clk = {
3135 .cbcr_reg = GFX_TBU_CBCR,
3136 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3137 .en_mask = BIT(3),
3138 .base = &virt_bases[GCC_BASE],
3139 .c = {
3140 .dbg_name = "gcc_gfx_tbu_clk",
3141 .ops = &clk_ops_vote,
3142 CLK_INIT(gcc_gfx_tbu_clk.c),
3143 },
3144};
3145
3146static struct local_vote_clk gcc_gfx_tcu_clk = {
3147 .cbcr_reg = GFX_TCU_CBCR,
3148 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3149 .en_mask = BIT(2),
3150 .base = &virt_bases[GCC_BASE],
3151 .c = {
3152 .dbg_name = "gcc_gfx_tcu_clk",
3153 .ops = &clk_ops_vote,
3154 CLK_INIT(gcc_gfx_tcu_clk.c),
3155 },
3156};
3157
3158static struct local_vote_clk gcc_apss_tcu_clk = {
3159 .cbcr_reg = APSS_TCU_CBCR,
3160 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3161 .en_mask = BIT(1),
3162 .base = &virt_bases[GCC_BASE],
3163 .c = {
3164 .dbg_name = "gcc_apss_tcu_clk",
3165 .ops = &clk_ops_vote,
3166 CLK_INIT(gcc_apss_tcu_clk.c),
3167 },
3168};
3169
3170static struct local_vote_clk gcc_gtcu_ahb_clk = {
3171 .cbcr_reg = GTCU_AHB_CBCR,
3172 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3173 .en_mask = BIT(13),
3174 .base = &virt_bases[GCC_BASE],
3175 .c = {
3176 .dbg_name = "gcc_gtcu_ahb_clk",
3177 .ops = &clk_ops_vote,
3178 CLK_INIT(gcc_gtcu_ahb_clk.c),
3179 },
3180};
3181
3182static struct local_vote_clk gcc_ipa_tbu_clk = {
3183 .cbcr_reg = IPA_TBU_CBCR,
3184 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3185 .en_mask = BIT(16),
3186 .base = &virt_bases[GCC_BASE],
3187 .c = {
3188 .dbg_name = "gcc_ipa_tbu_clk",
3189 .ops = &clk_ops_vote,
3190 CLK_INIT(gcc_ipa_tbu_clk.c),
3191 },
3192};
3193
3194static struct local_vote_clk gcc_jpeg_tbu_clk = {
3195 .cbcr_reg = JPEG_TBU_CBCR,
3196 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3197 .en_mask = BIT(10),
3198 .base = &virt_bases[GCC_BASE],
3199 .c = {
3200 .dbg_name = "gcc_jpeg_tbu_clk",
3201 .ops = &clk_ops_vote,
3202 CLK_INIT(gcc_jpeg_tbu_clk.c),
3203 },
3204};
3205
3206static struct local_vote_clk gcc_mdp_tbu_clk = {
3207 .cbcr_reg = MDP_TBU_CBCR,
3208 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3209 .en_mask = BIT(4),
3210 .base = &virt_bases[GCC_BASE],
3211 .c = {
3212 .dbg_name = "gcc_mdp_tbu_clk",
3213 .ops = &clk_ops_vote,
3214 CLK_INIT(gcc_mdp_tbu_clk.c),
3215 },
3216};
3217
3218static struct local_vote_clk gcc_smmu_cfg_clk = {
3219 .cbcr_reg = SMMU_CFG_CBCR,
3220 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3221 .en_mask = BIT(12),
3222 .base = &virt_bases[GCC_BASE],
3223 .c = {
3224 .dbg_name = "gcc_smmu_cfg_clk",
3225 .ops = &clk_ops_vote,
3226 CLK_INIT(gcc_smmu_cfg_clk.c),
3227 },
3228};
3229
3230static struct local_vote_clk gcc_venus_tbu_clk = {
3231 .cbcr_reg = VENUS_TBU_CBCR,
3232 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3233 .en_mask = BIT(5),
3234 .base = &virt_bases[GCC_BASE],
3235 .c = {
3236 .dbg_name = "gcc_venus_tbu_clk",
3237 .ops = &clk_ops_vote,
3238 CLK_INIT(gcc_venus_tbu_clk.c),
3239 },
3240};
3241
3242static struct local_vote_clk gcc_vfe1_tbu_clk = {
3243 .cbcr_reg = VFE1_TBU_CBCR,
3244 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3245 .en_mask = BIT(17),
3246 .base = &virt_bases[GCC_BASE],
3247 .c = {
3248 .dbg_name = "gcc_vfe1_tbu_clk",
3249 .ops = &clk_ops_vote,
3250 CLK_INIT(gcc_vfe1_tbu_clk.c),
3251 },
3252};
3253
3254static struct local_vote_clk gcc_vfe_tbu_clk = {
3255 .cbcr_reg = VFE_TBU_CBCR,
3256 .vote_reg = APCS_SMMU_CLOCK_BRANCH_ENA_VOTE,
3257 .en_mask = BIT(9),
3258 .base = &virt_bases[GCC_BASE],
3259 .c = {
3260 .dbg_name = "gcc_vfe_tbu_clk",
3261 .ops = &clk_ops_vote,
3262 CLK_INIT(gcc_vfe_tbu_clk.c),
3263 },
3264};
3265
3266static struct branch_clk gcc_usb2a_phy_sleep_clk = {
3267 .cbcr_reg = USB2A_PHY_SLEEP_CBCR,
3268 .has_sibling = 1,
3269 .base = &virt_bases[GCC_BASE],
3270 .c = {
3271 .dbg_name = "gcc_usb2a_phy_sleep_clk",
3272 .ops = &clk_ops_branch,
3273 CLK_INIT(gcc_usb2a_phy_sleep_clk.c),
3274 },
3275};
3276
3277static struct branch_clk gcc_usb_hs_phy_cfg_ahb_clk = {
3278 .cbcr_reg = USB_HS_PHY_CFG_AHB_CBCR,
3279 .has_sibling = 1,
3280 .base = &virt_bases[GCC_BASE],
3281 .c = {
3282 .dbg_name = "gcc_usb_hs_phy_cfg_ahb_clk",
3283 .ops = &clk_ops_branch,
3284 CLK_INIT(gcc_usb_hs_phy_cfg_ahb_clk.c),
3285 },
3286};
3287
3288static struct branch_clk gcc_usb_fs_ahb_clk = {
3289 .cbcr_reg = USB_FS_AHB_CBCR,
3290 .has_sibling = 1,
3291 .base = &virt_bases[GCC_BASE],
3292 .c = {
3293 .dbg_name = "gcc_usb_fs_ahb_clk",
3294 .ops = &clk_ops_branch,
3295 CLK_INIT(gcc_usb_fs_ahb_clk.c),
3296 },
3297};
3298
3299static struct branch_clk gcc_usb_fs_ic_clk = {
3300 .cbcr_reg = USB_FS_IC_CBCR,
3301 .has_sibling = 0,
3302 .base = &virt_bases[GCC_BASE],
3303 .c = {
3304 .dbg_name = "gcc_usb_fs_ic_clk",
3305 .parent = &usb_fs_ic_clk_src.c,
3306 .ops = &clk_ops_branch,
3307 CLK_INIT(gcc_usb_fs_ic_clk.c),
3308 },
3309};
3310
3311static struct branch_clk gcc_usb_fs_system_clk = {
3312 .cbcr_reg = USB_FS_SYSTEM_CBCR,
3313 .bcr_reg = USB_FS_BCR,
3314 .has_sibling = 0,
3315 .base = &virt_bases[GCC_BASE],
3316 .c = {
3317 .dbg_name = "gcc_usb_fs_system_clk",
3318 .parent = &usb_fs_system_clk_src.c,
3319 .ops = &clk_ops_branch,
3320 CLK_INIT(gcc_usb_fs_system_clk.c),
3321 },
3322};
3323
3324static struct branch_clk gcc_usb_hs_ahb_clk = {
3325 .cbcr_reg = USB_HS_AHB_CBCR,
3326 .has_sibling = 1,
3327 .base = &virt_bases[GCC_BASE],
3328 .c = {
3329 .dbg_name = "gcc_usb_hs_ahb_clk",
3330 .ops = &clk_ops_branch,
3331 CLK_INIT(gcc_usb_hs_ahb_clk.c),
3332 },
3333};
3334
3335static struct branch_clk gcc_usb_hs_system_clk = {
3336 .cbcr_reg = USB_HS_SYSTEM_CBCR,
3337 .bcr_reg = USB_HS_BCR,
3338 .has_sibling = 0,
3339 .base = &virt_bases[GCC_BASE],
3340 .c = {
3341 .dbg_name = "gcc_usb_hs_system_clk",
3342 .parent = &usb_hs_system_clk_src.c,
3343 .ops = &clk_ops_branch,
3344 CLK_INIT(gcc_usb_hs_system_clk.c),
3345 },
3346};
3347
3348static struct reset_clk gcc_usb2_hs_phy_only_clk = {
3349 .reset_reg = USB2_HS_PHY_ONLY_BCR,
3350 .base = &virt_bases[GCC_BASE],
3351 .c = {
3352 .dbg_name = "gcc_usb2_hs_phy_only_clk",
3353 .ops = &clk_ops_rst,
3354 CLK_INIT(gcc_usb2_hs_phy_only_clk.c),
3355 },
3356};
3357
3358static struct reset_clk gcc_qusb2_phy_clk = {
3359 .reset_reg = QUSB2_PHY_BCR,
3360 .base = &virt_bases[GCC_BASE],
3361 .c = {
3362 .dbg_name = "gcc_qusb2_phy_clk",
3363 .ops = &clk_ops_rst,
3364 CLK_INIT(gcc_qusb2_phy_clk.c),
3365 },
3366};
3367
3368static struct branch_clk gcc_venus0_ahb_clk = {
3369 .cbcr_reg = VENUS0_AHB_CBCR,
3370 .has_sibling = 1,
3371 .base = &virt_bases[GCC_BASE],
3372 .c = {
3373 .dbg_name = "gcc_venus0_ahb_clk",
3374 .ops = &clk_ops_branch,
3375 CLK_INIT(gcc_venus0_ahb_clk.c),
3376 },
3377};
3378
3379static struct branch_clk gcc_venus0_axi_clk = {
3380 .cbcr_reg = VENUS0_AXI_CBCR,
3381 .has_sibling = 1,
3382 .base = &virt_bases[GCC_BASE],
3383 .c = {
3384 .dbg_name = "gcc_venus0_axi_clk",
3385 .ops = &clk_ops_branch,
3386 CLK_INIT(gcc_venus0_axi_clk.c),
3387 },
3388};
3389
3390static struct branch_clk gcc_venus0_core0_vcodec0_clk = {
3391 .cbcr_reg = VENUS0_CORE0_VCODEC0_CBCR,
3392 .has_sibling = 1,
3393 .base = &virt_bases[GCC_BASE],
3394 .c = {
3395 .dbg_name = "gcc_venus0_core0_vcodec0_clk",
3396 .parent = &vcodec0_clk_src.c,
3397 .ops = &clk_ops_branch,
3398 CLK_INIT(gcc_venus0_core0_vcodec0_clk.c),
3399 },
3400};
3401
3402static struct branch_clk gcc_venus0_core1_vcodec0_clk = {
3403 .cbcr_reg = VENUS0_CORE1_VCODEC0_CBCR,
3404 .has_sibling = 1,
3405 .base = &virt_bases[GCC_BASE],
3406 .c = {
3407 .dbg_name = "gcc_venus0_core1_vcodec0_clk",
3408 .parent = &vcodec0_clk_src.c,
3409 .ops = &clk_ops_branch,
3410 CLK_INIT(gcc_venus0_core1_vcodec0_clk.c),
3411 },
3412};
3413
3414static struct branch_clk gcc_venus0_vcodec0_clk = {
3415 .cbcr_reg = VENUS0_VCODEC0_CBCR,
3416 .has_sibling = 0,
3417 .base = &virt_bases[GCC_BASE],
3418 .c = {
3419 .dbg_name = "gcc_venus0_vcodec0_clk",
3420 .parent = &vcodec0_clk_src.c,
3421 .ops = &clk_ops_branch,
3422 CLK_INIT(gcc_venus0_vcodec0_clk.c),
3423 },
3424};
3425
3426static struct clk_ops clk_ops_debug_mux;
3427
3428static void __iomem *meas_base;
3429
3430static struct measure_clk apc0_m_clk = {
3431 .c = {
3432 .ops = &clk_ops_empty,
3433 .dbg_name = "apc0_m_clk",
3434 CLK_INIT(apc0_m_clk.c),
3435 },
3436};
3437
3438static struct measure_clk apc1_m_clk = {
3439 .c = {
3440 .ops = &clk_ops_empty,
3441 .dbg_name = "apc1_m_clk",
3442 CLK_INIT(apc1_m_clk.c),
3443 },
3444};
3445
3446static struct measure_clk cci_m_clk = {
3447 .c = {
3448 .ops = &clk_ops_empty,
3449 .dbg_name = "cci_m_clk",
3450 CLK_INIT(cci_m_clk.c),
3451 },
3452};
3453
3454static struct mux_clk apss_debug_ter_mux = {
3455 .ops = &mux_reg_ops,
3456 .mask = 0x3,
3457 .shift = 8,
3458 MUX_SRC_LIST(
3459 {&apc0_m_clk.c, 0},
3460 {&apc1_m_clk.c, 1},
3461 {&cci_m_clk.c, 2},
3462 ),
3463 .base = &meas_base,
3464 .c = {
3465 .dbg_name = "apss_debug_ter_mux",
3466 .ops = &clk_ops_gen_mux,
3467 CLK_INIT(apss_debug_ter_mux.c),
3468 },
3469};
3470
3471static struct mux_clk apss_debug_sec_mux = {
3472 .ops = &mux_reg_ops,
3473 .mask = 0x7,
3474 .shift = 12,
3475 MUX_SRC_LIST(
3476 {&apss_debug_ter_mux.c, 0},
3477 ),
3478 MUX_REC_SRC_LIST(
3479 &apss_debug_ter_mux.c,
3480 ),
3481 .base = &meas_base,
3482 .c = {
3483 .dbg_name = "apss_debug_sec_mux",
3484 .ops = &clk_ops_gen_mux,
3485 CLK_INIT(apss_debug_sec_mux.c),
3486 },
3487};
3488
3489static struct mux_clk apss_debug_pri_mux = {
3490 .ops = &mux_reg_ops,
3491 .mask = 0x3,
3492 .shift = 16,
3493 MUX_SRC_LIST(
3494 {&apss_debug_sec_mux.c, 0},
3495 ),
3496 MUX_REC_SRC_LIST(
3497 &apss_debug_sec_mux.c,
3498 ),
3499 .base = &meas_base,
3500 .c = {
3501 .dbg_name = "apss_debug_pri_mux",
3502 .ops = &clk_ops_gen_mux,
3503 CLK_INIT(apss_debug_pri_mux.c),
3504 },
3505};
3506
3507static struct measure_clk_data debug_mux_priv = {
3508 .cxo = &xo_clk_src.c,
3509 .plltest_reg = GCC_PLLTEST_PAD_CFG,
3510 .plltest_val = 0x51A00,
3511 .xo_div4_cbcr = GCC_XO_DIV4_CBCR,
3512 .ctl_reg = CLOCK_FRQ_MEASURE_CTL,
3513 .status_reg = CLOCK_FRQ_MEASURE_STATUS,
3514 .base = &virt_bases[GCC_BASE],
3515};
3516
3517static struct mux_clk gcc_debug_mux = {
3518 .priv = &debug_mux_priv,
3519 .ops = &mux_reg_ops,
3520 .offset = GCC_DEBUG_CLK_CTL,
3521 .mask = 0x1FF,
3522 .en_offset = GCC_DEBUG_CLK_CTL,
3523 .en_mask = BIT(16),
3524 .base = &virt_bases[GCC_BASE],
3525 MUX_REC_SRC_LIST(
3526 &apss_debug_pri_mux.c,
3527 ),
3528 MUX_SRC_LIST(
3529 { &apss_debug_pri_mux.c, 0x016A},
3530 { &snoc_clk.c, 0x0000 },
3531 { &sysmmnoc_clk.c, 0x0001 },
3532 { &pnoc_clk.c, 0x0008 },
3533 { &bimc_clk.c, 0x0154 },
3534 { &gcc_gp1_clk.c, 0x0010 },
3535 { &gcc_gp2_clk.c, 0x0011 },
3536 { &gcc_gp3_clk.c, 0x0012 },
3537 { &gcc_bimc_gfx_clk.c, 0x002d },
3538 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3539 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3540 { &gcc_apss_tcu_clk.c, 0x0050 },
3541 { &gcc_mdp_tbu_clk.c, 0x0051 },
3542 { &gcc_gfx_tbu_clk.c, 0x0052 },
3543 { &gcc_gfx_tcu_clk.c, 0x0053 },
3544 { &gcc_venus_tbu_clk.c, 0x0054 },
3545 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3546 { &gcc_vfe_tbu_clk.c, 0x005a },
3547 { &gcc_smmu_cfg_clk.c, 0x005b },
3548 { &gcc_jpeg_tbu_clk.c, 0x005c },
3549 { &gcc_usb_hs_system_clk.c, 0x0060 },
3550 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3551 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3552 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3553 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3554 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3555 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3556 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3557 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3558 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3559 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3560 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3561 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3562 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3563 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3564 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3565 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3566 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3567 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3568 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3569 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3570 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3571 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3572 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3573 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3574 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3575 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3576 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3577 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3578 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3579 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3580 { &gcc_camss_ahb_clk.c, 0x00a8 },
3581 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3582 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3583 { &gcc_camss_gp0_clk.c, 0x00ab },
3584 { &gcc_camss_gp1_clk.c, 0x00ac },
3585 { &gcc_camss_mclk0_clk.c, 0x00ad },
3586 { &gcc_camss_mclk1_clk.c, 0x00ae },
3587 { &gcc_camss_cci_clk.c, 0x00af },
3588 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3589 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3590 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3591 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3592 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3593 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3594 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3595 { &gcc_camss_cpp_clk.c, 0x00b9 },
3596 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3597 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3598 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3599 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3600 { &gcc_camss_csi0_clk.c, 0x00c0 },
3601 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3602 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3603 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3604 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3605 { &gcc_camss_csi1_clk.c, 0x00c5 },
3606 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3607 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3608 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3609 { &gcc_pdm2_clk.c, 0x00d2 },
3610 { &gcc_prng_ahb_clk.c, 0x00d8 },
3611 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3612 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3613 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3614 { &gcc_camss_csi2_clk.c, 0x00e3 },
3615 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3616 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3617 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3618 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3619 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3620 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3621 { &gcc_usb_fs_ahb_clk.c, 0x00f1 },
3622 { &gcc_usb_fs_ic_clk.c, 0x00f4 },
3623 { &gcc_crypto_clk.c, 0x0138 },
3624 { &gcc_crypto_axi_clk.c, 0x0139 },
3625 { &gcc_crypto_ahb_clk.c, 0x013a },
3626 { &gcc_bimc_gpu_clk.c, 0x0157 },
3627 { &gcc_ipa_tbu_clk.c, 0x0198 },
3628 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3629 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3630 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3631 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3632 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3633 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3634 { &gcc_venus0_core1_vcodec0_clk.c, 0x01b9 },
3635 { &gcc_camss_mclk2_clk.c, 0x01bd },
3636 { &gcc_oxili_timer_clk.c, 0x01e9 },
3637 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3638 { &gcc_oxili_ahb_clk.c, 0x01eb },
3639 { &gcc_oxili_gmem_clk.c, 0x01f0 },
3640 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3641 { &gcc_venus0_axi_clk.c, 0x01f2 },
3642 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3643 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3644 { &gcc_mdss_axi_clk.c, 0x01f7 },
3645 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3646 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3647 { &gcc_mdss_vsync_clk.c, 0x01fb },
3648 { &gcc_mdss_byte0_clk.c, 0x01fc },
3649 { &gcc_mdss_esc0_clk.c, 0x01fd },
3650 { &wcnss_m_clk.c, 0x0ec },
3651 ),
3652 .c = {
3653 .dbg_name = "gcc_debug_mux",
3654 .ops = &clk_ops_debug_mux,
3655 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3656 CLK_INIT(gcc_debug_mux.c),
3657 },
3658};
3659
3660static struct mux_clk gcc_debug_mux_8937 = {
3661 .priv = &debug_mux_priv,
3662 .ops = &mux_reg_ops,
3663 .offset = GCC_DEBUG_CLK_CTL,
3664 .mask = 0x1FF,
3665 .en_offset = GCC_DEBUG_CLK_CTL,
3666 .en_mask = BIT(16),
3667 .base = &virt_bases[GCC_BASE],
3668 MUX_REC_SRC_LIST(
3669 &apss_debug_pri_mux.c,
3670 ),
3671 MUX_SRC_LIST(
3672 { &apss_debug_pri_mux.c, 0x016A},
3673 { &snoc_clk.c, 0x0000 },
3674 { &sysmmnoc_clk.c, 0x0001 },
3675 { &pnoc_clk.c, 0x0008 },
3676 { &bimc_clk.c, 0x015A },
3677 { &ipa_clk.c, 0x1B0 },
3678 { &gcc_gp1_clk.c, 0x0010 },
3679 { &gcc_gp2_clk.c, 0x0011 },
3680 { &gcc_gp3_clk.c, 0x0012 },
3681 { &gcc_bimc_gfx_clk.c, 0x002d },
3682 { &gcc_mss_cfg_ahb_clk.c, 0x0030 },
3683 { &gcc_mss_q6_bimc_axi_clk.c, 0x0031 },
3684 { &gcc_qdss_dap_clk.c, 0x0049 },
3685 { &gcc_apss_tcu_clk.c, 0x0050 },
3686 { &gcc_mdp_tbu_clk.c, 0x0051 },
3687 { &gcc_gfx_tbu_clk.c, 0x0052 },
3688 { &gcc_gfx_tcu_clk.c, 0x0053 },
3689 { &gcc_venus_tbu_clk.c, 0x0054 },
3690 { &gcc_gtcu_ahb_clk.c, 0x0058 },
3691 { &gcc_vfe_tbu_clk.c, 0x005a },
3692 { &gcc_smmu_cfg_clk.c, 0x005b },
3693 { &gcc_jpeg_tbu_clk.c, 0x005c },
3694 { &gcc_usb_hs_system_clk.c, 0x0060 },
3695 { &gcc_usb_hs_ahb_clk.c, 0x0061 },
3696 { &gcc_usb2a_phy_sleep_clk.c, 0x0063 },
3697 { &gcc_usb_hs_phy_cfg_ahb_clk.c, 0x0064 },
3698 { &gcc_sdcc1_apps_clk.c, 0x0068 },
3699 { &gcc_sdcc1_ahb_clk.c, 0x0069 },
3700 { &gcc_sdcc1_ice_core_clk.c, 0x006a },
3701 { &gcc_sdcc2_apps_clk.c, 0x0070 },
3702 { &gcc_sdcc2_ahb_clk.c, 0x0071 },
3703 { &gcc_blsp1_ahb_clk.c, 0x0088 },
3704 { &gcc_blsp1_qup1_spi_apps_clk.c, 0x008a },
3705 { &gcc_blsp1_qup1_i2c_apps_clk.c, 0x008b },
3706 { &gcc_blsp1_uart1_apps_clk.c, 0x008c },
3707 { &gcc_blsp1_qup2_spi_apps_clk.c, 0x008e },
3708 { &gcc_blsp1_qup2_i2c_apps_clk.c, 0x0090 },
3709 { &gcc_blsp1_uart2_apps_clk.c, 0x0091 },
3710 { &gcc_blsp1_qup3_spi_apps_clk.c, 0x0093 },
3711 { &gcc_blsp1_qup3_i2c_apps_clk.c, 0x0094 },
3712 { &gcc_blsp1_qup4_spi_apps_clk.c, 0x0095 },
3713 { &gcc_blsp1_qup4_i2c_apps_clk.c, 0x0096 },
3714 { &gcc_blsp2_ahb_clk.c, 0x0098 },
3715 { &gcc_blsp2_qup1_spi_apps_clk.c, 0x009a },
3716 { &gcc_blsp2_qup1_i2c_apps_clk.c, 0x009b },
3717 { &gcc_blsp2_uart1_apps_clk.c, 0x009c },
3718 { &gcc_blsp2_qup2_spi_apps_clk.c, 0x009e },
3719 { &gcc_blsp2_qup2_i2c_apps_clk.c, 0x00a0 },
3720 { &gcc_blsp2_uart2_apps_clk.c, 0x00a1 },
3721 { &gcc_blsp2_qup3_spi_apps_clk.c, 0x00a3 },
3722 { &gcc_blsp2_qup3_i2c_apps_clk.c, 0x00a4 },
3723 { &gcc_blsp2_qup4_spi_apps_clk.c, 0x00a5 },
3724 { &gcc_blsp2_qup4_i2c_apps_clk.c, 0x00a6 },
3725 { &gcc_camss_ahb_clk.c, 0x00a8 },
3726 { &gcc_camss_top_ahb_clk.c, 0x00a9 },
3727 { &gcc_camss_micro_ahb_clk.c, 0x00aa },
3728 { &gcc_camss_gp0_clk.c, 0x00ab },
3729 { &gcc_camss_gp1_clk.c, 0x00ac },
3730 { &gcc_camss_mclk0_clk.c, 0x00ad },
3731 { &gcc_camss_mclk1_clk.c, 0x00ae },
3732 { &gcc_camss_cci_clk.c, 0x00af },
3733 { &gcc_camss_cci_ahb_clk.c, 0x00b0 },
3734 { &gcc_camss_csi0phytimer_clk.c, 0x00b1 },
3735 { &gcc_camss_csi1phytimer_clk.c, 0x00b2 },
3736 { &gcc_camss_jpeg0_clk.c, 0x00b3 },
3737 { &gcc_camss_jpeg_ahb_clk.c, 0x00b4 },
3738 { &gcc_camss_jpeg_axi_clk.c, 0x00b5 },
3739 { &gcc_camss_vfe0_clk.c, 0x00b8 },
3740 { &gcc_camss_cpp_clk.c, 0x00b9 },
3741 { &gcc_camss_cpp_ahb_clk.c, 0x00ba },
3742 { &gcc_camss_vfe_ahb_clk.c, 0x00bb },
3743 { &gcc_camss_vfe_axi_clk.c, 0x00bc },
3744 { &gcc_camss_csi_vfe0_clk.c, 0x00bf },
3745 { &gcc_camss_csi0_clk.c, 0x00c0 },
3746 { &gcc_camss_csi0_ahb_clk.c, 0x00c1 },
3747 { &gcc_camss_csi0phy_clk.c, 0x00c2 },
3748 { &gcc_camss_csi0rdi_clk.c, 0x00c3 },
3749 { &gcc_camss_csi0pix_clk.c, 0x00c4 },
3750 { &gcc_camss_csi1_clk.c, 0x00c5 },
3751 { &gcc_camss_csi1_ahb_clk.c, 0x00c6 },
3752 { &gcc_camss_csi1phy_clk.c, 0x00c7 },
3753 { &gcc_pdm_ahb_clk.c, 0x00d0 },
3754 { &gcc_pdm2_clk.c, 0x00d2 },
3755 { &gcc_prng_ahb_clk.c, 0x00d8 },
3756 { &gcc_camss_csi1rdi_clk.c, 0x00e0 },
3757 { &gcc_camss_csi1pix_clk.c, 0x00e1 },
3758 { &gcc_camss_ispif_ahb_clk.c, 0x00e2 },
3759 { &gcc_camss_csi2_clk.c, 0x00e3 },
3760 { &gcc_camss_csi2_ahb_clk.c, 0x00e4 },
3761 { &gcc_camss_csi2phy_clk.c, 0x00e5 },
3762 { &gcc_camss_csi2rdi_clk.c, 0x00e6 },
3763 { &gcc_camss_csi2pix_clk.c, 0x00e7 },
3764 { &gcc_cpp_tbu_clk.c, 0x00e9 },
3765 { &gcc_boot_rom_ahb_clk.c, 0x00f8 },
3766 { &gcc_crypto_clk.c, 0x0138 },
3767 { &gcc_crypto_axi_clk.c, 0x0139 },
3768 { &gcc_crypto_ahb_clk.c, 0x013a },
3769 { &gcc_bimc_gpu_clk.c, 0x0157 },
3770 { &gcc_ipa_tbu_clk.c, 0x0198 },
3771 { &gcc_vfe1_tbu_clk.c, 0x0199 },
3772 { &gcc_camss_csi_vfe1_clk.c, 0x01a0 },
3773 { &gcc_camss_vfe1_clk.c, 0x01a1 },
3774 { &gcc_camss_vfe1_ahb_clk.c, 0x01a2 },
3775 { &gcc_camss_vfe1_axi_clk.c, 0x01a3 },
3776 { &gcc_camss_cpp_axi_clk.c, 0x01a4 },
3777 { &gcc_venus0_core0_vcodec0_clk.c, 0x01b8 },
3778 { &gcc_dcc_clk.c, 0x01b9 },
3779 { &gcc_camss_mclk2_clk.c, 0x01bd },
3780 { &gcc_oxili_timer_clk.c, 0x01e9 },
3781 { &gcc_oxili_gfx3d_clk.c, 0x01ea },
3782 { &gcc_oxili_aon_clk.c, 0x00ee },
3783 { &gcc_oxili_ahb_clk.c, 0x01eb },
3784 { &gcc_venus0_vcodec0_clk.c, 0x01f1 },
3785 { &gcc_venus0_axi_clk.c, 0x01f2 },
3786 { &gcc_venus0_ahb_clk.c, 0x01f3 },
3787 { &gcc_mdss_ahb_clk.c, 0x01f6 },
3788 { &gcc_mdss_axi_clk.c, 0x01f7 },
3789 { &gcc_mdss_pclk0_clk.c, 0x01f8 },
3790 { &gcc_mdss_pclk1_clk.c, 0x01e3 },
3791 { &gcc_mdss_mdp_clk.c, 0x01f9 },
3792 { &gcc_mdss_vsync_clk.c, 0x01fb },
3793 { &gcc_mdss_byte0_clk.c, 0x01fc },
3794 { &gcc_mdss_byte1_clk.c, 0x01e4 },
3795 { &gcc_mdss_esc0_clk.c, 0x01fd },
3796 { &gcc_mdss_esc1_clk.c, 0x01e5 },
3797 { &wcnss_m_clk.c, 0x0ec },
3798 ),
3799 .c = {
3800 .dbg_name = "gcc_debug_mux_8937",
3801 .ops = &clk_ops_debug_mux,
3802 .flags = CLKFLAG_NO_RATE_CACHE | CLKFLAG_MEASURE,
3803 CLK_INIT(gcc_debug_mux_8937.c),
3804 },
3805};
3806
3807/* Clock lookup */
3808static struct clk_lookup msm_clocks_lookup_common[] = {
3809 /* RPM clocks */
3810 CLK_LIST(xo_clk_src),
3811 CLK_LIST(xo_a_clk_src),
3812 CLK_LIST(xo_otg_clk),
3813 CLK_LIST(xo_lpm_clk),
3814 CLK_LIST(xo_pil_mss_clk),
3815 CLK_LIST(xo_pil_pronto_clk),
3816 CLK_LIST(xo_wlan_clk),
3817 CLK_LIST(xo_pil_lpass_clk),
3818
3819 CLK_LIST(sysmmnoc_msmbus_clk),
3820 CLK_LIST(snoc_msmbus_clk),
3821 CLK_LIST(snoc_msmbus_a_clk),
3822 CLK_LIST(sysmmnoc_msmbus_a_clk),
3823 CLK_LIST(pnoc_msmbus_clk),
3824 CLK_LIST(pnoc_msmbus_a_clk),
3825 CLK_LIST(bimc_msmbus_clk),
3826 CLK_LIST(bimc_msmbus_a_clk),
3827 CLK_LIST(pnoc_keepalive_a_clk),
3828
3829 CLK_LIST(pnoc_usb_a_clk),
3830 CLK_LIST(snoc_usb_a_clk),
3831 CLK_LIST(bimc_usb_a_clk),
3832 CLK_LIST(pnoc_usb_clk),
3833 CLK_LIST(snoc_usb_clk),
3834 CLK_LIST(bimc_usb_clk),
3835
3836 CLK_LIST(snoc_wcnss_a_clk),
3837 CLK_LIST(bimc_wcnss_a_clk),
3838
3839 CLK_LIST(qdss_clk),
3840 CLK_LIST(qdss_a_clk),
3841
3842 CLK_LIST(snoc_clk),
3843 CLK_LIST(sysmmnoc_clk),
3844 CLK_LIST(pnoc_clk),
3845 CLK_LIST(bimc_clk),
3846 CLK_LIST(snoc_a_clk),
3847 CLK_LIST(sysmmnoc_a_clk),
3848 CLK_LIST(pnoc_a_clk),
3849 CLK_LIST(bimc_a_clk),
3850
3851 CLK_LIST(bb_clk1),
3852 CLK_LIST(bb_clk1_a),
3853 CLK_LIST(bb_clk2),
3854 CLK_LIST(bb_clk2_a),
3855 CLK_LIST(rf_clk2),
3856 CLK_LIST(rf_clk2_a),
3857 CLK_LIST(div_clk2),
3858 CLK_LIST(div_clk2_a),
3859
3860 CLK_LIST(bb_clk1_pin),
3861 CLK_LIST(bb_clk1_a_pin),
3862 CLK_LIST(bb_clk2_pin),
3863 CLK_LIST(bb_clk2_a_pin),
3864
3865 CLK_LIST(gpll0_clk_src),
3866 CLK_LIST(gpll0_ao_clk_src),
3867 CLK_LIST(gpll6_clk_src),
3868 CLK_LIST(gpll4_clk_src),
3869 CLK_LIST(gpll3_clk_src),
3870 CLK_LIST(a53ss_c1_pll),
3871 CLK_LIST(gcc_blsp1_ahb_clk),
3872 CLK_LIST(gcc_blsp2_ahb_clk),
3873 CLK_LIST(gcc_boot_rom_ahb_clk),
3874 CLK_LIST(gcc_crypto_ahb_clk),
3875 CLK_LIST(gcc_crypto_axi_clk),
3876 CLK_LIST(gcc_crypto_clk),
3877 CLK_LIST(gcc_prng_ahb_clk),
3878 CLK_LIST(gcc_cpp_tbu_clk),
3879 CLK_LIST(gcc_apss_tcu_clk),
3880 CLK_LIST(gcc_jpeg_tbu_clk),
3881 CLK_LIST(gcc_mdp_tbu_clk),
3882 CLK_LIST(gcc_smmu_cfg_clk),
3883 CLK_LIST(gcc_venus_tbu_clk),
3884 CLK_LIST(gcc_vfe1_tbu_clk),
3885 CLK_LIST(gcc_vfe_tbu_clk),
3886 CLK_LIST(camss_top_ahb_clk_src),
3887 CLK_LIST(apss_ahb_clk_src),
3888 CLK_LIST(csi0_clk_src),
3889 CLK_LIST(csi1_clk_src),
3890 CLK_LIST(csi2_clk_src),
3891 CLK_LIST(vcodec0_clk_src),
3892 CLK_LIST(vfe0_clk_src),
3893 CLK_LIST(vfe1_clk_src),
3894 CLK_LIST(gfx3d_clk_src),
3895 CLK_LIST(blsp1_qup2_i2c_apps_clk_src),
3896 CLK_LIST(blsp1_qup2_spi_apps_clk_src),
3897 CLK_LIST(blsp1_qup3_i2c_apps_clk_src),
3898 CLK_LIST(blsp1_qup3_spi_apps_clk_src),
3899 CLK_LIST(blsp1_qup4_i2c_apps_clk_src),
3900 CLK_LIST(blsp1_qup4_spi_apps_clk_src),
3901 CLK_LIST(blsp1_uart1_apps_clk_src),
3902 CLK_LIST(blsp1_uart2_apps_clk_src),
3903 CLK_LIST(blsp2_qup1_i2c_apps_clk_src),
3904 CLK_LIST(blsp2_qup1_spi_apps_clk_src),
3905 CLK_LIST(blsp2_qup2_i2c_apps_clk_src),
3906 CLK_LIST(blsp2_qup2_spi_apps_clk_src),
3907 CLK_LIST(blsp2_qup3_i2c_apps_clk_src),
3908 CLK_LIST(blsp2_qup3_spi_apps_clk_src),
3909 CLK_LIST(blsp2_uart1_apps_clk_src),
3910 CLK_LIST(blsp2_uart2_apps_clk_src),
3911 CLK_LIST(cci_clk_src),
3912 CLK_LIST(cpp_clk_src),
3913 CLK_LIST(camss_gp0_clk_src),
3914 CLK_LIST(camss_gp1_clk_src),
3915 CLK_LIST(jpeg0_clk_src),
3916 CLK_LIST(mclk0_clk_src),
3917 CLK_LIST(mclk1_clk_src),
3918 CLK_LIST(mclk2_clk_src),
3919 CLK_LIST(csi0phytimer_clk_src),
3920 CLK_LIST(csi1phytimer_clk_src),
3921 CLK_LIST(crypto_clk_src),
3922 CLK_LIST(gp1_clk_src),
3923 CLK_LIST(gp2_clk_src),
3924 CLK_LIST(gp3_clk_src),
3925 CLK_LIST(esc0_clk_src),
3926 CLK_LIST(mdp_clk_src),
3927 CLK_LIST(vsync_clk_src),
3928 CLK_LIST(pdm2_clk_src),
3929 CLK_LIST(sdcc1_apps_clk_src),
3930 CLK_LIST(sdcc1_ice_core_clk_src),
3931 CLK_LIST(sdcc2_apps_clk_src),
3932 CLK_LIST(usb_hs_system_clk_src),
3933 CLK_LIST(gcc_bimc_gpu_clk),
3934 CLK_LIST(gcc_blsp1_qup2_i2c_apps_clk),
3935 CLK_LIST(gcc_blsp1_qup2_spi_apps_clk),
3936 CLK_LIST(gcc_blsp1_qup3_i2c_apps_clk),
3937 CLK_LIST(gcc_blsp1_qup3_spi_apps_clk),
3938 CLK_LIST(gcc_blsp1_qup4_i2c_apps_clk),
3939 CLK_LIST(gcc_blsp1_qup4_spi_apps_clk),
3940 CLK_LIST(gcc_blsp1_uart1_apps_clk),
3941 CLK_LIST(gcc_blsp1_uart2_apps_clk),
3942 CLK_LIST(gcc_blsp2_qup1_i2c_apps_clk),
3943 CLK_LIST(gcc_blsp2_qup1_spi_apps_clk),
3944 CLK_LIST(gcc_blsp2_qup2_i2c_apps_clk),
3945 CLK_LIST(gcc_blsp2_qup2_spi_apps_clk),
3946 CLK_LIST(gcc_blsp2_qup3_i2c_apps_clk),
3947 CLK_LIST(gcc_blsp2_qup3_spi_apps_clk),
3948 CLK_LIST(gcc_blsp2_uart1_apps_clk),
3949 CLK_LIST(gcc_blsp2_uart2_apps_clk),
3950 CLK_LIST(gcc_camss_cci_ahb_clk),
3951 CLK_LIST(gcc_camss_cci_clk),
3952 CLK_LIST(gcc_camss_cpp_ahb_clk),
3953 CLK_LIST(gcc_camss_cpp_axi_clk),
3954 CLK_LIST(gcc_camss_cpp_clk),
3955 CLK_LIST(gcc_camss_csi0_ahb_clk),
3956 CLK_LIST(gcc_camss_csi0_clk),
3957 CLK_LIST(gcc_camss_csi0phy_clk),
3958 CLK_LIST(gcc_camss_csi0pix_clk),
3959 CLK_LIST(gcc_camss_csi0rdi_clk),
3960 CLK_LIST(gcc_camss_csi1_ahb_clk),
3961 CLK_LIST(gcc_camss_csi1_clk),
3962 CLK_LIST(gcc_camss_csi1phy_clk),
3963 CLK_LIST(gcc_camss_csi1pix_clk),
3964 CLK_LIST(gcc_camss_csi1rdi_clk),
3965 CLK_LIST(gcc_camss_csi2_ahb_clk),
3966 CLK_LIST(gcc_camss_csi2_clk),
3967 CLK_LIST(gcc_camss_csi2phy_clk),
3968 CLK_LIST(gcc_camss_csi2pix_clk),
3969 CLK_LIST(gcc_camss_csi2rdi_clk),
3970 CLK_LIST(gcc_camss_csi_vfe0_clk),
3971 CLK_LIST(gcc_camss_csi_vfe1_clk),
3972 CLK_LIST(gcc_camss_gp0_clk),
3973 CLK_LIST(gcc_camss_gp1_clk),
3974 CLK_LIST(gcc_camss_ispif_ahb_clk),
3975 CLK_LIST(gcc_camss_jpeg0_clk),
3976 CLK_LIST(gcc_camss_jpeg_ahb_clk),
3977 CLK_LIST(gcc_camss_jpeg_axi_clk),
3978 CLK_LIST(gcc_camss_mclk0_clk),
3979 CLK_LIST(gcc_camss_mclk1_clk),
3980 CLK_LIST(gcc_camss_mclk2_clk),
3981 CLK_LIST(gcc_camss_micro_ahb_clk),
3982 CLK_LIST(gcc_camss_csi0phytimer_clk),
3983 CLK_LIST(gcc_camss_csi1phytimer_clk),
3984 CLK_LIST(gcc_camss_ahb_clk),
3985 CLK_LIST(gcc_camss_top_ahb_clk),
3986 CLK_LIST(gcc_camss_vfe0_clk),
3987 CLK_LIST(gcc_camss_vfe_ahb_clk),
3988 CLK_LIST(gcc_camss_vfe_axi_clk),
3989 CLK_LIST(gcc_camss_vfe1_ahb_clk),
3990 CLK_LIST(gcc_camss_vfe1_axi_clk),
3991 CLK_LIST(gcc_camss_vfe1_clk),
3992 CLK_LIST(gcc_gp1_clk),
3993 CLK_LIST(gcc_gp2_clk),
3994 CLK_LIST(gcc_gp3_clk),
3995 CLK_LIST(gcc_mdss_ahb_clk),
3996 CLK_LIST(gcc_mdss_axi_clk),
3997 CLK_LIST(gcc_mdss_esc0_clk),
3998 CLK_LIST(gcc_mdss_mdp_clk),
3999 CLK_LIST(gcc_mdss_vsync_clk),
4000 CLK_LIST(gcc_mss_cfg_ahb_clk),
4001 CLK_LIST(gcc_mss_q6_bimc_axi_clk),
4002 CLK_LIST(gcc_bimc_gfx_clk),
4003 CLK_LIST(gcc_oxili_ahb_clk),
4004 CLK_LIST(gcc_oxili_gfx3d_clk),
4005 CLK_LIST(gcc_pdm2_clk),
4006 CLK_LIST(gcc_pdm_ahb_clk),
4007 CLK_LIST(gcc_sdcc1_ahb_clk),
4008 CLK_LIST(gcc_sdcc1_apps_clk),
4009 CLK_LIST(gcc_sdcc1_ice_core_clk),
4010 CLK_LIST(gcc_sdcc2_ahb_clk),
4011 CLK_LIST(gcc_sdcc2_apps_clk),
4012 CLK_LIST(gcc_usb2a_phy_sleep_clk),
4013 CLK_LIST(gcc_usb_hs_phy_cfg_ahb_clk),
4014 CLK_LIST(gcc_usb_hs_ahb_clk),
4015 CLK_LIST(gcc_usb_hs_system_clk),
4016 CLK_LIST(gcc_venus0_ahb_clk),
4017 CLK_LIST(gcc_venus0_axi_clk),
4018 CLK_LIST(gcc_venus0_core0_vcodec0_clk),
4019 CLK_LIST(gcc_venus0_vcodec0_clk),
4020
4021 /* Reset clks */
4022 CLK_LIST(gcc_usb2_hs_phy_only_clk),
4023 CLK_LIST(gcc_qusb2_phy_clk),
4024
4025 /* WCNSS Debug */
4026 CLK_LIST(wcnss_m_clk),
4027};
4028
4029static struct clk_lookup msm_clocks_lookup_8952[] = {
4030 CLK_LIST(a53ss_c0_pll),
4031 CLK_LIST(a53ss_cci_pll),
4032 CLK_LIST(ipa_clk),
4033 CLK_LIST(ipa_a_clk),
4034 CLK_LIST(gpll0_clk_src_8952),
4035 CLK_LIST(gpll0_ao_clk_src_8952),
4036 CLK_LIST(gcc_oxili_gmem_clk),
4037 CLK_LIST(usb_fs_ic_clk_src),
4038 CLK_LIST(gcc_usb_fs_ic_clk),
4039 CLK_LIST(usb_fs_system_clk_src),
4040 CLK_LIST(gcc_usb_fs_system_clk),
4041 CLK_LIST(gcc_gfx_tcu_clk),
4042 CLK_LIST(gcc_gfx_tbu_clk),
4043 CLK_LIST(gcc_gtcu_ahb_clk),
4044 CLK_LIST(gcc_ipa_tbu_clk),
4045 CLK_LIST(gcc_usb_fs_ahb_clk),
4046 CLK_LIST(gcc_venus0_core1_vcodec0_clk),
4047 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4048 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4049 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4050 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4051 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4052 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4053 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4054 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4055 CLK_LIST(gcc_oxili_timer_clk),
4056};
4057
4058static struct clk_lookup msm_clocks_lookup_8937[] = {
4059 CLK_LIST(gpll0_clk_src_8937),
4060 CLK_LIST(gpll0_ao_clk_src_8937),
4061 CLK_LIST(gpll0_sleep_clk_src),
4062 CLK_LIST(a53ss_c0_pll),
4063 CLK_LIST(esc1_clk_src),
4064 CLK_LIST(gcc_mdss_esc1_clk),
4065 CLK_LIST(gcc_dcc_clk),
4066 CLK_LIST(gcc_oxili_aon_clk),
4067 CLK_LIST(gcc_qdss_dap_clk),
4068 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4069 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4070 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4071 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4072 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4073 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4074 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4075 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4076 CLK_LIST(gcc_oxili_timer_clk),
4077};
4078
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4079static struct clk_lookup msm_clocks_lookup_sdm429[] = {
4080 CLK_LIST(gpll0_clk_src_8937),
4081 CLK_LIST(gpll0_ao_clk_src_8937),
4082 CLK_LIST(gpll0_sleep_clk_src),
4083 CLK_LIST(esc1_clk_src),
4084 CLK_LIST(gcc_mdss_esc1_clk),
4085 CLK_LIST(gcc_dcc_clk),
4086 CLK_LIST(gcc_oxili_aon_clk),
4087 CLK_LIST(gcc_qdss_dap_clk),
4088 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4089 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4090 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4091 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4092 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4093 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4094 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4095 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4096 CLK_LIST(gcc_oxili_timer_clk),
4097};
4098
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4099static struct clk_lookup msm_clocks_lookup_8917[] = {
4100 CLK_LIST(gpll0_clk_src_8937),
4101 CLK_LIST(gpll0_ao_clk_src_8937),
4102 CLK_LIST(gpll0_sleep_clk_src),
4103 CLK_LIST(bimc_gpu_clk),
4104 CLK_LIST(bimc_gpu_a_clk),
4105 CLK_LIST(gcc_dcc_clk),
4106 CLK_LIST(gcc_qdss_dap_clk),
4107 CLK_LIST(gcc_gfx_tcu_clk),
4108 CLK_LIST(gcc_gfx_tbu_clk),
4109 CLK_LIST(gcc_gtcu_ahb_clk),
4110};
4111
4112static struct clk_lookup msm_clocks_lookup_8920[] = {
4113 CLK_LIST(gpll0_clk_src_8937),
4114 CLK_LIST(gpll0_ao_clk_src_8937),
4115 CLK_LIST(gpll0_sleep_clk_src),
4116 CLK_LIST(bimc_gpu_clk),
4117 CLK_LIST(bimc_gpu_a_clk),
4118 CLK_LIST(gcc_dcc_clk),
4119 CLK_LIST(gcc_qdss_dap_clk),
4120 CLK_LIST(gcc_gfx_tcu_clk),
4121 CLK_LIST(gcc_gfx_tbu_clk),
4122 CLK_LIST(gcc_gtcu_ahb_clk),
4123 CLK_LIST(ipa_clk),
4124 CLK_LIST(ipa_a_clk),
4125 CLK_LIST(gcc_ipa_tbu_clk),
4126};
4127
4128static struct clk_lookup msm_clocks_lookup_8940[] = {
4129 CLK_LIST(gpll0_clk_src_8937),
4130 CLK_LIST(gpll0_ao_clk_src_8937),
4131 CLK_LIST(gpll0_sleep_clk_src),
4132 CLK_LIST(a53ss_c0_pll),
4133 CLK_LIST(esc1_clk_src),
4134 CLK_LIST(gcc_mdss_esc1_clk),
4135 CLK_LIST(gcc_dcc_clk),
4136 CLK_LIST(gcc_oxili_aon_clk),
4137 CLK_LIST(gcc_qdss_dap_clk),
4138 CLK_LIST(blsp1_qup1_i2c_apps_clk_src),
4139 CLK_LIST(blsp1_qup1_spi_apps_clk_src),
4140 CLK_LIST(gcc_blsp1_qup1_i2c_apps_clk),
4141 CLK_LIST(gcc_blsp1_qup1_spi_apps_clk),
4142 CLK_LIST(blsp2_qup4_i2c_apps_clk_src),
4143 CLK_LIST(blsp2_qup4_spi_apps_clk_src),
4144 CLK_LIST(gcc_blsp2_qup4_i2c_apps_clk),
4145 CLK_LIST(gcc_blsp2_qup4_spi_apps_clk),
4146 CLK_LIST(gcc_oxili_timer_clk),
4147 CLK_LIST(ipa_clk),
4148 CLK_LIST(ipa_a_clk),
4149 CLK_LIST(gcc_ipa_tbu_clk),
4150};
4151
4152/* Please note that the order of reg-names is important */
4153static int get_mmio_addr(struct platform_device *pdev, u32 nbases)
4154{
4155 int i, count;
4156 const char *str;
4157 struct resource *res;
4158 struct device *dev = &pdev->dev;
4159
4160 count = of_property_count_strings(dev->of_node, "reg-names");
4161 if (count < nbases) {
4162 dev_err(dev, "missing reg-names property, expected %d strings\n",
4163 nbases);
4164 return -EINVAL;
4165 }
4166
4167 for (i = 0; i < nbases; i++) {
4168 of_property_read_string_index(dev->of_node, "reg-names", i,
4169 &str);
4170 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, str);
4171 if (!res) {
4172 dev_err(dev, "Unable to retrieve register base.\n");
4173 return -ENOMEM;
4174 }
4175
4176 virt_bases[i] = devm_ioremap(dev, res->start,
4177 resource_size(res));
4178 if (!virt_bases[i]) {
4179 dev_err(dev, "Failed to map in CC registers.\n");
4180 return -ENOMEM;
4181 }
4182 }
4183
4184 return 0;
4185}
4186
4187static const struct msm_reset_map gcc_8952_resets[] = {
4188 [GCC_CAMSS_MICRO_BCR] = {0x56008},
4189 [GCC_USB_FS_BCR] = {0x3F000},
4190 [GCC_USB_HS_BCR] = {0x41000},
4191 [GCC_USB2_HS_PHY_ONLY_BCR] = {0x41034},
4192 [GCC_QUSB2_PHY_BCR] = {0x4103C},
4193};
4194
4195static void override_for_8917(int speed_bin)
4196{
4197 gpll3_clk_src.c.rate = 930000000;
4198
4199 OVERRIDE_FMAX3(csi0,
4200 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4201 /* Frequency Table same as 8937 */
4202 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4203 OVERRIDE_FMAX3(csi1,
4204 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4205 /* Frequency Table same as 8937 */
4206 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4207 OVERRIDE_FMAX3(csi2,
4208 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4209 /* Frequency Table same as 8937 */
4210 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4211
4212 OVERRIDE_FMAX5(vfe0,
4213 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4214 NOM_PLUS, 329140000, HIGH, 360000000);
4215 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8917);
4216 OVERRIDE_FMAX5(vfe1,
4217 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4218 NOM_PLUS, 329140000, HIGH, 360000000);
4219 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8917);
4220 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8917);
4221 OVERRIDE_FMAX5(vcodec0,
4222 LOWER, 200000000, LOW, 270000000, NOMINAL, 308570000,
4223 NOM_PLUS, 329140000, HIGH, 360000000);
4224 OVERRIDE_FMAX4(cpp,
4225 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4226 NOM_PLUS, 360000000);
4227 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8917);
4228 OVERRIDE_FMAX5(jpeg0,
4229 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4230 NOM_PLUS, 308570000, HIGH, 320000000);
4231 /* Frequency Table same as 8937 */
4232 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4233
4234 if (speed_bin) {
4235 OVERRIDE_FMAX5(gfx3d,
4236 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4237 NOM_PLUS, 523200000, HIGH, 650000000);
4238 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917_650MHz);
4239 } else {
4240 OVERRIDE_FMAX5(gfx3d,
4241 LOWER, 270000000, LOW, 400000000, NOMINAL, 484800000,
4242 NOM_PLUS, 523200000, HIGH, 598000000);
4243 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8917);
4244 }
4245
4246 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4247
4248 OVERRIDE_FTABLE(csi0phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4249 OVERRIDE_FMAX3(csi0phytimer, LOWER, 100000000, LOW, 200000000,
4250 NOMINAL, 266670000);
4251 OVERRIDE_FTABLE(csi1phytimer, ftbl_gcc_camss_csi0_1phytimer_clk, 8917);
4252 OVERRIDE_FMAX3(csi1phytimer, LOWER, 100000000, LOW, 200000000,
4253 NOMINAL, 266670000);
4254 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4255 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4256 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4257
4258 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4259 /* Frequency Table same as 8937 */
4260 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4261 byte0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4262
4263 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4264 /* Frequency Table same as 8937 */
4265 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4266 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4267
4268 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 200000000, NOMINAL, 400000000);
4269 OVERRIDE_FTABLE(usb_hs_system, ftbl_gcc_usb_hs_system_clk, 8917);
4270 OVERRIDE_FMAX3(usb_hs_system, LOWER, 800000000, NOMINAL, 133333000,
4271 HIGH, 177780000);
4272}
4273
4274static void override_for_8937(int speed_bin)
4275{
4276 gpll3_clk_src.c.rate = 900000000;
4277 gpll3_clk_src.vco_tbl = p_vco_8937;
4278 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco_8937);
4279 OVERRIDE_FMAX2(gpll3, LOW, 800000000, NOMINAL, 1066000000);
4280
4281 OVERRIDE_FMAX1(cci, LOWER, 37500000);
4282 OVERRIDE_FMAX3(csi0,
4283 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4284 OVERRIDE_FTABLE(csi0, ftbl_gcc_camss_csi0_2_clk, 8937);
4285 OVERRIDE_FMAX3(csi1,
4286 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4287 OVERRIDE_FTABLE(csi1, ftbl_gcc_camss_csi0_2_clk, 8937);
4288 OVERRIDE_FMAX3(csi2,
4289 LOWER, 100000000, LOW, 200000000, NOMINAL, 266670000);
4290 OVERRIDE_FTABLE(csi2, ftbl_gcc_camss_csi0_2_clk, 8937);
4291 OVERRIDE_FMAX4(vfe0,
4292 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4293 NOM_PLUS, 432000000);
4294 OVERRIDE_FTABLE(vfe0, ftbl_gcc_camss_vfe0_1_clk, 8937);
4295 OVERRIDE_FMAX4(vfe1,
4296 LOWER, 160000000, LOW, 308570000, NOMINAL, 400000000,
4297 NOM_PLUS, 432000000);
4298 OVERRIDE_FTABLE(vfe1, ftbl_gcc_camss_vfe0_1_clk, 8937);
4299
4300 if (speed_bin) {
4301 OVERRIDE_FMAX6(gfx3d,
4302 LOWER, 216000000, LOW, 300000000,
4303 NOMINAL, 375000000, NOM_PLUS, 400000000,
4304 HIGH, 450000000, SUPER_TUR, 475000000);
4305 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937_475MHz);
4306 } else {
4307 OVERRIDE_FMAX5(gfx3d,
4308 LOWER, 216000000, LOW, 300000000,
4309 NOMINAL, 375000000, NOM_PLUS, 400000000,
4310 HIGH, 450000000);
4311 OVERRIDE_FTABLE(gfx3d, ftbl_gcc_oxili_gfx3d_clk, 8937);
4312 }
4313
4314 OVERRIDE_FMAX5(cpp,
4315 LOWER, 160000000, LOW, 266670000, NOMINAL, 320000000,
4316 NOM_PLUS, 342860000, HIGH, 360000000);
4317 OVERRIDE_FTABLE(cpp, ftbl_gcc_camss_cpp_clk, 8937);
4318 OVERRIDE_FMAX5(jpeg0,
4319 LOWER, 133330000, LOW, 200000000, NOMINAL, 266670000,
4320 NOM_PLUS, 308570000, HIGH, 320000000);
4321 OVERRIDE_FTABLE(jpeg0, ftbl_gcc_camss_jpeg0_clk, 8937);
4322 OVERRIDE_FMAX2(csi0phytimer, LOWER, 100000000, LOW, 200000000);
4323 OVERRIDE_FMAX2(csi1phytimer, LOWER, 100000000, LOW, 200000000);
4324 OVERRIDE_FMAX2(gp1, LOWER, 100000000, NOMINAL, 200000000);
4325 OVERRIDE_FMAX2(gp2, LOWER, 100000000, NOMINAL, 200000000);
4326 OVERRIDE_FMAX2(gp3, LOWER, 100000000, NOMINAL, 200000000);
4327 OVERRIDE_FMAX2(byte0, LOWER, 125000000, NOMINAL, 187500000);
4328 OVERRIDE_FTABLE(byte0, ftbl_gcc_mdss_byte0_clk, 8937);
4329 OVERRIDE_FMAX2(byte1, LOWER, 125000000, NOMINAL, 187500000);
4330 byte0_clk_src.current_freq = ftbl_gcc_mdss_byte0_clk_8937;
4331 OVERRIDE_FMAX2(pclk0, LOWER, 166670000, NOMINAL, 250000000);
4332 OVERRIDE_FTABLE(pclk0, ftbl_gcc_mdss_pclk0_clk, 8937);
4333 OVERRIDE_FMAX2(pclk1, LOWER, 166670000, NOMINAL, 250000000);
4334 pclk0_clk_src.current_freq = ftbl_gcc_mdss_pclk0_clk_8937;
4335 OVERRIDE_FTABLE(vcodec0, ftbl_gcc_venus0_vcodec0_clk, 8937);
4336 OVERRIDE_FMAX5(vcodec0,
4337 LOWER, 166150000, LOW, 240000000, NOMINAL, 308570000,
4338 NOM_PLUS, 320000000, HIGH, 360000000);
4339 OVERRIDE_FMAX2(sdcc1_apps, LOWER, 100000000,
4340 NOMINAL, 400000000);
4341}
4342
4343static void get_speed_bin(struct platform_device *pdev, int *bin)
4344{
4345 struct resource *res;
4346 void __iomem *base;
4347 u32 config_efuse;
4348
4349 *bin = 0;
4350
4351 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
4352 if (!res) {
4353 dev_info(&pdev->dev,
4354 "No GPU speed binning available. Defaulting to 0.\n");
4355 return;
4356 }
4357
4358 base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4359 if (!base) {
4360 dev_warn(&pdev->dev,
4361 "Unable to ioremap efuse reg address. Defaulting to 0.\n");
4362 return;
4363 }
4364
4365 config_efuse = readl_relaxed(base);
4366 devm_iounmap(&pdev->dev, base);
4367 *bin = (config_efuse >> 31) & 0x1;
4368
4369 dev_info(&pdev->dev, "GPU speed bin: %d\n", *bin);
4370}
4371
4372static int msm_gcc_probe(struct platform_device *pdev)
4373{
4374 struct resource *res;
4375 int ret;
4376 int speed_bin;
4377 u32 regval, nbases = N_BASES;
4378 bool compat_bin = false;
4379 bool compat_bin2 = false;
4380 bool compat_bin3 = false;
4381 bool compat_bin4 = false;
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4382 bool compat_bin5 = false;
4383 bool compat_bin6 = false;
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4384
4385 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4386 "qcom,gcc-8937");
4387
4388 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4389 "qcom,gcc-8917");
4390
4391 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4392 "qcom,gcc-8940");
4393
4394 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4395 "qcom,gcc-8920");
4396
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4397 compat_bin5 = of_device_is_compatible(pdev->dev.of_node,
4398 "qcom,gcc-sdm429");
4399
4400 compat_bin6 = of_device_is_compatible(pdev->dev.of_node,
4401 "qcom,gcc-sdm439");
4402
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4403 ret = vote_bimc(&bimc_clk, INT_MAX);
4404 if (ret < 0)
4405 return ret;
4406
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4407 if (compat_bin2 || compat_bin4 || compat_bin5)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4408 nbases = APCS_C0_PLL_BASE;
4409
4410 ret = get_mmio_addr(pdev, nbases);
4411 if (ret)
4412 return ret;
4413
4414 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
4415 if (!res) {
4416 dev_err(&pdev->dev, "Register base not defined\n");
4417 return -ENOMEM;
4418 }
4419
4420 virt_bases[GCC_BASE] = devm_ioremap(&pdev->dev, res->start,
4421 resource_size(res));
4422 if (!virt_bases[GCC_BASE]) {
4423 dev_err(&pdev->dev, "Failed to ioremap CC registers\n");
4424 return -ENOMEM;
4425 }
4426
4427 vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig");
4428 if (IS_ERR(vdd_dig.regulator[0])) {
4429 if (!(PTR_ERR(vdd_dig.regulator[0]) == -EPROBE_DEFER))
4430 dev_err(&pdev->dev,
4431 "Unable to get vdd_dig regulator!!!\n");
4432 return PTR_ERR(vdd_dig.regulator[0]);
4433 }
4434
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4435 if (!compat_bin2 && !compat_bin4 && !compat_bin5) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4436 vdd_sr2_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4437 "vdd_sr2_pll");
4438 if (IS_ERR(vdd_sr2_pll.regulator[0])) {
4439 if (PTR_ERR(vdd_sr2_pll.regulator[0]) != -EPROBE_DEFER)
4440 dev_err(&pdev->dev,
4441 "Unable to get vdd_sr2_pll regulator!!!\n");
4442 return PTR_ERR(vdd_sr2_pll.regulator[0]);
4443 }
4444
4445 vdd_sr2_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4446 "vdd_sr2_dig");
4447 if (IS_ERR(vdd_sr2_pll.regulator[1])) {
4448 if (PTR_ERR(vdd_sr2_pll.regulator[1]) != -EPROBE_DEFER)
4449 dev_err(&pdev->dev,
4450 "Unable to get vdd_sr2_dig regulator!!!\n");
4451 return PTR_ERR(vdd_sr2_pll.regulator[1]);
4452 }
4453 }
4454
4455 vdd_hf_pll.regulator[0] = devm_regulator_get(&pdev->dev,
4456 "vdd_hf_pll");
4457 if (IS_ERR(vdd_hf_pll.regulator[0])) {
4458 if (PTR_ERR(vdd_hf_pll.regulator[0]) != -EPROBE_DEFER)
4459 dev_err(&pdev->dev,
4460 "Unable to get vdd_sr2_pll regulator!!!\n");
4461 return PTR_ERR(vdd_hf_pll.regulator[0]);
4462 }
4463
4464 vdd_hf_pll.regulator[1] = devm_regulator_get(&pdev->dev,
4465 "vdd_hf_dig");
4466 if (IS_ERR(vdd_hf_pll.regulator[1])) {
4467 if (PTR_ERR(vdd_hf_pll.regulator[1]) != -EPROBE_DEFER)
4468 dev_err(&pdev->dev,
4469 "Unable to get vdd_hf_dig regulator!!!\n");
4470 return PTR_ERR(vdd_hf_pll.regulator[1]);
4471 }
4472
4473 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
4474 regval = readl_relaxed(GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4475 regval |= BIT(0);
4476 writel_relaxed(regval, GCC_REG_BASE(APCS_GPLL_ENA_VOTE));
4477
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4478 if (compat_bin || compat_bin3 || compat_bin5 || compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4479 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4480 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4481 /* Oxili Ocmem in GX rail: OXILI_GMEM_CLAMP_IO */
4482 regval = readl_relaxed(GCC_REG_BASE(GX_DOMAIN_MISC));
4483 regval &= ~BIT(0);
4484 writel_relaxed(regval, GCC_REG_BASE(GX_DOMAIN_MISC));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4485
4486 if (compat_bin5 || compat_bin6)
4487 speed_bin = 0;
4488 else
4489 get_speed_bin(pdev, &speed_bin);
4490
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4491 override_for_8937(speed_bin);
4492
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4493 if (compat_bin5 || compat_bin6) {
4494 vdd_dig.num_levels = VDD_DIG_NUM_439;
4495 vdd_dig.cur_level = VDD_DIG_NUM_439;
4496 vdd_sr2_pll.num_levels = VDD_SR2_PLL_NUM_439;
4497 vdd_sr2_pll.cur_level = VDD_SR2_PLL_NUM_439;
4498 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_439;
4499 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_439;
4500
4501 gpll3_clk_src.vco_tbl = p_vco;
4502 gpll3_clk_src.num_vco = ARRAY_SIZE(p_vco);
4503 gpll3_clk_src.c.fmax[VDD_DIG_LOW] = 800000000;
4504 gpll3_clk_src.c.fmax[VDD_DIG_NOMINAL] = 1400000000;
4505 gfx3d_clk_src.freq_tbl =
4506 ftbl_gcc_oxili_gfx3d_clk_sdm439;
4507
4508 gfx3d_clk_src.c.fmax[VDD_DIG_LOWER] = 320000000;
4509 gfx3d_clk_src.c.fmax[VDD_DIG_LOW] = 400000000;
4510 gfx3d_clk_src.c.fmax[VDD_DIG_NOMINAL] = 510000000;
4511 gfx3d_clk_src.c.fmax[VDD_DIG_NOM_PLUS] = 560000000;
4512 gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 650000000;
4513 }
4514
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4515 if (compat_bin3) {
4516 if (speed_bin) {
4517 gfx3d_clk_src.freq_tbl =
4518 ftbl_gcc_oxili_gfx3d_clk_8940_500MHz;
4519 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4520 500000000;
4521 } else {
4522 gfx3d_clk_src.freq_tbl =
4523 ftbl_gcc_oxili_gfx3d_clk_8937_475MHz;
4524 gfx3d_clk_src.c.fmax[VDD_DIG_SUPER_TUR] =
4525 475000000;
4526 }
4527 }
4528 } else if (compat_bin2 || compat_bin4) {
4529 gpll0_clk_src.c.parent = &gpll0_clk_src_8937.c;
4530 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8937.c;
4531 vdd_dig.num_levels = VDD_DIG_NUM_8917;
4532 vdd_dig.cur_level = VDD_DIG_NUM_8917;
4533 vdd_hf_pll.num_levels = VDD_HF_PLL_NUM_8917;
4534 vdd_hf_pll.cur_level = VDD_HF_PLL_NUM_8917;
4535 get_speed_bin(pdev, &speed_bin);
4536 override_for_8917(speed_bin);
4537
4538 if (compat_bin2) {
4539 blsp1_qup2_spi_apps_clk_src.freq_tbl =
4540 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4541 blsp1_qup3_spi_apps_clk_src.freq_tbl =
4542 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4543 blsp1_qup4_spi_apps_clk_src.freq_tbl =
4544 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4545 blsp2_qup1_spi_apps_clk_src.freq_tbl =
4546 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4547 blsp2_qup2_spi_apps_clk_src.freq_tbl =
4548 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4549 blsp2_qup3_spi_apps_clk_src.freq_tbl =
4550 ftbl_gcc_blsp1_2_qup1_4_spi_apps_clk_8917;
4551 }
4552 } else {
4553 gpll0_clk_src.c.parent = &gpll0_clk_src_8952.c;
4554 gpll0_ao_clk_src.c.parent = &gpll0_ao_clk_src_8952.c;
4555 }
4556
4557 ret = of_msm_clock_register(pdev->dev.of_node,
4558 msm_clocks_lookup_common,
4559 ARRAY_SIZE(msm_clocks_lookup_common));
4560 if (ret)
4561 return ret;
4562
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4563 if (compat_bin || compat_bin6)
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4564 ret = of_msm_clock_register(pdev->dev.of_node,
4565 msm_clocks_lookup_8937,
4566 ARRAY_SIZE(msm_clocks_lookup_8937));
4567 else if (compat_bin2)
4568 ret = of_msm_clock_register(pdev->dev.of_node,
4569 msm_clocks_lookup_8917,
4570 ARRAY_SIZE(msm_clocks_lookup_8917));
4571 else if (compat_bin3)
4572 ret = of_msm_clock_register(pdev->dev.of_node,
4573 msm_clocks_lookup_8940,
4574 ARRAY_SIZE(msm_clocks_lookup_8940));
4575 else if (compat_bin4)
4576 ret = of_msm_clock_register(pdev->dev.of_node,
4577 msm_clocks_lookup_8920,
4578 ARRAY_SIZE(msm_clocks_lookup_8920));
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4579 else if (compat_bin5)
4580 ret = of_msm_clock_register(pdev->dev.of_node,
4581 msm_clocks_lookup_sdm429,
4582 ARRAY_SIZE(msm_clocks_lookup_sdm429));
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4583 else
4584 ret = of_msm_clock_register(pdev->dev.of_node,
4585 msm_clocks_lookup_8952,
4586 ARRAY_SIZE(msm_clocks_lookup_8952));
4587 if (ret)
4588 return ret;
4589
4590 ret = enable_rpm_scaling();
4591 if (ret)
4592 return ret;
4593
4594 clk_set_rate(&apss_ahb_clk_src.c, 19200000);
4595 clk_prepare_enable(&apss_ahb_clk_src.c);
4596
4597 /*
4598 * Hold an active set vote for PCNOC AHB source. Sleep set vote is 0.
4599 */
4600 clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
4601 clk_prepare_enable(&pnoc_keepalive_a_clk.c);
4602
4603 clk_prepare_enable(&xo_a_clk_src.c);
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4604
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4605 if (!compat_bin && !compat_bin3 && !compat_bin5 && !compat_bin6) {
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4606 /* Configure Sleep and Wakeup cycles for GMEM clock */
4607 regval = readl_relaxed(GCC_REG_BASE(OXILI_GMEM_CBCR));
4608 regval ^= 0xFF0;
4609 regval |= CLKFLAG_WAKEUP_CYCLES << 8;
4610 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4611 writel_relaxed(regval, GCC_REG_BASE(OXILI_GMEM_CBCR));
4612 } else {
4613 /* Configure Sleep and Wakeup cycles for OXILI clock */
4614 regval = readl_relaxed(GCC_REG_BASE(OXILI_GFX3D_CBCR));
4615 regval &= ~0xF0;
4616 regval |= CLKFLAG_SLEEP_CYCLES << 4;
4617 writel_relaxed(regval, GCC_REG_BASE(OXILI_GFX3D_CBCR));
4618 }
4619
4620 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
4621 if (ret)
4622 return ret;
4623
4624 msm_reset_controller_register(pdev, gcc_8952_resets,
4625 ARRAY_SIZE(gcc_8952_resets), virt_bases[GCC_BASE]);
4626
4627 dev_info(&pdev->dev, "Registered GCC clocks\n");
4628
4629 return 0;
4630}
4631
4632static const struct of_device_id msm_clock_gcc_match_table[] = {
4633 { .compatible = "qcom,gcc-8952" },
4634 { .compatible = "qcom,gcc-8937" },
4635 { .compatible = "qcom,gcc-8917" },
4636 { .compatible = "qcom,gcc-8940" },
4637 { .compatible = "qcom,gcc-8920" },
Odelu Kukatla678382b2018-03-27 22:58:52 +0530[diff] [blame^]4638 { .compatible = "qcom,gcc-sdm439" },
4639 { .compatible = "qcom,gcc-sdm429" },
Shefali Jain79729af2018-01-29 15:15:20 +0530[diff] [blame]4640 {}
4641};
4642
4643static struct platform_driver msm_clock_gcc_driver = {
4644 .probe = msm_gcc_probe,
4645 .driver = {
4646 .name = "qcom,gcc-8952",
4647 .of_match_table = msm_clock_gcc_match_table,
4648 .owner = THIS_MODULE,
4649 },
4650};
4651
4652static int msm_gcc_spm_probe(struct platform_device *pdev)
4653{
4654 struct resource *res = NULL;
4655 bool compat_bin = false;
4656
4657 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4658 "qcom,spm-8952");
4659
4660 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c0_base");
4661 if (!res) {
4662 dev_err(&pdev->dev, "SPM register base not defined for c0\n");
4663 return -ENOMEM;
4664 }
4665
4666 a53ss_c0_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4667 resource_size(res));
4668 if (!a53ss_c0_pll.spm_ctrl.spm_base) {
4669 dev_err(&pdev->dev, "Failed to ioremap c0 spm registers\n");
4670 return -ENOMEM;
4671 }
4672
4673 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spm_c1_base");
4674 if (!res) {
4675 dev_err(&pdev->dev, "SPM register base not defined for c1\n");
4676 return -ENOMEM;
4677 }
4678
4679 a53ss_c1_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev, res->start,
4680 resource_size(res));
4681 if (!a53ss_c1_pll.spm_ctrl.spm_base) {
4682 dev_err(&pdev->dev, "Failed to ioremap c1 spm registers\n");
4683 return -ENOMEM;
4684 }
4685
4686 if (compat_bin) {
4687 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
4688 "spm_cci_base");
4689 if (!res) {
4690 dev_err(&pdev->dev, "SPM register base not defined for cci\n");
4691 return -ENOMEM;
4692 }
4693
4694 a53ss_cci_pll.spm_ctrl.spm_base = devm_ioremap(&pdev->dev,
4695 res->start, resource_size(res));
4696 if (!a53ss_cci_pll.spm_ctrl.spm_base) {
4697 dev_err(&pdev->dev, "Failed to ioremap cci spm registers\n");
4698 return -ENOMEM;
4699 }
4700 }
4701
4702 dev_info(&pdev->dev, "Registered GCC SPM clocks\n");
4703
4704 return 0;
4705}
4706
4707static const struct of_device_id msm_clock_spm_match_table[] = {
4708 { .compatible = "qcom,gcc-spm-8952" },
4709 { .compatible = "qcom,gcc-spm-8937" },
4710 {}
4711};
4712
4713static struct platform_driver msm_clock_spm_driver = {
4714 .probe = msm_gcc_spm_probe,
4715 .driver = {
4716 .name = "qcom,gcc-spm-8952",
4717 .of_match_table = msm_clock_spm_match_table,
4718 .owner = THIS_MODULE,
4719 },
4720};
4721
4722static int __init msm_gcc_init(void)
4723{
4724 int ret;
4725
4726 ret = platform_driver_register(&msm_clock_gcc_driver);
4727 if (!ret)
4728 ret = platform_driver_register(&msm_clock_spm_driver);
4729
4730 return ret;
4731}
4732
4733static struct clk_lookup msm_clocks_measure[] = {
4734 CLK_LOOKUP_OF("measure", gcc_debug_mux, "debug"),
4735 CLK_LIST(apss_debug_pri_mux),
4736 CLK_LIST(apc0_m_clk),
4737 CLK_LIST(apc1_m_clk),
4738 CLK_LIST(cci_m_clk),
4739};
4740
4741static struct clk_lookup msm_clocks_measure_8937[] = {
4742 CLK_LOOKUP_OF("measure", gcc_debug_mux_8937, "debug"),
4743 CLK_LIST(apss_debug_pri_mux),
4744 CLK_LIST(apc0_m_clk),
4745 CLK_LIST(apc1_m_clk),
4746 CLK_LIST(cci_m_clk),
4747};
4748
4749static int msm_clock_debug_probe(struct platform_device *pdev)
4750{
4751 int ret;
4752 struct resource *res;
4753 bool compat_bin = false, compat_bin2 = false;
4754 bool compat_bin3 = false;
4755 bool compat_bin4 = false;
4756
4757 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4758 "qcom,cc-debug-8937");
4759
4760 compat_bin2 = of_device_is_compatible(pdev->dev.of_node,
4761 "qcom,cc-debug-8917");
4762
4763 compat_bin3 = of_device_is_compatible(pdev->dev.of_node,
4764 "qcom,cc-debug-8940");
4765
4766 compat_bin4 = of_device_is_compatible(pdev->dev.of_node,
4767 "qcom,cc-debug-8920");
4768
4769 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "meas");
4770 if (!res) {
4771 dev_err(&pdev->dev, "GLB clock diag base not defined.\n");
4772 return -EINVAL;
4773 }
4774
4775 meas_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
4776 if (!meas_base) {
4777 dev_err(&pdev->dev, "Unable to map GLB clock diag base.\n");
4778 return -ENOMEM;
4779 }
4780
4781 clk_ops_debug_mux = clk_ops_gen_mux;
4782 clk_ops_debug_mux.get_rate = measure_get_rate;
4783
4784 if (compat_bin2)
4785 gcc_debug_mux_8937.post_div = 0x3;
4786
4787 if (!compat_bin && !compat_bin2 && !compat_bin3 && !compat_bin4)
4788 ret = of_msm_clock_register(pdev->dev.of_node,
4789 msm_clocks_measure, ARRAY_SIZE(msm_clocks_measure));
4790 else
4791 ret = of_msm_clock_register(pdev->dev.of_node,
4792 msm_clocks_measure_8937,
4793 ARRAY_SIZE(msm_clocks_measure_8937));
4794 if (ret) {
4795 dev_err(&pdev->dev, "Failed to register debug Mux\n");
4796 return ret;
4797 }
4798
4799 dev_info(&pdev->dev, "Registered Debug Mux successfully\n");
4800 return ret;
4801}
4802
4803static const struct of_device_id msm_clock_debug_match_table[] = {
4804 { .compatible = "qcom,cc-debug-8952" },
4805 { .compatible = "qcom,cc-debug-8937" },
4806 { .compatible = "qcom,cc-debug-8917" },
4807 { .compatible = "qcom,cc-debug-8940" },
4808 { .compatible = "qcom,cc-debug-8920" },
4809 {}
4810};
4811
4812static struct platform_driver msm_clock_debug_driver = {
4813 .probe = msm_clock_debug_probe,
4814 .driver = {
4815 .name = "qcom,cc-debug-8952",
4816 .of_match_table = msm_clock_debug_match_table,
4817 .owner = THIS_MODULE,
4818 },
4819};
4820
4821static int __init msm_clock_debug_init(void)
4822{
4823 return platform_driver_register(&msm_clock_debug_driver);
4824}
4825
4826/* MDSS DSI_PHY_PLL */
4827static struct clk_lookup msm_clocks_gcc_mdss_common[] = {
4828 CLK_LIST(ext_pclk0_clk_src),
4829 CLK_LIST(ext_byte0_clk_src),
4830 CLK_LIST(byte0_clk_src),
4831 CLK_LIST(pclk0_clk_src),
4832 CLK_LIST(gcc_mdss_pclk0_clk),
4833 CLK_LIST(gcc_mdss_byte0_clk),
4834 CLK_LIST(mdss_mdp_vote_clk),
4835 CLK_LIST(mdss_rotator_vote_clk),
4836};
4837
4838static struct clk_lookup msm_clocks_gcc_mdss_8937[] = {
4839 CLK_LIST(ext_pclk1_clk_src),
4840 CLK_LIST(ext_byte1_clk_src),
4841 CLK_LIST(byte1_clk_src),
4842 CLK_LIST(pclk1_clk_src),
4843 CLK_LIST(gcc_mdss_pclk1_clk),
4844 CLK_LIST(gcc_mdss_byte1_clk),
4845};
4846
4847static int msm_gcc_mdss_probe(struct platform_device *pdev)
4848{
4849 int ret = 0;
4850 struct clk *curr_p;
4851 bool compat_bin = false;
4852
4853 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4854 "qcom,gcc-mdss-8937");
4855 if (!compat_bin)
4856 compat_bin = of_device_is_compatible(pdev->dev.of_node,
4857 "qcom,gcc-mdss-8940");
4858
4859 curr_p = ext_pclk0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4860 "pclk0_src");
4861 if (IS_ERR(curr_p)) {
4862 dev_err(&pdev->dev, "Failed to get pclk0 source.\n");
4863 return PTR_ERR(curr_p);
4864 }
4865
4866 curr_p = ext_byte0_clk_src.c.parent = devm_clk_get(&pdev->dev,
4867 "byte0_src");
4868 if (IS_ERR(curr_p)) {
4869 dev_err(&pdev->dev, "Failed to get byte source.\n");
4870 ret = PTR_ERR(curr_p);
4871 goto byte0_fail;
4872 }
4873
4874 ext_pclk0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4875 ext_byte0_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4876
4877 if (compat_bin) {
4878 curr_p = ext_pclk1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4879 "pclk1_src");
4880 if (IS_ERR(curr_p)) {
4881 dev_err(&pdev->dev, "Failed to get pclk1 source.\n");
4882 ret = PTR_ERR(curr_p);
4883 goto fail;
4884 }
4885
4886 curr_p = ext_byte1_clk_src.c.parent = devm_clk_get(&pdev->dev,
4887 "byte1_src");
4888 if (IS_ERR(curr_p)) {
4889 dev_err(&pdev->dev, "Failed to get byte1 source.\n");
4890 ret = PTR_ERR(curr_p);
4891 goto byte1_fail;
4892 }
4893
4894 ext_pclk1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4895 ext_byte1_clk_src.c.flags = CLKFLAG_NO_RATE_CACHE;
4896 }
4897
4898 ret = of_msm_clock_register(pdev->dev.of_node,
4899 msm_clocks_gcc_mdss_common,
4900 ARRAY_SIZE(msm_clocks_gcc_mdss_common));
4901 if (ret)
4902 goto fail;
4903
4904 if (compat_bin) {
4905 ret = of_msm_clock_register(pdev->dev.of_node,
4906 msm_clocks_gcc_mdss_8937,
4907 ARRAY_SIZE(msm_clocks_gcc_mdss_8937));
4908 if (ret)
4909 goto fail_8937;
4910 }
4911
4912 dev_info(&pdev->dev, "Registered GCC MDSS clocks.\n");
4913
4914 return ret;
4915fail_8937:
4916 devm_clk_put(&pdev->dev, ext_byte1_clk_src.c.parent);
4917byte1_fail:
4918 devm_clk_put(&pdev->dev, ext_pclk1_clk_src.c.parent);
4919fail:
4920 devm_clk_put(&pdev->dev, ext_byte0_clk_src.c.parent);
4921byte0_fail:
4922 devm_clk_put(&pdev->dev, ext_pclk0_clk_src.c.parent);
4923 return ret;
4924
4925}
4926
4927static const struct of_device_id msm_clock_mdss_match_table[] = {
4928 { .compatible = "qcom,gcc-mdss-8952" },
4929 { .compatible = "qcom,gcc-mdss-8937" },
4930 { .compatible = "qcom,gcc-mdss-8917" },
4931 { .compatible = "qcom,gcc-mdss-8940" },
4932 { .compatible = "qcom,gcc-mdss-8920" },
4933 {}
4934};
4935
4936static struct platform_driver msm_clock_gcc_mdss_driver = {
4937 .probe = msm_gcc_mdss_probe,
4938 .driver = {
4939 .name = "gcc-mdss-8952",
4940 .of_match_table = msm_clock_mdss_match_table,
4941 .owner = THIS_MODULE,
4942 },
4943};
4944
4945static int __init msm_gcc_mdss_init(void)
4946{
4947 return platform_driver_register(&msm_clock_gcc_mdss_driver);
4948}
4949arch_initcall(msm_gcc_init);
4950fs_initcall_sync(msm_gcc_mdss_init);
4951late_initcall(msm_clock_debug_init);