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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * eisa.c - provide support for EISA adapters in PA-RISC machines
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Copyright (c) 2001 Matthew Wilcox for Hewlett Packard
10 * Copyright (c) 2001 Daniel Engstrom <5116@telia.com>
11 *
12 * There are two distinct EISA adapters. Mongoose is found in machines
13 * before the 712; then the Wax ASIC is used. To complicate matters, the
14 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * dealt with elsewhere; this file is concerned only with the EISA portions
16 * of Wax.
17 *
18 *
19 * HINT:
20 * -----
21 * To allow an ISA card to work properly in the EISA slot you need to
22 * set an edge trigger level. This may be done on the palo command line
23 * by adding the kernel parameter "eisa_irq_edge=n,n2,[...]]", with
24 * n and n2 as the irq levels you want to use.
25 *
26 * Example: "eisa_irq_edge=10,11" allows ISA cards to operate at
27 * irq levels 10 and 11.
28 */
29
30#include <linux/init.h>
31#include <linux/ioport.h>
32#include <linux/interrupt.h>
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/sched.h>
37#include <linux/spinlock.h>
38#include <linux/eisa.h>
39
40#include <asm/byteorder.h>
41#include <asm/io.h>
42#include <asm/hardware.h>
43#include <asm/processor.h>
44#include <asm/parisc-device.h>
45#include <asm/delay.h>
46#include <asm/eisa_bus.h>
47#include <asm/eisa_eeprom.h>
48
49#if 0
50#define EISA_DBG(msg, arg... ) printk(KERN_DEBUG "eisa: " msg , ## arg )
51#else
52#define EISA_DBG(msg, arg... )
53#endif
54
55#define SNAKES_EEPROM_BASE_ADDR 0xF0810400
56#define MIRAGE_EEPROM_BASE_ADDR 0xF00C0400
57
58static DEFINE_SPINLOCK(eisa_irq_lock);
59
60void __iomem *eisa_eeprom_addr;
61
62/* We can only have one EISA adapter in the system because neither
63 * implementation can be flexed.
64 */
65static struct eisa_ba {
66 struct pci_hba_data hba;
67 unsigned long eeprom_addr;
68 struct eisa_root_device root;
69} eisa_dev;
70
71/* Port ops */
72
73static inline unsigned long eisa_permute(unsigned short port)
74{
75 if (port & 0x300) {
76 return 0xfc000000 | ((port & 0xfc00) >> 6)
77 | ((port & 0x3f8) << 9) | (port & 7);
78 } else {
79 return 0xfc000000 | port;
80 }
81}
82
83unsigned char eisa_in8(unsigned short port)
84{
85 if (EISA_bus)
86 return gsc_readb(eisa_permute(port));
87 return 0xff;
88}
89
90unsigned short eisa_in16(unsigned short port)
91{
92 if (EISA_bus)
93 return le16_to_cpu(gsc_readw(eisa_permute(port)));
94 return 0xffff;
95}
96
97unsigned int eisa_in32(unsigned short port)
98{
99 if (EISA_bus)
100 return le32_to_cpu(gsc_readl(eisa_permute(port)));
101 return 0xffffffff;
102}
103
104void eisa_out8(unsigned char data, unsigned short port)
105{
106 if (EISA_bus)
107 gsc_writeb(data, eisa_permute(port));
108}
109
110void eisa_out16(unsigned short data, unsigned short port)
111{
112 if (EISA_bus)
113 gsc_writew(cpu_to_le16(data), eisa_permute(port));
114}
115
116void eisa_out32(unsigned int data, unsigned short port)
117{
118 if (EISA_bus)
119 gsc_writel(cpu_to_le32(data), eisa_permute(port));
120}
121
122#ifndef CONFIG_PCI
123/* We call these directly without PCI. See asm/io.h. */
124EXPORT_SYMBOL(eisa_in8);
125EXPORT_SYMBOL(eisa_in16);
126EXPORT_SYMBOL(eisa_in32);
127EXPORT_SYMBOL(eisa_out8);
128EXPORT_SYMBOL(eisa_out16);
129EXPORT_SYMBOL(eisa_out32);
130#endif
131
132/* Interrupt handling */
133
134/* cached interrupt mask registers */
135static int master_mask;
136static int slave_mask;
137
138/* the trig level can be set with the
139 * eisa_irq_edge=n,n,n commandline parameter
140 * We should really read this from the EEPROM
141 * in the furure.
142 */
143/* irq 13,8,2,1,0 must be edge */
144static unsigned int eisa_irq_level; /* default to edge triggered */
145
146
147/* called by free irq */
148static void eisa_disable_irq(unsigned int irq)
149{
150 unsigned long flags;
151
152 EISA_DBG("disable irq %d\n", irq);
153 /* just mask for now */
154 spin_lock_irqsave(&eisa_irq_lock, flags);
155 if (irq & 8) {
156 slave_mask |= (1 << (irq&7));
157 eisa_out8(slave_mask, 0xa1);
158 } else {
159 master_mask |= (1 << (irq&7));
160 eisa_out8(master_mask, 0x21);
161 }
162 spin_unlock_irqrestore(&eisa_irq_lock, flags);
163 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
164 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
165}
166
167/* called by request irq */
168static void eisa_enable_irq(unsigned int irq)
169{
170 unsigned long flags;
171 EISA_DBG("enable irq %d\n", irq);
172
173 spin_lock_irqsave(&eisa_irq_lock, flags);
174 if (irq & 8) {
175 slave_mask &= ~(1 << (irq&7));
176 eisa_out8(slave_mask, 0xa1);
177 } else {
178 master_mask &= ~(1 << (irq&7));
179 eisa_out8(master_mask, 0x21);
180 }
181 spin_unlock_irqrestore(&eisa_irq_lock, flags);
182 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
183 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
184}
185
186static unsigned int eisa_startup_irq(unsigned int irq)
187{
188 eisa_enable_irq(irq);
189 return 0;
190}
191
192static struct hw_interrupt_type eisa_interrupt_type = {
193 .typename = "EISA",
194 .startup = eisa_startup_irq,
195 .shutdown = eisa_disable_irq,
196 .enable = eisa_enable_irq,
197 .disable = eisa_disable_irq,
198 .ack = no_ack_irq,
199 .end = no_end_irq,
200};
201
202static irqreturn_t eisa_irq(int wax_irq, void *intr_dev, struct pt_regs *regs)
203{
204 int irq = gsc_readb(0xfc01f000); /* EISA supports 16 irqs */
205 unsigned long flags;
206
207 spin_lock_irqsave(&eisa_irq_lock, flags);
208 /* read IRR command */
209 eisa_out8(0x0a, 0x20);
210 eisa_out8(0x0a, 0xa0);
211
212 EISA_DBG("irq IAR %02x 8259-1 irr %02x 8259-2 irr %02x\n",
213 irq, eisa_in8(0x20), eisa_in8(0xa0));
214
215 /* read ISR command */
216 eisa_out8(0x0a, 0x20);
217 eisa_out8(0x0a, 0xa0);
218 EISA_DBG("irq 8259-1 isr %02x imr %02x 8259-2 isr %02x imr %02x\n",
219 eisa_in8(0x20), eisa_in8(0x21), eisa_in8(0xa0), eisa_in8(0xa1));
220
221 irq &= 0xf;
222
223 /* mask irq and write eoi */
224 if (irq & 8) {
225 slave_mask |= (1 << (irq&7));
226 eisa_out8(slave_mask, 0xa1);
227 eisa_out8(0x60 | (irq&7),0xa0);/* 'Specific EOI' to slave */
228 eisa_out8(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
229
230 } else {
231 master_mask |= (1 << (irq&7));
232 eisa_out8(master_mask, 0x21);
233 eisa_out8(0x60|irq,0x20); /* 'Specific EOI' to master */
234 }
235 spin_unlock_irqrestore(&eisa_irq_lock, flags);
236
237 __do_IRQ(irq, regs);
238
239 spin_lock_irqsave(&eisa_irq_lock, flags);
240 /* unmask */
241 if (irq & 8) {
242 slave_mask &= ~(1 << (irq&7));
243 eisa_out8(slave_mask, 0xa1);
244 } else {
245 master_mask &= ~(1 << (irq&7));
246 eisa_out8(master_mask, 0x21);
247 }
248 spin_unlock_irqrestore(&eisa_irq_lock, flags);
249 return IRQ_HANDLED;
250}
251
252static irqreturn_t dummy_irq2_handler(int _, void *dev, struct pt_regs *regs)
253{
254 printk(KERN_ALERT "eisa: uhh, irq2?\n");
255 return IRQ_HANDLED;
256}
257
258static struct irqaction irq2_action = {
259 .handler = dummy_irq2_handler,
260 .name = "cascade",
261};
262
263static void init_eisa_pic(void)
264{
265 unsigned long flags;
266
267 spin_lock_irqsave(&eisa_irq_lock, flags);
268
269 eisa_out8(0xff, 0x21); /* mask during init */
270 eisa_out8(0xff, 0xa1); /* mask during init */
271
272 /* master pic */
273 eisa_out8(0x11,0x20); /* ICW1 */
274 eisa_out8(0x00,0x21); /* ICW2 */
275 eisa_out8(0x04,0x21); /* ICW3 */
276 eisa_out8(0x01,0x21); /* ICW4 */
277 eisa_out8(0x40,0x20); /* OCW2 */
278
279 /* slave pic */
280 eisa_out8(0x11,0xa0); /* ICW1 */
281 eisa_out8(0x08,0xa1); /* ICW2 */
282 eisa_out8(0x02,0xa1); /* ICW3 */
283 eisa_out8(0x01,0xa1); /* ICW4 */
284 eisa_out8(0x40,0xa0); /* OCW2 */
285
286 udelay(100);
287
288 slave_mask = 0xff;
289 master_mask = 0xfb;
290 eisa_out8(slave_mask, 0xa1); /* OCW1 */
291 eisa_out8(master_mask, 0x21); /* OCW1 */
292
293 /* setup trig level */
294 EISA_DBG("EISA edge/level %04x\n", eisa_irq_level);
295
296 eisa_out8(eisa_irq_level&0xff, 0x4d0); /* Set all irq's to edge */
297 eisa_out8((eisa_irq_level >> 8) & 0xff, 0x4d1);
298
299 EISA_DBG("pic0 mask %02x\n", eisa_in8(0x21));
300 EISA_DBG("pic1 mask %02x\n", eisa_in8(0xa1));
301 EISA_DBG("pic0 edge/level %02x\n", eisa_in8(0x4d0));
302 EISA_DBG("pic1 edge/level %02x\n", eisa_in8(0x4d1));
303
304 spin_unlock_irqrestore(&eisa_irq_lock, flags);
305}
306
307/* Device initialisation */
308
309#define is_mongoose(dev) (dev->id.sversion == 0x00076)
310
311static int __devinit eisa_probe(struct parisc_device *dev)
312{
313 int i, result;
314
315 char *name = is_mongoose(dev) ? "Mongoose" : "Wax";
316
317 printk(KERN_INFO "%s EISA Adapter found at 0x%08lx\n",
318 name, dev->hpa);
319
320 eisa_dev.hba.dev = dev;
321 eisa_dev.hba.iommu = ccio_get_iommu(dev);
322
323 eisa_dev.hba.lmmio_space.name = "EISA";
324 eisa_dev.hba.lmmio_space.start = F_EXTEND(0xfc000000);
325 eisa_dev.hba.lmmio_space.end = F_EXTEND(0xffbfffff);
326 eisa_dev.hba.lmmio_space.flags = IORESOURCE_MEM;
327 result = ccio_request_resource(dev, &eisa_dev.hba.lmmio_space);
328 if (result < 0) {
329 printk(KERN_ERR "EISA: failed to claim EISA Bus address space!\n");
330 return result;
331 }
332 eisa_dev.hba.io_space.name = "EISA";
333 eisa_dev.hba.io_space.start = 0;
334 eisa_dev.hba.io_space.end = 0xffff;
335 eisa_dev.hba.lmmio_space.flags = IORESOURCE_IO;
336 result = request_resource(&ioport_resource, &eisa_dev.hba.io_space);
337 if (result < 0) {
338 printk(KERN_ERR "EISA: failed to claim EISA Bus port space!\n");
339 return result;
340 }
341 pcibios_register_hba(&eisa_dev.hba);
342
343 result = request_irq(dev->irq, eisa_irq, SA_SHIRQ, "EISA", &eisa_dev);
344 if (result) {
345 printk(KERN_ERR "EISA: request_irq failed!\n");
346 return result;
347 }
348
349 /* Reserve IRQ2 */
350 irq_desc[2].action = &irq2_action;
351
352 for (i = 0; i < 16; i++) {
353 irq_desc[i].handler = &eisa_interrupt_type;
354 }
355
356 EISA_bus = 1;
357
358 if (dev->num_addrs) {
359 /* newer firmware hand out the eeprom address */
360 eisa_dev.eeprom_addr = dev->addr[0];
361 } else {
362 /* old firmware, need to figure out the box */
363 if (is_mongoose(dev)) {
364 eisa_dev.eeprom_addr = SNAKES_EEPROM_BASE_ADDR;
365 } else {
366 eisa_dev.eeprom_addr = MIRAGE_EEPROM_BASE_ADDR;
367 }
368 }
369 eisa_eeprom_addr = ioremap(eisa_dev.eeprom_addr, HPEE_MAX_LENGTH);
370 result = eisa_enumerator(eisa_dev.eeprom_addr, &eisa_dev.hba.io_space,
371 &eisa_dev.hba.lmmio_space);
372 init_eisa_pic();
373
374 if (result >= 0) {
375 /* FIXME : Don't enumerate the bus twice. */
376 eisa_dev.root.dev = &dev->dev;
377 dev->dev.driver_data = &eisa_dev.root;
378 eisa_dev.root.bus_base_addr = 0;
379 eisa_dev.root.res = &eisa_dev.hba.io_space;
380 eisa_dev.root.slots = result;
381 eisa_dev.root.dma_mask = 0xffffffff; /* wild guess */
382 if (eisa_root_register (&eisa_dev.root)) {
383 printk(KERN_ERR "EISA: Failed to register EISA root\n");
384 return -1;
385 }
386 }
387
388 return 0;
389}
390
391static struct parisc_device_id eisa_tbl[] = {
392 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00076 }, /* Mongoose */
393 { HPHW_BA, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00090 }, /* Wax EISA */
394 { 0, }
395};
396
397MODULE_DEVICE_TABLE(parisc, eisa_tbl);
398
399static struct parisc_driver eisa_driver = {
400 .name = "EISA Bus Adapter",
401 .id_table = eisa_tbl,
402 .probe = eisa_probe,
403};
404
405void __init eisa_init(void)
406{
407 register_parisc_driver(&eisa_driver);
408}
409
410
411static unsigned int eisa_irq_configured;
412void eisa_make_irq_level(int num)
413{
414 if (eisa_irq_configured& (1<<num)) {
415 printk(KERN_WARNING
416 "IRQ %d polarity configured twice (last to level)\n",
417 num);
418 }
419 eisa_irq_level |= (1<<num); /* set the corresponding bit */
420 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
421}
422
423void eisa_make_irq_edge(int num)
424{
425 if (eisa_irq_configured& (1<<num)) {
426 printk(KERN_WARNING
427 "IRQ %d polarity configured twice (last to edge)\n",
428 num);
429 }
430 eisa_irq_level &= ~(1<<num); /* clear the corresponding bit */
431 eisa_irq_configured |= (1<<num); /* set the corresponding bit */
432}
433
434static int __init eisa_irq_setup(char *str)
435{
436 char *cur = str;
437 int val;
438
439 EISA_DBG("IRQ setup\n");
440 while (cur != NULL) {
441 char *pe;
442
443 val = (int) simple_strtoul(cur, &pe, 0);
444 if (val > 15 || val < 0) {
445 printk(KERN_ERR "eisa: EISA irq value are 0-15\n");
446 continue;
447 }
448 if (val == 2) {
449 val = 9;
450 }
451 eisa_make_irq_edge(val); /* clear the corresponding bit */
452 EISA_DBG("setting IRQ %d to edge-triggered mode\n", val);
453
454 if ((cur = strchr(cur, ','))) {
455 cur++;
456 } else {
457 break;
458 }
459 }
460 return 1;
461}
462
463__setup("eisa_irq_edge=", eisa_irq_setup);
464