blob: 1550692973dc2ebcaa6864bc3e2c51607872b818 [file] [log] [blame]
Linus Walleij6c009ab2010-09-13 00:35:22 +02001/*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19#include <linux/clk.h>
Vipin Kumar4774fb02012-03-14 11:47:18 +053020#include <linux/completion.h>
21#include <linux/dmaengine.h>
22#include <linux/dma-direction.h>
23#include <linux/dma-mapping.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020024#include <linux/err.h>
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/resource.h>
28#include <linux/sched.h>
29#include <linux/types.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/nand.h>
32#include <linux/mtd/nand_ecc.h>
33#include <linux/platform_device.h>
Stefan Roeseeea62812012-03-16 10:19:31 +010034#include <linux/of.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020035#include <linux/mtd/partitions.h>
36#include <linux/io.h>
37#include <linux/slab.h>
38#include <linux/mtd/fsmc.h>
Linus Walleij593cd872010-11-29 13:52:19 +010039#include <linux/amba/bus.h>
Linus Walleij6c009ab2010-09-13 00:35:22 +020040#include <mtd/mtd-abi.h>
41
Bhavna Yadave29ee572012-03-07 17:00:50 +053042static struct nand_ecclayout fsmc_ecc1_128_layout = {
Linus Walleij6c009ab2010-09-13 00:35:22 +020043 .eccbytes = 24,
44 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
45 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
46 .oobfree = {
47 {.offset = 8, .length = 8},
48 {.offset = 24, .length = 8},
49 {.offset = 40, .length = 8},
50 {.offset = 56, .length = 8},
51 {.offset = 72, .length = 8},
52 {.offset = 88, .length = 8},
53 {.offset = 104, .length = 8},
54 {.offset = 120, .length = 8}
55 }
56};
57
Bhavna Yadave29ee572012-03-07 17:00:50 +053058static struct nand_ecclayout fsmc_ecc1_64_layout = {
59 .eccbytes = 12,
60 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
61 .oobfree = {
62 {.offset = 8, .length = 8},
63 {.offset = 24, .length = 8},
64 {.offset = 40, .length = 8},
65 {.offset = 56, .length = 8},
66 }
67};
68
69static struct nand_ecclayout fsmc_ecc1_16_layout = {
70 .eccbytes = 3,
71 .eccpos = {2, 3, 4},
72 .oobfree = {
73 {.offset = 8, .length = 8},
74 }
75};
76
77/*
78 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
79 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
80 * bytes are free for use.
81 */
82static struct nand_ecclayout fsmc_ecc4_256_layout = {
83 .eccbytes = 208,
84 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
85 9, 10, 11, 12, 13, 14,
86 18, 19, 20, 21, 22, 23, 24,
87 25, 26, 27, 28, 29, 30,
88 34, 35, 36, 37, 38, 39, 40,
89 41, 42, 43, 44, 45, 46,
90 50, 51, 52, 53, 54, 55, 56,
91 57, 58, 59, 60, 61, 62,
92 66, 67, 68, 69, 70, 71, 72,
93 73, 74, 75, 76, 77, 78,
94 82, 83, 84, 85, 86, 87, 88,
95 89, 90, 91, 92, 93, 94,
96 98, 99, 100, 101, 102, 103, 104,
97 105, 106, 107, 108, 109, 110,
98 114, 115, 116, 117, 118, 119, 120,
99 121, 122, 123, 124, 125, 126,
100 130, 131, 132, 133, 134, 135, 136,
101 137, 138, 139, 140, 141, 142,
102 146, 147, 148, 149, 150, 151, 152,
103 153, 154, 155, 156, 157, 158,
104 162, 163, 164, 165, 166, 167, 168,
105 169, 170, 171, 172, 173, 174,
106 178, 179, 180, 181, 182, 183, 184,
107 185, 186, 187, 188, 189, 190,
108 194, 195, 196, 197, 198, 199, 200,
109 201, 202, 203, 204, 205, 206,
110 210, 211, 212, 213, 214, 215, 216,
111 217, 218, 219, 220, 221, 222,
112 226, 227, 228, 229, 230, 231, 232,
113 233, 234, 235, 236, 237, 238,
114 242, 243, 244, 245, 246, 247, 248,
115 249, 250, 251, 252, 253, 254
116 },
117 .oobfree = {
118 {.offset = 15, .length = 3},
119 {.offset = 31, .length = 3},
120 {.offset = 47, .length = 3},
121 {.offset = 63, .length = 3},
122 {.offset = 79, .length = 3},
123 {.offset = 95, .length = 3},
124 {.offset = 111, .length = 3},
125 {.offset = 127, .length = 3},
126 {.offset = 143, .length = 3},
127 {.offset = 159, .length = 3},
128 {.offset = 175, .length = 3},
129 {.offset = 191, .length = 3},
130 {.offset = 207, .length = 3},
131 {.offset = 223, .length = 3},
132 {.offset = 239, .length = 3},
133 {.offset = 255, .length = 1}
134 }
135};
136
137/*
Armando Visconti0c78e932012-03-07 17:00:55 +0530138 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
139 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
140 * bytes are free for use.
141 */
142static struct nand_ecclayout fsmc_ecc4_224_layout = {
143 .eccbytes = 104,
144 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
145 9, 10, 11, 12, 13, 14,
146 18, 19, 20, 21, 22, 23, 24,
147 25, 26, 27, 28, 29, 30,
148 34, 35, 36, 37, 38, 39, 40,
149 41, 42, 43, 44, 45, 46,
150 50, 51, 52, 53, 54, 55, 56,
151 57, 58, 59, 60, 61, 62,
152 66, 67, 68, 69, 70, 71, 72,
153 73, 74, 75, 76, 77, 78,
154 82, 83, 84, 85, 86, 87, 88,
155 89, 90, 91, 92, 93, 94,
156 98, 99, 100, 101, 102, 103, 104,
157 105, 106, 107, 108, 109, 110,
158 114, 115, 116, 117, 118, 119, 120,
159 121, 122, 123, 124, 125, 126
160 },
161 .oobfree = {
162 {.offset = 15, .length = 3},
163 {.offset = 31, .length = 3},
164 {.offset = 47, .length = 3},
165 {.offset = 63, .length = 3},
166 {.offset = 79, .length = 3},
167 {.offset = 95, .length = 3},
168 {.offset = 111, .length = 3},
169 {.offset = 127, .length = 97}
170 }
171};
172
173/*
Bhavna Yadave29ee572012-03-07 17:00:50 +0530174 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
175 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
176 * bytes are free for use.
177 */
178static struct nand_ecclayout fsmc_ecc4_128_layout = {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200179 .eccbytes = 104,
180 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
181 9, 10, 11, 12, 13, 14,
182 18, 19, 20, 21, 22, 23, 24,
183 25, 26, 27, 28, 29, 30,
184 34, 35, 36, 37, 38, 39, 40,
185 41, 42, 43, 44, 45, 46,
186 50, 51, 52, 53, 54, 55, 56,
187 57, 58, 59, 60, 61, 62,
188 66, 67, 68, 69, 70, 71, 72,
189 73, 74, 75, 76, 77, 78,
190 82, 83, 84, 85, 86, 87, 88,
191 89, 90, 91, 92, 93, 94,
192 98, 99, 100, 101, 102, 103, 104,
193 105, 106, 107, 108, 109, 110,
194 114, 115, 116, 117, 118, 119, 120,
195 121, 122, 123, 124, 125, 126
196 },
197 .oobfree = {
198 {.offset = 15, .length = 3},
199 {.offset = 31, .length = 3},
200 {.offset = 47, .length = 3},
201 {.offset = 63, .length = 3},
202 {.offset = 79, .length = 3},
203 {.offset = 95, .length = 3},
204 {.offset = 111, .length = 3},
205 {.offset = 127, .length = 1}
206 }
207};
208
209/*
Bhavna Yadave29ee572012-03-07 17:00:50 +0530210 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
211 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
212 * bytes are free for use.
213 */
214static struct nand_ecclayout fsmc_ecc4_64_layout = {
215 .eccbytes = 52,
216 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
217 9, 10, 11, 12, 13, 14,
218 18, 19, 20, 21, 22, 23, 24,
219 25, 26, 27, 28, 29, 30,
220 34, 35, 36, 37, 38, 39, 40,
221 41, 42, 43, 44, 45, 46,
222 50, 51, 52, 53, 54, 55, 56,
223 57, 58, 59, 60, 61, 62,
224 },
225 .oobfree = {
226 {.offset = 15, .length = 3},
227 {.offset = 31, .length = 3},
228 {.offset = 47, .length = 3},
229 {.offset = 63, .length = 1},
230 }
231};
232
233/*
234 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
235 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
236 * byte is free for use.
237 */
238static struct nand_ecclayout fsmc_ecc4_16_layout = {
239 .eccbytes = 13,
240 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
241 9, 10, 11, 12, 13, 14
242 },
243 .oobfree = {
244 {.offset = 15, .length = 1},
245 }
246};
247
248/*
Linus Walleij6c009ab2010-09-13 00:35:22 +0200249 * ECC placement definitions in oobfree type format.
250 * There are 13 bytes of ecc for every 512 byte block and it has to be read
251 * consecutively and immediately after the 512 byte data block for hardware to
252 * generate the error bit offsets in 512 byte data.
253 * Managing the ecc bytes in the following way makes it easier for software to
254 * read ecc bytes consecutive to data bytes. This way is similar to
255 * oobfree structure maintained already in generic nand driver
256 */
257static struct fsmc_eccplace fsmc_ecc4_lp_place = {
258 .eccplace = {
259 {.offset = 2, .length = 13},
260 {.offset = 18, .length = 13},
261 {.offset = 34, .length = 13},
262 {.offset = 50, .length = 13},
263 {.offset = 66, .length = 13},
264 {.offset = 82, .length = 13},
265 {.offset = 98, .length = 13},
266 {.offset = 114, .length = 13}
267 }
268};
269
Linus Walleij6c009ab2010-09-13 00:35:22 +0200270static struct fsmc_eccplace fsmc_ecc4_sp_place = {
271 .eccplace = {
272 {.offset = 0, .length = 4},
273 {.offset = 6, .length = 9}
274 }
275};
276
Linus Walleij6c009ab2010-09-13 00:35:22 +0200277/**
Linus Walleij593cd872010-11-29 13:52:19 +0100278 * struct fsmc_nand_data - structure for FSMC NAND device state
Linus Walleij6c009ab2010-09-13 00:35:22 +0200279 *
Linus Walleij593cd872010-11-29 13:52:19 +0100280 * @pid: Part ID on the AMBA PrimeCell format
Linus Walleij6c009ab2010-09-13 00:35:22 +0200281 * @mtd: MTD info for a NAND flash.
282 * @nand: Chip related info for a NAND flash.
Vipin Kumar71470322012-03-14 11:47:07 +0530283 * @partitions: Partition info for a NAND Flash.
284 * @nr_partitions: Total number of partition of a NAND flash.
Linus Walleij6c009ab2010-09-13 00:35:22 +0200285 *
286 * @ecc_place: ECC placing locations in oobfree type format.
287 * @bank: Bank number for probed device.
288 * @clk: Clock structure for FSMC.
289 *
Vipin Kumar4774fb02012-03-14 11:47:18 +0530290 * @read_dma_chan: DMA channel for read access
291 * @write_dma_chan: DMA channel for write access to NAND
292 * @dma_access_complete: Completion structure
293 *
294 * @data_pa: NAND Physical port for Data.
Linus Walleij6c009ab2010-09-13 00:35:22 +0200295 * @data_va: NAND port for Data.
296 * @cmd_va: NAND port for Command.
297 * @addr_va: NAND port for Address.
298 * @regs_va: FSMC regs base address.
299 */
300struct fsmc_nand_data {
Linus Walleij593cd872010-11-29 13:52:19 +0100301 u32 pid;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200302 struct mtd_info mtd;
303 struct nand_chip nand;
Vipin Kumar71470322012-03-14 11:47:07 +0530304 struct mtd_partition *partitions;
305 unsigned int nr_partitions;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200306
307 struct fsmc_eccplace *ecc_place;
308 unsigned int bank;
Vipin Kumar712c4ad2012-03-14 11:47:16 +0530309 struct device *dev;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530310 enum access_mode mode;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200311 struct clk *clk;
312
Vipin Kumar4774fb02012-03-14 11:47:18 +0530313 /* DMA related objects */
314 struct dma_chan *read_dma_chan;
315 struct dma_chan *write_dma_chan;
316 struct completion dma_access_complete;
317
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530318 struct fsmc_nand_timings *dev_timings;
319
Vipin Kumar4774fb02012-03-14 11:47:18 +0530320 dma_addr_t data_pa;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200321 void __iomem *data_va;
322 void __iomem *cmd_va;
323 void __iomem *addr_va;
324 void __iomem *regs_va;
325
326 void (*select_chip)(uint32_t bank, uint32_t busw);
327};
328
329/* Assert CS signal based on chipnr */
330static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
331{
332 struct nand_chip *chip = mtd->priv;
333 struct fsmc_nand_data *host;
334
335 host = container_of(mtd, struct fsmc_nand_data, mtd);
336
337 switch (chipnr) {
338 case -1:
339 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
340 break;
341 case 0:
342 case 1:
343 case 2:
344 case 3:
345 if (host->select_chip)
346 host->select_chip(chipnr,
347 chip->options & NAND_BUSWIDTH_16);
348 break;
349
350 default:
351 BUG();
352 }
353}
354
355/*
356 * fsmc_cmd_ctrl - For facilitaing Hardware access
357 * This routine allows hardware specific access to control-lines(ALE,CLE)
358 */
359static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
360{
361 struct nand_chip *this = mtd->priv;
362 struct fsmc_nand_data *host = container_of(mtd,
363 struct fsmc_nand_data, mtd);
Vipin Kumar605add72012-10-09 16:14:43 +0530364 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200365 unsigned int bank = host->bank;
366
367 if (ctrl & NAND_CTRL_CHANGE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530368 u32 pc;
369
Linus Walleij6c009ab2010-09-13 00:35:22 +0200370 if (ctrl & NAND_CLE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530371 this->IO_ADDR_R = host->cmd_va;
372 this->IO_ADDR_W = host->cmd_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200373 } else if (ctrl & NAND_ALE) {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530374 this->IO_ADDR_R = host->addr_va;
375 this->IO_ADDR_W = host->addr_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200376 } else {
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530377 this->IO_ADDR_R = host->data_va;
378 this->IO_ADDR_W = host->data_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200379 }
380
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530381 pc = readl(FSMC_NAND_REG(regs, bank, PC));
382 if (ctrl & NAND_NCE)
383 pc |= FSMC_ENABLE;
384 else
385 pc &= ~FSMC_ENABLE;
Vipin Kumara4742d52012-10-09 16:14:50 +0530386 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200387 }
388
389 mb();
390
391 if (cmd != NAND_CMD_NONE)
Vipin Kumara4742d52012-10-09 16:14:50 +0530392 writeb_relaxed(cmd, this->IO_ADDR_W);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200393}
394
395/*
396 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
397 *
398 * This routine initializes timing parameters related to NAND memory access in
399 * FSMC registers
400 */
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530401static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530402 uint32_t busw, struct fsmc_nand_timings *timings)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200403{
404 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
Vipin Kumare2f6bce2012-03-14 11:47:14 +0530405 uint32_t tclr, tar, thiz, thold, twait, tset;
406 struct fsmc_nand_timings *tims;
407 struct fsmc_nand_timings default_timings = {
408 .tclr = FSMC_TCLR_1,
409 .tar = FSMC_TAR_1,
410 .thiz = FSMC_THIZ_1,
411 .thold = FSMC_THOLD_4,
412 .twait = FSMC_TWAIT_6,
413 .tset = FSMC_TSET_0,
414 };
415
416 if (timings)
417 tims = timings;
418 else
419 tims = &default_timings;
420
421 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
422 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
423 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
424 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
425 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
426 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200427
428 if (busw)
Vipin Kumara4742d52012-10-09 16:14:50 +0530429 writel_relaxed(value | FSMC_DEVWID_16,
430 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200431 else
Vipin Kumara4742d52012-10-09 16:14:50 +0530432 writel_relaxed(value | FSMC_DEVWID_8,
433 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200434
Vipin Kumara4742d52012-10-09 16:14:50 +0530435 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530436 FSMC_NAND_REG(regs, bank, PC));
Vipin Kumara4742d52012-10-09 16:14:50 +0530437 writel_relaxed(thiz | thold | twait | tset,
438 FSMC_NAND_REG(regs, bank, COMM));
439 writel_relaxed(thiz | thold | twait | tset,
440 FSMC_NAND_REG(regs, bank, ATTRIB));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200441}
442
443/*
444 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
445 */
446static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
447{
448 struct fsmc_nand_data *host = container_of(mtd,
449 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530450 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200451 uint32_t bank = host->bank;
452
Vipin Kumara4742d52012-10-09 16:14:50 +0530453 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530454 FSMC_NAND_REG(regs, bank, PC));
Vipin Kumara4742d52012-10-09 16:14:50 +0530455 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530456 FSMC_NAND_REG(regs, bank, PC));
Vipin Kumara4742d52012-10-09 16:14:50 +0530457 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530458 FSMC_NAND_REG(regs, bank, PC));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200459}
460
461/*
462 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300463 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
Linus Walleij6c009ab2010-09-13 00:35:22 +0200464 * max of 8-bits)
465 */
466static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
467 uint8_t *ecc)
468{
469 struct fsmc_nand_data *host = container_of(mtd,
470 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530471 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200472 uint32_t bank = host->bank;
473 uint32_t ecc_tmp;
474 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
475
476 do {
Vipin Kumara4742d52012-10-09 16:14:50 +0530477 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200478 break;
479 else
480 cond_resched();
481 } while (!time_after_eq(jiffies, deadline));
482
Vipin Kumar712c4ad2012-03-14 11:47:16 +0530483 if (time_after_eq(jiffies, deadline)) {
484 dev_err(host->dev, "calculate ecc timed out\n");
485 return -ETIMEDOUT;
486 }
487
Vipin Kumara4742d52012-10-09 16:14:50 +0530488 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200489 ecc[0] = (uint8_t) (ecc_tmp >> 0);
490 ecc[1] = (uint8_t) (ecc_tmp >> 8);
491 ecc[2] = (uint8_t) (ecc_tmp >> 16);
492 ecc[3] = (uint8_t) (ecc_tmp >> 24);
493
Vipin Kumara4742d52012-10-09 16:14:50 +0530494 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200495 ecc[4] = (uint8_t) (ecc_tmp >> 0);
496 ecc[5] = (uint8_t) (ecc_tmp >> 8);
497 ecc[6] = (uint8_t) (ecc_tmp >> 16);
498 ecc[7] = (uint8_t) (ecc_tmp >> 24);
499
Vipin Kumara4742d52012-10-09 16:14:50 +0530500 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200501 ecc[8] = (uint8_t) (ecc_tmp >> 0);
502 ecc[9] = (uint8_t) (ecc_tmp >> 8);
503 ecc[10] = (uint8_t) (ecc_tmp >> 16);
504 ecc[11] = (uint8_t) (ecc_tmp >> 24);
505
Vipin Kumara4742d52012-10-09 16:14:50 +0530506 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200507 ecc[12] = (uint8_t) (ecc_tmp >> 16);
508
509 return 0;
510}
511
512/*
513 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300514 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
Linus Walleij6c009ab2010-09-13 00:35:22 +0200515 * max of 1-bit)
516 */
517static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
518 uint8_t *ecc)
519{
520 struct fsmc_nand_data *host = container_of(mtd,
521 struct fsmc_nand_data, mtd);
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530522 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200523 uint32_t bank = host->bank;
524 uint32_t ecc_tmp;
525
Vipin Kumara4742d52012-10-09 16:14:50 +0530526 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200527 ecc[0] = (uint8_t) (ecc_tmp >> 0);
528 ecc[1] = (uint8_t) (ecc_tmp >> 8);
529 ecc[2] = (uint8_t) (ecc_tmp >> 16);
530
531 return 0;
532}
533
Vipin Kumar519300c2012-03-07 17:00:49 +0530534/* Count the number of 0's in buff upto a max of max_bits */
535static int count_written_bits(uint8_t *buff, int size, int max_bits)
536{
537 int k, written_bits = 0;
538
539 for (k = 0; k < size; k++) {
540 written_bits += hweight8(~buff[k]);
541 if (written_bits > max_bits)
542 break;
543 }
544
545 return written_bits;
546}
547
Vipin Kumar4774fb02012-03-14 11:47:18 +0530548static void dma_complete(void *param)
549{
550 struct fsmc_nand_data *host = param;
551
552 complete(&host->dma_access_complete);
553}
554
555static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
556 enum dma_data_direction direction)
557{
558 struct dma_chan *chan;
559 struct dma_device *dma_dev;
560 struct dma_async_tx_descriptor *tx;
561 dma_addr_t dma_dst, dma_src, dma_addr;
562 dma_cookie_t cookie;
563 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
564 int ret;
565
566 if (direction == DMA_TO_DEVICE)
567 chan = host->write_dma_chan;
568 else if (direction == DMA_FROM_DEVICE)
569 chan = host->read_dma_chan;
570 else
571 return -EINVAL;
572
573 dma_dev = chan->device;
574 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
575
576 if (direction == DMA_TO_DEVICE) {
577 dma_src = dma_addr;
578 dma_dst = host->data_pa;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530579 } else {
580 dma_src = host->data_pa;
581 dma_dst = dma_addr;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530582 }
583
584 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
585 len, flags);
Vipin Kumar4774fb02012-03-14 11:47:18 +0530586 if (!tx) {
587 dev_err(host->dev, "device_prep_dma_memcpy error\n");
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000588 ret = -EIO;
589 goto unmap_dma;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530590 }
591
592 tx->callback = dma_complete;
593 tx->callback_param = host;
594 cookie = tx->tx_submit(tx);
595
596 ret = dma_submit_error(cookie);
597 if (ret) {
598 dev_err(host->dev, "dma_submit_error %d\n", cookie);
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000599 goto unmap_dma;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530600 }
601
602 dma_async_issue_pending(chan);
603
604 ret =
Vipin Kumar928aa2a2012-10-09 16:14:48 +0530605 wait_for_completion_timeout(&host->dma_access_complete,
Vipin Kumar4774fb02012-03-14 11:47:18 +0530606 msecs_to_jiffies(3000));
607 if (ret <= 0) {
608 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
609 dev_err(host->dev, "wait_for_completion_timeout\n");
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000610 if (!ret)
611 ret = -ETIMEDOUT;
612 goto unmap_dma;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530613 }
614
Bartlomiej Zolnierkiewiczd1806a52012-11-05 10:00:14 +0000615 ret = 0;
616
617unmap_dma:
618 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
619
620 return ret;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530621}
622
Linus Walleij6c009ab2010-09-13 00:35:22 +0200623/*
Vipin Kumar604e7542012-03-14 11:47:17 +0530624 * fsmc_write_buf - write buffer to chip
625 * @mtd: MTD device structure
626 * @buf: data buffer
627 * @len: number of bytes to write
628 */
629static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
630{
631 int i;
632 struct nand_chip *chip = mtd->priv;
633
634 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
635 IS_ALIGNED(len, sizeof(uint32_t))) {
636 uint32_t *p = (uint32_t *)buf;
637 len = len >> 2;
638 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530639 writel_relaxed(p[i], chip->IO_ADDR_W);
Vipin Kumar604e7542012-03-14 11:47:17 +0530640 } else {
641 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530642 writeb_relaxed(buf[i], chip->IO_ADDR_W);
Vipin Kumar604e7542012-03-14 11:47:17 +0530643 }
644}
645
646/*
647 * fsmc_read_buf - read chip data into buffer
648 * @mtd: MTD device structure
649 * @buf: buffer to store date
650 * @len: number of bytes to read
651 */
652static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
653{
654 int i;
655 struct nand_chip *chip = mtd->priv;
656
657 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
658 IS_ALIGNED(len, sizeof(uint32_t))) {
659 uint32_t *p = (uint32_t *)buf;
660 len = len >> 2;
661 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530662 p[i] = readl_relaxed(chip->IO_ADDR_R);
Vipin Kumar604e7542012-03-14 11:47:17 +0530663 } else {
664 for (i = 0; i < len; i++)
Vipin Kumara4742d52012-10-09 16:14:50 +0530665 buf[i] = readb_relaxed(chip->IO_ADDR_R);
Vipin Kumar604e7542012-03-14 11:47:17 +0530666 }
667}
668
669/*
Vipin Kumar4774fb02012-03-14 11:47:18 +0530670 * fsmc_read_buf_dma - read chip data into buffer
671 * @mtd: MTD device structure
672 * @buf: buffer to store date
673 * @len: number of bytes to read
674 */
675static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
676{
677 struct fsmc_nand_data *host;
678
679 host = container_of(mtd, struct fsmc_nand_data, mtd);
680 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
681}
682
683/*
684 * fsmc_write_buf_dma - write buffer to chip
685 * @mtd: MTD device structure
686 * @buf: data buffer
687 * @len: number of bytes to write
688 */
689static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
690 int len)
691{
692 struct fsmc_nand_data *host;
693
694 host = container_of(mtd, struct fsmc_nand_data, mtd);
695 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
696}
697
698/*
Linus Walleij6c009ab2010-09-13 00:35:22 +0200699 * fsmc_read_page_hwecc
700 * @mtd: mtd info structure
701 * @chip: nand chip info structure
702 * @buf: buffer to store read data
Brian Norris1fbb9382012-05-02 10:14:55 -0700703 * @oob_required: caller expects OOB data read to chip->oob_poi
Linus Walleij6c009ab2010-09-13 00:35:22 +0200704 * @page: page number to read
705 *
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300706 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
Linus Walleij6c009ab2010-09-13 00:35:22 +0200707 * performed in a strict sequence as follows:
708 * data(512 byte) -> ecc(13 byte)
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300709 * After this read, fsmc hardware generates and reports error data bits(up to a
Linus Walleij6c009ab2010-09-13 00:35:22 +0200710 * max of 8 bits)
711 */
712static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
Brian Norris1fbb9382012-05-02 10:14:55 -0700713 uint8_t *buf, int oob_required, int page)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200714{
715 struct fsmc_nand_data *host = container_of(mtd,
716 struct fsmc_nand_data, mtd);
717 struct fsmc_eccplace *ecc_place = host->ecc_place;
718 int i, j, s, stat, eccsize = chip->ecc.size;
719 int eccbytes = chip->ecc.bytes;
720 int eccsteps = chip->ecc.steps;
721 uint8_t *p = buf;
722 uint8_t *ecc_calc = chip->buffers->ecccalc;
723 uint8_t *ecc_code = chip->buffers->ecccode;
724 int off, len, group = 0;
725 /*
726 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
727 * end up reading 14 bytes (7 words) from oob. The local array is
728 * to maintain word alignment
729 */
730 uint16_t ecc_oob[7];
731 uint8_t *oob = (uint8_t *)&ecc_oob[0];
Mike Dunn3f91e942012-04-25 12:06:09 -0700732 unsigned int max_bitflips = 0;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200733
734 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200735 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
736 chip->ecc.hwctl(mtd, NAND_ECC_READ);
737 chip->read_buf(mtd, p, eccsize);
738
739 for (j = 0; j < eccbytes;) {
740 off = ecc_place->eccplace[group].offset;
741 len = ecc_place->eccplace[group].length;
742 group++;
743
744 /*
Vipin Kumar4cbe1bf02012-03-14 11:47:09 +0530745 * length is intentionally kept a higher multiple of 2
746 * to read at least 13 bytes even in case of 16 bit NAND
747 * devices
748 */
Vipin Kumaraea686b2012-03-14 11:47:10 +0530749 if (chip->options & NAND_BUSWIDTH_16)
750 len = roundup(len, 2);
751
Linus Walleij6c009ab2010-09-13 00:35:22 +0200752 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
753 chip->read_buf(mtd, oob + j, len);
754 j += len;
755 }
756
Vipin Kumar519300c2012-03-07 17:00:49 +0530757 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200758 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
759
760 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
Mike Dunn3f91e942012-04-25 12:06:09 -0700761 if (stat < 0) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200762 mtd->ecc_stats.failed++;
Mike Dunn3f91e942012-04-25 12:06:09 -0700763 } else {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200764 mtd->ecc_stats.corrected += stat;
Mike Dunn3f91e942012-04-25 12:06:09 -0700765 max_bitflips = max_t(unsigned int, max_bitflips, stat);
766 }
Linus Walleij6c009ab2010-09-13 00:35:22 +0200767 }
768
Mike Dunn3f91e942012-04-25 12:06:09 -0700769 return max_bitflips;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200770}
771
772/*
Armando Visconti753e0132012-03-07 17:00:54 +0530773 * fsmc_bch8_correct_data
Linus Walleij6c009ab2010-09-13 00:35:22 +0200774 * @mtd: mtd info structure
775 * @dat: buffer of read data
776 * @read_ecc: ecc read from device spare area
777 * @calc_ecc: ecc calculated from read data
778 *
779 * calc_ecc is a 104 bit information containing maximum of 8 error
780 * offset informations of 13 bits each in 512 bytes of read data.
781 */
Armando Visconti753e0132012-03-07 17:00:54 +0530782static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
Linus Walleij6c009ab2010-09-13 00:35:22 +0200783 uint8_t *read_ecc, uint8_t *calc_ecc)
784{
785 struct fsmc_nand_data *host = container_of(mtd,
786 struct fsmc_nand_data, mtd);
Vipin Kumar519300c2012-03-07 17:00:49 +0530787 struct nand_chip *chip = mtd->priv;
Vipin Kumar2a5dbead2012-03-14 11:47:19 +0530788 void __iomem *regs = host->regs_va;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200789 unsigned int bank = host->bank;
Armando Viscontia612c2a2012-03-07 17:00:53 +0530790 uint32_t err_idx[8];
Linus Walleij6c009ab2010-09-13 00:35:22 +0200791 uint32_t num_err, i;
Armando Visconti753e0132012-03-07 17:00:54 +0530792 uint32_t ecc1, ecc2, ecc3, ecc4;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200793
Vipin Kumara4742d52012-10-09 16:14:50 +0530794 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
Vipin Kumar519300c2012-03-07 17:00:49 +0530795
796 /* no bit flipping */
797 if (likely(num_err == 0))
798 return 0;
799
800 /* too many errors */
801 if (unlikely(num_err > 8)) {
802 /*
803 * This is a temporary erase check. A newly erased page read
804 * would result in an ecc error because the oob data is also
805 * erased to FF and the calculated ecc for an FF data is not
806 * FF..FF.
807 * This is a workaround to skip performing correction in case
808 * data is FF..FF
809 *
810 * Logic:
811 * For every page, each bit written as 0 is counted until these
812 * number of bits are greater than 8 (the maximum correction
813 * capability of FSMC for each 512 + 13 bytes)
814 */
815
816 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
817 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
818
819 if ((bits_ecc + bits_data) <= 8) {
820 if (bits_data)
821 memset(dat, 0xff, chip->ecc.size);
822 return bits_data;
823 }
824
825 return -EBADMSG;
826 }
827
Linus Walleij6c009ab2010-09-13 00:35:22 +0200828 /*
829 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
830 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
831 *
832 * calc_ecc is a 104 bit information containing maximum of 8 error
833 * offset informations of 13 bits each. calc_ecc is copied into a
834 * uint64_t array and error offset indexes are populated in err_idx
835 * array
836 */
Vipin Kumara4742d52012-10-09 16:14:50 +0530837 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
838 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
839 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
840 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
Linus Walleij6c009ab2010-09-13 00:35:22 +0200841
Armando Visconti753e0132012-03-07 17:00:54 +0530842 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
843 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
844 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
845 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
846 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
847 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
848 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
849 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200850
851 i = 0;
852 while (num_err--) {
853 change_bit(0, (unsigned long *)&err_idx[i]);
854 change_bit(1, (unsigned long *)&err_idx[i]);
855
Vipin Kumarb533f8d2012-03-14 11:47:11 +0530856 if (err_idx[i] < chip->ecc.size * 8) {
Linus Walleij6c009ab2010-09-13 00:35:22 +0200857 change_bit(err_idx[i], (unsigned long *)dat);
858 i++;
859 }
860 }
861 return i;
862}
863
Vipin Kumar4774fb02012-03-14 11:47:18 +0530864static bool filter(struct dma_chan *chan, void *slave)
865{
866 chan->private = slave;
867 return true;
868}
869
Stefan Roeseeea62812012-03-16 10:19:31 +0100870#ifdef CONFIG_OF
Bill Pemberton06f25512012-11-19 13:23:07 -0500871static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
Greg Kroah-Hartmand8929942012-12-21 13:19:05 -0800872 struct device_node *np)
Stefan Roeseeea62812012-03-16 10:19:31 +0100873{
874 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
875 u32 val;
876
877 /* Set default NAND width to 8 bits */
878 pdata->width = 8;
879 if (!of_property_read_u32(np, "bank-width", &val)) {
880 if (val == 2) {
881 pdata->width = 16;
882 } else if (val != 1) {
883 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
884 return -EINVAL;
885 }
886 }
Stefan Roeseeea62812012-03-16 10:19:31 +0100887 if (of_get_property(np, "nand-skip-bbtscan", NULL))
888 pdata->options = NAND_SKIP_BBTSCAN;
889
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200890 pdata->nand_timings = devm_kzalloc(&pdev->dev,
891 sizeof(*pdata->nand_timings), GFP_KERNEL);
Jingoo Hand9a21ae2013-12-26 12:16:38 +0900892 if (!pdata->nand_timings)
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200893 return -ENOMEM;
Mian Yousaf Kaukab64ddba42013-04-29 14:07:48 +0200894 of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
895 sizeof(*pdata->nand_timings));
896
897 /* Set default NAND bank to 0 */
898 pdata->bank = 0;
899 if (!of_property_read_u32(np, "bank", &val)) {
900 if (val > 3) {
901 dev_err(&pdev->dev, "invalid bank %u\n", val);
902 return -EINVAL;
903 }
904 pdata->bank = val;
905 }
Stefan Roeseeea62812012-03-16 10:19:31 +0100906 return 0;
907}
908#else
Bill Pemberton06f25512012-11-19 13:23:07 -0500909static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
Greg Kroah-Hartmand8929942012-12-21 13:19:05 -0800910 struct device_node *np)
Stefan Roeseeea62812012-03-16 10:19:31 +0100911{
912 return -ENOSYS;
913}
914#endif
915
Linus Walleij6c009ab2010-09-13 00:35:22 +0200916/*
917 * fsmc_nand_probe - Probe function
918 * @pdev: platform device structure
919 */
920static int __init fsmc_nand_probe(struct platform_device *pdev)
921{
922 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
Stefan Roeseeea62812012-03-16 10:19:31 +0100923 struct device_node __maybe_unused *np = pdev->dev.of_node;
924 struct mtd_part_parser_data ppdata = {};
Linus Walleij6c009ab2010-09-13 00:35:22 +0200925 struct fsmc_nand_data *host;
926 struct mtd_info *mtd;
927 struct nand_chip *nand;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200928 struct resource *res;
Vipin Kumar4774fb02012-03-14 11:47:18 +0530929 dma_cap_mask_t mask;
Linus Walleij4ad916b2010-11-29 13:52:06 +0100930 int ret = 0;
Linus Walleij593cd872010-11-29 13:52:19 +0100931 u32 pid;
932 int i;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200933
Stefan Roeseeea62812012-03-16 10:19:31 +0100934 if (np) {
935 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
936 pdev->dev.platform_data = pdata;
937 ret = fsmc_nand_probe_config_dt(pdev, np);
938 if (ret) {
939 dev_err(&pdev->dev, "no platform data\n");
940 return -ENODEV;
941 }
942 }
943
Linus Walleij6c009ab2010-09-13 00:35:22 +0200944 if (!pdata) {
945 dev_err(&pdev->dev, "platform data is NULL\n");
946 return -EINVAL;
947 }
948
949 /* Allocate memory for the device structure (and zero it) */
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530950 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
Jingoo Hand9a21ae2013-12-26 12:16:38 +0900951 if (!host)
Linus Walleij6c009ab2010-09-13 00:35:22 +0200952 return -ENOMEM;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200953
954 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
Thierry Redingb0de7742013-01-21 11:09:12 +0100955 host->data_va = devm_ioremap_resource(&pdev->dev, res);
956 if (IS_ERR(host->data_va))
957 return PTR_ERR(host->data_va);
958
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200959 host->data_pa = (dma_addr_t)res->start;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200960
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200961 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
Thierry Redingb0de7742013-01-21 11:09:12 +0100962 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
963 if (IS_ERR(host->addr_va))
964 return PTR_ERR(host->addr_va);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200965
Jean-Christophe PLAGNIOL-VILLARD6d7b42a2012-10-04 15:14:16 +0200966 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
Thierry Redingb0de7742013-01-21 11:09:12 +0100967 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
968 if (IS_ERR(host->cmd_va))
969 return PTR_ERR(host->cmd_va);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200970
971 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
Thierry Redingb0de7742013-01-21 11:09:12 +0100972 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
973 if (IS_ERR(host->regs_va))
974 return PTR_ERR(host->regs_va);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200975
976 host->clk = clk_get(&pdev->dev, NULL);
977 if (IS_ERR(host->clk)) {
978 dev_err(&pdev->dev, "failed to fetch block clock\n");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +0530979 return PTR_ERR(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200980 }
981
Viresh Kumare25da1c2012-04-17 17:07:57 +0530982 ret = clk_prepare_enable(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +0200983 if (ret)
Viresh Kumare25da1c2012-04-17 17:07:57 +0530984 goto err_clk_prepare_enable;
Linus Walleij6c009ab2010-09-13 00:35:22 +0200985
Linus Walleij593cd872010-11-29 13:52:19 +0100986 /*
987 * This device ID is actually a common AMBA ID as used on the
988 * AMBA PrimeCell bus. However it is not a PrimeCell.
989 */
990 for (pid = 0, i = 0; i < 4; i++)
991 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
992 host->pid = pid;
993 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
994 "revision %02x, config %02x\n",
995 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
996 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
997
Linus Walleij6c009ab2010-09-13 00:35:22 +0200998 host->bank = pdata->bank;
999 host->select_chip = pdata->select_bank;
Vipin Kumar71470322012-03-14 11:47:07 +05301000 host->partitions = pdata->partitions;
1001 host->nr_partitions = pdata->nr_partitions;
Vipin Kumar712c4ad2012-03-14 11:47:16 +05301002 host->dev = &pdev->dev;
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301003 host->dev_timings = pdata->nand_timings;
Vipin Kumar4774fb02012-03-14 11:47:18 +05301004 host->mode = pdata->mode;
1005
1006 if (host->mode == USE_DMA_ACCESS)
1007 init_completion(&host->dma_access_complete);
1008
Linus Walleij6c009ab2010-09-13 00:35:22 +02001009 /* Link all private pointers */
1010 mtd = &host->mtd;
1011 nand = &host->nand;
1012 mtd->priv = nand;
1013 nand->priv = host;
1014
1015 host->mtd.owner = THIS_MODULE;
1016 nand->IO_ADDR_R = host->data_va;
1017 nand->IO_ADDR_W = host->data_va;
1018 nand->cmd_ctrl = fsmc_cmd_ctrl;
1019 nand->chip_delay = 30;
1020
1021 nand->ecc.mode = NAND_ECC_HW;
1022 nand->ecc.hwctl = fsmc_enable_hwecc;
1023 nand->ecc.size = 512;
1024 nand->options = pdata->options;
1025 nand->select_chip = fsmc_select_chip;
Vipin Kumar467e6e72012-03-14 11:47:12 +05301026 nand->badblockbits = 7;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001027
1028 if (pdata->width == FSMC_NAND_BW16)
1029 nand->options |= NAND_BUSWIDTH_16;
1030
Vipin Kumar4774fb02012-03-14 11:47:18 +05301031 switch (host->mode) {
1032 case USE_DMA_ACCESS:
1033 dma_cap_zero(mask);
1034 dma_cap_set(DMA_MEMCPY, mask);
1035 host->read_dma_chan = dma_request_channel(mask, filter,
1036 pdata->read_dma_priv);
1037 if (!host->read_dma_chan) {
1038 dev_err(&pdev->dev, "Unable to get read dma channel\n");
1039 goto err_req_read_chnl;
1040 }
1041 host->write_dma_chan = dma_request_channel(mask, filter,
1042 pdata->write_dma_priv);
1043 if (!host->write_dma_chan) {
1044 dev_err(&pdev->dev, "Unable to get write dma channel\n");
1045 goto err_req_write_chnl;
1046 }
1047 nand->read_buf = fsmc_read_buf_dma;
1048 nand->write_buf = fsmc_write_buf_dma;
1049 break;
1050
1051 default:
1052 case USE_WORD_ACCESS:
Vipin Kumar604e7542012-03-14 11:47:17 +05301053 nand->read_buf = fsmc_read_buf;
1054 nand->write_buf = fsmc_write_buf;
Vipin Kumar4774fb02012-03-14 11:47:18 +05301055 break;
Vipin Kumar604e7542012-03-14 11:47:17 +05301056 }
1057
Vipin Kumar2a5dbead2012-03-14 11:47:19 +05301058 fsmc_nand_setup(host->regs_va, host->bank,
1059 nand->options & NAND_BUSWIDTH_16,
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301060 host->dev_timings);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001061
Linus Walleij593cd872010-11-29 13:52:19 +01001062 if (AMBA_REV_BITS(host->pid) >= 8) {
Linus Walleij6c009ab2010-09-13 00:35:22 +02001063 nand->ecc.read_page = fsmc_read_page_hwecc;
1064 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
Armando Visconti753e0132012-03-07 17:00:54 +05301065 nand->ecc.correct = fsmc_bch8_correct_data;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001066 nand->ecc.bytes = 13;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001067 nand->ecc.strength = 8;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001068 } else {
1069 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1070 nand->ecc.correct = nand_correct_data;
1071 nand->ecc.bytes = 3;
Mike Dunn6a918ba2012-03-11 14:21:11 -07001072 nand->ecc.strength = 1;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001073 }
1074
1075 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001076 * Scan to find existence of the device
Linus Walleij6c009ab2010-09-13 00:35:22 +02001077 */
1078 if (nand_scan_ident(&host->mtd, 1, NULL)) {
1079 ret = -ENXIO;
1080 dev_err(&pdev->dev, "No NAND Device found!\n");
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301081 goto err_scan_ident;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001082 }
1083
Linus Walleij593cd872010-11-29 13:52:19 +01001084 if (AMBA_REV_BITS(host->pid) >= 8) {
Bhavna Yadave29ee572012-03-07 17:00:50 +05301085 switch (host->mtd.oobsize) {
1086 case 16:
1087 nand->ecc.layout = &fsmc_ecc4_16_layout;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001088 host->ecc_place = &fsmc_ecc4_sp_place;
Bhavna Yadave29ee572012-03-07 17:00:50 +05301089 break;
1090 case 64:
1091 nand->ecc.layout = &fsmc_ecc4_64_layout;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001092 host->ecc_place = &fsmc_ecc4_lp_place;
Bhavna Yadave29ee572012-03-07 17:00:50 +05301093 break;
1094 case 128:
1095 nand->ecc.layout = &fsmc_ecc4_128_layout;
1096 host->ecc_place = &fsmc_ecc4_lp_place;
1097 break;
Armando Visconti0c78e932012-03-07 17:00:55 +05301098 case 224:
1099 nand->ecc.layout = &fsmc_ecc4_224_layout;
1100 host->ecc_place = &fsmc_ecc4_lp_place;
1101 break;
Bhavna Yadave29ee572012-03-07 17:00:50 +05301102 case 256:
1103 nand->ecc.layout = &fsmc_ecc4_256_layout;
1104 host->ecc_place = &fsmc_ecc4_lp_place;
1105 break;
1106 default:
Jingoo Han67b19a62013-12-26 12:31:25 +09001107 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1108 mtd->oobsize);
Bhavna Yadave29ee572012-03-07 17:00:50 +05301109 BUG();
Linus Walleij6c009ab2010-09-13 00:35:22 +02001110 }
1111 } else {
Bhavna Yadave29ee572012-03-07 17:00:50 +05301112 switch (host->mtd.oobsize) {
1113 case 16:
1114 nand->ecc.layout = &fsmc_ecc1_16_layout;
1115 break;
1116 case 64:
1117 nand->ecc.layout = &fsmc_ecc1_64_layout;
1118 break;
1119 case 128:
1120 nand->ecc.layout = &fsmc_ecc1_128_layout;
1121 break;
1122 default:
Jingoo Han67b19a62013-12-26 12:31:25 +09001123 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1124 mtd->oobsize);
Bhavna Yadave29ee572012-03-07 17:00:50 +05301125 BUG();
1126 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001127 }
1128
1129 /* Second stage of scan to fill MTD data-structures */
1130 if (nand_scan_tail(&host->mtd)) {
1131 ret = -ENXIO;
1132 goto err_probe;
1133 }
1134
1135 /*
1136 * The partition information can is accessed by (in the same precedence)
1137 *
1138 * command line through Bootloader,
1139 * platform data,
1140 * default partition information present in driver.
1141 */
Linus Walleij6c009ab2010-09-13 00:35:22 +02001142 /*
Dmitry Eremin-Solenikov8d3f8bb2011-05-29 20:16:57 +04001143 * Check for partition info passed
Linus Walleij6c009ab2010-09-13 00:35:22 +02001144 */
1145 host->mtd.name = "nand";
Stefan Roeseeea62812012-03-16 10:19:31 +01001146 ppdata.of_node = np;
1147 ret = mtd_device_parse_register(&host->mtd, NULL, &ppdata,
Vipin Kumar71470322012-03-14 11:47:07 +05301148 host->partitions, host->nr_partitions);
Jamie Iles99335d02011-05-23 10:23:23 +01001149 if (ret)
Linus Walleij6c009ab2010-09-13 00:35:22 +02001150 goto err_probe;
Linus Walleij6c009ab2010-09-13 00:35:22 +02001151
1152 platform_set_drvdata(pdev, host);
1153 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1154 return 0;
1155
1156err_probe:
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301157err_scan_ident:
Vipin Kumar4774fb02012-03-14 11:47:18 +05301158 if (host->mode == USE_DMA_ACCESS)
1159 dma_release_channel(host->write_dma_chan);
1160err_req_write_chnl:
1161 if (host->mode == USE_DMA_ACCESS)
1162 dma_release_channel(host->read_dma_chan);
1163err_req_read_chnl:
Viresh Kumare25da1c2012-04-17 17:07:57 +05301164 clk_disable_unprepare(host->clk);
1165err_clk_prepare_enable:
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301166 clk_put(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001167 return ret;
1168}
1169
1170/*
1171 * Clean up routine
1172 */
1173static int fsmc_nand_remove(struct platform_device *pdev)
1174{
1175 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1176
Linus Walleij6c009ab2010-09-13 00:35:22 +02001177 if (host) {
Axel Lin82e023a2011-06-03 13:15:30 +08001178 nand_release(&host->mtd);
Vipin Kumar4774fb02012-03-14 11:47:18 +05301179
1180 if (host->mode == USE_DMA_ACCESS) {
1181 dma_release_channel(host->write_dma_chan);
1182 dma_release_channel(host->read_dma_chan);
1183 }
Viresh Kumare25da1c2012-04-17 17:07:57 +05301184 clk_disable_unprepare(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001185 clk_put(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001186 }
Vipin Kumar82b9dbe2012-03-14 11:47:15 +05301187
Linus Walleij6c009ab2010-09-13 00:35:22 +02001188 return 0;
1189}
1190
Jingoo Han80ce4dd2013-03-26 15:53:48 +09001191#ifdef CONFIG_PM_SLEEP
Linus Walleij6c009ab2010-09-13 00:35:22 +02001192static int fsmc_nand_suspend(struct device *dev)
1193{
1194 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1195 if (host)
Viresh Kumare25da1c2012-04-17 17:07:57 +05301196 clk_disable_unprepare(host->clk);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001197 return 0;
1198}
1199
1200static int fsmc_nand_resume(struct device *dev)
1201{
1202 struct fsmc_nand_data *host = dev_get_drvdata(dev);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301203 if (host) {
Viresh Kumare25da1c2012-04-17 17:07:57 +05301204 clk_prepare_enable(host->clk);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301205 fsmc_nand_setup(host->regs_va, host->bank,
Vipin Kumare2f6bce2012-03-14 11:47:14 +05301206 host->nand.options & NAND_BUSWIDTH_16,
1207 host->dev_timings);
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301208 }
Linus Walleij6c009ab2010-09-13 00:35:22 +02001209 return 0;
1210}
Jingoo Han80ce4dd2013-03-26 15:53:48 +09001211#endif
Linus Walleij6c009ab2010-09-13 00:35:22 +02001212
Shiraz Hashimf63acb72012-03-14 11:47:13 +05301213static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001214
Stefan Roeseeea62812012-03-16 10:19:31 +01001215#ifdef CONFIG_OF
1216static const struct of_device_id fsmc_nand_id_table[] = {
1217 { .compatible = "st,spear600-fsmc-nand" },
Linus Walleijba785202013-01-05 22:28:32 +01001218 { .compatible = "stericsson,fsmc-nand" },
Stefan Roeseeea62812012-03-16 10:19:31 +01001219 {}
1220};
1221MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1222#endif
1223
Linus Walleij6c009ab2010-09-13 00:35:22 +02001224static struct platform_driver fsmc_nand_driver = {
1225 .remove = fsmc_nand_remove,
1226 .driver = {
1227 .owner = THIS_MODULE,
1228 .name = "fsmc-nand",
Stefan Roeseeea62812012-03-16 10:19:31 +01001229 .of_match_table = of_match_ptr(fsmc_nand_id_table),
Linus Walleij6c009ab2010-09-13 00:35:22 +02001230 .pm = &fsmc_nand_pm_ops,
Linus Walleij6c009ab2010-09-13 00:35:22 +02001231 },
1232};
1233
Jingoo Han307d2a512013-03-05 13:30:36 +09001234module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
Linus Walleij6c009ab2010-09-13 00:35:22 +02001235
1236MODULE_LICENSE("GPL");
1237MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1238MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");