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Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -07001/*
2 * pci_regs.h
3 *
4 * PCI standard defines
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
7 *
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
10 *
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
Eric W. Biedermane78d0162006-10-04 02:16:54 -070015 *
16 * For hypertransport information, please consult the following manuals
17 * from http://www.hypertransport.org
18 *
19 * The Hypertransport I/O Link Specification
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -070020 */
21
22#ifndef LINUX_PCI_REGS_H
23#define LINUX_PCI_REGS_H
24
25/*
26 * Under PCI, each device has 256 bytes of configuration address space,
27 * of which the first 64 bytes are standardized as follows:
28 */
29#define PCI_VENDOR_ID 0x00 /* 16 bits */
30#define PCI_DEVICE_ID 0x02 /* 16 bits */
31#define PCI_COMMAND 0x04 /* 16 bits */
32#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
33#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
34#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
35#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
36#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
37#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
38#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
39#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
40#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
41#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
42#define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
43
44#define PCI_STATUS 0x06 /* 16 bits */
45#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
46#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
47#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
48#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
49#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
50#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
51#define PCI_STATUS_DEVSEL_FAST 0x000
52#define PCI_STATUS_DEVSEL_MEDIUM 0x200
53#define PCI_STATUS_DEVSEL_SLOW 0x400
54#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
55#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
56#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
57#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
58#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
59
60#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
61#define PCI_REVISION_ID 0x08 /* Revision ID */
62#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
63#define PCI_CLASS_DEVICE 0x0a /* Device class */
64
65#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
66#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
67#define PCI_HEADER_TYPE 0x0e /* 8 bits */
68#define PCI_HEADER_TYPE_NORMAL 0
69#define PCI_HEADER_TYPE_BRIDGE 1
70#define PCI_HEADER_TYPE_CARDBUS 2
71
72#define PCI_BIST 0x0f /* 8 bits */
73#define PCI_BIST_CODE_MASK 0x0f /* Return result */
74#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
75#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
76
77/*
78 * Base addresses specify locations in memory or I/O space.
79 * Decoded size can be determined by writing a value of
80 * 0xffffffff to the register, and reading it back. Only
81 * 1 bits are decoded.
82 */
83#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
84#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
85#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
86#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
87#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
88#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
89#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
90#define PCI_BASE_ADDRESS_SPACE_IO 0x01
91#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
92#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
93#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
94#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
95#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
96#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
97#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
98#define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
99/* bit 1 is reserved if address_space = 1 */
100
101/* Header type 0 (normal devices) */
102#define PCI_CARDBUS_CIS 0x28
103#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
104#define PCI_SUBSYSTEM_ID 0x2e
105#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
106#define PCI_ROM_ADDRESS_ENABLE 0x01
107#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
108
109#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
110
111/* 0x35-0x3b are reserved */
112#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
113#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
114#define PCI_MIN_GNT 0x3e /* 8 bits */
115#define PCI_MAX_LAT 0x3f /* 8 bits */
116
117/* Header type 1 (PCI-to-PCI bridges) */
118#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
119#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
120#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
121#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
122#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
123#define PCI_IO_LIMIT 0x1d
124#define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
125#define PCI_IO_RANGE_TYPE_16 0x00
126#define PCI_IO_RANGE_TYPE_32 0x01
127#define PCI_IO_RANGE_MASK (~0x0fUL)
128#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
129#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
130#define PCI_MEMORY_LIMIT 0x22
131#define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
132#define PCI_MEMORY_RANGE_MASK (~0x0fUL)
133#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
134#define PCI_PREF_MEMORY_LIMIT 0x26
135#define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
136#define PCI_PREF_RANGE_TYPE_32 0x00
137#define PCI_PREF_RANGE_TYPE_64 0x01
138#define PCI_PREF_RANGE_MASK (~0x0fUL)
139#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
140#define PCI_PREF_LIMIT_UPPER32 0x2c
141#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
142#define PCI_IO_LIMIT_UPPER16 0x32
143/* 0x34 same as for htype 0 */
144/* 0x35-0x3b is reserved */
145#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
146/* 0x3c-0x3d are same as for htype 0 */
147#define PCI_BRIDGE_CONTROL 0x3e
148#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
149#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
Gary Hade11949252007-10-08 16:24:16 -0700150#define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700151#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
152#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
153#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
154#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
155
156/* Header type 2 (CardBus bridges) */
157#define PCI_CB_CAPABILITY_LIST 0x14
158/* 0x15 reserved */
159#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
160#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
161#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
162#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
163#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
164#define PCI_CB_MEMORY_BASE_0 0x1c
165#define PCI_CB_MEMORY_LIMIT_0 0x20
166#define PCI_CB_MEMORY_BASE_1 0x24
167#define PCI_CB_MEMORY_LIMIT_1 0x28
168#define PCI_CB_IO_BASE_0 0x2c
169#define PCI_CB_IO_BASE_0_HI 0x2e
170#define PCI_CB_IO_LIMIT_0 0x30
171#define PCI_CB_IO_LIMIT_0_HI 0x32
172#define PCI_CB_IO_BASE_1 0x34
173#define PCI_CB_IO_BASE_1_HI 0x36
174#define PCI_CB_IO_LIMIT_1 0x38
175#define PCI_CB_IO_LIMIT_1_HI 0x3a
176#define PCI_CB_IO_RANGE_MASK (~0x03UL)
177/* 0x3c-0x3d are same as for htype 0 */
178#define PCI_CB_BRIDGE_CONTROL 0x3e
179#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
180#define PCI_CB_BRIDGE_CTL_SERR 0x02
181#define PCI_CB_BRIDGE_CTL_ISA 0x04
182#define PCI_CB_BRIDGE_CTL_VGA 0x08
183#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
184#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
185#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
186#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
187#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
188#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
189#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
190#define PCI_CB_SUBSYSTEM_ID 0x42
191#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
192/* 0x48-0x7f reserved */
193
194/* Capability lists */
195
196#define PCI_CAP_LIST_ID 0 /* Capability ID */
197#define PCI_CAP_ID_PM 0x01 /* Power Management */
198#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
199#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
200#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
201#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
202#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
203#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
Brice Goglin46ff3462006-08-31 01:55:24 -0400204#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
Alex Chiang9f672152007-08-21 17:49:07 -0600205#define PCI_CAP_ID_VNDR 0x09 /* Vendor specific */
206#define PCI_CAP_ID_DBG 0x0A /* Debug port */
207#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700208#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
Alex Chiang9f672152007-08-21 17:49:07 -0600209#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
210#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700211#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
212#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
Sheng Yangf7b7baa2008-11-11 17:17:46 +0800213#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700214#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
215#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
216#define PCI_CAP_SIZEOF 4
217
218/* Power Management Registers */
219
220#define PCI_PM_PMC 2 /* PM Capabilities Register */
221#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
222#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
223#define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
224#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
225#define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
226#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
227#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
228#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
229#define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
230#define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
231#define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
232#define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
233#define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
234#define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200235#define PCI_PM_CAP_PME_SHIFT 11 /* Start of the PME Mask in PMC */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700236#define PCI_PM_CTRL 4 /* PM control and status register */
237#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
Yu Zhao998dd7c2009-02-25 13:15:52 +0800238#define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 /* No reset for D3hot->D0 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700239#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
240#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
241#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
242#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
243#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
244#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
245#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
246#define PCI_PM_DATA_REGISTER 7 /* (??) */
247#define PCI_PM_SIZEOF 8
248
249/* AGP registers */
250
251#define PCI_AGP_VERSION 2 /* BCD version number */
252#define PCI_AGP_RFU 3 /* Rest of capability flags */
253#define PCI_AGP_STATUS 4 /* Status register */
254#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
255#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
256#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
257#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
258#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
259#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
260#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
261#define PCI_AGP_COMMAND 8 /* Control register */
262#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
263#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
264#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
265#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
266#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
267#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
268#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
269#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
270#define PCI_AGP_SIZEOF 12
271
272/* Vital Product Data */
273
274#define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
275#define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
276#define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
277#define PCI_VPD_DATA 4 /* 32-bits of data returned here */
278
279/* Slot Identification */
280
281#define PCI_SID_ESR 2 /* Expansion Slot Register */
282#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
283#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
284#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
285
286/* Message Signalled Interrupts registers */
287
288#define PCI_MSI_FLAGS 2 /* Various flags */
289#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
290#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
291#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
292#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
293#define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
294#define PCI_MSI_RFU 3 /* Rest of capability flags */
295#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
296#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
297#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
Hidetoshi Seto67b5db62009-04-20 10:54:59 +0900298#define PCI_MSI_MASK_32 12 /* Mask bits register for 32-bit devices */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700299#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
Hidetoshi Seto67b5db62009-04-20 10:54:59 +0900300#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700301
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -0800302/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
303#define PCI_MSIX_FLAGS 2
304#define PCI_MSIX_FLAGS_QSIZE 0x7FF
305#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
Eric W. Biederman392ee1e2007-03-08 13:04:57 -0700306#define PCI_MSIX_FLAGS_MASKALL (1 << 14)
Michael Ellermane65e5fb2006-11-07 18:21:21 +1100307#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
Michael Ellermane65e5fb2006-11-07 18:21:21 +1100308
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700309/* CompactPCI Hotswap Register */
310
311#define PCI_CHSWP_CSR 2 /* Control and Status Register */
312#define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
313#define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
314#define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
315#define PCI_CHSWP_LOO 0x08 /* LED On / Off */
316#define PCI_CHSWP_PI 0x30 /* Programming Interface */
317#define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
318#define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
319
Sheng Yangf7b7baa2008-11-11 17:17:46 +0800320/* PCI Advanced Feature registers */
321
322#define PCI_AF_LENGTH 2
323#define PCI_AF_CAP 3
324#define PCI_AF_CAP_TP 0x01
325#define PCI_AF_CAP_FLR 0x02
326#define PCI_AF_CTRL 4
327#define PCI_AF_CTRL_FLR 0x01
328#define PCI_AF_STATUS 5
329#define PCI_AF_STATUS_TP 0x01
330
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700331/* PCI-X registers */
332
333#define PCI_X_CMD 2 /* Modes & Features */
334#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
335#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
Matt Carlson9974a352007-10-07 23:27:28 -0700336#define PCI_X_CMD_READ_512 0x0000 /* 512 byte maximum read byte count */
337#define PCI_X_CMD_READ_1K 0x0004 /* 1Kbyte maximum read byte count */
338#define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
339#define PCI_X_CMD_READ_4K 0x000c /* 4Kbyte maximum read byte count */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700340#define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
Matt Carlson9974a352007-10-07 23:27:28 -0700341 /* Max # of outstanding split transactions */
342#define PCI_X_CMD_SPLIT_1 0x0000 /* Max 1 */
343#define PCI_X_CMD_SPLIT_2 0x0010 /* Max 2 */
344#define PCI_X_CMD_SPLIT_3 0x0020 /* Max 3 */
345#define PCI_X_CMD_SPLIT_4 0x0030 /* Max 4 */
346#define PCI_X_CMD_SPLIT_8 0x0040 /* Max 8 */
347#define PCI_X_CMD_SPLIT_12 0x0050 /* Max 12 */
348#define PCI_X_CMD_SPLIT_16 0x0060 /* Max 16 */
349#define PCI_X_CMD_SPLIT_32 0x0070 /* Max 32 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700350#define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
351#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
352#define PCI_X_STATUS 4 /* PCI-X capabilities */
353#define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
354#define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
355#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
356#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
357#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
358#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
359#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
360#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
361#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
362#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
363#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
364#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
365#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
366
367/* PCI Express capability registers */
368
369#define PCI_EXP_FLAGS 2 /* Capabilities register */
370#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
371#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
372#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
373#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
374#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
375#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
376#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
377#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
Yu Zhaod1b054d2009-03-20 11:25:11 +0800378#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
Yu Zhao1b6b8ce2009-04-09 14:57:39 +0800379#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700380#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
381#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
382#define PCI_EXP_DEVCAP 4 /* Device capabilities */
383#define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
384#define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
385#define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
386#define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
387#define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
388#define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
389#define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
390#define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
Shaohua Li149e1632008-07-23 10:32:31 +0800391#define PCI_EXP_DEVCAP_RBER 0x8000 /* Role-Based Error Reporting */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700392#define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
393#define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
Sheng Yang8dd7f802008-10-21 17:38:25 +0800394#define PCI_EXP_DEVCAP_FLR 0x10000000 /* Function Level Reset */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700395#define PCI_EXP_DEVCTL 8 /* Device Control */
396#define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
397#define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
398#define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
399#define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
400#define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
401#define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
402#define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
403#define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
404#define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
405#define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
406#define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
Sheng Yang8dd7f802008-10-21 17:38:25 +0800407#define PCI_EXP_DEVCTL_BCR_FLR 0x8000 /* Bridge Configuration Retry / FLR */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700408#define PCI_EXP_DEVSTA 10 /* Device Status */
409#define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
410#define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
411#define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
412#define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
413#define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
414#define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
415#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900416#define PCI_EXP_LNKCAP_SLS 0x0000000f /* Supported Link Speeds */
417#define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */
418#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
419#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
420#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
421#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */
422#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */
423#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
424#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
425#define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700426#define PCI_EXP_LNKCTL 16 /* Link Control */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900427#define PCI_EXP_LNKCTL_ASPMC 0x0003 /* ASPM Control */
428#define PCI_EXP_LNKCTL_RCB 0x0008 /* Read Completion Boundary */
429#define PCI_EXP_LNKCTL_LD 0x0010 /* Link Disable */
430#define PCI_EXP_LNKCTL_RL 0x0020 /* Retrain Link */
431#define PCI_EXP_LNKCTL_CCC 0x0040 /* Common Clock Configuration */
432#define PCI_EXP_LNKCTL_ES 0x0080 /* Extended Synch */
Michael Chanc7835a72006-11-15 21:14:42 -0800433#define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900434#define PCI_EXP_LNKCTL_HAWD 0x0200 /* Hardware Autonomous Width Disable */
435#define PCI_EXP_LNKCTL_LBMIE 0x0400 /* Link Bandwidth Management Interrupt Enable */
436#define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700437#define PCI_EXP_LNKSTA 18 /* Link Status */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900438#define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
439#define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
440#define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
Shaohua Li7d715a62008-02-25 09:46:41 +0800441#define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900442#define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
443#define PCI_EXP_LNKSTA_LBMS 0x4000 /* Link Bandwidth Management Status */
444#define PCI_EXP_LNKSTA_LABS 0x8000 /* Link Autonomous Bandwidth Status */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700445#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900446#define PCI_EXP_SLTCAP_ABP 0x00000001 /* Attention Button Present */
447#define PCI_EXP_SLTCAP_PCP 0x00000002 /* Power Controller Present */
448#define PCI_EXP_SLTCAP_MRLSP 0x00000004 /* MRL Sensor Present */
449#define PCI_EXP_SLTCAP_AIP 0x00000008 /* Attention Indicator Present */
450#define PCI_EXP_SLTCAP_PIP 0x00000010 /* Power Indicator Present */
451#define PCI_EXP_SLTCAP_HPS 0x00000020 /* Hot-Plug Surprise */
452#define PCI_EXP_SLTCAP_HPC 0x00000040 /* Hot-Plug Capable */
453#define PCI_EXP_SLTCAP_SPLV 0x00007f80 /* Slot Power Limit Value */
454#define PCI_EXP_SLTCAP_SPLS 0x00018000 /* Slot Power Limit Scale */
455#define PCI_EXP_SLTCAP_EIP 0x00020000 /* Electromechanical Interlock Present */
456#define PCI_EXP_SLTCAP_NCCS 0x00040000 /* No Command Completed Support */
457#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700458#define PCI_EXP_SLTCTL 24 /* Slot Control */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900459#define PCI_EXP_SLTCTL_ABPE 0x0001 /* Attention Button Pressed Enable */
460#define PCI_EXP_SLTCTL_PFDE 0x0002 /* Power Fault Detected Enable */
461#define PCI_EXP_SLTCTL_MRLSCE 0x0004 /* MRL Sensor Changed Enable */
462#define PCI_EXP_SLTCTL_PDCE 0x0008 /* Presence Detect Changed Enable */
463#define PCI_EXP_SLTCTL_CCIE 0x0010 /* Command Completed Interrupt Enable */
464#define PCI_EXP_SLTCTL_HPIE 0x0020 /* Hot-Plug Interrupt Enable */
465#define PCI_EXP_SLTCTL_AIC 0x00c0 /* Attention Indicator Control */
466#define PCI_EXP_SLTCTL_PIC 0x0300 /* Power Indicator Control */
467#define PCI_EXP_SLTCTL_PCC 0x0400 /* Power Controller Control */
468#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
469#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700470#define PCI_EXP_SLTSTA 26 /* Slot Status */
Kenji Kaneshige322162a2008-12-19 15:19:02 +0900471#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
472#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */
473#define PCI_EXP_SLTSTA_MRLSC 0x0004 /* MRL Sensor Changed */
474#define PCI_EXP_SLTSTA_PDC 0x0008 /* Presence Detect Changed */
475#define PCI_EXP_SLTSTA_CC 0x0010 /* Command Completed */
476#define PCI_EXP_SLTSTA_MRLSS 0x0020 /* MRL Sensor State */
477#define PCI_EXP_SLTSTA_PDS 0x0040 /* Presence Detect State */
478#define PCI_EXP_SLTSTA_EIS 0x0080 /* Electromechanical Interlock Status */
479#define PCI_EXP_SLTSTA_DLLSC 0x0100 /* Data Link Layer State Changed */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700480#define PCI_EXP_RTCTL 28 /* Root Control */
481#define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
482#define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
483#define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
484#define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
485#define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
486#define PCI_EXP_RTCAP 30 /* Root Capabilities */
487#define PCI_EXP_RTSTA 32 /* Root Status */
Yu Zhao58c3a722008-10-14 14:02:53 +0800488#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
489#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
490#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
491#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
Yu Zhao89858512009-02-16 02:55:47 +0800492#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
493#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700494
495/* Extended Capabilities (PCI-X 2.0 and Express) */
496#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
497#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
498#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
499
500#define PCI_EXT_CAP_ID_ERR 1
501#define PCI_EXT_CAP_ID_VC 2
502#define PCI_EXT_CAP_ID_DSN 3
503#define PCI_EXT_CAP_ID_PWR 4
Yu Zhao58c3a722008-10-14 14:02:53 +0800504#define PCI_EXT_CAP_ID_ARI 14
Yu Zhaod1b054d2009-03-20 11:25:11 +0800505#define PCI_EXT_CAP_ID_SRIOV 16
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700506
507/* Advanced Error Reporting */
508#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
509#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
510#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
511#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
512#define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
513#define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
514#define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
515#define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
516#define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
517#define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
518#define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
519#define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
520#define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
521 /* Same bits as above */
522#define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
523 /* Same bits as above */
524#define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
525#define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
526#define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
527#define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
528#define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
529#define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
530#define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
531 /* Same bits as above */
532#define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
533#define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
534#define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
535#define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
536#define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
537#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
538#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
539#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
Zhang, Yanmin6f0312f2006-07-12 09:41:47 +0800540/* Correctable Err Reporting Enable */
541#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
542/* Non-fatal Err Reporting Enable */
543#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
544/* Fatal Err Reporting Enable */
545#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700546#define PCI_ERR_ROOT_STATUS 48
Zhang, Yanmin6f0312f2006-07-12 09:41:47 +0800547#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
548/* Multi ERR_COR Received */
549#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
550/* ERR_FATAL/NONFATAL Recevied */
551#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
552/* Multi ERR_FATAL/NONFATAL Recevied */
553#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
554#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
555#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
556#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700557#define PCI_ERR_ROOT_COR_SRC 52
558#define PCI_ERR_ROOT_SRC 54
559
560/* Virtual Channel */
561#define PCI_VC_PORT_REG1 4
562#define PCI_VC_PORT_REG2 8
563#define PCI_VC_PORT_CTRL 12
564#define PCI_VC_PORT_STATUS 14
565#define PCI_VC_RES_CAP 16
566#define PCI_VC_RES_CTRL 20
567#define PCI_VC_RES_STATUS 26
568
569/* Power Budgeting */
570#define PCI_PWR_DSR 4 /* Data Select Register */
571#define PCI_PWR_DATA 8 /* Data Register */
572#define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
573#define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
574#define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
575#define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
576#define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
577#define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
578#define PCI_PWR_CAP 12 /* Capability */
579#define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
580
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100581/*
582 * Hypertransport sub capability types
583 *
584 * Unfortunately there are both 3 bit and 5 bit capability types defined
585 * in the HT spec, catering for that is a little messy. You probably don't
586 * want to use these directly, just use pci_find_ht_capability() and it
587 * will do the right thing for you.
588 */
589#define HT_3BIT_CAP_MASK 0xE0
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700590#define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */
591#define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100592
593#define HT_5BIT_CAP_MASK 0xF8
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700594#define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */
595#define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */
596#define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */
597#define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */
598#define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */
599#define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */
Michael Ellermand010b512006-11-22 18:26:20 +1100600#define HT_MSI_FLAGS 0x02 /* Offset to flags */
601#define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */
602#define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */
603#define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */
604#define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */
605#define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */
606#define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700607#define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
608#define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */
609#define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
610#define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
611#define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
612
Yu Zhao58c3a722008-10-14 14:02:53 +0800613/* Alternative Routing-ID Interpretation */
614#define PCI_ARI_CAP 0x04 /* ARI Capability Register */
615#define PCI_ARI_CAP_MFVC 0x0001 /* MFVC Function Groups Capability */
616#define PCI_ARI_CAP_ACS 0x0002 /* ACS Function Groups Capability */
617#define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) /* Next Function Number */
618#define PCI_ARI_CTRL 0x06 /* ARI Control Register */
619#define PCI_ARI_CTRL_MFVC 0x0001 /* MFVC Function Groups Enable */
620#define PCI_ARI_CTRL_ACS 0x0002 /* ACS Function Groups Enable */
621#define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) /* Function Group */
Eric W. Biedermane78d0162006-10-04 02:16:54 -0700622
Yu Zhaod1b054d2009-03-20 11:25:11 +0800623/* Single Root I/O Virtualization */
624#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
625#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
626#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
627#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
628#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
629#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
630#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
631#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
632#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
633#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
634#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
635#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
636#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
637#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
638#define PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
639#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
640#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
641#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
642#define PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
643#define PCI_SRIOV_SYS_PGSIZE 0x20 /* System Page Size */
644#define PCI_SRIOV_BAR 0x24 /* VF BAR0 */
645#define PCI_SRIOV_NUM_BARS 6 /* Number of VF BARs */
646#define PCI_SRIOV_VFM 0x3c /* VF Migration State Array Offset*/
647#define PCI_SRIOV_VFM_BIR(x) ((x) & 7) /* State BIR */
648#define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) /* State Offset */
649#define PCI_SRIOV_VFM_UA 0x0 /* Inactive.Unavailable */
650#define PCI_SRIOV_VFM_MI 0x1 /* Dormant.MigrateIn */
651#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
652#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
653
Greg Kroah-Hartman4352dfd2005-07-28 11:37:33 -0700654#endif /* LINUX_PCI_REGS_H */