blob: e7fcea7f33008b3e8ee5c3288475a726fd88c13d [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-integrator/pci_v3.c
3 *
4 * PCI functions for V3 host PCI bridge
5 *
6 * Copyright (C) 1999 ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070023#include <linux/kernel.h>
24#include <linux/pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070025#include <linux/ioport.h>
26#include <linux/interrupt.h>
27#include <linux/spinlock.h>
28#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010029#include <linux/io.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Russell Kinga09e64f2008-08-05 16:14:15 +010031#include <mach/hardware.h>
Russell Kinga285edc2010-01-14 19:59:37 +000032#include <mach/platform.h>
Linus Walleij695436e2012-02-26 10:46:48 +010033#include <mach/irqs.h>
34
Alexey Dobriyand43c36d2009-10-07 17:09:06 +040035#include <asm/signal.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include <asm/mach/pci.h>
Russell Kingc6af66b2007-05-17 10:16:55 +010037#include <asm/irq_regs.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070038
39#include <asm/hardware/pci_v3.h>
40
41/*
42 * The V3 PCI interface chip in Integrator provides several windows from
43 * local bus memory into the PCI memory areas. Unfortunately, there
Rob Herring29d39602012-07-13 16:27:43 -050044 * are not really enough windows for our usage, therefore we reuse
Linus Torvalds1da177e2005-04-16 15:20:36 -070045 * one of the windows for access to PCI configuration space. The
46 * memory map is as follows:
Rob Herring29d39602012-07-13 16:27:43 -050047 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070048 * Local Bus Memory Usage
Rob Herring29d39602012-07-13 16:27:43 -050049 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070050 * 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
51 * 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
52 * 60000000 - 60FFFFFF PCI IO. 16M
53 * 61000000 - 61FFFFFF PCI Configuration. 16M
Rob Herring29d39602012-07-13 16:27:43 -050054 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 * There are three V3 windows, each described by a pair of V3 registers.
56 * These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
57 * Base0 and Base1 can be used for any type of PCI memory access. Base2
58 * can be used either for PCI I/O or for I20 accesses. By default, uHAL
59 * uses this only for PCI IO space.
Rob Herring29d39602012-07-13 16:27:43 -050060 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070061 * Normally these spaces are mapped using the following base registers:
Rob Herring29d39602012-07-13 16:27:43 -050062 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070063 * Usage Local Bus Memory Base/Map registers used
Rob Herring29d39602012-07-13 16:27:43 -050064 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070065 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
66 * Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
67 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
68 * Cfg 61000000 - 61FFFFFF
Rob Herring29d39602012-07-13 16:27:43 -050069 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070070 * This means that I20 and PCI configuration space accesses will fail.
Rob Herring29d39602012-07-13 16:27:43 -050071 * When PCI configuration accesses are needed (via the uHAL PCI
Linus Torvalds1da177e2005-04-16 15:20:36 -070072 * configuration space primitives) we must remap the spaces as follows:
Rob Herring29d39602012-07-13 16:27:43 -050073 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070074 * Usage Local Bus Memory Base/Map registers used
Rob Herring29d39602012-07-13 16:27:43 -050075 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 * Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
77 * Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
78 * IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
79 * Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
Rob Herring29d39602012-07-13 16:27:43 -050080 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 * To make this work, the code depends on overlapping windows working.
Rob Herring29d39602012-07-13 16:27:43 -050082 * The V3 chip translates an address by checking its range within
Linus Torvalds1da177e2005-04-16 15:20:36 -070083 * each of the BASE/MAP pairs in turn (in ascending register number
84 * order). It will use the first matching pair. So, for example,
85 * if the same address is mapped by both LB_BASE0/LB_MAP0 and
Rob Herring29d39602012-07-13 16:27:43 -050086 * LB_BASE1/LB_MAP1, the V3 will use the translation from
Linus Torvalds1da177e2005-04-16 15:20:36 -070087 * LB_BASE0/LB_MAP0.
Rob Herring29d39602012-07-13 16:27:43 -050088 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 * To allow PCI Configuration space access, the code enlarges the
90 * window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
91 * the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
92 * be remapped for use by configuration cycles.
Rob Herring29d39602012-07-13 16:27:43 -050093 *
94 * At the end of the PCI Configuration space accesses,
Linus Torvalds1da177e2005-04-16 15:20:36 -070095 * LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
96 * mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
97 * reveal the now restored LB_BASE1/LB_MAP1 window.
Rob Herring29d39602012-07-13 16:27:43 -050098 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070099 * NOTE: We do not set up I2O mapping. I suspect that this is only
100 * for an intelligent (target) device. Using I2O disables most of
101 * the mappings into PCI memory.
102 */
103
104// V3 access routines
105#define v3_writeb(o,v) __raw_writeb(v, PCI_V3_VADDR + (unsigned int)(o))
106#define v3_readb(o) (__raw_readb(PCI_V3_VADDR + (unsigned int)(o)))
107
108#define v3_writew(o,v) __raw_writew(v, PCI_V3_VADDR + (unsigned int)(o))
109#define v3_readw(o) (__raw_readw(PCI_V3_VADDR + (unsigned int)(o)))
110
111#define v3_writel(o,v) __raw_writel(v, PCI_V3_VADDR + (unsigned int)(o))
112#define v3_readl(o) (__raw_readl(PCI_V3_VADDR + (unsigned int)(o)))
113
114/*============================================================================
115 *
116 * routine: uHALir_PCIMakeConfigAddress()
117 *
118 * parameters: bus = which bus
119 * device = which device
120 * function = which function
121 * offset = configuration space register we are interested in
122 *
123 * description: this routine will generate a platform dependent config
124 * address.
125 *
126 * calls: none
127 *
128 * returns: configuration address to play on the PCI bus
129 *
Rob Herring29d39602012-07-13 16:27:43 -0500130 * To generate the appropriate PCI configuration cycles in the PCI
131 * configuration address space, you present the V3 with the following pattern
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 * (which is very nearly a type 1 (except that the lower two bits are 00 and
133 * not 01). In order for this mapping to work you need to set up one of
134 * the local to PCI aperatures to 16Mbytes in length translating to
135 * PCI configuration space starting at 0x0000.0000.
136 *
137 * PCI configuration cycles look like this:
138 *
139 * Type 0:
140 *
Rob Herring29d39602012-07-13 16:27:43 -0500141 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
143 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
144 * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
145 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
146 *
147 * 31:11 Device select bit.
148 * 10:8 Function number
149 * 7:2 Register number
150 *
151 * Type 1:
152 *
Rob Herring29d39602012-07-13 16:27:43 -0500153 * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
155 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
156 * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
157 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
158 *
159 * 31:24 reserved
160 * 23:16 bus number (8 bits = 128 possible buses)
161 * 15:11 Device number (5 bits)
162 * 10:8 function number
163 * 7:2 register number
Rob Herring29d39602012-07-13 16:27:43 -0500164 *
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 */
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500166static DEFINE_RAW_SPINLOCK(v3_lock);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167
168#define PCI_BUS_NONMEM_START 0x00000000
169#define PCI_BUS_NONMEM_SIZE SZ_256M
170
171#define PCI_BUS_PREMEM_START PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE
172#define PCI_BUS_PREMEM_SIZE SZ_256M
173
174#if PCI_BUS_NONMEM_START & 0x000fffff
175#error PCI_BUS_NONMEM_START must be megabyte aligned
176#endif
177#if PCI_BUS_PREMEM_START & 0x000fffff
178#error PCI_BUS_PREMEM_START must be megabyte aligned
179#endif
180
181#undef V3_LB_BASE_PREFETCH
182#define V3_LB_BASE_PREFETCH 0
183
Arnd Bergmannb7a3f8d2012-09-14 20:16:39 +0000184static void __iomem *v3_open_config_window(struct pci_bus *bus,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700185 unsigned int devfn, int offset)
186{
187 unsigned int address, mapaddress, busnr;
188
189 busnr = bus->number;
190
191 /*
192 * Trap out illegal values
193 */
Sasha Levinf7a9b362012-11-08 15:23:08 -0500194 BUG_ON(offset > 255);
195 BUG_ON(busnr > 255);
196 BUG_ON(devfn > 255);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700197
198 if (busnr == 0) {
199 int slot = PCI_SLOT(devfn);
200
201 /*
202 * local bus segment so need a type 0 config cycle
203 *
204 * build the PCI configuration "address" with one-hot in
205 * A31-A11
206 *
207 * mapaddress:
208 * 3:1 = config cycle (101)
209 * 0 = PCI A1 & A0 are 0 (0)
210 */
211 address = PCI_FUNC(devfn) << 8;
212 mapaddress = V3_LB_MAP_TYPE_CONFIG;
213
214 if (slot > 12)
215 /*
216 * high order bits are handled by the MAP register
217 */
218 mapaddress |= 1 << (slot - 5);
219 else
220 /*
221 * low order bits handled directly in the address
222 */
223 address |= 1 << (slot + 11);
224 } else {
225 /*
226 * not the local bus segment so need a type 1 config cycle
227 *
228 * address:
229 * 23:16 = bus number
230 * 15:11 = slot number (7:3 of devfn)
231 * 10:8 = func number (2:0 of devfn)
232 *
233 * mapaddress:
234 * 3:1 = config cycle (101)
235 * 0 = PCI A1 & A0 from host bus (1)
236 */
237 mapaddress = V3_LB_MAP_TYPE_CONFIG | V3_LB_MAP_AD_LOW_EN;
238 address = (busnr << 16) | (devfn << 8);
239 }
240
241 /*
242 * Set up base0 to see all 512Mbytes of memory space (not
243 * prefetchable), this frees up base1 for re-use by
244 * configuration memory
245 */
246 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
247 V3_LB_BASE_ADR_SIZE_512MB | V3_LB_BASE_ENABLE);
248
249 /*
250 * Set up base1/map1 to point into configuration space.
251 */
252 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_CONFIG_BASE) |
253 V3_LB_BASE_ADR_SIZE_16MB | V3_LB_BASE_ENABLE);
254 v3_writew(V3_LB_MAP1, mapaddress);
255
256 return PCI_CONFIG_VADDR + address + offset;
257}
258
259static void v3_close_config_window(void)
260{
261 /*
262 * Reassign base1 for use by prefetchable PCI memory
263 */
264 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
265 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
266 V3_LB_BASE_ENABLE);
267 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
268 V3_LB_MAP_TYPE_MEM_MULTIPLE);
269
270 /*
271 * And shrink base0 back to a 256M window (NOTE: MAP0 already correct)
272 */
273 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
274 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
275}
276
277static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
278 int size, u32 *val)
279{
Arnd Bergmannb7a3f8d2012-09-14 20:16:39 +0000280 void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700281 unsigned long flags;
282 u32 v;
283
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500284 raw_spin_lock_irqsave(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 addr = v3_open_config_window(bus, devfn, where);
286
287 switch (size) {
288 case 1:
289 v = __raw_readb(addr);
290 break;
291
292 case 2:
293 v = __raw_readw(addr);
294 break;
295
296 default:
297 v = __raw_readl(addr);
298 break;
299 }
300
301 v3_close_config_window();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500302 raw_spin_unlock_irqrestore(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303
304 *val = v;
305 return PCIBIOS_SUCCESSFUL;
306}
307
308static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
309 int size, u32 val)
310{
Arnd Bergmannb7a3f8d2012-09-14 20:16:39 +0000311 void __iomem *addr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700312 unsigned long flags;
313
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500314 raw_spin_lock_irqsave(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 addr = v3_open_config_window(bus, devfn, where);
316
317 switch (size) {
318 case 1:
319 __raw_writeb((u8)val, addr);
320 __raw_readb(addr);
321 break;
322
323 case 2:
324 __raw_writew((u16)val, addr);
325 __raw_readw(addr);
326 break;
327
328 case 4:
329 __raw_writel(val, addr);
330 __raw_readl(addr);
331 break;
332 }
333
334 v3_close_config_window();
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500335 raw_spin_unlock_irqrestore(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700336
337 return PCIBIOS_SUCCESSFUL;
338}
339
Russell Kingc23bfc32012-03-10 12:49:16 +0000340struct pci_ops pci_v3_ops = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700341 .read = v3_read_config,
342 .write = v3_write_config,
343};
344
345static struct resource non_mem = {
346 .name = "PCI non-prefetchable",
347 .start = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START,
348 .end = PHYS_PCI_MEM_BASE + PCI_BUS_NONMEM_START + PCI_BUS_NONMEM_SIZE - 1,
349 .flags = IORESOURCE_MEM,
350};
351
352static struct resource pre_mem = {
353 .name = "PCI prefetchable",
354 .start = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START,
355 .end = PHYS_PCI_MEM_BASE + PCI_BUS_PREMEM_START + PCI_BUS_PREMEM_SIZE - 1,
356 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
357};
358
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600359static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700360{
361 if (request_resource(&iomem_resource, &non_mem)) {
362 printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
363 "memory region\n");
364 return -EBUSY;
365 }
366 if (request_resource(&iomem_resource, &pre_mem)) {
367 release_resource(&non_mem);
368 printk(KERN_ERR "PCI: unable to allocate prefetchable "
369 "memory region\n");
370 return -EBUSY;
371 }
372
373 /*
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600374 * the mem resource for this bus
375 * the prefetch mem resource for this bus
Linus Torvalds1da177e2005-04-16 15:20:36 -0700376 */
Bjorn Helgaas9f786d02012-02-23 20:19:01 -0700377 pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
378 pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700379
380 return 1;
381}
382
383/*
384 * These don't seem to be implemented on the Integrator I have, which
385 * means I can't get additional information on the reason for the pm2fb
386 * problems. I suppose I'll just have to mind-meld with the machine. ;)
387 */
Linus Walleij379df272012-11-17 19:24:23 +0100388static void __iomem *ap_syscon_base;
389#define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18
390#define INTEGRATOR_SC_LBFADDR_OFFSET 0x20
391#define INTEGRATOR_SC_LBFCODE_OFFSET 0x24
Linus Torvalds1da177e2005-04-16 15:20:36 -0700392
393static int
394v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
395{
396 unsigned long pc = instruction_pointer(regs);
397 unsigned long instr = *(unsigned long *)pc;
398#if 0
399 char buf[128];
400
401 sprintf(buf, "V3 fault: addr 0x%08lx, FSR 0x%03x, PC 0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x ISTAT=%02x\n",
Linus Walleij379df272012-11-17 19:24:23 +0100402 addr, fsr, pc, instr, __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET), __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700403 v3_readb(V3_LB_ISTAT));
404 printk(KERN_DEBUG "%s", buf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405#endif
406
407 v3_writeb(V3_LB_ISTAT, 0);
Linus Walleij379df272012-11-17 19:24:23 +0100408 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409
410 /*
411 * If the instruction being executed was a read,
412 * make it look like it read all-ones.
413 */
414 if ((instr & 0x0c100000) == 0x04100000) {
415 int reg = (instr >> 12) & 15;
416 unsigned long val;
417
418 if (instr & 0x00400000)
419 val = 255;
420 else
421 val = -1;
422
423 regs->uregs[reg] = val;
424 regs->ARM_pc += 4;
425 return 0;
426 }
427
428 if ((instr & 0x0e100090) == 0x00100090) {
429 int reg = (instr >> 12) & 15;
430
431 regs->uregs[reg] = -1;
432 regs->ARM_pc += 4;
433 return 0;
434 }
435
436 return 1;
437}
438
Jeff Garzike8f2af12007-10-26 05:40:25 -0400439static irqreturn_t v3_irq(int dummy, void *devid)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700440{
441#ifdef CONFIG_DEBUG_LL
Linus Torvalds0cd61b62006-10-06 10:53:39 -0700442 struct pt_regs *regs = get_irq_regs();
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 unsigned long pc = instruction_pointer(regs);
444 unsigned long instr = *(unsigned long *)pc;
445 char buf[128];
Russell King7c284722008-05-23 19:35:52 +0100446 extern void printascii(const char *);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
Jeff Garzike8f2af12007-10-26 05:40:25 -0400448 sprintf(buf, "V3 int %d: pc=0x%08lx [%08lx] LBFADDR=%08x LBFCODE=%02x "
449 "ISTAT=%02x\n", IRQ_AP_V3INT, pc, instr,
Linus Walleij379df272012-11-17 19:24:23 +0100450 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFADDR_OFFSET),
451 __raw_readl(ap_syscon_base + INTEGRATOR_SC_LBFCODE_OFFSET) & 255,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 v3_readb(V3_LB_ISTAT));
453 printascii(buf);
454#endif
455
456 v3_writew(V3_PCI_STAT, 0xf000);
457 v3_writeb(V3_LB_ISTAT, 0);
Linus Walleij379df272012-11-17 19:24:23 +0100458 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459
460#ifdef CONFIG_DEBUG_LL
461 /*
462 * If the instruction being executed was a read,
463 * make it look like it read all-ones.
464 */
465 if ((instr & 0x0c100000) == 0x04100000) {
466 int reg = (instr >> 16) & 15;
467 sprintf(buf, " reg%d = %08lx\n", reg, regs->uregs[reg]);
468 printascii(buf);
469 }
470#endif
471 return IRQ_HANDLED;
472}
473
474int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
475{
476 int ret = 0;
477
Linus Walleij67c6b2e2013-01-10 10:18:49 +0100478 if (!ap_syscon_base)
479 return -EINVAL;
480
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481 if (nr == 0) {
482 sys->mem_offset = PHYS_PCI_MEM_BASE;
Bjorn Helgaas37d15902011-10-28 16:26:16 -0600483 ret = pci_v3_setup_resources(sys);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 }
485
486 return ret;
487}
488
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489/*
490 * V3_LB_BASE? - local bus address
491 * V3_LB_MAP? - pci bus address
492 */
493void __init pci_v3_preinit(void)
494{
495 unsigned long flags;
496 unsigned int temp;
497 int ret;
498
Linus Walleij67c6b2e2013-01-10 10:18:49 +0100499 /* Remap the Integrator system controller */
500 ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100);
501 if (!ap_syscon_base) {
502 pr_err("unable to remap the AP syscon for PCIv3\n");
503 return;
504 }
505
Rob Herringc9d95fb2011-06-28 21:16:13 -0500506 pcibios_min_mem = 0x00100000;
507
Linus Torvalds1da177e2005-04-16 15:20:36 -0700508 /*
509 * Hook in our fault handler for PCI errors
510 */
Kirill A. Shutemov6338a6a2010-07-22 13:18:19 +0100511 hook_fault_code(4, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
512 hook_fault_code(6, v3_pci_fault, SIGBUS, 0, "external abort on linefetch");
513 hook_fault_code(8, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
514 hook_fault_code(10, v3_pci_fault, SIGBUS, 0, "external abort on non-linefetch");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700515
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500516 raw_spin_lock_irqsave(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700517
518 /*
519 * Unlock V3 registers, but only if they were previously locked.
520 */
521 if (v3_readw(V3_SYSTEM) & V3_SYSTEM_M_LOCK)
522 v3_writew(V3_SYSTEM, 0xa05f);
523
524 /*
525 * Setup window 0 - PCI non-prefetchable memory
526 * Local: 0x40000000 Bus: 0x00000000 Size: 256MB
527 */
528 v3_writel(V3_LB_BASE0, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE) |
529 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_ENABLE);
530 v3_writew(V3_LB_MAP0, v3_addr_to_lb_map(PCI_BUS_NONMEM_START) |
531 V3_LB_MAP_TYPE_MEM);
532
533 /*
534 * Setup window 1 - PCI prefetchable memory
535 * Local: 0x50000000 Bus: 0x10000000 Size: 256MB
536 */
537 v3_writel(V3_LB_BASE1, v3_addr_to_lb_base(PHYS_PCI_MEM_BASE + SZ_256M) |
538 V3_LB_BASE_ADR_SIZE_256MB | V3_LB_BASE_PREFETCH |
539 V3_LB_BASE_ENABLE);
540 v3_writew(V3_LB_MAP1, v3_addr_to_lb_map(PCI_BUS_PREMEM_START) |
541 V3_LB_MAP_TYPE_MEM_MULTIPLE);
542
543 /*
544 * Setup window 2 - PCI IO
545 */
546 v3_writel(V3_LB_BASE2, v3_addr_to_lb_base2(PHYS_PCI_IO_BASE) |
547 V3_LB_BASE_ENABLE);
548 v3_writew(V3_LB_MAP2, v3_addr_to_lb_map2(0));
549
550 /*
551 * Disable PCI to host IO cycles
552 */
553 temp = v3_readw(V3_PCI_CFG) & ~V3_PCI_CFG_M_I2O_EN;
554 temp |= V3_PCI_CFG_M_IO_REG_DIS | V3_PCI_CFG_M_IO_DIS;
555 v3_writew(V3_PCI_CFG, temp);
556
557 printk(KERN_DEBUG "FIFO_CFG: %04x FIFO_PRIO: %04x\n",
558 v3_readw(V3_FIFO_CFG), v3_readw(V3_FIFO_PRIORITY));
559
560 /*
561 * Set the V3 FIFO such that writes have higher priority than
562 * reads, and local bus write causes local bus read fifo flush.
563 * Same for PCI.
564 */
565 v3_writew(V3_FIFO_PRIORITY, 0x0a0a);
566
567 /*
568 * Re-lock the system register.
569 */
570 temp = v3_readw(V3_SYSTEM) | V3_SYSTEM_M_LOCK;
571 v3_writew(V3_SYSTEM, temp);
572
573 /*
574 * Clear any error conditions, and enable write errors.
575 */
576 v3_writeb(V3_LB_ISTAT, 0);
577 v3_writew(V3_LB_CFG, v3_readw(V3_LB_CFG) | (1 << 10));
578 v3_writeb(V3_LB_IMASK, 0x28);
Linus Walleij379df272012-11-17 19:24:23 +0100579 __raw_writel(3, ap_syscon_base + INTEGRATOR_SC_PCIENABLE_OFFSET);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700580
581 /*
582 * Grab the PCI error interrupt.
583 */
584 ret = request_irq(IRQ_AP_V3INT, v3_irq, 0, "V3", NULL);
585 if (ret)
586 printk(KERN_ERR "PCI: unable to grab PCI error "
587 "interrupt: %d\n", ret);
588
Thomas Gleixnerbd31b852009-07-03 08:44:46 -0500589 raw_spin_unlock_irqrestore(&v3_lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700590}
591
592void __init pci_v3_postinit(void)
593{
594 unsigned int pci_cmd;
595
596 pci_cmd = PCI_COMMAND_MEMORY |
597 PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE;
598
599 v3_writew(V3_PCI_CMD, pci_cmd);
600
601 v3_writeb(V3_LB_ISTAT, ~0x40);
602 v3_writeb(V3_LB_IMASK, 0x68);
603
604#if 0
605 ret = request_irq(IRQ_AP_LBUSTIMEOUT, lb_timeout, 0, "bus timeout", NULL);
606 if (ret)
607 printk(KERN_ERR "PCI: unable to grab local bus timeout "
608 "interrupt: %d\n", ret);
609#endif
Russell King863dab42006-08-28 12:47:05 +0100610
611 register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700612}