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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/arch/arm/mach-footbridge/dc21285-timer.c
3 *
4 * Copyright (C) 1998 Russell King.
5 * Copyright (C) 1998 Phil Blundell
6 */
Russell King4e8d7632011-01-28 21:00:39 +00007#include <linux/clockchips.h>
8#include <linux/clocksource.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -07009#include <linux/init.h>
10#include <linux/interrupt.h>
Thomas Gleixner55e86982006-07-01 22:32:17 +010011#include <linux/irq.h>
Russell King6cefe922013-11-29 01:03:35 +000012#include <linux/sched_clock.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070013
14#include <asm/irq.h>
15
16#include <asm/hardware/dec21285.h>
17#include <asm/mach/time.h>
David Howells9f97da72012-03-28 18:30:01 +010018#include <asm/system_info.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070019
20#include "common.h"
21
Russell King4e8d7632011-01-28 21:00:39 +000022static cycle_t cksrc_dc21285_read(struct clocksource *cs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070023{
Russell King4e8d7632011-01-28 21:00:39 +000024 return cs->mask - *CSR_TIMER2_VALUE;
Linus Torvalds1da177e2005-04-16 15:20:36 -070025}
26
Russell King4e8d7632011-01-28 21:00:39 +000027static int cksrc_dc21285_enable(struct clocksource *cs)
Linus Torvalds1da177e2005-04-16 15:20:36 -070028{
Russell King4e8d7632011-01-28 21:00:39 +000029 *CSR_TIMER2_LOAD = cs->mask;
30 *CSR_TIMER2_CLR = 0;
31 *CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
32 return 0;
33}
34
Thomas Gleixnerf2e0bf22011-03-28 11:25:40 +020035static void cksrc_dc21285_disable(struct clocksource *cs)
Russell King4e8d7632011-01-28 21:00:39 +000036{
37 *CSR_TIMER2_CNTL = 0;
38}
39
40static struct clocksource cksrc_dc21285 = {
41 .name = "dc21285_timer2",
42 .rating = 200,
43 .read = cksrc_dc21285_read,
44 .enable = cksrc_dc21285_enable,
45 .disable = cksrc_dc21285_disable,
46 .mask = CLOCKSOURCE_MASK(24),
47 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
48};
49
Russell King48089722013-11-30 12:21:21 +000050static int ckevt_dc21285_set_next_event(unsigned long delta,
51 struct clock_event_device *c)
52{
53 *CSR_TIMER1_CLR = 0;
54 *CSR_TIMER1_LOAD = delta;
55 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
56
57 return 0;
58}
59
Viresh Kumar947d9cf2015-02-27 13:39:52 +053060static int ckevt_dc21285_shutdown(struct clock_event_device *c)
Russell King4e8d7632011-01-28 21:00:39 +000061{
Viresh Kumar947d9cf2015-02-27 13:39:52 +053062 *CSR_TIMER1_CNTL = 0;
63 return 0;
64}
Russell King4e8d7632011-01-28 21:00:39 +000065
Viresh Kumar947d9cf2015-02-27 13:39:52 +053066static int ckevt_dc21285_set_periodic(struct clock_event_device *c)
67{
68 *CSR_TIMER1_CLR = 0;
69 *CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ);
70 *CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD |
71 TIMER_CNTL_DIV16;
72 return 0;
Russell King4e8d7632011-01-28 21:00:39 +000073}
74
75static struct clock_event_device ckevt_dc21285 = {
Viresh Kumar947d9cf2015-02-27 13:39:52 +053076 .name = "dc21285_timer1",
77 .features = CLOCK_EVT_FEAT_PERIODIC |
78 CLOCK_EVT_FEAT_ONESHOT,
79 .rating = 200,
80 .irq = IRQ_TIMER1,
81 .set_next_event = ckevt_dc21285_set_next_event,
82 .set_state_shutdown = ckevt_dc21285_shutdown,
83 .set_state_periodic = ckevt_dc21285_set_periodic,
84 .set_state_oneshot = ckevt_dc21285_shutdown,
85 .tick_resume = ckevt_dc21285_set_periodic,
Russell King4e8d7632011-01-28 21:00:39 +000086};
87
88static irqreturn_t timer1_interrupt(int irq, void *dev_id)
89{
90 struct clock_event_device *ce = dev_id;
91
Linus Torvalds1da177e2005-04-16 15:20:36 -070092 *CSR_TIMER1_CLR = 0;
93
Russell King48089722013-11-30 12:21:21 +000094 /* Stop the timer if in one-shot mode */
Viresh Kumar947d9cf2015-02-27 13:39:52 +053095 if (clockevent_state_oneshot(ce))
Russell King48089722013-11-30 12:21:21 +000096 *CSR_TIMER1_CNTL = 0;
97
Russell King4e8d7632011-01-28 21:00:39 +000098 ce->event_handler(ce);
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
Linus Torvalds1da177e2005-04-16 15:20:36 -0700100 return IRQ_HANDLED;
101}
102
103static struct irqaction footbridge_timer_irq = {
Russell King4e8d7632011-01-28 21:00:39 +0000104 .name = "dc21285_timer1",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 .handler = timer1_interrupt,
Michael Opdenacker26632be2014-03-04 21:45:48 +0100106 .flags = IRQF_TIMER | IRQF_IRQPOLL,
Russell King4e8d7632011-01-28 21:00:39 +0000107 .dev_id = &ckevt_dc21285,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108};
109
110/*
111 * Set up timer interrupt.
112 */
Stephen Warren6bb27d72012-11-08 12:40:59 -0700113void __init footbridge_timer_init(void)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700114{
Russell King4e8d7632011-01-28 21:00:39 +0000115 struct clock_event_device *ce = &ckevt_dc21285;
Russell King4ff859f2013-12-29 12:39:50 +0000116 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700117
Russell King4ff859f2013-12-29 12:39:50 +0000118 clocksource_register_hz(&cksrc_dc21285, rate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119
Russell King4e8d7632011-01-28 21:00:39 +0000120 setup_irq(ce->irq, &footbridge_timer_irq);
121
Russell King7d7975a2011-06-11 00:46:17 +0100122 ce->cpumask = cpumask_of(smp_processor_id());
Russell King4ff859f2013-12-29 12:39:50 +0000123 clockevents_config_and_register(ce, rate, 0x4, 0xffffff);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700124}
Russell King6cefe922013-11-29 01:03:35 +0000125
Stephen Boyd889f1722014-01-17 20:42:48 +0100126static u64 notrace footbridge_read_sched_clock(void)
Russell King6cefe922013-11-29 01:03:35 +0000127{
128 return ~*CSR_TIMER3_VALUE;
129}
130
131void __init footbridge_sched_clock(void)
132{
133 unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16);
134
135 *CSR_TIMER3_LOAD = 0;
136 *CSR_TIMER3_CLR = 0;
137 *CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16;
138
Stephen Boyd889f1722014-01-17 20:42:48 +0100139 sched_clock_register(footbridge_read_sched_clock, 24, rate);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140}