Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1 | /* |
| 2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers |
| 3 | * |
| 4 | * Copyright 2005 Tejun Heo |
| 5 | * |
| 6 | * Based on preview driver from Silicon Image. |
| 7 | * |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2, or (at your option) any |
| 11 | * later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/pci.h> |
| 23 | #include <linux/blkdev.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/interrupt.h> |
| 26 | #include <linux/dma-mapping.h> |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 27 | #include <linux/device.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 28 | #include <scsi/scsi_host.h> |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 29 | #include <scsi/scsi_cmnd.h> |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 30 | #include <linux/libata.h> |
| 31 | #include <asm/io.h> |
| 32 | |
| 33 | #define DRV_NAME "sata_sil24" |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 34 | #define DRV_VERSION "0.23" |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 35 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 36 | /* |
| 37 | * Port request block (PRB) 32 bytes |
| 38 | */ |
| 39 | struct sil24_prb { |
| 40 | u16 ctrl; |
| 41 | u16 prot; |
| 42 | u32 rx_cnt; |
| 43 | u8 fis[6 * 4]; |
| 44 | }; |
| 45 | |
| 46 | /* |
| 47 | * Scatter gather entry (SGE) 16 bytes |
| 48 | */ |
| 49 | struct sil24_sge { |
| 50 | u64 addr; |
| 51 | u32 cnt; |
| 52 | u32 flags; |
| 53 | }; |
| 54 | |
| 55 | /* |
| 56 | * Port multiplier |
| 57 | */ |
| 58 | struct sil24_port_multiplier { |
| 59 | u32 diag; |
| 60 | u32 sactive; |
| 61 | }; |
| 62 | |
| 63 | enum { |
| 64 | /* |
| 65 | * Global controller registers (128 bytes @ BAR0) |
| 66 | */ |
| 67 | /* 32 bit regs */ |
| 68 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ |
| 69 | HOST_CTRL = 0x40, |
| 70 | HOST_IRQ_STAT = 0x44, |
| 71 | HOST_PHY_CFG = 0x48, |
| 72 | HOST_BIST_CTRL = 0x50, |
| 73 | HOST_BIST_PTRN = 0x54, |
| 74 | HOST_BIST_STAT = 0x58, |
| 75 | HOST_MEM_BIST_STAT = 0x5c, |
| 76 | HOST_FLASH_CMD = 0x70, |
| 77 | /* 8 bit regs */ |
| 78 | HOST_FLASH_DATA = 0x74, |
| 79 | HOST_TRANSITION_DETECT = 0x75, |
| 80 | HOST_GPIO_CTRL = 0x76, |
| 81 | HOST_I2C_ADDR = 0x78, /* 32 bit */ |
| 82 | HOST_I2C_DATA = 0x7c, |
| 83 | HOST_I2C_XFER_CNT = 0x7e, |
| 84 | HOST_I2C_CTRL = 0x7f, |
| 85 | |
| 86 | /* HOST_SLOT_STAT bits */ |
| 87 | HOST_SSTAT_ATTN = (1 << 31), |
| 88 | |
| 89 | /* |
| 90 | * Port registers |
| 91 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) |
| 92 | */ |
| 93 | PORT_REGS_SIZE = 0x2000, |
| 94 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 95 | |
| 96 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ |
| 97 | /* 32 bit regs */ |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 98 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
| 99 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ |
| 100 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ |
| 101 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ |
| 102 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 103 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 104 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
| 105 | PORT_CMD_ERR = 0x1024, /* command error number */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 106 | PORT_FIS_CFG = 0x1028, |
| 107 | PORT_FIFO_THRES = 0x102c, |
| 108 | /* 16 bit regs */ |
| 109 | PORT_DECODE_ERR_CNT = 0x1040, |
| 110 | PORT_DECODE_ERR_THRESH = 0x1042, |
| 111 | PORT_CRC_ERR_CNT = 0x1044, |
| 112 | PORT_CRC_ERR_THRESH = 0x1046, |
| 113 | PORT_HSHK_ERR_CNT = 0x1048, |
| 114 | PORT_HSHK_ERR_THRESH = 0x104a, |
| 115 | /* 32 bit regs */ |
| 116 | PORT_PHY_CFG = 0x1050, |
| 117 | PORT_SLOT_STAT = 0x1800, |
| 118 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ |
| 119 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
| 120 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ |
| 121 | PORT_SCONTROL = 0x1f00, |
| 122 | PORT_SSTATUS = 0x1f04, |
| 123 | PORT_SERROR = 0x1f08, |
| 124 | PORT_SACTIVE = 0x1f0c, |
| 125 | |
| 126 | /* PORT_CTRL_STAT bits */ |
| 127 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ |
| 128 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ |
| 129 | PORT_CS_INIT = (1 << 2), /* port initialize */ |
| 130 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 131 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
Tejun Heo | e382eb1 | 2005-08-17 13:09:13 +0900 | [diff] [blame] | 132 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
| 133 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
| 134 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ |
| 135 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 136 | |
| 137 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ |
| 138 | /* bits[11:0] are masked */ |
| 139 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ |
| 140 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ |
| 141 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ |
| 142 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ |
| 143 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ |
| 144 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ |
| 145 | PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */ |
| 146 | PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */ |
| 147 | |
| 148 | /* bits[27:16] are unmasked (raw) */ |
| 149 | PORT_IRQ_RAW_SHIFT = 16, |
| 150 | PORT_IRQ_MASKED_MASK = 0x7ff, |
| 151 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), |
| 152 | |
| 153 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ |
| 154 | PORT_IRQ_STEER_SHIFT = 30, |
| 155 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), |
| 156 | |
| 157 | /* PORT_CMD_ERR constants */ |
| 158 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ |
| 159 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ |
| 160 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ |
| 161 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ |
| 162 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ |
| 163 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ |
| 164 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ |
| 165 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ |
| 166 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ |
| 167 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ |
| 168 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ |
| 169 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ |
| 170 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ |
| 171 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ |
| 172 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ |
| 173 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ |
| 174 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ |
| 175 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ |
| 176 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ |
| 177 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ |
| 178 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
Tejun Heo | 83bbecc | 2005-08-17 13:09:18 +0900 | [diff] [blame] | 179 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 180 | |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 181 | /* bits of PRB control field */ |
| 182 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ |
| 183 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ |
| 184 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ |
| 185 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ |
| 186 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ |
| 187 | |
| 188 | /* PRB protocol field */ |
| 189 | PRB_PROT_PACKET = (1 << 0), |
| 190 | PRB_PROT_TCQ = (1 << 1), |
| 191 | PRB_PROT_NCQ = (1 << 2), |
| 192 | PRB_PROT_READ = (1 << 3), |
| 193 | PRB_PROT_WRITE = (1 << 4), |
| 194 | PRB_PROT_TRANSPARENT = (1 << 5), |
| 195 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 196 | /* |
| 197 | * Other constants |
| 198 | */ |
| 199 | SGE_TRM = (1 << 31), /* Last SGE in chain */ |
Tejun Heo | d10cb35 | 2005-11-16 16:56:49 +0900 | [diff] [blame] | 200 | SGE_LNK = (1 << 30), /* linked list |
| 201 | Points to SGT, not SGE */ |
| 202 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) |
| 203 | data address ignored */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 204 | |
| 205 | /* board id */ |
| 206 | BID_SIL3124 = 0, |
| 207 | BID_SIL3132 = 1, |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 208 | BID_SIL3131 = 2, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 209 | |
| 210 | IRQ_STAT_4PORTS = 0xf, |
| 211 | }; |
| 212 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 213 | struct sil24_ata_block { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 214 | struct sil24_prb prb; |
| 215 | struct sil24_sge sge[LIBATA_MAX_PRD]; |
| 216 | }; |
| 217 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 218 | struct sil24_atapi_block { |
| 219 | struct sil24_prb prb; |
| 220 | u8 cdb[16]; |
| 221 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; |
| 222 | }; |
| 223 | |
| 224 | union sil24_cmd_block { |
| 225 | struct sil24_ata_block ata; |
| 226 | struct sil24_atapi_block atapi; |
| 227 | }; |
| 228 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 229 | /* |
| 230 | * ap->private_data |
| 231 | * |
| 232 | * The preview driver always returned 0 for status. We emulate it |
| 233 | * here from the previous interrupt. |
| 234 | */ |
| 235 | struct sil24_port_priv { |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 236 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 237 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 238 | struct ata_taskfile tf; /* Cached taskfile registers */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 239 | }; |
| 240 | |
| 241 | /* ap->host_set->private_data */ |
| 242 | struct sil24_host_priv { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 243 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
| 244 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 245 | }; |
| 246 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 247 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 248 | static u8 sil24_check_status(struct ata_port *ap); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 249 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
| 250 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); |
Tejun Heo | 7f726d1 | 2005-10-07 01:43:19 +0900 | [diff] [blame] | 251 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 252 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 253 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 254 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 255 | static void sil24_irq_clear(struct ata_port *ap); |
| 256 | static void sil24_eng_timeout(struct ata_port *ap); |
| 257 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); |
| 258 | static int sil24_port_start(struct ata_port *ap); |
| 259 | static void sil24_port_stop(struct ata_port *ap); |
| 260 | static void sil24_host_stop(struct ata_host_set *host_set); |
| 261 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
| 262 | |
Jeff Garzik | 3b7d697 | 2005-11-10 11:04:11 -0500 | [diff] [blame] | 263 | static const struct pci_device_id sil24_pci_tbl[] = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 264 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
Tejun Heo | 4b9d7e0 | 2006-02-23 10:46:47 +0900 | [diff] [blame] | 265 | { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 266 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 267 | { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
| 268 | { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
Tejun Heo | 1fcce839 | 2005-10-09 09:31:33 -0400 | [diff] [blame] | 269 | { } /* terminate list */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 270 | }; |
| 271 | |
| 272 | static struct pci_driver sil24_pci_driver = { |
| 273 | .name = DRV_NAME, |
| 274 | .id_table = sil24_pci_tbl, |
| 275 | .probe = sil24_init_one, |
| 276 | .remove = ata_pci_remove_one, /* safe? */ |
| 277 | }; |
| 278 | |
Jeff Garzik | 193515d | 2005-11-07 00:59:37 -0500 | [diff] [blame] | 279 | static struct scsi_host_template sil24_sht = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 280 | .module = THIS_MODULE, |
| 281 | .name = DRV_NAME, |
| 282 | .ioctl = ata_scsi_ioctl, |
| 283 | .queuecommand = ata_scsi_queuecmd, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 284 | .can_queue = ATA_DEF_QUEUE, |
| 285 | .this_id = ATA_SHT_THIS_ID, |
| 286 | .sg_tablesize = LIBATA_MAX_PRD, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 287 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
| 288 | .emulated = ATA_SHT_EMULATED, |
| 289 | .use_clustering = ATA_SHT_USE_CLUSTERING, |
| 290 | .proc_name = DRV_NAME, |
| 291 | .dma_boundary = ATA_DMA_BOUNDARY, |
| 292 | .slave_configure = ata_scsi_slave_config, |
| 293 | .bios_param = ata_std_bios_param, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 294 | }; |
| 295 | |
Jeff Garzik | 057ace5 | 2005-10-22 14:27:05 -0400 | [diff] [blame] | 296 | static const struct ata_port_operations sil24_ops = { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 297 | .port_disable = ata_port_disable, |
| 298 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 299 | .dev_config = sil24_dev_config, |
| 300 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 301 | .check_status = sil24_check_status, |
| 302 | .check_altstatus = sil24_check_status, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 303 | .dev_select = ata_noop_dev_select, |
| 304 | |
Tejun Heo | 7f726d1 | 2005-10-07 01:43:19 +0900 | [diff] [blame] | 305 | .tf_read = sil24_tf_read, |
| 306 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 307 | .probe_reset = sil24_probe_reset, |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 308 | |
| 309 | .qc_prep = sil24_qc_prep, |
| 310 | .qc_issue = sil24_qc_issue, |
| 311 | |
| 312 | .eng_timeout = sil24_eng_timeout, |
| 313 | |
| 314 | .irq_handler = sil24_interrupt, |
| 315 | .irq_clear = sil24_irq_clear, |
| 316 | |
| 317 | .scr_read = sil24_scr_read, |
| 318 | .scr_write = sil24_scr_write, |
| 319 | |
| 320 | .port_start = sil24_port_start, |
| 321 | .port_stop = sil24_port_stop, |
| 322 | .host_stop = sil24_host_stop, |
| 323 | }; |
| 324 | |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 325 | /* |
| 326 | * Use bits 30-31 of host_flags to encode available port numbers. |
| 327 | * Current maxium is 4. |
| 328 | */ |
| 329 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) |
| 330 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) |
| 331 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 332 | static struct ata_port_info sil24_port_info[] = { |
| 333 | /* sil_3124 */ |
| 334 | { |
| 335 | .sht = &sil24_sht, |
| 336 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 337 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
| 338 | SIL24_NPORTS2FLAG(4), |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 339 | .pio_mask = 0x1f, /* pio0-4 */ |
| 340 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 341 | .udma_mask = 0x3f, /* udma0-5 */ |
| 342 | .port_ops = &sil24_ops, |
| 343 | }, |
Jeff Garzik | 2e9edbf | 2006-03-24 09:56:57 -0500 | [diff] [blame] | 344 | /* sil_3132 */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 345 | { |
| 346 | .sht = &sil24_sht, |
| 347 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 348 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
| 349 | SIL24_NPORTS2FLAG(2), |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 350 | .pio_mask = 0x1f, /* pio0-4 */ |
| 351 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 352 | .udma_mask = 0x3f, /* udma0-5 */ |
| 353 | .port_ops = &sil24_ops, |
| 354 | }, |
| 355 | /* sil_3131/sil_3531 */ |
| 356 | { |
| 357 | .sht = &sil24_sht, |
| 358 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 359 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
| 360 | SIL24_NPORTS2FLAG(1), |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 361 | .pio_mask = 0x1f, /* pio0-4 */ |
| 362 | .mwdma_mask = 0x07, /* mwdma0-2 */ |
| 363 | .udma_mask = 0x3f, /* udma0-5 */ |
| 364 | .port_ops = &sil24_ops, |
| 365 | }, |
| 366 | }; |
| 367 | |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 368 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
| 369 | { |
| 370 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
| 371 | |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 372 | if (dev->cdb_len == 16) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 373 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
| 374 | else |
| 375 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); |
| 376 | } |
| 377 | |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 378 | static inline void sil24_update_tf(struct ata_port *ap) |
| 379 | { |
| 380 | struct sil24_port_priv *pp = ap->private_data; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 381 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
| 382 | struct sil24_prb __iomem *prb = port; |
| 383 | u8 fis[6 * 4]; |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 384 | |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 385 | memcpy_fromio(fis, prb->fis, 6 * 4); |
| 386 | ata_tf_from_fis(fis, &pp->tf); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 387 | } |
| 388 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 389 | static u8 sil24_check_status(struct ata_port *ap) |
| 390 | { |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 391 | struct sil24_port_priv *pp = ap->private_data; |
| 392 | return pp->tf.command; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 393 | } |
| 394 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 395 | static int sil24_scr_map[] = { |
| 396 | [SCR_CONTROL] = 0, |
| 397 | [SCR_STATUS] = 1, |
| 398 | [SCR_ERROR] = 2, |
| 399 | [SCR_ACTIVE] = 3, |
| 400 | }; |
| 401 | |
| 402 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) |
| 403 | { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 404 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 405 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 406 | void __iomem *addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 407 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
| 408 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); |
| 409 | } |
| 410 | return 0xffffffffU; |
| 411 | } |
| 412 | |
| 413 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) |
| 414 | { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 415 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 416 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 417 | void __iomem *addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 418 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
| 419 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); |
| 420 | } |
| 421 | } |
| 422 | |
Tejun Heo | 7f726d1 | 2005-10-07 01:43:19 +0900 | [diff] [blame] | 423 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
| 424 | { |
| 425 | struct sil24_port_priv *pp = ap->private_data; |
| 426 | *tf = pp->tf; |
| 427 | } |
| 428 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 429 | static int sil24_softreset(struct ata_port *ap, int verbose, |
| 430 | unsigned int *class) |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 431 | { |
| 432 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
| 433 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 434 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 435 | dma_addr_t paddr = pp->cmd_block_dma; |
Tejun Heo | 8645984 | 2006-03-11 11:44:08 +0900 | [diff] [blame] | 436 | unsigned long timeout = jiffies + ATA_TMOUT_BOOT * HZ; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 437 | u32 irq_enable, irq_stat; |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 438 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 439 | DPRINTK("ENTER\n"); |
| 440 | |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 441 | if (!sata_dev_present(ap)) { |
| 442 | DPRINTK("PHY reports no device\n"); |
| 443 | *class = ATA_DEV_NONE; |
| 444 | goto out; |
| 445 | } |
| 446 | |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 447 | /* temporarily turn off IRQs during SRST */ |
| 448 | irq_enable = readl(port + PORT_IRQ_ENABLE_SET); |
| 449 | writel(irq_enable, port + PORT_IRQ_ENABLE_CLR); |
| 450 | |
| 451 | /* |
| 452 | * XXX: Not sure whether the following sleep is needed or not. |
| 453 | * The original driver had it. So.... |
| 454 | */ |
| 455 | msleep(10); |
| 456 | |
Rune Torgersen | 67f672f | 2006-06-04 02:51:41 -0700 | [diff] [blame^] | 457 | prb->ctrl = cpu_to_le16(PRB_CTRL_SRST); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 458 | prb->fis[1] = 0; /* no PM yet */ |
| 459 | |
| 460 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
| 461 | |
Tejun Heo | 8645984 | 2006-03-11 11:44:08 +0900 | [diff] [blame] | 462 | do { |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 463 | irq_stat = readl(port + PORT_IRQ_STAT); |
| 464 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
| 465 | |
| 466 | irq_stat >>= PORT_IRQ_RAW_SHIFT; |
| 467 | if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR)) |
| 468 | break; |
| 469 | |
Tejun Heo | 8645984 | 2006-03-11 11:44:08 +0900 | [diff] [blame] | 470 | msleep(100); |
| 471 | } while (time_before(jiffies, timeout)); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 472 | |
| 473 | /* restore IRQs */ |
| 474 | writel(irq_enable, port + PORT_IRQ_ENABLE_SET); |
| 475 | |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 476 | if (!(irq_stat & PORT_IRQ_COMPLETE)) { |
| 477 | DPRINTK("EXIT, srst failed\n"); |
| 478 | return -EIO; |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 479 | } |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 480 | |
| 481 | sil24_update_tf(ap); |
| 482 | *class = ata_dev_classify(&pp->tf); |
| 483 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 484 | if (*class == ATA_DEV_UNKNOWN) |
| 485 | *class = ATA_DEV_NONE; |
| 486 | |
Tejun Heo | 10d996a | 2006-03-11 11:42:34 +0900 | [diff] [blame] | 487 | out: |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 488 | DPRINTK("EXIT, class=%u\n", *class); |
Tejun Heo | ca45160 | 2005-11-18 14:14:01 +0900 | [diff] [blame] | 489 | return 0; |
| 490 | } |
| 491 | |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 492 | static int sil24_hardreset(struct ata_port *ap, int verbose, |
| 493 | unsigned int *class) |
| 494 | { |
| 495 | unsigned int dummy_class; |
| 496 | |
| 497 | /* sil24 doesn't report device signature after hard reset */ |
| 498 | return sata_std_hardreset(ap, verbose, &dummy_class); |
| 499 | } |
| 500 | |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 501 | static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 502 | { |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 503 | return ata_drive_probe_reset(ap, ata_std_probeinit, |
Tejun Heo | 489ff4c | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 504 | sil24_softreset, sil24_hardreset, |
Tejun Heo | 07b7347 | 2006-02-10 23:58:48 +0900 | [diff] [blame] | 505 | ata_std_postreset, classes); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 509 | struct sil24_sge *sge) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 510 | { |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 511 | struct scatterlist *sg; |
| 512 | unsigned int idx = 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 513 | |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 514 | ata_for_each_sg(sg, qc) { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 515 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
| 516 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); |
Jeff Garzik | 972c26b | 2005-10-18 22:14:54 -0400 | [diff] [blame] | 517 | if (ata_sg_is_last(sg, qc)) |
| 518 | sge->flags = cpu_to_le32(SGE_TRM); |
| 519 | else |
| 520 | sge->flags = 0; |
| 521 | |
| 522 | sge++; |
| 523 | idx++; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 524 | } |
| 525 | } |
| 526 | |
| 527 | static void sil24_qc_prep(struct ata_queued_cmd *qc) |
| 528 | { |
| 529 | struct ata_port *ap = qc->ap; |
| 530 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 531 | union sil24_cmd_block *cb = pp->cmd_block + qc->tag; |
| 532 | struct sil24_prb *prb; |
| 533 | struct sil24_sge *sge; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 534 | |
| 535 | switch (qc->tf.protocol) { |
| 536 | case ATA_PROT_PIO: |
| 537 | case ATA_PROT_DMA: |
| 538 | case ATA_PROT_NODATA: |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 539 | prb = &cb->ata.prb; |
| 540 | sge = cb->ata.sge; |
| 541 | prb->ctrl = 0; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 542 | break; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 543 | |
| 544 | case ATA_PROT_ATAPI: |
| 545 | case ATA_PROT_ATAPI_DMA: |
| 546 | case ATA_PROT_ATAPI_NODATA: |
| 547 | prb = &cb->atapi.prb; |
| 548 | sge = cb->atapi.sge; |
| 549 | memset(cb->atapi.cdb, 0, 32); |
Tejun Heo | 6e7846e | 2006-02-12 23:32:58 +0900 | [diff] [blame] | 550 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 551 | |
| 552 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { |
| 553 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
Rune Torgersen | 67f672f | 2006-06-04 02:51:41 -0700 | [diff] [blame^] | 554 | prb->ctrl = cpu_to_le16(PRB_CTRL_PACKET_WRITE); |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 555 | else |
Rune Torgersen | 67f672f | 2006-06-04 02:51:41 -0700 | [diff] [blame^] | 556 | prb->ctrl = cpu_to_le16(PRB_CTRL_PACKET_READ); |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 557 | } else |
| 558 | prb->ctrl = 0; |
| 559 | |
| 560 | break; |
| 561 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 562 | default: |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 563 | prb = NULL; /* shut up, gcc */ |
| 564 | sge = NULL; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 565 | BUG(); |
| 566 | } |
| 567 | |
| 568 | ata_tf_to_fis(&qc->tf, prb->fis, 0); |
| 569 | |
| 570 | if (qc->flags & ATA_QCFLAG_DMAMAP) |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 571 | sil24_fill_sg(qc, sge); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 572 | } |
| 573 | |
Tejun Heo | 9a3d9eb | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 574 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 575 | { |
| 576 | struct ata_port *ap = qc->ap; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 577 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 578 | struct sil24_port_priv *pp = ap->private_data; |
| 579 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); |
| 580 | |
Tejun Heo | 4f50c3c | 2005-08-17 13:09:07 +0900 | [diff] [blame] | 581 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 582 | return 0; |
| 583 | } |
| 584 | |
| 585 | static void sil24_irq_clear(struct ata_port *ap) |
| 586 | { |
| 587 | /* unused */ |
| 588 | } |
| 589 | |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 590 | static int __sil24_restart_controller(void __iomem *port) |
| 591 | { |
| 592 | u32 tmp; |
| 593 | int cnt; |
| 594 | |
| 595 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
| 596 | |
| 597 | /* Max ~10ms */ |
| 598 | for (cnt = 0; cnt < 10000; cnt++) { |
| 599 | tmp = readl(port + PORT_CTRL_STAT); |
| 600 | if (tmp & PORT_CS_RDY) |
| 601 | return 0; |
| 602 | udelay(1); |
| 603 | } |
| 604 | |
| 605 | return -1; |
| 606 | } |
| 607 | |
| 608 | static void sil24_restart_controller(struct ata_port *ap) |
| 609 | { |
| 610 | if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
| 611 | printk(KERN_ERR DRV_NAME |
| 612 | " ata%u: failed to restart controller\n", ap->id); |
| 613 | } |
| 614 | |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 615 | static int __sil24_reset_controller(void __iomem *port) |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 616 | { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 617 | int cnt; |
| 618 | u32 tmp; |
| 619 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 620 | /* Reset controller state. Is this correct? */ |
| 621 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); |
| 622 | readl(port + PORT_CTRL_STAT); /* sync */ |
| 623 | |
| 624 | /* Max ~100ms */ |
| 625 | for (cnt = 0; cnt < 1000; cnt++) { |
| 626 | udelay(100); |
| 627 | tmp = readl(port + PORT_CTRL_STAT); |
| 628 | if (!(tmp & PORT_CS_DEV_RST)) |
| 629 | break; |
| 630 | } |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 631 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 632 | if (tmp & PORT_CS_DEV_RST) |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 633 | return -1; |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 634 | |
| 635 | if (tmp & PORT_CS_RDY) |
| 636 | return 0; |
| 637 | |
| 638 | return __sil24_restart_controller(port); |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | static void sil24_reset_controller(struct ata_port *ap) |
| 642 | { |
| 643 | printk(KERN_NOTICE DRV_NAME |
| 644 | " ata%u: resetting controller...\n", ap->id); |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 645 | if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 646 | printk(KERN_ERR DRV_NAME |
| 647 | " ata%u: failed to reset controller\n", ap->id); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 648 | } |
| 649 | |
| 650 | static void sil24_eng_timeout(struct ata_port *ap) |
| 651 | { |
| 652 | struct ata_queued_cmd *qc; |
| 653 | |
| 654 | qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 655 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 656 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); |
Tejun Heo | 11a56d2 | 2006-01-23 13:09:36 +0900 | [diff] [blame] | 657 | qc->err_mask |= AC_ERR_TIMEOUT; |
Tejun Heo | a72ec4c | 2006-01-23 13:09:37 +0900 | [diff] [blame] | 658 | ata_eh_qc_complete(qc); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 659 | |
| 660 | sil24_reset_controller(ap); |
| 661 | } |
| 662 | |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 663 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
| 664 | { |
| 665 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 666 | struct sil24_port_priv *pp = ap->private_data; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 667 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 668 | u32 irq_stat, cmd_err, sstatus, serror; |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 669 | unsigned int err_mask; |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 670 | |
| 671 | irq_stat = readl(port + PORT_IRQ_STAT); |
Tejun Heo | ad6e90f | 2005-10-06 11:43:29 +0900 | [diff] [blame] | 672 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
| 673 | |
| 674 | if (!(irq_stat & PORT_IRQ_ERROR)) { |
| 675 | /* ignore non-completion, non-error irqs for now */ |
| 676 | printk(KERN_WARNING DRV_NAME |
| 677 | "ata%u: non-error exception irq (irq_stat %x)\n", |
| 678 | ap->id, irq_stat); |
| 679 | return; |
| 680 | } |
| 681 | |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 682 | cmd_err = readl(port + PORT_CMD_ERR); |
| 683 | sstatus = readl(port + PORT_SSTATUS); |
| 684 | serror = readl(port + PORT_SERROR); |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 685 | if (serror) |
| 686 | writel(serror, port + PORT_SERROR); |
| 687 | |
Tejun Heo | c0ab424 | 2005-11-18 14:22:03 +0900 | [diff] [blame] | 688 | /* |
| 689 | * Don't log ATAPI device errors. They're supposed to happen |
| 690 | * and any serious errors will be logged using sense data by |
| 691 | * the SCSI layer. |
| 692 | */ |
| 693 | if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB) |
| 694 | printk("ata%u: error interrupt on port%d\n" |
| 695 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", |
| 696 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 697 | |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 698 | if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { |
| 699 | /* |
| 700 | * Device is reporting error, tf registers are valid. |
| 701 | */ |
| 702 | sil24_update_tf(ap); |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 703 | err_mask = ac_err_mask(pp->tf.command); |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 704 | sil24_restart_controller(ap); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 705 | } else { |
| 706 | /* |
| 707 | * Other errors. libata currently doesn't have any |
| 708 | * mechanism to report these errors. Just turn on |
| 709 | * ATA_ERR. |
| 710 | */ |
Jeff Garzik | a7dac44 | 2005-10-30 04:44:42 -0500 | [diff] [blame] | 711 | err_mask = AC_ERR_OTHER; |
Tejun Heo | 7d1ce68 | 2005-11-18 14:09:05 +0900 | [diff] [blame] | 712 | sil24_reset_controller(ap); |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 713 | } |
| 714 | |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 715 | if (qc) { |
| 716 | qc->err_mask |= err_mask; |
| 717 | ata_qc_complete(qc); |
| 718 | } |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 719 | } |
| 720 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 721 | static inline void sil24_host_intr(struct ata_port *ap) |
| 722 | { |
| 723 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 724 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 725 | u32 slot_stat; |
| 726 | |
| 727 | slot_stat = readl(port + PORT_SLOT_STAT); |
| 728 | if (!(slot_stat & HOST_SSTAT_ATTN)) { |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 729 | struct sil24_port_priv *pp = ap->private_data; |
| 730 | /* |
| 731 | * !HOST_SSAT_ATTN guarantees successful completion, |
| 732 | * so reading back tf registers is unnecessary for |
| 733 | * most commands. TODO: read tf registers for |
| 734 | * commands which require these values on successful |
| 735 | * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER, |
| 736 | * DEVICE RESET and READ PORT MULTIPLIER (any more?). |
| 737 | */ |
| 738 | sil24_update_tf(ap); |
| 739 | |
Albert Lee | a22e2eb | 2005-12-05 15:38:02 +0800 | [diff] [blame] | 740 | if (qc) { |
| 741 | qc->err_mask |= ac_err_mask(pp->tf.command); |
| 742 | ata_qc_complete(qc); |
| 743 | } |
Tejun Heo | 8746618 | 2005-08-17 13:08:57 +0900 | [diff] [blame] | 744 | } else |
| 745 | sil24_error_intr(ap, slot_stat); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 746 | } |
| 747 | |
| 748 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) |
| 749 | { |
| 750 | struct ata_host_set *host_set = dev_instance; |
| 751 | struct sil24_host_priv *hpriv = host_set->private_data; |
| 752 | unsigned handled = 0; |
| 753 | u32 status; |
| 754 | int i; |
| 755 | |
| 756 | status = readl(hpriv->host_base + HOST_IRQ_STAT); |
| 757 | |
Tejun Heo | 06460ae | 2005-08-17 13:08:52 +0900 | [diff] [blame] | 758 | if (status == 0xffffffff) { |
| 759 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " |
| 760 | "PCI fault or device removal?\n"); |
| 761 | goto out; |
| 762 | } |
| 763 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 764 | if (!(status & IRQ_STAT_4PORTS)) |
| 765 | goto out; |
| 766 | |
| 767 | spin_lock(&host_set->lock); |
| 768 | |
| 769 | for (i = 0; i < host_set->n_ports; i++) |
| 770 | if (status & (1 << i)) { |
| 771 | struct ata_port *ap = host_set->ports[i]; |
Tejun Heo | 3cc4571 | 2005-08-17 13:08:47 +0900 | [diff] [blame] | 772 | if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) { |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 773 | sil24_host_intr(host_set->ports[i]); |
Tejun Heo | 3cc4571 | 2005-08-17 13:08:47 +0900 | [diff] [blame] | 774 | handled++; |
| 775 | } else |
| 776 | printk(KERN_ERR DRV_NAME |
| 777 | ": interrupt from disabled port %d\n", i); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 778 | } |
| 779 | |
| 780 | spin_unlock(&host_set->lock); |
| 781 | out: |
| 782 | return IRQ_RETVAL(handled); |
| 783 | } |
| 784 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 785 | static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev) |
| 786 | { |
| 787 | const size_t cb_size = sizeof(*pp->cmd_block); |
| 788 | |
| 789 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); |
| 790 | } |
| 791 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 792 | static int sil24_port_start(struct ata_port *ap) |
| 793 | { |
| 794 | struct device *dev = ap->host_set->dev; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 795 | struct sil24_port_priv *pp; |
Tejun Heo | 69ad185 | 2005-11-18 14:16:45 +0900 | [diff] [blame] | 796 | union sil24_cmd_block *cb; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 797 | size_t cb_size = sizeof(*cb); |
| 798 | dma_addr_t cb_dma; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 799 | int rc = -ENOMEM; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 800 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 801 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 802 | if (!pp) |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 803 | goto err_out; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 804 | |
Tejun Heo | 6a575fa | 2005-10-06 11:43:39 +0900 | [diff] [blame] | 805 | pp->tf.command = ATA_DRDY; |
| 806 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 807 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 808 | if (!cb) |
| 809 | goto err_out_pp; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 810 | memset(cb, 0, cb_size); |
| 811 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 812 | rc = ata_pad_alloc(ap, dev); |
| 813 | if (rc) |
| 814 | goto err_out_pad; |
| 815 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 816 | pp->cmd_block = cb; |
| 817 | pp->cmd_block_dma = cb_dma; |
| 818 | |
| 819 | ap->private_data = pp; |
| 820 | |
| 821 | return 0; |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 822 | |
| 823 | err_out_pad: |
| 824 | sil24_cblk_free(pp, dev); |
| 825 | err_out_pp: |
| 826 | kfree(pp); |
| 827 | err_out: |
| 828 | return rc; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 829 | } |
| 830 | |
| 831 | static void sil24_port_stop(struct ata_port *ap) |
| 832 | { |
| 833 | struct device *dev = ap->host_set->dev; |
| 834 | struct sil24_port_priv *pp = ap->private_data; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 835 | |
Jeff Garzik | 6037d6b | 2005-11-04 22:08:00 -0500 | [diff] [blame] | 836 | sil24_cblk_free(pp, dev); |
Tejun Heo | e9c05af | 2005-11-14 00:24:18 +0900 | [diff] [blame] | 837 | ata_pad_free(ap, dev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 838 | kfree(pp); |
| 839 | } |
| 840 | |
| 841 | static void sil24_host_stop(struct ata_host_set *host_set) |
| 842 | { |
| 843 | struct sil24_host_priv *hpriv = host_set->private_data; |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 844 | struct pci_dev *pdev = to_pci_dev(host_set->dev); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 845 | |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 846 | pci_iounmap(pdev, hpriv->host_base); |
| 847 | pci_iounmap(pdev, hpriv->port_base); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 848 | kfree(hpriv); |
| 849 | } |
| 850 | |
| 851 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 852 | { |
| 853 | static int printed_version = 0; |
| 854 | unsigned int board_id = (unsigned int)ent->driver_data; |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 855 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 856 | struct ata_probe_ent *probe_ent = NULL; |
| 857 | struct sil24_host_priv *hpriv = NULL; |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 858 | void __iomem *host_base = NULL; |
| 859 | void __iomem *port_base = NULL; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 860 | int i, rc; |
| 861 | |
| 862 | if (!printed_version++) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 863 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 864 | |
| 865 | rc = pci_enable_device(pdev); |
| 866 | if (rc) |
| 867 | return rc; |
| 868 | |
| 869 | rc = pci_request_regions(pdev, DRV_NAME); |
| 870 | if (rc) |
| 871 | goto out_disable; |
| 872 | |
| 873 | rc = -ENOMEM; |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 874 | /* map mmio registers */ |
| 875 | host_base = pci_iomap(pdev, 0, 0); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 876 | if (!host_base) |
| 877 | goto out_free; |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 878 | port_base = pci_iomap(pdev, 2, 0); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 879 | if (!port_base) |
| 880 | goto out_free; |
| 881 | |
| 882 | /* allocate & init probe_ent and hpriv */ |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 883 | probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 884 | if (!probe_ent) |
| 885 | goto out_free; |
| 886 | |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 887 | hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 888 | if (!hpriv) |
| 889 | goto out_free; |
| 890 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 891 | probe_ent->dev = pci_dev_to_dev(pdev); |
| 892 | INIT_LIST_HEAD(&probe_ent->node); |
| 893 | |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 894 | probe_ent->sht = pinfo->sht; |
| 895 | probe_ent->host_flags = pinfo->host_flags; |
| 896 | probe_ent->pio_mask = pinfo->pio_mask; |
Tejun Heo | fbfda6e | 2006-03-05 23:03:42 +0900 | [diff] [blame] | 897 | probe_ent->mwdma_mask = pinfo->mwdma_mask; |
Tejun Heo | 042c21f | 2005-10-09 09:35:46 -0400 | [diff] [blame] | 898 | probe_ent->udma_mask = pinfo->udma_mask; |
| 899 | probe_ent->port_ops = pinfo->port_ops; |
| 900 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 901 | |
| 902 | probe_ent->irq = pdev->irq; |
| 903 | probe_ent->irq_flags = SA_SHIRQ; |
| 904 | probe_ent->mmio_base = port_base; |
| 905 | probe_ent->private_data = hpriv; |
| 906 | |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 907 | hpriv->host_base = host_base; |
| 908 | hpriv->port_base = port_base; |
| 909 | |
| 910 | /* |
| 911 | * Configure the device |
| 912 | */ |
| 913 | /* |
| 914 | * FIXME: This device is certainly 64-bit capable. We just |
| 915 | * don't know how to use it. After fixing 32bit activation in |
| 916 | * this function, enable 64bit masks here. |
| 917 | */ |
| 918 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
| 919 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 920 | dev_printk(KERN_ERR, &pdev->dev, |
| 921 | "32-bit DMA enable failed\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 922 | goto out_free; |
| 923 | } |
| 924 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); |
| 925 | if (rc) { |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 926 | dev_printk(KERN_ERR, &pdev->dev, |
| 927 | "32-bit consistent DMA enable failed\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 928 | goto out_free; |
| 929 | } |
| 930 | |
| 931 | /* GPIO off */ |
| 932 | writel(0, host_base + HOST_FLASH_CMD); |
| 933 | |
| 934 | /* Mask interrupts during initialization */ |
| 935 | writel(0, host_base + HOST_CTRL); |
| 936 | |
| 937 | for (i = 0; i < probe_ent->n_ports; i++) { |
Al Viro | 4b4a5ea | 2005-10-29 06:38:44 +0100 | [diff] [blame] | 938 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 939 | unsigned long portu = (unsigned long)port; |
| 940 | u32 tmp; |
| 941 | int cnt; |
| 942 | |
Tejun Heo | 4f50c3c | 2005-08-17 13:09:07 +0900 | [diff] [blame] | 943 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 944 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
| 945 | |
| 946 | ata_std_ports(&probe_ent->port[i]); |
| 947 | |
| 948 | /* Initial PHY setting */ |
| 949 | writel(0x20c, port + PORT_PHY_CFG); |
| 950 | |
| 951 | /* Clear port RST */ |
| 952 | tmp = readl(port + PORT_CTRL_STAT); |
| 953 | if (tmp & PORT_CS_PORT_RST) { |
| 954 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); |
| 955 | readl(port + PORT_CTRL_STAT); /* sync */ |
| 956 | for (cnt = 0; cnt < 10; cnt++) { |
| 957 | msleep(10); |
| 958 | tmp = readl(port + PORT_CTRL_STAT); |
| 959 | if (!(tmp & PORT_CS_PORT_RST)) |
| 960 | break; |
| 961 | } |
| 962 | if (tmp & PORT_CS_PORT_RST) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 963 | dev_printk(KERN_ERR, &pdev->dev, |
| 964 | "failed to clear port RST\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 965 | } |
| 966 | |
| 967 | /* Zero error counters. */ |
| 968 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); |
| 969 | writel(0x8000, port + PORT_CRC_ERR_THRESH); |
| 970 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); |
| 971 | writel(0x0000, port + PORT_DECODE_ERR_CNT); |
| 972 | writel(0x0000, port + PORT_CRC_ERR_CNT); |
| 973 | writel(0x0000, port + PORT_HSHK_ERR_CNT); |
| 974 | |
| 975 | /* FIXME: 32bit activation? */ |
| 976 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); |
| 977 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); |
| 978 | |
| 979 | /* Configure interrupts */ |
| 980 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); |
| 981 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS, |
| 982 | port + PORT_IRQ_ENABLE_SET); |
| 983 | |
| 984 | /* Clear interrupts */ |
| 985 | writel(0x0fff0fff, port + PORT_IRQ_STAT); |
| 986 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); |
Tejun Heo | 923f122 | 2005-09-13 13:21:29 +0900 | [diff] [blame] | 987 | |
| 988 | /* Clear port multiplier enable and resume bits */ |
| 989 | writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); |
| 990 | |
| 991 | /* Reset itself */ |
| 992 | if (__sil24_reset_controller(port)) |
Jeff Garzik | a9524a7 | 2005-10-30 14:39:11 -0500 | [diff] [blame] | 993 | dev_printk(KERN_ERR, &pdev->dev, |
| 994 | "failed to reset controller\n"); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 995 | } |
| 996 | |
| 997 | /* Turn on interrupts */ |
| 998 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); |
| 999 | |
| 1000 | pci_set_master(pdev); |
| 1001 | |
Tejun Heo | 1483467 | 2005-08-17 13:08:42 +0900 | [diff] [blame] | 1002 | /* FIXME: check ata_device_add return value */ |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1003 | ata_device_add(probe_ent); |
| 1004 | |
| 1005 | kfree(probe_ent); |
| 1006 | return 0; |
| 1007 | |
| 1008 | out_free: |
| 1009 | if (host_base) |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 1010 | pci_iounmap(pdev, host_base); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1011 | if (port_base) |
Jeff Garzik | 142877b | 2006-03-22 23:30:34 -0500 | [diff] [blame] | 1012 | pci_iounmap(pdev, port_base); |
Tejun Heo | edb3366 | 2005-07-28 10:36:22 +0900 | [diff] [blame] | 1013 | kfree(probe_ent); |
| 1014 | kfree(hpriv); |
| 1015 | pci_release_regions(pdev); |
| 1016 | out_disable: |
| 1017 | pci_disable_device(pdev); |
| 1018 | return rc; |
| 1019 | } |
| 1020 | |
| 1021 | static int __init sil24_init(void) |
| 1022 | { |
| 1023 | return pci_module_init(&sil24_pci_driver); |
| 1024 | } |
| 1025 | |
| 1026 | static void __exit sil24_exit(void) |
| 1027 | { |
| 1028 | pci_unregister_driver(&sil24_pci_driver); |
| 1029 | } |
| 1030 | |
| 1031 | MODULE_AUTHOR("Tejun Heo"); |
| 1032 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); |
| 1033 | MODULE_LICENSE("GPL"); |
| 1034 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); |
| 1035 | |
| 1036 | module_init(sil24_init); |
| 1037 | module_exit(sil24_exit); |