blob: 574aba0eba4e0c64d2c6eb13ee4c2119c0ef1873 [file] [log] [blame]
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +02001/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -030021#include <linux/irqchip/chained_irq.h>
Thomas Petazzonid7df84b2014-04-14 15:54:02 +020022#include <linux/cpu.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020023#include <linux/io.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020026#include <linux/of_pci.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020027#include <linux/irqdomain.h>
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020028#include <linux/slab.h>
29#include <linux/msi.h>
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020030#include <asm/mach/arch.h>
31#include <asm/exception.h>
Gregory CLEMENT344e8732012-08-02 11:19:12 +030032#include <asm/smp_plat.h>
Thomas Petazzoni9339d432013-04-09 23:26:15 +020033#include <asm/mach/irq.h>
34
35#include "irqchip.h"
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020036
37/* Interrupt Controller Registers Map */
38#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
39#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
40
Ben Dooksf3e16cc2012-06-04 18:50:12 +020041#define ARMADA_370_XP_INT_CONTROL (0x00)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020042#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
43#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010044#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +000045#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020046
47#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -030048#define ARMADA_375_PPI_CAUSE (0x10)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020049
Gregory CLEMENT344e8732012-08-02 11:19:12 +030050#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x4)
51#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0xc)
52#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x8)
53
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010054#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
55
Gregory CLEMENT7f23f622013-03-20 16:09:35 +010056#define ARMADA_370_XP_TIMER0_PER_CPU_IRQ (5)
57
Thomas Petazzoni5ec69012013-04-09 23:26:17 +020058#define IPI_DOORBELL_START (0)
59#define IPI_DOORBELL_END (8)
60#define IPI_DOORBELL_MASK 0xFF
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020061#define PCI_MSI_DOORBELL_START (16)
62#define PCI_MSI_DOORBELL_NR (16)
63#define PCI_MSI_DOORBELL_END (32)
64#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
Gregory CLEMENT344e8732012-08-02 11:19:12 +030065
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020066static void __iomem *per_cpu_int_base;
67static void __iomem *main_int_base;
68static struct irq_domain *armada_370_xp_mpic_domain;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +020069#ifdef CONFIG_PCI_MSI
70static struct irq_domain *armada_370_xp_msi_domain;
71static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
72static DEFINE_MUTEX(msi_used_lock);
73static phys_addr_t msi_doorbell_addr;
74#endif
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020075
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010076/*
77 * In SMP mode:
78 * For shared global interrupts, mask/unmask global enable bit
Marek Belisko097ef182013-03-15 23:34:04 +010079 * For CPU interrupts, mask/unmask the calling CPU's bit
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010080 */
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020081static void armada_370_xp_irq_mask(struct irq_data *d)
82{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010083 irq_hw_number_t hwirq = irqd_to_hwirq(d);
84
Gregory CLEMENT7f23f622013-03-20 16:09:35 +010085 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010086 writel(hwirq, main_int_base +
87 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
88 else
89 writel(hwirq, per_cpu_int_base +
90 ARMADA_370_XP_INT_SET_MASK_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +020091}
92
93static void armada_370_xp_irq_unmask(struct irq_data *d)
94{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010095 irq_hw_number_t hwirq = irqd_to_hwirq(d);
96
Gregory CLEMENT7f23f622013-03-20 16:09:35 +010097 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
Gregory CLEMENT3202bf02012-12-05 21:43:23 +010098 writel(hwirq, main_int_base +
99 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
100 else
101 writel(hwirq, per_cpu_int_base +
102 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200103}
104
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200105#ifdef CONFIG_PCI_MSI
106
107static int armada_370_xp_alloc_msi(void)
108{
109 int hwirq;
110
111 mutex_lock(&msi_used_lock);
112 hwirq = find_first_zero_bit(&msi_used, PCI_MSI_DOORBELL_NR);
113 if (hwirq >= PCI_MSI_DOORBELL_NR)
114 hwirq = -ENOSPC;
115 else
116 set_bit(hwirq, msi_used);
117 mutex_unlock(&msi_used_lock);
118
119 return hwirq;
120}
121
122static void armada_370_xp_free_msi(int hwirq)
123{
124 mutex_lock(&msi_used_lock);
125 if (!test_bit(hwirq, msi_used))
126 pr_err("trying to free unused MSI#%d\n", hwirq);
127 else
128 clear_bit(hwirq, msi_used);
129 mutex_unlock(&msi_used_lock);
130}
131
132static int armada_370_xp_setup_msi_irq(struct msi_chip *chip,
133 struct pci_dev *pdev,
134 struct msi_desc *desc)
135{
136 struct msi_msg msg;
Thomas Petazzonida343fc2014-04-18 14:19:47 +0200137 int virq, hwirq;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200138
139 hwirq = armada_370_xp_alloc_msi();
140 if (hwirq < 0)
141 return hwirq;
142
143 virq = irq_create_mapping(armada_370_xp_msi_domain, hwirq);
144 if (!virq) {
145 armada_370_xp_free_msi(hwirq);
146 return -EINVAL;
147 }
148
149 irq_set_msi_desc(virq, desc);
150
151 msg.address_lo = msi_doorbell_addr;
152 msg.address_hi = 0;
153 msg.data = 0xf00 | (hwirq + 16);
154
155 write_msi_msg(virq, &msg);
156 return 0;
157}
158
159static void armada_370_xp_teardown_msi_irq(struct msi_chip *chip,
160 unsigned int irq)
161{
162 struct irq_data *d = irq_get_irq_data(irq);
Neil Greatorexff3c6642014-04-18 14:19:49 +0200163 unsigned long hwirq = d->hwirq;
164
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200165 irq_dispose_mapping(irq);
Neil Greatorexff3c6642014-04-18 14:19:49 +0200166 armada_370_xp_free_msi(hwirq);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200167}
168
Thomas Petazzoni830cbe42014-04-18 14:19:48 +0200169static int armada_370_xp_check_msi_device(struct msi_chip *chip, struct pci_dev *dev,
170 int nvec, int type)
171{
172 /* We support MSI, but not MSI-X */
173 if (type == PCI_CAP_ID_MSI)
174 return 0;
175 return -EINVAL;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200176}
177
178static struct irq_chip armada_370_xp_msi_irq_chip = {
179 .name = "armada_370_xp_msi_irq",
180 .irq_enable = unmask_msi_irq,
181 .irq_disable = mask_msi_irq,
182 .irq_mask = mask_msi_irq,
183 .irq_unmask = unmask_msi_irq,
184};
185
186static int armada_370_xp_msi_map(struct irq_domain *domain, unsigned int virq,
187 irq_hw_number_t hw)
188{
189 irq_set_chip_and_handler(virq, &armada_370_xp_msi_irq_chip,
190 handle_simple_irq);
191 set_irq_flags(virq, IRQF_VALID);
192
193 return 0;
194}
195
196static const struct irq_domain_ops armada_370_xp_msi_irq_ops = {
197 .map = armada_370_xp_msi_map,
198};
199
200static int armada_370_xp_msi_init(struct device_node *node,
201 phys_addr_t main_int_phys_base)
202{
203 struct msi_chip *msi_chip;
204 u32 reg;
205 int ret;
206
207 msi_doorbell_addr = main_int_phys_base +
208 ARMADA_370_XP_SW_TRIG_INT_OFFS;
209
210 msi_chip = kzalloc(sizeof(*msi_chip), GFP_KERNEL);
211 if (!msi_chip)
212 return -ENOMEM;
213
214 msi_chip->setup_irq = armada_370_xp_setup_msi_irq;
215 msi_chip->teardown_irq = armada_370_xp_teardown_msi_irq;
Thomas Petazzoni830cbe42014-04-18 14:19:48 +0200216 msi_chip->check_device = armada_370_xp_check_msi_device;
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200217 msi_chip->of_node = node;
218
219 armada_370_xp_msi_domain =
220 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
221 &armada_370_xp_msi_irq_ops,
222 NULL);
223 if (!armada_370_xp_msi_domain) {
224 kfree(msi_chip);
225 return -ENOMEM;
226 }
227
228 ret = of_pci_msi_chip_add(msi_chip);
229 if (ret < 0) {
230 irq_domain_remove(armada_370_xp_msi_domain);
231 kfree(msi_chip);
232 return ret;
233 }
234
235 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
236 | PCI_MSI_DOORBELL_MASK;
237
238 writel(reg, per_cpu_int_base +
239 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
240
241 /* Unmask IPI interrupt */
242 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
243
244 return 0;
245}
246#else
247static inline int armada_370_xp_msi_init(struct device_node *node,
248 phys_addr_t main_int_phys_base)
249{
250 return 0;
251}
252#endif
253
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300254#ifdef CONFIG_SMP
Arnaud Ebalard19e61d42014-01-20 22:52:05 +0100255static DEFINE_RAW_SPINLOCK(irq_controller_lock);
256
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300257static int armada_xp_set_affinity(struct irq_data *d,
258 const struct cpumask *mask_val, bool force)
259{
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100260 irq_hw_number_t hwirq = irqd_to_hwirq(d);
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000261 unsigned long reg, mask;
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100262 int cpu;
263
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000264 /* Select a single core from the affinity mask which is online */
265 cpu = cpumask_any_and(mask_val, cpu_online_mask);
266 mask = 1UL << cpu_logical_map(cpu);
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100267
268 raw_spin_lock(&irq_controller_lock);
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100269 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
Thomas Gleixner8cc3cfc2014-03-04 20:43:41 +0000270 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100271 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
Gregory CLEMENT3202bf02012-12-05 21:43:23 +0100272 raw_spin_unlock(&irq_controller_lock);
273
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300274 return 0;
275}
276#endif
277
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200278static struct irq_chip armada_370_xp_irq_chip = {
279 .name = "armada_370_xp_irq",
280 .irq_mask = armada_370_xp_irq_mask,
281 .irq_mask_ack = armada_370_xp_irq_mask,
282 .irq_unmask = armada_370_xp_irq_unmask,
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300283#ifdef CONFIG_SMP
284 .irq_set_affinity = armada_xp_set_affinity,
285#endif
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200286};
287
288static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
289 unsigned int virq, irq_hw_number_t hw)
290{
291 armada_370_xp_irq_mask(irq_get_irq_data(virq));
Gregory CLEMENT600468d2013-04-05 14:32:52 +0200292 if (hw != ARMADA_370_XP_TIMER0_PER_CPU_IRQ)
293 writel(hw, per_cpu_int_base +
294 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
295 else
296 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200297 irq_set_status_flags(virq, IRQ_LEVEL);
Gregory CLEMENT3a6f08a2013-01-25 18:32:41 +0100298
Gregory CLEMENT7f23f622013-03-20 16:09:35 +0100299 if (hw == ARMADA_370_XP_TIMER0_PER_CPU_IRQ) {
Gregory CLEMENT3a6f08a2013-01-25 18:32:41 +0100300 irq_set_percpu_devid(virq);
301 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
302 handle_percpu_devid_irq);
303
304 } else {
305 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
306 handle_level_irq);
307 }
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200308 set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
309
310 return 0;
311}
312
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300313#ifdef CONFIG_SMP
Thomas Petazzonief37d332014-04-14 15:54:01 +0200314static void armada_mpic_send_doorbell(const struct cpumask *mask,
315 unsigned int irq)
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300316{
317 int cpu;
318 unsigned long map = 0;
319
320 /* Convert our logical CPU mask into a physical one. */
321 for_each_cpu(cpu, mask)
322 map |= 1 << cpu_logical_map(cpu);
323
324 /*
325 * Ensure that stores to Normal memory are visible to the
326 * other CPUs before issuing the IPI.
327 */
328 dsb();
329
330 /* submit softirq */
331 writel((map << 8) | irq, main_int_base +
332 ARMADA_370_XP_SW_TRIG_INT_OFFS);
333}
334
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200335static void armada_xp_mpic_smp_cpu_init(void)
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300336{
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200337 u32 control;
338 int nr_irqs, i;
339
340 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
341 nr_irqs = (control >> 2) & 0x3ff;
342
343 for (i = 0; i < nr_irqs; i++)
344 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
345
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300346 /* Clear pending IPIs */
347 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
348
349 /* Enable first 8 IPIs */
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200350 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300351 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
352
353 /* Unmask IPI interrupt */
354 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
355}
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200356
357static int armada_xp_mpic_secondary_init(struct notifier_block *nfb,
358 unsigned long action, void *hcpu)
359{
360 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
361 armada_xp_mpic_smp_cpu_init();
362 return NOTIFY_OK;
363}
364
365static struct notifier_block armada_370_xp_mpic_cpu_notifier = {
366 .notifier_call = armada_xp_mpic_secondary_init,
367 .priority = 100,
368};
369
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300370#endif /* CONFIG_SMP */
371
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200372static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
373 .map = armada_370_xp_mpic_irq_map,
374 .xlate = irq_domain_xlate_onecell,
375};
376
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300377#ifdef CONFIG_PCI_MSI
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300378static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300379{
380 u32 msimask, msinr;
381
382 msimask = readl_relaxed(per_cpu_int_base +
383 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
384 & PCI_MSI_DOORBELL_MASK;
385
386 writel(~msimask, per_cpu_int_base +
387 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
388
389 for (msinr = PCI_MSI_DOORBELL_START;
390 msinr < PCI_MSI_DOORBELL_END; msinr++) {
391 int irq;
392
393 if (!(msimask & BIT(msinr)))
394 continue;
395
396 irq = irq_find_mapping(armada_370_xp_msi_domain,
397 msinr - 16);
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300398
399 if (is_chained)
400 generic_handle_irq(irq);
401 else
402 handle_IRQ(irq, regs);
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300403 }
404}
405#else
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300406static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300407#endif
408
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300409static void armada_370_xp_mpic_handle_cascade_irq(unsigned int irq,
410 struct irq_desc *desc)
411{
412 struct irq_chip *chip = irq_get_chip(irq);
413 unsigned long irqmap, irqn;
414 unsigned int cascade_irq;
415
416 chained_irq_enter(chip, desc);
417
418 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
419
420 if (irqmap & BIT(0)) {
421 armada_370_xp_handle_msi_irq(NULL, true);
422 irqmap &= ~BIT(0);
423 }
424
425 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
426 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
427 generic_handle_irq(cascade_irq);
428 }
429
430 chained_irq_exit(chip, desc);
431}
432
Stephen Boyd8783dd32014-03-04 16:40:30 -0800433static void __exception_irq_entry
Thomas Petazzoni9339d432013-04-09 23:26:15 +0200434armada_370_xp_handle_irq(struct pt_regs *regs)
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200435{
436 u32 irqstat, irqnr;
437
438 do {
439 irqstat = readl_relaxed(per_cpu_int_base +
440 ARMADA_370_XP_CPU_INTACK_OFFS);
441 irqnr = irqstat & 0x3FF;
442
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300443 if (irqnr > 1022)
444 break;
445
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200446 if (irqnr > 1) {
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300447 irqnr = irq_find_mapping(armada_370_xp_mpic_domain,
448 irqnr);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200449 handle_IRQ(irqnr, regs);
450 continue;
451 }
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200452
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200453 /* MSI handling */
Ezequiel Garcia9b8cf772014-02-10 17:00:01 -0300454 if (irqnr == 1)
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300455 armada_370_xp_handle_msi_irq(regs, false);
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200456
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300457#ifdef CONFIG_SMP
458 /* IPI Handling */
459 if (irqnr == 0) {
460 u32 ipimask, ipinr;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200461
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300462 ipimask = readl_relaxed(per_cpu_int_base +
463 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200464 & IPI_DOORBELL_MASK;
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300465
Lior Amsalema6f089e2013-11-25 17:26:44 +0100466 writel(~ipimask, per_cpu_int_base +
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300467 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
468
469 /* Handle all pending doorbells */
Thomas Petazzoni5ec69012013-04-09 23:26:17 +0200470 for (ipinr = IPI_DOORBELL_START;
471 ipinr < IPI_DOORBELL_END; ipinr++) {
Gregory CLEMENT344e8732012-08-02 11:19:12 +0300472 if (ipimask & (0x1 << ipinr))
473 handle_IPI(ipinr, regs);
474 }
475 continue;
476 }
477#endif
478
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200479 } while (1);
480}
481
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200482static int __init armada_370_xp_mpic_of_init(struct device_node *node,
483 struct device_node *parent)
484{
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200485 struct resource main_int_res, per_cpu_int_res;
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200486 int parent_irq, nr_irqs, i;
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200487 u32 control;
488
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200489 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
490 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200491
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200492 BUG_ON(!request_mem_region(main_int_res.start,
493 resource_size(&main_int_res),
494 node->full_name));
495 BUG_ON(!request_mem_region(per_cpu_int_res.start,
496 resource_size(&per_cpu_int_res),
497 node->full_name));
498
499 main_int_base = ioremap(main_int_res.start,
500 resource_size(&main_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200501 BUG_ON(!main_int_base);
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200502
503 per_cpu_int_base = ioremap(per_cpu_int_res.start,
504 resource_size(&per_cpu_int_res));
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200505 BUG_ON(!per_cpu_int_base);
Gregory CLEMENTd792b1e2012-09-26 18:02:48 +0200506
507 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200508 nr_irqs = (control >> 2) & 0x3ff;
509
510 for (i = 0; i < nr_irqs; i++)
511 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
Gregory CLEMENTd792b1e2012-09-26 18:02:48 +0200512
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200513 armada_370_xp_mpic_domain =
Thomas Petazzonib73842b2014-05-30 22:18:18 +0200514 irq_domain_add_linear(node, nr_irqs,
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200515 &armada_370_xp_mpic_irq_ops, NULL);
516
Thomas Petazzoni627dfcc2013-08-09 22:27:10 +0200517 BUG_ON(!armada_370_xp_mpic_domain);
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200518
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200519#ifdef CONFIG_SMP
520 armada_xp_mpic_smp_cpu_init();
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200521#endif
522
Thomas Petazzoni31f614e2013-08-09 22:27:11 +0200523 armada_370_xp_msi_init(node, main_int_res.start);
524
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300525 parent_irq = irq_of_parse_and_map(node, 0);
526 if (parent_irq <= 0) {
527 irq_set_default_host(armada_370_xp_mpic_domain);
528 set_handle_irq(armada_370_xp_handle_irq);
Thomas Petazzonief37d332014-04-14 15:54:01 +0200529#ifdef CONFIG_SMP
530 set_smp_cross_call(armada_mpic_send_doorbell);
Thomas Petazzonid7df84b2014-04-14 15:54:02 +0200531 register_cpu_notifier(&armada_370_xp_mpic_cpu_notifier);
Thomas Petazzonief37d332014-04-14 15:54:01 +0200532#endif
Ezequiel Garciabc69b8a2014-02-10 17:00:02 -0300533 } else {
534 irq_set_chained_handler(parent_irq,
535 armada_370_xp_mpic_handle_cascade_irq);
536 }
Thomas Petazzonib313ada2013-04-09 23:26:16 +0200537
Thomas Petazzoni9ae6f742012-06-13 19:01:28 +0200538 return 0;
539}
540
Thomas Petazzoni9339d432013-04-09 23:26:15 +0200541IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);