blob: 473f09a74d4d4c53f80777f3173753e89d82b33e [file] [log] [blame]
Russell Kingfa0fe482006-01-13 21:30:48 +00001/*
2 * linux/arch/arm/common/vic.c
3 *
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
Hartley Sweetenbb06b732010-01-12 19:09:12 +010021
Jamie Ilesf9b28cc2011-09-27 11:00:46 +010022#include <linux/export.h>
Russell Kingfa0fe482006-01-13 21:30:48 +000023#include <linux/init.h>
24#include <linux/list.h>
Russell Kingfced80c2008-09-06 12:10:45 +010025#include <linux/io.h>
Olof Johanssonbc895b52013-04-02 15:07:37 -070026#include <linux/irq.h>
Jamie Ilesf9b28cc2011-09-27 11:00:46 +010027#include <linux/irqdomain.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/of_irq.h>
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +020031#include <linux/syscore_ops.h>
Linus Walleij59fcf482009-09-14 12:25:34 +010032#include <linux/device.h>
Linus Walleijf17a1f02009-08-04 01:01:02 +010033#include <linux/amba/bus.h>
Rob Herring9e47b8b2013-01-07 09:45:59 -060034#include <linux/irqchip/arm-vic.h>
Russell Kingfa0fe482006-01-13 21:30:48 +000035
Jamie Iles15583682011-09-28 09:40:11 +010036#include <asm/exception.h>
Catalin Marinasf36a3bb12013-01-18 15:20:06 +000037#include <asm/irq.h>
Russell Kingfa0fe482006-01-13 21:30:48 +000038
Rob Herring44430ec2012-10-27 17:25:26 -050039#include "irqchip.h"
40
Rob Herringcf21af52012-11-06 13:14:26 -060041#define VIC_IRQ_STATUS 0x00
42#define VIC_FIQ_STATUS 0x04
43#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
44#define VIC_INT_SOFT 0x18
45#define VIC_INT_SOFT_CLEAR 0x1c
46#define VIC_PROTECT 0x20
47#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
48#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
49
50#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
51#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
52#define VIC_ITCR 0x300 /* VIC test control register */
53
54#define VIC_VECT_CNTL_ENABLE (1 << 5)
55
56#define VIC_PL192_VECT_ADDR 0xF00
57
Ben Dooksc07f87f2009-03-24 15:30:07 +000058/**
59 * struct vic_device - VIC PM device
Ben Dooksc07f87f2009-03-24 15:30:07 +000060 * @irq: The IRQ number for the base of the VIC.
61 * @base: The register base for the VIC.
Linus Walleijce94df92012-04-20 08:02:36 +010062 * @valid_sources: A bitmask of valid interrupts
Ben Dooksc07f87f2009-03-24 15:30:07 +000063 * @resume_sources: A bitmask of interrupts for resume.
64 * @resume_irqs: The IRQs enabled for resume.
65 * @int_select: Save for VIC_INT_SELECT.
66 * @int_enable: Save for VIC_INT_ENABLE.
67 * @soft_int: Save for VIC_INT_SOFT.
68 * @protect: Save for VIC_PROTECT.
Jamie Ilesf9b28cc2011-09-27 11:00:46 +010069 * @domain: The IRQ domain for the VIC.
Ben Dooksc07f87f2009-03-24 15:30:07 +000070 */
71struct vic_device {
Ben Dooksc07f87f2009-03-24 15:30:07 +000072 void __iomem *base;
73 int irq;
Linus Walleijce94df92012-04-20 08:02:36 +010074 u32 valid_sources;
Ben Dooksc07f87f2009-03-24 15:30:07 +000075 u32 resume_sources;
76 u32 resume_irqs;
77 u32 int_select;
78 u32 int_enable;
79 u32 soft_int;
80 u32 protect;
Grant Likely75294952012-02-14 14:06:57 -070081 struct irq_domain *domain;
Ben Dooksc07f87f2009-03-24 15:30:07 +000082};
83
84/* we cannot allocate memory when VICs are initially registered */
85static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
86
Hartley Sweetenbb06b732010-01-12 19:09:12 +010087static int vic_id;
Ben Dooksc07f87f2009-03-24 15:30:07 +000088
Rob Herringa0368022012-11-05 16:32:29 -060089static void vic_handle_irq(struct pt_regs *regs);
90
Hartley Sweetenbb06b732010-01-12 19:09:12 +010091/**
92 * vic_init2 - common initialisation code
93 * @base: Base of the VIC.
94 *
Uwe Kleine-Königb5950762010-11-01 15:38:34 -040095 * Common initialisation code for registration
Hartley Sweetenbb06b732010-01-12 19:09:12 +010096 * and resume.
97*/
98static void vic_init2(void __iomem *base)
99{
100 int i;
Ben Dooksc07f87f2009-03-24 15:30:07 +0000101
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100102 for (i = 0; i < 16; i++) {
103 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
104 writel(VIC_VECT_CNTL_ENABLE | i, reg);
105 }
106
107 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
108}
109
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +0200110#ifdef CONFIG_PM
111static void resume_one_vic(struct vic_device *vic)
Ben Dooksc07f87f2009-03-24 15:30:07 +0000112{
Ben Dooksc07f87f2009-03-24 15:30:07 +0000113 void __iomem *base = vic->base;
114
115 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
116
117 /* re-initialise static settings */
118 vic_init2(base);
119
120 writel(vic->int_select, base + VIC_INT_SELECT);
121 writel(vic->protect, base + VIC_PROTECT);
122
123 /* set the enabled ints and then clear the non-enabled */
124 writel(vic->int_enable, base + VIC_INT_ENABLE);
125 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
126
127 /* and the same for the soft-int register */
128
129 writel(vic->soft_int, base + VIC_INT_SOFT);
130 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
Ben Dooksc07f87f2009-03-24 15:30:07 +0000131}
132
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +0200133static void vic_resume(void)
Ben Dooksc07f87f2009-03-24 15:30:07 +0000134{
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +0200135 int id;
136
137 for (id = vic_id - 1; id >= 0; id--)
138 resume_one_vic(vic_devices + id);
139}
140
141static void suspend_one_vic(struct vic_device *vic)
142{
Ben Dooksc07f87f2009-03-24 15:30:07 +0000143 void __iomem *base = vic->base;
144
145 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
146
147 vic->int_select = readl(base + VIC_INT_SELECT);
148 vic->int_enable = readl(base + VIC_INT_ENABLE);
149 vic->soft_int = readl(base + VIC_INT_SOFT);
150 vic->protect = readl(base + VIC_PROTECT);
151
152 /* set the interrupts (if any) that are used for
153 * resuming the system */
154
155 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
156 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +0200157}
158
159static int vic_suspend(void)
160{
161 int id;
162
163 for (id = 0; id < vic_id; id++)
164 suspend_one_vic(vic_devices + id);
Ben Dooksc07f87f2009-03-24 15:30:07 +0000165
166 return 0;
167}
168
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +0200169struct syscore_ops vic_syscore_ops = {
170 .suspend = vic_suspend,
171 .resume = vic_resume,
Ben Dooksc07f87f2009-03-24 15:30:07 +0000172};
173
174/**
Ben Dooksc07f87f2009-03-24 15:30:07 +0000175 * vic_pm_init - initicall to register VIC pm
176 *
177 * This is called via late_initcall() to register
178 * the resources for the VICs due to the early
179 * nature of the VIC's registration.
180*/
181static int __init vic_pm_init(void)
182{
Rafael J. Wysocki328f5cc2011-04-22 22:02:33 +0200183 if (vic_id > 0)
184 register_syscore_ops(&vic_syscore_ops);
Ben Dooksc07f87f2009-03-24 15:30:07 +0000185
186 return 0;
187}
Ben Dooksc07f87f2009-03-24 15:30:07 +0000188late_initcall(vic_pm_init);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100189#endif /* CONFIG_PM */
Ben Dooksc07f87f2009-03-24 15:30:07 +0000190
Linus Walleijce94df92012-04-20 08:02:36 +0100191static struct irq_chip vic_chip;
192
193static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
194 irq_hw_number_t hwirq)
195{
196 struct vic_device *v = d->host_data;
197
198 /* Skip invalid IRQs, only register handlers for the real ones */
199 if (!(v->valid_sources & (1 << hwirq)))
Grant Likelyd94ea3f2013-06-06 14:11:38 +0100200 return -EPERM;
Linus Walleijce94df92012-04-20 08:02:36 +0100201 irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
202 irq_set_chip_data(irq, v->base);
203 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
204 return 0;
205}
206
Rob Herringa0368022012-11-05 16:32:29 -0600207/*
208 * Handle each interrupt in a single VIC. Returns non-zero if we've
209 * handled at least one interrupt. This reads the status register
210 * before handling each interrupt, which is necessary given that
211 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
212 */
213static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
214{
215 u32 stat, irq;
216 int handled = 0;
217
218 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
219 irq = ffs(stat) - 1;
220 handle_IRQ(irq_find_mapping(vic->domain, irq), regs);
221 handled = 1;
222 }
223
224 return handled;
225}
226
227/*
228 * Keep iterating over all registered VIC's until there are no pending
229 * interrupts.
230 */
Stephen Boyd8783dd32014-03-04 16:40:30 -0800231static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
Rob Herringa0368022012-11-05 16:32:29 -0600232{
233 int i, handled;
234
235 do {
236 for (i = 0, handled = 0; i < vic_id; ++i)
237 handled |= handle_one_vic(&vic_devices[i], regs);
238 } while (handled);
239}
240
Linus Walleijce94df92012-04-20 08:02:36 +0100241static struct irq_domain_ops vic_irqdomain_ops = {
242 .map = vic_irqdomain_map,
243 .xlate = irq_domain_xlate_onetwocell,
244};
245
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100246/**
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100247 * vic_register() - Register a VIC.
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100248 * @base: The base address of the VIC.
249 * @irq: The base IRQ for the VIC.
Linus Walleijfa943be2012-04-20 08:02:03 +0100250 * @valid_sources: bitmask of valid interrupts
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100251 * @resume_sources: bitmask of interrupts allowed for resume sources.
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100252 * @node: The device tree node associated with the VIC.
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100253 *
254 * Register the VIC with the system device tree so that it can be notified
255 * of suspend and resume requests and ensure that the correct actions are
256 * taken to re-instate the settings on resume.
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100257 *
258 * This also configures the IRQ domain for the VIC.
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100259 */
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100260static void __init vic_register(void __iomem *base, unsigned int irq,
Linus Walleijfa943be2012-04-20 08:02:03 +0100261 u32 valid_sources, u32 resume_sources,
262 struct device_node *node)
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100263{
264 struct vic_device *v;
Linus Walleij5ced33b2012-12-26 01:39:16 +0100265 int i;
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100266
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100267 if (vic_id >= ARRAY_SIZE(vic_devices)) {
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100268 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100269 return;
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100270 }
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100271
272 v = &vic_devices[vic_id];
273 v->base = base;
Linus Walleijce94df92012-04-20 08:02:36 +0100274 v->valid_sources = valid_sources;
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100275 v->resume_sources = resume_sources;
276 v->irq = irq;
Rob Herring7fb7d8a2012-11-20 19:55:27 -0600277 set_handle_irq(vic_handle_irq);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100278 vic_id++;
Linus Walleij07c92492012-10-16 18:50:00 +0100279 v->domain = irq_domain_add_simple(node, fls(valid_sources), irq,
Linus Walleijfa943be2012-04-20 08:02:03 +0100280 &vic_irqdomain_ops, v);
Linus Walleij5ced33b2012-12-26 01:39:16 +0100281 /* create an IRQ mapping for each valid IRQ */
282 for (i = 0; i < fls(valid_sources); i++)
283 if (valid_sources & (1 << i))
284 irq_create_mapping(v->domain, i);
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100285}
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100286
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100287static void vic_ack_irq(struct irq_data *d)
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100288{
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100289 void __iomem *base = irq_data_get_irq_chip_data(d);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100290 unsigned int irq = d->hwirq;
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100291 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
292 /* moreover, clear the soft-triggered, in case it was the reason */
293 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
294}
295
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100296static void vic_mask_irq(struct irq_data *d)
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100297{
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100298 void __iomem *base = irq_data_get_irq_chip_data(d);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100299 unsigned int irq = d->hwirq;
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100300 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
301}
302
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100303static void vic_unmask_irq(struct irq_data *d)
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100304{
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100305 void __iomem *base = irq_data_get_irq_chip_data(d);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100306 unsigned int irq = d->hwirq;
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100307 writel(1 << irq, base + VIC_INT_ENABLE);
308}
309
310#if defined(CONFIG_PM)
Ben Dooksc07f87f2009-03-24 15:30:07 +0000311static struct vic_device *vic_from_irq(unsigned int irq)
312{
313 struct vic_device *v = vic_devices;
314 unsigned int base_irq = irq & ~31;
315 int id;
316
317 for (id = 0; id < vic_id; id++, v++) {
318 if (v->irq == base_irq)
319 return v;
320 }
321
322 return NULL;
323}
324
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100325static int vic_set_wake(struct irq_data *d, unsigned int on)
Ben Dooksc07f87f2009-03-24 15:30:07 +0000326{
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100327 struct vic_device *v = vic_from_irq(d->irq);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100328 unsigned int off = d->hwirq;
Ben Dooks3f1a5672009-06-02 09:31:03 +0100329 u32 bit = 1 << off;
Ben Dooksc07f87f2009-03-24 15:30:07 +0000330
331 if (!v)
332 return -EINVAL;
333
Ben Dooks3f1a5672009-06-02 09:31:03 +0100334 if (!(bit & v->resume_sources))
335 return -EINVAL;
336
Ben Dooksc07f87f2009-03-24 15:30:07 +0000337 if (on)
Ben Dooks3f1a5672009-06-02 09:31:03 +0100338 v->resume_irqs |= bit;
Ben Dooksc07f87f2009-03-24 15:30:07 +0000339 else
Ben Dooks3f1a5672009-06-02 09:31:03 +0100340 v->resume_irqs &= ~bit;
Ben Dooksc07f87f2009-03-24 15:30:07 +0000341
342 return 0;
343}
Ben Dooksc07f87f2009-03-24 15:30:07 +0000344#else
Ben Dooksc07f87f2009-03-24 15:30:07 +0000345#define vic_set_wake NULL
346#endif /* CONFIG_PM */
347
David Brownell38c677c2006-08-01 22:26:25 +0100348static struct irq_chip vic_chip = {
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100349 .name = "VIC",
Lennert Buytenhekf013c982010-11-29 10:20:21 +0100350 .irq_ack = vic_ack_irq,
351 .irq_mask = vic_mask_irq,
352 .irq_unmask = vic_unmask_irq,
353 .irq_set_wake = vic_set_wake,
Russell Kingfa0fe482006-01-13 21:30:48 +0000354};
355
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100356static void __init vic_disable(void __iomem *base)
357{
358 writel(0, base + VIC_INT_SELECT);
359 writel(0, base + VIC_INT_ENABLE);
360 writel(~0, base + VIC_INT_ENABLE_CLEAR);
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100361 writel(0, base + VIC_ITCR);
362 writel(~0, base + VIC_INT_SOFT_CLEAR);
363}
364
365static void __init vic_clear_interrupts(void __iomem *base)
366{
367 unsigned int i;
368
369 writel(0, base + VIC_PL190_VECT_ADDR);
370 for (i = 0; i < 19; i++) {
371 unsigned int value;
372
373 value = readl(base + VIC_PL190_VECT_ADDR);
374 writel(value, base + VIC_PL190_VECT_ADDR);
375 }
376}
377
Alessandro Rubini87e88242009-07-02 15:28:41 +0100378/*
379 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
380 * The original cell has 32 interrupts, while the modified one has 64,
381 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
382 * the probe function is called twice, with base set to offset 000
383 * and 020 within the page. We call this "second block".
384 */
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100385static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
Jamie Ilesad622672011-12-01 11:16:46 +0100386 u32 vic_sources, struct device_node *node)
Alessandro Rubini87e88242009-07-02 15:28:41 +0100387{
388 unsigned int i;
389 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
390
391 /* Disable all interrupts initially. */
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100392 vic_disable(base);
Alessandro Rubini87e88242009-07-02 15:28:41 +0100393
394 /*
395 * Make sure we clear all existing interrupts. The vector registers
396 * in this cell are after the second block of general registers,
397 * so we can address them using standard offsets, but only from
398 * the second base address, which is 0x20 in the page
399 */
400 if (vic_2nd_block) {
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100401 vic_clear_interrupts(base);
Alessandro Rubini87e88242009-07-02 15:28:41 +0100402
Alessandro Rubini87e88242009-07-02 15:28:41 +0100403 /* ST has 16 vectors as well, but we don't enable them by now */
404 for (i = 0; i < 16; i++) {
405 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
406 writel(0, reg);
407 }
408
409 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
410 }
411
Linus Walleijfa943be2012-04-20 08:02:03 +0100412 vic_register(base, irq_start, vic_sources, 0, node);
Alessandro Rubini87e88242009-07-02 15:28:41 +0100413}
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100414
Linus Walleij07c92492012-10-16 18:50:00 +0100415void __init __vic_init(void __iomem *base, int irq_start,
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100416 u32 vic_sources, u32 resume_sources,
417 struct device_node *node)
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100418{
419 unsigned int i;
420 u32 cellid = 0;
421 enum amba_vendor vendor;
422
423 /* Identify which VIC cell this one is, by reading the ID */
424 for (i = 0; i < 4; i++) {
Arnd Bergmannd4f3add2011-09-23 10:13:49 +0200425 void __iomem *addr;
426 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100427 cellid |= (readl(addr) & 0xff) << (8 * i);
428 }
429 vendor = (cellid >> 12) & 0xff;
430 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
431 base, cellid, vendor);
432
433 switch(vendor) {
434 case AMBA_VENDOR_ST:
Jamie Ilesad622672011-12-01 11:16:46 +0100435 vic_init_st(base, irq_start, vic_sources, node);
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100436 return;
437 default:
438 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
439 /* fall through */
440 case AMBA_VENDOR_ARM:
441 break;
442 }
443
444 /* Disable all interrupts initially. */
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100445 vic_disable(base);
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100446
Hartley Sweetenb0c4c892010-04-02 18:04:47 +0100447 /* Make sure we clear all existing interrupts */
448 vic_clear_interrupts(base);
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100449
450 vic_init2(base);
451
Linus Walleijfa943be2012-04-20 08:02:03 +0100452 vic_register(base, irq_start, vic_sources, resume_sources, node);
Hartley Sweetenbb06b732010-01-12 19:09:12 +0100453}
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100454
455/**
456 * vic_init() - initialise a vectored interrupt controller
457 * @base: iomem base address
458 * @irq_start: starting interrupt number, must be muliple of 32
459 * @vic_sources: bitmask of interrupt sources to allow
460 * @resume_sources: bitmask of interrupt sources to allow for resume
461 */
462void __init vic_init(void __iomem *base, unsigned int irq_start,
463 u32 vic_sources, u32 resume_sources)
464{
465 __vic_init(base, irq_start, vic_sources, resume_sources, NULL);
466}
467
468#ifdef CONFIG_OF
469int __init vic_of_init(struct device_node *node, struct device_node *parent)
470{
471 void __iomem *regs;
Tomasz Figa81e9c172013-08-26 02:37:24 +0900472 u32 interrupt_mask = ~0;
473 u32 wakeup_mask = ~0;
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100474
475 if (WARN(parent, "non-root VICs are not supported"))
476 return -EINVAL;
477
478 regs = of_iomap(node, 0);
479 if (WARN_ON(!regs))
480 return -EIO;
481
Tomasz Figa81e9c172013-08-26 02:37:24 +0900482 of_property_read_u32(node, "valid-mask", &interrupt_mask);
483 of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
484
Linus Walleij07c92492012-10-16 18:50:00 +0100485 /*
Linus Walleij5ced33b2012-12-26 01:39:16 +0100486 * Passing 0 as first IRQ makes the simple domain allocate descriptors
Linus Walleij07c92492012-10-16 18:50:00 +0100487 */
Tomasz Figa81e9c172013-08-26 02:37:24 +0900488 __vic_init(regs, 0, interrupt_mask, wakeup_mask, node);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100489
490 return 0;
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100491}
Rob Herring44430ec2012-10-27 17:25:26 -0500492IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
493IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
494IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
Jamie Ilesf9b28cc2011-09-27 11:00:46 +0100495#endif /* CONFIG OF */