blob: e25681ff5a70a290db704ca419e4e5221dbb4045 [file] [log] [blame]
Mythri P K94c52982011-09-08 19:06:21 +05301/*
Archit Tanejaef269582013-09-12 17:45:57 +05302 * HDMI driver definition for TI OMAP4 Processor.
Mythri P K94c52982011-09-08 19:06:21 +05303 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
Archit Tanejaef269582013-09-12 17:45:57 +053019#ifndef _HDMI_H
20#define _HDMI_H
Mythri P K94c52982011-09-08 19:06:21 +053021
Archit Tanejabdb8bfc2013-09-12 18:07:49 +053022#include <linux/delay.h>
23#include <linux/io.h>
Archit Tanejaf382d9e2013-08-06 14:56:55 +053024#include <linux/platform_device.h>
Archit Tanejabdb8bfc2013-09-12 18:07:49 +053025#include <video/omapdss.h>
26
27#include "dss.h"
28
29/* HDMI Wrapper */
30
31#define HDMI_WP_REVISION 0x0
32#define HDMI_WP_SYSCONFIG 0x10
33#define HDMI_WP_IRQSTATUS_RAW 0x24
34#define HDMI_WP_IRQSTATUS 0x28
35#define HDMI_WP_IRQENABLE_SET 0x2C
36#define HDMI_WP_IRQENABLE_CLR 0x30
37#define HDMI_WP_IRQWAKEEN 0x34
38#define HDMI_WP_PWR_CTRL 0x40
39#define HDMI_WP_DEBOUNCE 0x44
40#define HDMI_WP_VIDEO_CFG 0x50
41#define HDMI_WP_VIDEO_SIZE 0x60
42#define HDMI_WP_VIDEO_TIMING_H 0x68
43#define HDMI_WP_VIDEO_TIMING_V 0x6C
Tomi Valkeinen42116512013-10-28 11:47:29 +020044#define HDMI_WP_CLK 0x70
Archit Tanejabdb8bfc2013-09-12 18:07:49 +053045#define HDMI_WP_AUDIO_CFG 0x80
46#define HDMI_WP_AUDIO_CFG2 0x84
47#define HDMI_WP_AUDIO_CTRL 0x88
48#define HDMI_WP_AUDIO_DATA 0x8C
49
Archit Taneja86961312013-09-10 16:34:02 +053050/* HDMI WP IRQ flags */
Tomi Valkeinen6873efe2013-10-28 11:47:28 +020051#define HDMI_IRQ_CORE (1 << 0)
Archit Taneja86961312013-09-10 16:34:02 +053052#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
53#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
54#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
55#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
56#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
57#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
58#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
59#define HDMI_IRQ_LINK_CONNECT (1 << 25)
60#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
61#define HDMI_IRQ_PLL_LOCK (1 << 29)
62#define HDMI_IRQ_PLL_UNLOCK (1 << 30)
63#define HDMI_IRQ_PLL_RECAL (1 << 31)
64
Archit Tanejabdb8bfc2013-09-12 18:07:49 +053065/* HDMI PLL */
66
67#define PLLCTRL_PLL_CONTROL 0x0
68#define PLLCTRL_PLL_STATUS 0x4
69#define PLLCTRL_PLL_GO 0x8
70#define PLLCTRL_CFG1 0xC
71#define PLLCTRL_CFG2 0x10
72#define PLLCTRL_CFG3 0x14
73#define PLLCTRL_SSC_CFG1 0x18
74#define PLLCTRL_SSC_CFG2 0x1C
75#define PLLCTRL_CFG4 0x20
76
77/* HDMI PHY */
78
79#define HDMI_TXPHY_TX_CTRL 0x0
80#define HDMI_TXPHY_DIGITAL_CTRL 0x4
81#define HDMI_TXPHY_POWER_CTRL 0x8
82#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
Archit Tanejaf382d9e2013-08-06 14:56:55 +053083
Mythri P K94c52982011-09-08 19:06:21 +053084enum hdmi_pll_pwr {
85 HDMI_PLLPWRCMD_ALLOFF = 0,
86 HDMI_PLLPWRCMD_PLLONLY = 1,
87 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
88 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
89};
90
Archit Tanejaf382d9e2013-08-06 14:56:55 +053091enum hdmi_phy_pwr {
92 HDMI_PHYPWRCMD_OFF = 0,
93 HDMI_PHYPWRCMD_LDOON = 1,
94 HDMI_PHYPWRCMD_TXON = 2
95};
96
Mythri P K94c52982011-09-08 19:06:21 +053097enum hdmi_core_hdmi_dvi {
98 HDMI_DVI = 0,
99 HDMI_HDMI = 1
100};
101
102enum hdmi_clk_refsel {
103 HDMI_REFSEL_PCLK = 0,
104 HDMI_REFSEL_REF1 = 1,
105 HDMI_REFSEL_REF2 = 2,
106 HDMI_REFSEL_SYSCLK = 3
107};
108
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530109enum hdmi_packing_mode {
110 HDMI_PACK_10b_RGB_YUV444 = 0,
111 HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
112 HDMI_PACK_20b_YUV422 = 2,
113 HDMI_PACK_ALREADYPACKED = 7
114};
115
116enum hdmi_stereo_channels {
117 HDMI_AUDIO_STEREO_NOCHANNELS = 0,
118 HDMI_AUDIO_STEREO_ONECHANNEL = 1,
119 HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
120 HDMI_AUDIO_STEREO_THREECHANNELS = 3,
121 HDMI_AUDIO_STEREO_FOURCHANNELS = 4
122};
123
124enum hdmi_audio_type {
125 HDMI_AUDIO_TYPE_LPCM = 0,
126 HDMI_AUDIO_TYPE_IEC = 1
127};
128
129enum hdmi_audio_justify {
130 HDMI_AUDIO_JUSTIFY_LEFT = 0,
131 HDMI_AUDIO_JUSTIFY_RIGHT = 1
132};
133
134enum hdmi_audio_sample_order {
135 HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
136 HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
137};
138
139enum hdmi_audio_samples_perword {
140 HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
141 HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
142};
143
144enum hdmi_audio_sample_size {
145 HDMI_AUDIO_SAMPLE_16BITS = 0,
146 HDMI_AUDIO_SAMPLE_24BITS = 1
147};
148
149enum hdmi_audio_transf_mode {
150 HDMI_AUDIO_TRANSF_DMA = 0,
151 HDMI_AUDIO_TRANSF_IRQ = 1
152};
153
154enum hdmi_audio_blk_strt_end_sig {
155 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
156 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
157};
158
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530159enum hdmi_core_audio_layout {
160 HDMI_AUDIO_LAYOUT_2CH = 0,
161 HDMI_AUDIO_LAYOUT_8CH = 1
162};
163
164enum hdmi_core_cts_mode {
165 HDMI_AUDIO_CTS_MODE_HW = 0,
166 HDMI_AUDIO_CTS_MODE_SW = 1
167};
168
169enum hdmi_audio_mclk_mode {
170 HDMI_AUDIO_MCLK_128FS = 0,
171 HDMI_AUDIO_MCLK_256FS = 1,
172 HDMI_AUDIO_MCLK_384FS = 2,
173 HDMI_AUDIO_MCLK_512FS = 3,
174 HDMI_AUDIO_MCLK_768FS = 4,
175 HDMI_AUDIO_MCLK_1024FS = 5,
176 HDMI_AUDIO_MCLK_1152FS = 6,
177 HDMI_AUDIO_MCLK_192FS = 7
178};
179
180/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
181enum hdmi_core_infoframe {
182 HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
183 HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
184 HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
185 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
186 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
187 HDMI_INFOFRAME_AVI_DB1B_NO = 0,
188 HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
189 HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
190 HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
191 HDMI_INFOFRAME_AVI_DB1S_0 = 0,
192 HDMI_INFOFRAME_AVI_DB1S_1 = 1,
193 HDMI_INFOFRAME_AVI_DB1S_2 = 2,
194 HDMI_INFOFRAME_AVI_DB2C_NO = 0,
195 HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
196 HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
197 HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
198 HDMI_INFOFRAME_AVI_DB2M_NO = 0,
199 HDMI_INFOFRAME_AVI_DB2M_43 = 1,
200 HDMI_INFOFRAME_AVI_DB2M_169 = 2,
201 HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
202 HDMI_INFOFRAME_AVI_DB2R_43 = 9,
203 HDMI_INFOFRAME_AVI_DB2R_169 = 10,
204 HDMI_INFOFRAME_AVI_DB2R_149 = 11,
205 HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
206 HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
207 HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
208 HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
209 HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
210 HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
211 HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
212 HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
213 HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
214 HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
215 HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
216 HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
217 HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
218 HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
219 HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
220 HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
221 HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
222 HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
223 HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
224 HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
225 HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
226};
227
Mythri P K94c52982011-09-08 19:06:21 +0530228struct hdmi_cm {
229 int code;
230 int mode;
231};
232
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530233struct hdmi_video_format {
234 enum hdmi_packing_mode packing_mode;
235 u32 y_res; /* Line per panel */
236 u32 x_res; /* pixel per line */
237};
238
Mythri P K94c52982011-09-08 19:06:21 +0530239struct hdmi_config {
Archit Tanejacc937e52012-06-24 13:08:10 +0530240 struct omap_video_timings timings;
Mythri P K94c52982011-09-08 19:06:21 +0530241 struct hdmi_cm cm;
242};
243
244/* HDMI PLL structure */
245struct hdmi_pll_info {
246 u16 regn;
247 u16 regm;
248 u32 regmf;
249 u16 regm2;
250 u16 regsd;
251 u16 dcofreq;
252 enum hdmi_clk_refsel refsel;
253};
254
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530255struct hdmi_audio_format {
256 enum hdmi_stereo_channels stereo_channels;
257 u8 active_chnnls_msk;
258 enum hdmi_audio_type type;
259 enum hdmi_audio_justify justification;
260 enum hdmi_audio_sample_order sample_order;
261 enum hdmi_audio_samples_perword samples_per_word;
262 enum hdmi_audio_sample_size sample_size;
263 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
264};
265
266struct hdmi_audio_dma {
267 u8 transfer_size;
268 u8 block_size;
269 enum hdmi_audio_transf_mode mode;
270 u16 fifo_threshold;
271};
272
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530273struct hdmi_core_audio_i2s_config {
274 u8 in_length_bits;
275 u8 justification;
276 u8 sck_edge_mode;
277 u8 vbit;
278 u8 direction;
279 u8 shift;
280 u8 active_sds;
281};
282
283struct hdmi_core_audio_config {
284 struct hdmi_core_audio_i2s_config i2s_cfg;
285 struct snd_aes_iec958 *iec60958_cfg;
286 bool fs_override;
287 u32 n;
288 u32 cts;
289 u32 aud_par_busclk;
290 enum hdmi_core_audio_layout layout;
291 enum hdmi_core_cts_mode cts_mode;
292 bool use_mclk;
293 enum hdmi_audio_mclk_mode mclk_mode;
294 bool en_acr_pkt;
295 bool en_dsd_audio;
296 bool en_parallel_aud_input;
297 bool en_spdif;
298};
299
Mythri P Kda8f14f2012-02-08 11:54:19 +0530300/*
301 * Refer to section 8.2 in HDMI 1.3 specification for
302 * details about infoframe databytes
303 */
304struct hdmi_core_infoframe_avi {
305 /* Y0, Y1 rgb,yCbCr */
306 u8 db1_format;
307 /* A0 Active information Present */
308 u8 db1_active_info;
309 /* B0, B1 Bar info data valid */
310 u8 db1_bar_info_dv;
311 /* S0, S1 scan information */
312 u8 db1_scan_info;
313 /* C0, C1 colorimetry */
314 u8 db2_colorimetry;
315 /* M0, M1 Aspect ratio (4:3, 16:9) */
316 u8 db2_aspect_ratio;
317 /* R0...R3 Active format aspect ratio */
318 u8 db2_active_fmt_ar;
319 /* ITC IT content. */
320 u8 db3_itc;
321 /* EC0, EC1, EC2 Extended colorimetry */
322 u8 db3_ec;
323 /* Q1, Q0 Quantization range */
324 u8 db3_q_range;
325 /* SC1, SC0 Non-uniform picture scaling */
326 u8 db3_nup_scaling;
327 /* VIC0..6 Video format identification */
328 u8 db4_videocode;
329 /* PR0..PR3 Pixel repetition factor */
330 u8 db5_pixel_repeat;
331 /* Line number end of top bar */
332 u16 db6_7_line_eoftop;
333 /* Line number start of bottom bar */
334 u16 db8_9_line_sofbottom;
335 /* Pixel number end of left bar */
336 u16 db10_11_pixel_eofleft;
337 /* Pixel number start of right bar */
338 u16 db12_13_pixel_sofright;
339};
340
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530341struct hdmi_wp_data {
342 void __iomem *base;
343};
344
Archit Tanejac1577c12013-10-08 12:55:26 +0530345struct hdmi_pll_data {
346 void __iomem *base;
347
348 struct hdmi_pll_info info;
349};
350
Archit Taneja5cac5ae2013-10-08 13:07:00 +0530351struct hdmi_phy_data {
352 void __iomem *base;
353
354 int irq;
355};
356
Archit Taneja425f02f2013-10-08 14:16:05 +0530357struct hdmi_core_data {
358 void __iomem *base;
359
360 struct hdmi_core_infoframe_avi avi_cfg;
361};
362
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530363static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx,
364 u32 val)
365{
366 __raw_writel(val, base_addr + idx);
367}
368
369static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx)
370{
371 return __raw_readl(base_addr + idx);
372}
373
374#define REG_FLD_MOD(base, idx, val, start, end) \
375 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
376 val, start, end))
377#define REG_GET(base, idx, start, end) \
378 FLD_GET(hdmi_read_reg(base, idx), start, end)
379
380static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
Tomi Valkeinen91b53e62013-10-28 11:47:30 +0200381 const u32 idx, int b2, int b1, u32 val)
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530382{
Tomi Valkeinen91b53e62013-10-28 11:47:30 +0200383 u32 t = 0, v;
384 while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530385 if (t++ > 10000)
Tomi Valkeinen91b53e62013-10-28 11:47:30 +0200386 return v;
387 udelay(1);
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530388 }
Tomi Valkeinen91b53e62013-10-28 11:47:30 +0200389 return v;
Archit Tanejabdb8bfc2013-09-12 18:07:49 +0530390}
391
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530392/* HDMI wrapper funcs */
393int hdmi_wp_video_start(struct hdmi_wp_data *wp);
394void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
395void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
396u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
397void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
398void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
399void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
400int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
401int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
402void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
403 struct hdmi_video_format *video_fmt);
404void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
405 struct omap_video_timings *timings);
406void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
407 struct omap_video_timings *timings);
408void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
409 struct omap_video_timings *timings, struct hdmi_config *param);
410int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
411
Archit Tanejac1577c12013-10-08 12:55:26 +0530412/* HDMI PLL funcs */
413int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
414void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
415void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
416void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
417int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
418
Archit Taneja5cac5ae2013-10-08 13:07:00 +0530419/* HDMI PHY funcs */
420int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp,
421 struct hdmi_config *cfg);
422void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp);
423void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
424int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
425
Archit Taneja08d83e42013-09-17 11:43:15 +0530426/* HDMI common funcs */
427const struct hdmi_config *hdmi_default_timing(void);
428const struct hdmi_config *hdmi_get_timings(int mode, int code);
429struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing);
430
Ricardo Neri7e151f72012-03-15 14:08:03 -0600431#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
Archit Taneja08d83e42013-09-17 11:43:15 +0530432int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
Archit Tanejaf382d9e2013-08-06 14:56:55 +0530433int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
434int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
435void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
436 struct hdmi_audio_format *aud_fmt);
437void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
438 struct hdmi_audio_dma *aud_dma);
Archit Taneja08d83e42013-09-17 11:43:15 +0530439static inline bool hdmi_mode_has_audio(int mode)
440{
441 return mode == HDMI_HDMI ? true : false;
442}
Ricardo Neri80a48592011-11-27 16:09:58 -0600443#endif
Mythri P K94c52982011-09-08 19:06:21 +0530444#endif