blob: 1a1c00ca39a2527b56c7a7103cc66f890483c98a [file] [log] [blame]
Magnus Damm863b1712010-12-28 08:27:01 +00001/*
2 * ARM Interrupt demux handler using INTC
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <asm/entry-macro-multi.S>
13
14#define INTCA_BASE 0xe6980000
15#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
16#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
17#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
18#define INTLVLB_OFFS 0x00000034 /* previous priority level */
19
20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =INTCA_BASE
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 /* The single INTFLGA read access below results in the following:
26 *
27 * 1. INTLVLB is updated with old priority value from INTLVLA
28 * 2. Highest priority interrupt is accepted
29 * 3. INTLVLA is updated to contain priority of accepted interrupt
30 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
31 */
32 ldr \irqnr, [\base, #INTFLGA_OFFS]
33
34 /* Restore INTLVLA with the value saved in INTLVLB.
35 * This is required to support interrupt priorities properly.
36 */
37 ldrb \tmp, [\base, #INTLVLB_OFFS]
38 strb \tmp, [\base, #INTLVLA_OFFS]
39
40 /* Handle invalid vector number case */
41 cmp \irqnr, #0
42 beq 1000f
43
44 /* Convert vector to irq number, same as the evt2irq() macro */
45 lsr \irqnr, \irqnr, #0x5
46 subs \irqnr, \irqnr, #16
47
481000:
49 .endm
50
51 .macro test_for_ipi, irqnr, irqstat, base, tmp
52 .endm
53
Magnus Damm863b1712010-12-28 08:27:01 +000054 arch_irq_handler shmobile_handle_irq_intc