blob: c95dbce2468e62010c8df64e3be4751869bd7abc [file] [log] [blame]
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +01001/*
2 * arch/arm/mach-ep93xx/clock.c
3 * Clock control for Cirrus EP93xx chips.
4 *
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or (at
10 * your option) any later version.
11 */
12
Hartley Sweeten99acbb92010-01-11 18:30:41 +010013#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
14
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010015#include <linux/kernel.h>
16#include <linux/clk.h>
17#include <linux/err.h>
Lennert Buytenhek51dd2492007-02-04 22:45:33 +010018#include <linux/module.h>
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010019#include <linux/string.h>
Russell Kingfced80c2008-09-06 12:10:45 +010020#include <linux/io.h>
Hartley Sweetenebd00c02009-10-08 23:44:41 +010021#include <linux/spinlock.h>
Jean-Christop PLAGNIOL-VILLARD6d803ba2010-11-17 10:04:33 +010022#include <linux/clkdev.h>
Hartley Sweetenebd00c02009-10-08 23:44:41 +010023
24#include <mach/hardware.h>
Russell Kingae696fd2008-11-30 17:11:49 +000025
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010026#include <asm/div64.h>
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010027
Ryan Mallon999c53f2012-01-11 13:43:02 +110028#include "soc.h"
Hartley Sweetenff05c032009-05-07 18:41:47 +010029
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010030struct clk {
Hartley Sweetenebd00c02009-10-08 23:44:41 +010031 struct clk *parent;
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010032 unsigned long rate;
33 int users;
Hartley Sweetenff05c032009-05-07 18:41:47 +010034 int sw_locked;
Hartley Sweetenc3e3bad2009-07-06 17:40:53 +010035 void __iomem *enable_reg;
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010036 u32 enable_mask;
Hartley Sweetenff05c032009-05-07 18:41:47 +010037
38 unsigned long (*get_rate)(struct clk *clk);
Hartley Sweeten701fac82009-06-30 23:06:43 +010039 int (*set_rate)(struct clk *clk, unsigned long rate);
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010040};
41
Hartley Sweetenff05c032009-05-07 18:41:47 +010042
43static unsigned long get_uart_rate(struct clk *clk);
44
Hartley Sweeten701fac82009-06-30 23:06:43 +010045static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
Ryan Mallonc6012182009-09-22 16:47:09 -070046static int set_div_rate(struct clk *clk, unsigned long rate);
Ryan Malloned67ea82010-06-08 22:01:10 +120047static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
Hartley Sweetenebd00c02009-10-08 23:44:41 +010049
50static struct clk clk_xtali = {
51 .rate = EP93XX_EXT_CLK_RATE,
52};
Hartley Sweetenff05c032009-05-07 18:41:47 +010053static struct clk clk_uart1 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +010054 .parent = &clk_xtali,
Hartley Sweetenff05c032009-05-07 18:41:47 +010055 .sw_locked = 1,
Hartley Sweeten02239f02009-07-08 02:00:49 +010056 .enable_reg = EP93XX_SYSCON_DEVCFG,
57 .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN,
Hartley Sweetenff05c032009-05-07 18:41:47 +010058 .get_rate = get_uart_rate,
59};
60static struct clk clk_uart2 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +010061 .parent = &clk_xtali,
Hartley Sweetenff05c032009-05-07 18:41:47 +010062 .sw_locked = 1,
Hartley Sweeten02239f02009-07-08 02:00:49 +010063 .enable_reg = EP93XX_SYSCON_DEVCFG,
64 .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN,
Hartley Sweetenff05c032009-05-07 18:41:47 +010065 .get_rate = get_uart_rate,
66};
67static struct clk clk_uart3 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +010068 .parent = &clk_xtali,
Hartley Sweetenff05c032009-05-07 18:41:47 +010069 .sw_locked = 1,
Hartley Sweeten02239f02009-07-08 02:00:49 +010070 .enable_reg = EP93XX_SYSCON_DEVCFG,
71 .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN,
Hartley Sweetenff05c032009-05-07 18:41:47 +010072 .get_rate = get_uart_rate,
Russell Kinged519de2007-04-22 12:30:41 +010073};
Hartley Sweetenebd00c02009-10-08 23:44:41 +010074static struct clk clk_pll1 = {
75 .parent = &clk_xtali,
76};
77static struct clk clk_f = {
78 .parent = &clk_pll1,
79};
80static struct clk clk_h = {
81 .parent = &clk_pll1,
82};
83static struct clk clk_p = {
84 .parent = &clk_pll1,
85};
86static struct clk clk_pll2 = {
87 .parent = &clk_xtali,
88};
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010089static struct clk clk_usb_host = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +010090 .parent = &clk_pll2,
Hartley Sweeten40702432009-05-28 20:07:03 +010091 .enable_reg = EP93XX_SYSCON_PWRCNT,
92 .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN,
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +010093};
Hartley Sweeten701fac82009-06-30 23:06:43 +010094static struct clk clk_keypad = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +010095 .parent = &clk_xtali,
Hartley Sweeten701fac82009-06-30 23:06:43 +010096 .sw_locked = 1,
97 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
98 .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
99 .set_rate = set_keytchclk_rate,
100};
Mika Westerberg4fec9972010-05-11 15:34:54 +0100101static struct clk clk_spi = {
102 .parent = &clk_xtali,
103 .rate = EP93XX_EXT_CLK_RATE,
104};
Hartley Sweetenef123792009-07-29 22:41:06 +0100105static struct clk clk_pwm = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100106 .parent = &clk_xtali,
Hartley Sweetenef123792009-07-29 22:41:06 +0100107 .rate = EP93XX_EXT_CLK_RATE,
108};
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100109
Ryan Mallonc6012182009-09-22 16:47:09 -0700110static struct clk clk_video = {
111 .sw_locked = 1,
112 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
113 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
114 .set_rate = set_div_rate,
115};
116
Ryan Malloned67ea82010-06-08 22:01:10 +1200117static struct clk clk_i2s_mclk = {
118 .sw_locked = 1,
119 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
120 .enable_mask = EP93XX_SYSCON_CLKDIV_ENABLE,
121 .set_rate = set_div_rate,
122};
123
124static struct clk clk_i2s_sclk = {
125 .sw_locked = 1,
126 .parent = &clk_i2s_mclk,
127 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
128 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
129 .set_rate = set_i2s_sclk_rate,
130};
131
132static struct clk clk_i2s_lrclk = {
133 .sw_locked = 1,
134 .parent = &clk_i2s_sclk,
135 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
136 .enable_mask = EP93XX_SYSCON_I2SCLKDIV_SENA,
137 .set_rate = set_i2s_lrclk_rate,
138};
139
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100140/* DMA Clocks */
141static struct clk clk_m2p0 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100142 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100143 .enable_reg = EP93XX_SYSCON_PWRCNT,
144 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P0,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100145};
146static struct clk clk_m2p1 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100147 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100148 .enable_reg = EP93XX_SYSCON_PWRCNT,
149 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P1,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100150};
151static struct clk clk_m2p2 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100152 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100153 .enable_reg = EP93XX_SYSCON_PWRCNT,
154 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P2,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100155};
156static struct clk clk_m2p3 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100157 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100158 .enable_reg = EP93XX_SYSCON_PWRCNT,
159 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P3,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100160};
161static struct clk clk_m2p4 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100162 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100163 .enable_reg = EP93XX_SYSCON_PWRCNT,
164 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P4,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100165};
166static struct clk clk_m2p5 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100167 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100168 .enable_reg = EP93XX_SYSCON_PWRCNT,
169 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P5,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100170};
171static struct clk clk_m2p6 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100172 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100173 .enable_reg = EP93XX_SYSCON_PWRCNT,
174 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P6,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100175};
176static struct clk clk_m2p7 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100177 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100178 .enable_reg = EP93XX_SYSCON_PWRCNT,
179 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P7,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100180};
181static struct clk clk_m2p8 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100182 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100183 .enable_reg = EP93XX_SYSCON_PWRCNT,
184 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P8,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100185};
186static struct clk clk_m2p9 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100187 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100188 .enable_reg = EP93XX_SYSCON_PWRCNT,
189 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2P9,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100190};
191static struct clk clk_m2m0 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100192 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100193 .enable_reg = EP93XX_SYSCON_PWRCNT,
194 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M0,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100195};
196static struct clk clk_m2m1 = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100197 .parent = &clk_h,
Hartley Sweeten40702432009-05-28 20:07:03 +0100198 .enable_reg = EP93XX_SYSCON_PWRCNT,
199 .enable_mask = EP93XX_SYSCON_PWRCNT_DMA_M2M1,
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100200};
201
Russell Kingae696fd2008-11-30 17:11:49 +0000202#define INIT_CK(dev,con,ck) \
203 { .dev_id = dev, .con_id = con, .clk = ck }
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100204
Russell Kingae696fd2008-11-30 17:11:49 +0000205static struct clk_lookup clocks[] = {
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100206 INIT_CK(NULL, "xtali", &clk_xtali),
Hartley Sweeten701fac82009-06-30 23:06:43 +0100207 INIT_CK("apb:uart1", NULL, &clk_uart1),
208 INIT_CK("apb:uart2", NULL, &clk_uart2),
209 INIT_CK("apb:uart3", NULL, &clk_uart3),
210 INIT_CK(NULL, "pll1", &clk_pll1),
211 INIT_CK(NULL, "fclk", &clk_f),
212 INIT_CK(NULL, "hclk", &clk_h),
Russell King3126c7b2010-07-15 11:01:17 +0100213 INIT_CK(NULL, "apb_pclk", &clk_p),
Hartley Sweeten701fac82009-06-30 23:06:43 +0100214 INIT_CK(NULL, "pll2", &clk_pll2),
215 INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
216 INIT_CK("ep93xx-keypad", NULL, &clk_keypad),
Ryan Mallonc6012182009-09-22 16:47:09 -0700217 INIT_CK("ep93xx-fb", NULL, &clk_video),
Mika Westerberg4fec9972010-05-11 15:34:54 +0100218 INIT_CK("ep93xx-spi.0", NULL, &clk_spi),
Ryan Malloned67ea82010-06-08 22:01:10 +1200219 INIT_CK("ep93xx-i2s", "mclk", &clk_i2s_mclk),
220 INIT_CK("ep93xx-i2s", "sclk", &clk_i2s_sclk),
221 INIT_CK("ep93xx-i2s", "lrclk", &clk_i2s_lrclk),
Hartley Sweetenef123792009-07-29 22:41:06 +0100222 INIT_CK(NULL, "pwm_clk", &clk_pwm),
Hartley Sweeten701fac82009-06-30 23:06:43 +0100223 INIT_CK(NULL, "m2p0", &clk_m2p0),
224 INIT_CK(NULL, "m2p1", &clk_m2p1),
225 INIT_CK(NULL, "m2p2", &clk_m2p2),
226 INIT_CK(NULL, "m2p3", &clk_m2p3),
227 INIT_CK(NULL, "m2p4", &clk_m2p4),
228 INIT_CK(NULL, "m2p5", &clk_m2p5),
229 INIT_CK(NULL, "m2p6", &clk_m2p6),
230 INIT_CK(NULL, "m2p7", &clk_m2p7),
231 INIT_CK(NULL, "m2p8", &clk_m2p8),
232 INIT_CK(NULL, "m2p9", &clk_m2p9),
233 INIT_CK(NULL, "m2m0", &clk_m2m0),
234 INIT_CK(NULL, "m2m1", &clk_m2m1),
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100235};
236
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100237static DEFINE_SPINLOCK(clk_lock);
238
239static void __clk_enable(struct clk *clk)
240{
241 if (!clk->users++) {
242 if (clk->parent)
243 __clk_enable(clk->parent);
244
245 if (clk->enable_reg) {
246 u32 v;
247
248 v = __raw_readl(clk->enable_reg);
249 v |= clk->enable_mask;
250 if (clk->sw_locked)
251 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
252 else
253 __raw_writel(v, clk->enable_reg);
254 }
255 }
256}
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100257
258int clk_enable(struct clk *clk)
259{
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100260 unsigned long flags;
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100261
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100262 if (!clk)
263 return -EINVAL;
264
265 spin_lock_irqsave(&clk_lock, flags);
266 __clk_enable(clk);
267 spin_unlock_irqrestore(&clk_lock, flags);
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100268
269 return 0;
270}
Dmitry Baryshkov0c5d5b72008-07-10 14:44:23 +0100271EXPORT_SYMBOL(clk_enable);
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100272
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100273static void __clk_disable(struct clk *clk)
274{
275 if (!--clk->users) {
276 if (clk->enable_reg) {
277 u32 v;
278
279 v = __raw_readl(clk->enable_reg);
280 v &= ~clk->enable_mask;
281 if (clk->sw_locked)
282 ep93xx_syscon_swlocked_write(v, clk->enable_reg);
283 else
284 __raw_writel(v, clk->enable_reg);
285 }
286
287 if (clk->parent)
288 __clk_disable(clk->parent);
289 }
290}
291
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100292void clk_disable(struct clk *clk)
293{
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100294 unsigned long flags;
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100295
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100296 if (!clk)
297 return;
298
299 spin_lock_irqsave(&clk_lock, flags);
300 __clk_disable(clk);
301 spin_unlock_irqrestore(&clk_lock, flags);
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100302}
Dmitry Baryshkov0c5d5b72008-07-10 14:44:23 +0100303EXPORT_SYMBOL(clk_disable);
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100304
Hartley Sweetenff05c032009-05-07 18:41:47 +0100305static unsigned long get_uart_rate(struct clk *clk)
306{
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100307 unsigned long rate = clk_get_rate(clk->parent);
Hartley Sweetenff05c032009-05-07 18:41:47 +0100308 u32 value;
309
Matthias Kaehlckeca8cbc82009-06-11 19:57:34 +0100310 value = __raw_readl(EP93XX_SYSCON_PWRCNT);
311 if (value & EP93XX_SYSCON_PWRCNT_UARTBAUD)
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100312 return rate;
Hartley Sweetenff05c032009-05-07 18:41:47 +0100313 else
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100314 return rate / 2;
Hartley Sweetenff05c032009-05-07 18:41:47 +0100315}
316
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100317unsigned long clk_get_rate(struct clk *clk)
318{
Hartley Sweetenff05c032009-05-07 18:41:47 +0100319 if (clk->get_rate)
320 return clk->get_rate(clk);
321
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100322 return clk->rate;
323}
Dmitry Baryshkov0c5d5b72008-07-10 14:44:23 +0100324EXPORT_SYMBOL(clk_get_rate);
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100325
Hartley Sweeten701fac82009-06-30 23:06:43 +0100326static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
327{
328 u32 val;
329 u32 div_bit;
330
331 val = __raw_readl(clk->enable_reg);
332
333 /*
334 * The Key Matrix and ADC clocks are configured using the same
335 * System Controller register. The clock used will be either
336 * 1/4 or 1/16 the external clock rate depending on the
337 * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
338 * bit being set or cleared.
339 */
340 div_bit = clk->enable_mask >> 15;
341
342 if (rate == EP93XX_KEYTCHCLK_DIV4)
343 val |= div_bit;
344 else if (rate == EP93XX_KEYTCHCLK_DIV16)
345 val &= ~div_bit;
346 else
347 return -EINVAL;
348
349 ep93xx_syscon_swlocked_write(val, clk->enable_reg);
350 clk->rate = rate;
351 return 0;
352}
353
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100354static int calc_clk_div(struct clk *clk, unsigned long rate,
355 int *psel, int *esel, int *pdiv, int *div)
Ryan Mallonc6012182009-09-22 16:47:09 -0700356{
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100357 struct clk *mclk;
358 unsigned long max_rate, actual_rate, mclk_rate, rate_err = -1;
Ryan Mallonc6012182009-09-22 16:47:09 -0700359 int i, found = 0, __div = 0, __pdiv = 0;
360
361 /* Don't exceed the maximum rate */
Hagen Paul Pfeifer732eacc2010-10-26 14:22:23 -0700362 max_rate = max3(clk_pll1.rate / 4, clk_pll2.rate / 4, clk_xtali.rate / 4);
Ryan Mallonc6012182009-09-22 16:47:09 -0700363 rate = min(rate, max_rate);
364
365 /*
366 * Try the two pll's and the external clock
367 * Because the valid predividers are 2, 2.5 and 3, we multiply
368 * all the clocks by 2 to avoid floating point math.
369 *
370 * This is based on the algorithm in the ep93xx raster guide:
371 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
372 *
373 */
374 for (i = 0; i < 3; i++) {
375 if (i == 0)
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100376 mclk = &clk_xtali;
Ryan Mallonc6012182009-09-22 16:47:09 -0700377 else if (i == 1)
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100378 mclk = &clk_pll1;
379 else
380 mclk = &clk_pll2;
381 mclk_rate = mclk->rate * 2;
Ryan Mallonc6012182009-09-22 16:47:09 -0700382
383 /* Try each predivider value */
384 for (__pdiv = 4; __pdiv <= 6; __pdiv++) {
385 __div = mclk_rate / (rate * __pdiv);
386 if (__div < 2 || __div > 127)
387 continue;
388
389 actual_rate = mclk_rate / (__pdiv * __div);
390
391 if (!found || abs(actual_rate - rate) < rate_err) {
392 *pdiv = __pdiv - 3;
393 *div = __div;
394 *psel = (i == 2);
395 *esel = (i != 0);
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100396 clk->parent = mclk;
397 clk->rate = actual_rate;
Ryan Mallonc6012182009-09-22 16:47:09 -0700398 rate_err = abs(actual_rate - rate);
399 found = 1;
400 }
401 }
402 }
403
404 if (!found)
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100405 return -EINVAL;
Ryan Mallonc6012182009-09-22 16:47:09 -0700406
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100407 return 0;
Ryan Mallonc6012182009-09-22 16:47:09 -0700408}
409
410static int set_div_rate(struct clk *clk, unsigned long rate)
411{
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100412 int err, psel = 0, esel = 0, pdiv = 0, div = 0;
Ryan Mallonc6012182009-09-22 16:47:09 -0700413 u32 val;
414
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100415 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div);
416 if (err)
417 return err;
Ryan Mallonc6012182009-09-22 16:47:09 -0700418
419 /* Clear the esel, psel, pdiv and div bits */
420 val = __raw_readl(clk->enable_reg);
421 val &= ~0x7fff;
422
423 /* Set the new esel, psel, pdiv and div bits for the new clock rate */
424 val |= (esel ? EP93XX_SYSCON_CLKDIV_ESEL : 0) |
425 (psel ? EP93XX_SYSCON_CLKDIV_PSEL : 0) |
426 (pdiv << EP93XX_SYSCON_CLKDIV_PDIV_SHIFT) | div;
427 ep93xx_syscon_swlocked_write(val, clk->enable_reg);
428 return 0;
429}
430
Ryan Malloned67ea82010-06-08 22:01:10 +1200431static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
432{
433 unsigned val = __raw_readl(clk->enable_reg);
434
435 if (rate == clk_i2s_mclk.rate / 2)
436 ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV,
437 clk->enable_reg);
438 else if (rate == clk_i2s_mclk.rate / 4)
439 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV,
440 clk->enable_reg);
441 else
442 return -EINVAL;
443
444 clk_i2s_sclk.rate = rate;
445 return 0;
446}
447
448static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
449{
450 unsigned val = __raw_readl(clk->enable_reg) &
451 ~EP93XX_I2SCLKDIV_LRDIV_MASK;
452
453 if (rate == clk_i2s_sclk.rate / 32)
454 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
455 clk->enable_reg);
456 else if (rate == clk_i2s_sclk.rate / 64)
457 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
458 clk->enable_reg);
459 else if (rate == clk_i2s_sclk.rate / 128)
460 ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
461 clk->enable_reg);
462 else
463 return -EINVAL;
464
465 clk_i2s_lrclk.rate = rate;
466 return 0;
467}
468
Hartley Sweeten701fac82009-06-30 23:06:43 +0100469int clk_set_rate(struct clk *clk, unsigned long rate)
470{
471 if (clk->set_rate)
472 return clk->set_rate(clk, rate);
473
474 return -EINVAL;
475}
476EXPORT_SYMBOL(clk_set_rate);
477
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100478
479static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
480static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
481static char pclk_divisors[] = { 1, 2, 4, 8 };
482
483/*
484 * PLL rate = 14.7456 MHz * (X1FBD + 1) * (X2FBD + 1) / (X2IPD + 1) / 2^PS
485 */
486static unsigned long calc_pll_rate(u32 config_word)
487{
488 unsigned long long rate;
489 int i;
490
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100491 rate = clk_xtali.rate;
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100492 rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */
493 rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */
494 do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */
495 for (i = 0; i < ((config_word >> 16) & 3); i++) /* PS */
496 rate >>= 1;
497
498 return (unsigned long)rate;
499}
500
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100501static void __init ep93xx_dma_clock_init(void)
502{
503 clk_m2p0.rate = clk_h.rate;
504 clk_m2p1.rate = clk_h.rate;
505 clk_m2p2.rate = clk_h.rate;
506 clk_m2p3.rate = clk_h.rate;
507 clk_m2p4.rate = clk_h.rate;
508 clk_m2p5.rate = clk_h.rate;
509 clk_m2p6.rate = clk_h.rate;
510 clk_m2p7.rate = clk_h.rate;
511 clk_m2p8.rate = clk_h.rate;
512 clk_m2p9.rate = clk_h.rate;
513 clk_m2m0.rate = clk_h.rate;
514 clk_m2m1.rate = clk_h.rate;
515}
516
Lennert Buytenhek51dd2492007-02-04 22:45:33 +0100517static int __init ep93xx_clock_init(void)
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100518{
519 u32 value;
520
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100521 /* Determine the bootloader configured pll1 rate */
522 value = __raw_readl(EP93XX_SYSCON_CLKSET1);
523 if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100524 clk_pll1.rate = clk_xtali.rate;
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100525 else
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100526 clk_pll1.rate = calc_pll_rate(value);
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100527
528 /* Initialize the pll1 derived clocks */
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100529 clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
530 clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
531 clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
Ryan Mallon1c8daab2009-02-25 22:22:38 +0100532 ep93xx_dma_clock_init();
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100533
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100534 /* Determine the bootloader configured pll2 rate */
Hartley Sweetenba7c6a32010-02-23 21:20:31 +0100535 value = __raw_readl(EP93XX_SYSCON_CLKSET2);
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100536 if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
Hartley Sweetenebd00c02009-10-08 23:44:41 +0100537 clk_pll2.rate = clk_xtali.rate;
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100538 else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100539 clk_pll2.rate = calc_pll_rate(value);
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100540 else
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100541 clk_pll2.rate = 0;
Hartley Sweeten346e34a2010-01-11 21:41:29 +0100542
543 /* Initialize the pll2 derived clocks */
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100544 clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
545
Mika Westerberg4fec9972010-05-11 15:34:54 +0100546 /*
547 * EP93xx SSP clock rate was doubled in version E2. For more information
548 * see:
549 * http://www.cirrus.com/en/pubs/appNote/AN273REV4.pdf
550 */
551 if (ep93xx_chip_revision() < EP93XX_CHIP_REV_E2)
552 clk_spi.rate /= 2;
553
Hartley Sweeten99acbb92010-01-11 18:30:41 +0100554 pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100555 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
Hartley Sweeten99acbb92010-01-11 18:30:41 +0100556 pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100557 clk_f.rate / 1000000, clk_h.rate / 1000000,
558 clk_p.rate / 1000000);
Lennert Buytenhek51dd2492007-02-04 22:45:33 +0100559
Russell King0a0300d2010-01-12 12:28:00 +0000560 clkdev_add_table(clocks, ARRAY_SIZE(clocks));
Lennert Buytenhek51dd2492007-02-04 22:45:33 +0100561 return 0;
Lennert Buytenhek1d81eed2006-06-24 10:33:02 +0100562}
Mika Westerberga387f0f52010-09-03 17:14:54 +0100563postcore_initcall(ep93xx_clock_init);