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Russell King9e2697f2007-12-14 13:30:14 +00001/*
Eric Miao0d1bde92008-08-06 15:51:53 +08002 * linux/arch/arm/mach-pxa/cpufreq-pxa2xx.c
Russell King9e2697f2007-12-14 13:30:14 +00003 *
4 * Copyright (C) 2002,2003 Intrinsyc Software
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * History:
21 * 31-Jul-2002 : Initial version [FB]
22 * 29-Jan-2003 : added PXA255 support [FB]
23 * 20-Apr-2003 : ported to v2.5 (Dustin McIntire, Sensoria Corp.)
24 *
25 * Note:
26 * This driver may change the memory bus clock rate, but will not do any
27 * platform specific access timing changes... for example if you have flash
28 * memory connected to CS0, you will need to register a platform specific
29 * notifier which will adjust the memory access strobes to maintain a
30 * minimum strobe width.
31 *
32 */
33
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/sched.h>
37#include <linux/init.h>
38#include <linux/cpufreq.h>
Robert Jarzmik3dbeef22009-05-17 23:03:55 +020039#include <linux/err.h>
40#include <linux/regulator/consumer.h>
Russell King9e2697f2007-12-14 13:30:14 +000041
Russell Kinga09e64f2008-08-05 16:14:15 +010042#include <mach/pxa2xx-regs.h>
Russell King9e2697f2007-12-14 13:30:14 +000043
44#ifdef DEBUG
45static unsigned int freq_debug;
Randy Dunlapc710e392008-02-27 12:11:16 -080046module_param(freq_debug, uint, 0);
Russell King9e2697f2007-12-14 13:30:14 +000047MODULE_PARM_DESC(freq_debug, "Set the debug messages to on=1/off=0");
48#else
49#define freq_debug 0
50#endif
51
Robert Jarzmik3dbeef22009-05-17 23:03:55 +020052static struct regulator *vcc_core;
53
Robert Jarzmik592eb992008-05-07 20:39:06 +010054static unsigned int pxa27x_maxfreq;
55module_param(pxa27x_maxfreq, uint, 0);
56MODULE_PARM_DESC(pxa27x_maxfreq, "Set the pxa27x maxfreq in MHz"
57 "(typically 624=>pxa270, 416=>pxa271, 520=>pxa272)");
58
Russell King9e2697f2007-12-14 13:30:14 +000059typedef struct {
60 unsigned int khz;
61 unsigned int membus;
62 unsigned int cccr;
63 unsigned int div2;
Robert Jarzmik592eb992008-05-07 20:39:06 +010064 unsigned int cclkcfg;
Robert Jarzmik3dbeef22009-05-17 23:03:55 +020065 int vmin;
66 int vmax;
Russell King9e2697f2007-12-14 13:30:14 +000067} pxa_freqs_t;
68
69/* Define the refresh period in mSec for the SDRAM and the number of rows */
Robert Jarzmik36793892008-05-07 20:36:34 +010070#define SDRAM_TREF 64 /* standard 64ms SDRAM */
Philipp Zabela10c2872008-06-29 16:53:34 +020071static unsigned int sdram_rows;
Russell King9e2697f2007-12-14 13:30:14 +000072
Robert Jarzmik36793892008-05-07 20:36:34 +010073#define CCLKCFG_TURBO 0x1
74#define CCLKCFG_FCS 0x2
Robert Jarzmik592eb992008-05-07 20:39:06 +010075#define CCLKCFG_HALFTURBO 0x4
76#define CCLKCFG_FASTBUS 0x8
Robert Jarzmik36793892008-05-07 20:36:34 +010077#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
78#define MDREFR_DRI_MASK 0xFFF
Russell King9e2697f2007-12-14 13:30:14 +000079
Philipp Zabela10c2872008-06-29 16:53:34 +020080#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
81#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
82
Robert Jarzmik592eb992008-05-07 20:39:06 +010083/*
84 * PXA255 definitions
85 */
Russell King9e2697f2007-12-14 13:30:14 +000086/* Use the run mode frequencies for the CPUFREQ_POLICY_PERFORMANCE policy */
Robert Jarzmik592eb992008-05-07 20:39:06 +010087#define CCLKCFG CCLKCFG_TURBO | CCLKCFG_FCS
88
Russell King9e2697f2007-12-14 13:30:14 +000089static pxa_freqs_t pxa255_run_freqs[] =
90{
Robert Jarzmik3dbeef22009-05-17 23:03:55 +020091 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
92 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
93 {132700, 132700, 0x123, 1, CCLKCFG, -1, -1}, /* 133, 133, 66, 66 */
94 {199100, 99500, 0x141, 0, CCLKCFG, -1, -1}, /* 199, 199, 99, 99 */
95 {265400, 132700, 0x143, 1, CCLKCFG, -1, -1}, /* 265, 265, 133, 66 */
96 {331800, 165900, 0x145, 1, CCLKCFG, -1, -1}, /* 331, 331, 166, 83 */
97 {398100, 99500, 0x161, 0, CCLKCFG, -1, -1}, /* 398, 398, 196, 99 */
Russell King9e2697f2007-12-14 13:30:14 +000098};
Russell King9e2697f2007-12-14 13:30:14 +000099
100/* Use the turbo mode frequencies for the CPUFREQ_POLICY_POWERSAVE policy */
101static pxa_freqs_t pxa255_turbo_freqs[] =
102{
Robert Jarzmik592eb992008-05-07 20:39:06 +0100103 /* CPU MEMBUS CCCR DIV2 CCLKCFG run turbo PXbus SDRAM */
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200104 { 99500, 99500, 0x121, 1, CCLKCFG, -1, -1}, /* 99, 99, 50, 50 */
105 {199100, 99500, 0x221, 0, CCLKCFG, -1, -1}, /* 99, 199, 50, 99 */
106 {298500, 99500, 0x321, 0, CCLKCFG, -1, -1}, /* 99, 287, 50, 99 */
107 {298600, 99500, 0x1c1, 0, CCLKCFG, -1, -1}, /* 199, 287, 99, 99 */
108 {398100, 99500, 0x241, 0, CCLKCFG, -1, -1}, /* 199, 398, 99, 99 */
Russell King9e2697f2007-12-14 13:30:14 +0000109};
Robert Jarzmik592eb992008-05-07 20:39:06 +0100110
111#define NUM_PXA25x_RUN_FREQS ARRAY_SIZE(pxa255_run_freqs)
112#define NUM_PXA25x_TURBO_FREQS ARRAY_SIZE(pxa255_turbo_freqs)
Russell King9e2697f2007-12-14 13:30:14 +0000113
Robert Jarzmik36793892008-05-07 20:36:34 +0100114static struct cpufreq_frequency_table
Robert Jarzmik592eb992008-05-07 20:39:06 +0100115 pxa255_run_freq_table[NUM_PXA25x_RUN_FREQS+1];
116static struct cpufreq_frequency_table
117 pxa255_turbo_freq_table[NUM_PXA25x_TURBO_FREQS+1];
118
Marc Zyngier65587f72008-11-04 13:33:25 +0100119static unsigned int pxa255_turbo_table;
120module_param(pxa255_turbo_table, uint, 0);
121MODULE_PARM_DESC(pxa255_turbo_table, "Selects the frequency table (0 = run table, !0 = turbo table)");
122
Robert Jarzmik592eb992008-05-07 20:39:06 +0100123/*
124 * PXA270 definitions
125 *
126 * For the PXA27x:
127 * Control variables are A, L, 2N for CCCR; B, HT, T for CLKCFG.
128 *
129 * A = 0 => memory controller clock from table 3-7,
130 * A = 1 => memory controller clock = system bus clock
131 * Run mode frequency = 13 MHz * L
132 * Turbo mode frequency = 13 MHz * L * N
133 * System bus frequency = 13 MHz * L / (B + 1)
134 *
135 * In CCCR:
136 * A = 1
137 * L = 16 oscillator to run mode ratio
138 * 2N = 6 2 * (turbo mode to run mode ratio)
139 *
140 * In CCLKCFG:
141 * B = 1 Fast bus mode
142 * HT = 0 Half-Turbo mode
143 * T = 1 Turbo mode
144 *
145 * For now, just support some of the combinations in table 3-7 of
146 * PXA27x Processor Family Developer's Manual to simplify frequency
147 * change sequences.
148 */
149#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
150#define CCLKCFG2(B, HT, T) \
151 (CCLKCFG_FCS | \
152 ((B) ? CCLKCFG_FASTBUS : 0) | \
153 ((HT) ? CCLKCFG_HALFTURBO : 0) | \
154 ((T) ? CCLKCFG_TURBO : 0))
155
156static pxa_freqs_t pxa27x_freqs[] = {
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200157 {104000, 104000, PXA27x_CCCR(1, 8, 2), 0, CCLKCFG2(1, 0, 1), 900000, 1705000 },
Dennis O'Brien43672162009-10-10 15:08:52 +0800158 {156000, 104000, PXA27x_CCCR(1, 8, 3), 0, CCLKCFG2(1, 0, 1), 1000000, 1705000 },
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200159 {208000, 208000, PXA27x_CCCR(0, 16, 2), 1, CCLKCFG2(0, 0, 1), 1180000, 1705000 },
160 {312000, 208000, PXA27x_CCCR(1, 16, 3), 1, CCLKCFG2(1, 0, 1), 1250000, 1705000 },
161 {416000, 208000, PXA27x_CCCR(1, 16, 4), 1, CCLKCFG2(1, 0, 1), 1350000, 1705000 },
162 {520000, 208000, PXA27x_CCCR(1, 16, 5), 1, CCLKCFG2(1, 0, 1), 1450000, 1705000 },
163 {624000, 208000, PXA27x_CCCR(1, 16, 6), 1, CCLKCFG2(1, 0, 1), 1550000, 1705000 }
Robert Jarzmik592eb992008-05-07 20:39:06 +0100164};
165
166#define NUM_PXA27x_FREQS ARRAY_SIZE(pxa27x_freqs)
167static struct cpufreq_frequency_table
168 pxa27x_freq_table[NUM_PXA27x_FREQS+1];
Russell King9e2697f2007-12-14 13:30:14 +0000169
170extern unsigned get_clk_frequency_khz(int info);
171
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200172#ifdef CONFIG_REGULATOR
173
174static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
175{
176 int ret = 0;
177 int vmin, vmax;
178
179 if (!cpu_is_pxa27x())
180 return 0;
181
182 vmin = pxa_freq->vmin;
183 vmax = pxa_freq->vmax;
184 if ((vmin == -1) || (vmax == -1))
185 return 0;
186
187 ret = regulator_set_voltage(vcc_core, vmin, vmax);
188 if (ret)
189 pr_err("cpufreq: Failed to set vcc_core in [%dmV..%dmV]\n",
190 vmin, vmax);
191 return ret;
192}
193
194static __init void pxa_cpufreq_init_voltages(void)
195{
196 vcc_core = regulator_get(NULL, "vcc_core");
197 if (IS_ERR(vcc_core)) {
198 pr_info("cpufreq: Didn't find vcc_core regulator\n");
199 vcc_core = NULL;
200 } else {
201 pr_info("cpufreq: Found vcc_core regulator\n");
202 }
203}
204#else
205static int pxa_cpufreq_change_voltage(pxa_freqs_t *pxa_freq)
206{
207 return 0;
208}
209
210static __init void pxa_cpufreq_init_voltages(void) { }
211#endif
212
Marc Zyngier65587f72008-11-04 13:33:25 +0100213static void find_freq_tables(struct cpufreq_frequency_table **freq_table,
Robert Jarzmik592eb992008-05-07 20:39:06 +0100214 pxa_freqs_t **pxa_freqs)
215{
216 if (cpu_is_pxa25x()) {
Marc Zyngier65587f72008-11-04 13:33:25 +0100217 if (!pxa255_turbo_table) {
Robert Jarzmik592eb992008-05-07 20:39:06 +0100218 *pxa_freqs = pxa255_run_freqs;
219 *freq_table = pxa255_run_freq_table;
Marc Zyngier65587f72008-11-04 13:33:25 +0100220 } else {
Robert Jarzmik592eb992008-05-07 20:39:06 +0100221 *pxa_freqs = pxa255_turbo_freqs;
222 *freq_table = pxa255_turbo_freq_table;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100223 }
224 }
225 if (cpu_is_pxa27x()) {
226 *pxa_freqs = pxa27x_freqs;
227 *freq_table = pxa27x_freq_table;
228 }
229}
230
231static void pxa27x_guess_max_freq(void)
232{
233 if (!pxa27x_maxfreq) {
234 pxa27x_maxfreq = 416000;
235 printk(KERN_INFO "PXA CPU 27x max frequency not defined "
236 "(pxa27x_maxfreq), assuming pxa271 with %dkHz maxfreq\n",
237 pxa27x_maxfreq);
238 } else {
239 pxa27x_maxfreq *= 1000;
240 }
241}
242
Philipp Zabela10c2872008-06-29 16:53:34 +0200243static void init_sdram_rows(void)
244{
245 uint32_t mdcnfg = MDCNFG;
246 unsigned int drac2 = 0, drac0 = 0;
247
248 if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
249 drac2 = MDCNFG_DRAC2(mdcnfg);
250
251 if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
252 drac0 = MDCNFG_DRAC0(mdcnfg);
253
254 sdram_rows = 1 << (11 + max(drac0, drac2));
255}
256
Robert Jarzmik592eb992008-05-07 20:39:06 +0100257static u32 mdrefr_dri(unsigned int freq)
258{
259 u32 dri = 0;
260
261 if (cpu_is_pxa25x())
Philipp Zabela10c2872008-06-29 16:53:34 +0200262 dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
Robert Jarzmik592eb992008-05-07 20:39:06 +0100263 if (cpu_is_pxa27x())
Philipp Zabela10c2872008-06-29 16:53:34 +0200264 dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100265 return dri;
266}
267
Russell King9e2697f2007-12-14 13:30:14 +0000268/* find a valid frequency point */
269static int pxa_verify_policy(struct cpufreq_policy *policy)
270{
271 struct cpufreq_frequency_table *pxa_freqs_table;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100272 pxa_freqs_t *pxa_freqs;
Russell King9e2697f2007-12-14 13:30:14 +0000273 int ret;
274
Marc Zyngier65587f72008-11-04 13:33:25 +0100275 find_freq_tables(&pxa_freqs_table, &pxa_freqs);
Russell King9e2697f2007-12-14 13:30:14 +0000276 ret = cpufreq_frequency_table_verify(policy, pxa_freqs_table);
277
278 if (freq_debug)
279 pr_debug("Verified CPU policy: %dKhz min to %dKhz max\n",
Robert Jarzmik36793892008-05-07 20:36:34 +0100280 policy->min, policy->max);
Russell King9e2697f2007-12-14 13:30:14 +0000281
282 return ret;
283}
284
Robert Jarzmik592eb992008-05-07 20:39:06 +0100285static unsigned int pxa_cpufreq_get(unsigned int cpu)
286{
287 return get_clk_frequency_khz(0);
288}
289
Russell King9e2697f2007-12-14 13:30:14 +0000290static int pxa_set_target(struct cpufreq_policy *policy,
Robert Jarzmik36793892008-05-07 20:36:34 +0100291 unsigned int target_freq,
292 unsigned int relation)
Russell King9e2697f2007-12-14 13:30:14 +0000293{
294 struct cpufreq_frequency_table *pxa_freqs_table;
295 pxa_freqs_t *pxa_freq_settings;
296 struct cpufreq_freqs freqs;
Holger Schurigea833f02008-02-11 16:53:15 +0100297 unsigned int idx;
Russell King9e2697f2007-12-14 13:30:14 +0000298 unsigned long flags;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100299 unsigned int new_freq_cpu, new_freq_mem;
300 unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200301 int ret = 0;
Russell King9e2697f2007-12-14 13:30:14 +0000302
303 /* Get the current policy */
Marc Zyngier65587f72008-11-04 13:33:25 +0100304 find_freq_tables(&pxa_freqs_table, &pxa_freq_settings);
Russell King9e2697f2007-12-14 13:30:14 +0000305
306 /* Lookup the next frequency */
307 if (cpufreq_frequency_table_target(policy, pxa_freqs_table,
Robert Jarzmik36793892008-05-07 20:36:34 +0100308 target_freq, relation, &idx)) {
Russell King9e2697f2007-12-14 13:30:14 +0000309 return -EINVAL;
310 }
311
Robert Jarzmik592eb992008-05-07 20:39:06 +0100312 new_freq_cpu = pxa_freq_settings[idx].khz;
313 new_freq_mem = pxa_freq_settings[idx].membus;
Russell King9e2697f2007-12-14 13:30:14 +0000314 freqs.old = policy->cur;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100315 freqs.new = new_freq_cpu;
Russell King9e2697f2007-12-14 13:30:14 +0000316 freqs.cpu = policy->cpu;
317
318 if (freq_debug)
Robert Jarzmik36793892008-05-07 20:36:34 +0100319 pr_debug(KERN_INFO "Changing CPU frequency to %d Mhz, "
320 "(SDRAM %d Mhz)\n",
321 freqs.new / 1000, (pxa_freq_settings[idx].div2) ?
Robert Jarzmik592eb992008-05-07 20:39:06 +0100322 (new_freq_mem / 2000) : (new_freq_mem / 1000));
Russell King9e2697f2007-12-14 13:30:14 +0000323
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200324 if (vcc_core && freqs.new > freqs.old)
325 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
326 if (ret)
327 return ret;
Russell King9e2697f2007-12-14 13:30:14 +0000328 /*
329 * Tell everyone what we're about to do...
330 * you should add a notify client with any platform specific
331 * Vcc changing capability
332 */
333 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
334
335 /* Calculate the next MDREFR. If we're slowing down the SDRAM clock
Robert Jarzmik36793892008-05-07 20:36:34 +0100336 * we need to preset the smaller DRI before the change. If we're
337 * speeding up we need to set the larger DRI value after the change.
Russell King9e2697f2007-12-14 13:30:14 +0000338 */
339 preset_mdrefr = postset_mdrefr = MDREFR;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100340 if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
341 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
342 preset_mdrefr |= mdrefr_dri(new_freq_mem);
Russell King9e2697f2007-12-14 13:30:14 +0000343 }
Robert Jarzmik592eb992008-05-07 20:39:06 +0100344 postset_mdrefr =
345 (postset_mdrefr & ~MDREFR_DRI_MASK) | mdrefr_dri(new_freq_mem);
Russell King9e2697f2007-12-14 13:30:14 +0000346
347 /* If we're dividing the memory clock by two for the SDRAM clock, this
348 * must be set prior to the change. Clearing the divide must be done
349 * after the change.
350 */
351 if (pxa_freq_settings[idx].div2) {
352 preset_mdrefr |= MDREFR_DB2_MASK;
353 postset_mdrefr |= MDREFR_DB2_MASK;
354 } else {
355 postset_mdrefr &= ~MDREFR_DB2_MASK;
356 }
357
358 local_irq_save(flags);
359
Robert Jarzmik592eb992008-05-07 20:39:06 +0100360 /* Set new the CCCR and prepare CCLKCFG */
Russell King9e2697f2007-12-14 13:30:14 +0000361 CCCR = pxa_freq_settings[idx].cccr;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100362 cclkcfg = pxa_freq_settings[idx].cclkcfg;
Russell King9e2697f2007-12-14 13:30:14 +0000363
364 asm volatile(" \n\
365 ldr r4, [%1] /* load MDREFR */ \n\
366 b 2f \n\
Robert Jarzmik36793892008-05-07 20:36:34 +0100367 .align 5 \n\
Russell King9e2697f2007-12-14 13:30:14 +00003681: \n\
Robert Jarzmik592eb992008-05-07 20:39:06 +0100369 str %3, [%1] /* preset the MDREFR */ \n\
Russell King9e2697f2007-12-14 13:30:14 +0000370 mcr p14, 0, %2, c6, c0, 0 /* set CCLKCFG[FCS] */ \n\
Robert Jarzmik592eb992008-05-07 20:39:06 +0100371 str %4, [%1] /* postset the MDREFR */ \n\
Russell King9e2697f2007-12-14 13:30:14 +0000372 \n\
373 b 3f \n\
3742: b 1b \n\
3753: nop \n\
376 "
Robert Jarzmik36793892008-05-07 20:36:34 +0100377 : "=&r" (unused)
Robert Jarzmik592eb992008-05-07 20:39:06 +0100378 : "r" (&MDREFR), "r" (cclkcfg),
379 "r" (preset_mdrefr), "r" (postset_mdrefr)
Robert Jarzmik36793892008-05-07 20:36:34 +0100380 : "r4", "r5");
Russell King9e2697f2007-12-14 13:30:14 +0000381 local_irq_restore(flags);
382
383 /*
384 * Tell everyone what we've just done...
385 * you should add a notify client with any platform specific
386 * SDRAM refresh timer adjustments
387 */
388 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
389
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200390 /*
391 * Even if voltage setting fails, we don't report it, as the frequency
392 * change succeeded. The voltage reduction is not a critical failure,
393 * only power savings will suffer from this.
394 *
395 * Note: if the voltage change fails, and a return value is returned, a
396 * bug is triggered (seems a deadlock). Should anybody find out where,
397 * the "return 0" should become a "return ret".
398 */
399 if (vcc_core && freqs.new < freqs.old)
400 ret = pxa_cpufreq_change_voltage(&pxa_freq_settings[idx]);
401
Russell King9e2697f2007-12-14 13:30:14 +0000402 return 0;
403}
404
Robert Jarzmik592eb992008-05-07 20:39:06 +0100405static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
Russell King9e2697f2007-12-14 13:30:14 +0000406{
407 int i;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100408 unsigned int freq;
Marc Zyngier65587f72008-11-04 13:33:25 +0100409 struct cpufreq_frequency_table *pxa255_freq_table;
410 pxa_freqs_t *pxa255_freqs;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100411
412 /* try to guess pxa27x cpu */
413 if (cpu_is_pxa27x())
414 pxa27x_guess_max_freq();
Russell King9e2697f2007-12-14 13:30:14 +0000415
Robert Jarzmik3dbeef22009-05-17 23:03:55 +0200416 pxa_cpufreq_init_voltages();
417
Philipp Zabela10c2872008-06-29 16:53:34 +0200418 init_sdram_rows();
419
Russell King9e2697f2007-12-14 13:30:14 +0000420 /* set default policy and cpuinfo */
Russell King9e2697f2007-12-14 13:30:14 +0000421 policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
Robert Jarzmik36793892008-05-07 20:36:34 +0100422 policy->cur = get_clk_frequency_khz(0); /* current freq */
Russell King9e2697f2007-12-14 13:30:14 +0000423 policy->min = policy->max = policy->cur;
424
Robert Jarzmik592eb992008-05-07 20:39:06 +0100425 /* Generate pxa25x the run cpufreq_frequency_table struct */
426 for (i = 0; i < NUM_PXA25x_RUN_FREQS; i++) {
Russell King9e2697f2007-12-14 13:30:14 +0000427 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz;
428 pxa255_run_freq_table[i].index = i;
429 }
Russell King9e2697f2007-12-14 13:30:14 +0000430 pxa255_run_freq_table[i].frequency = CPUFREQ_TABLE_END;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100431
432 /* Generate pxa25x the turbo cpufreq_frequency_table struct */
433 for (i = 0; i < NUM_PXA25x_TURBO_FREQS; i++) {
Robert Jarzmik36793892008-05-07 20:36:34 +0100434 pxa255_turbo_freq_table[i].frequency =
435 pxa255_turbo_freqs[i].khz;
Russell King9e2697f2007-12-14 13:30:14 +0000436 pxa255_turbo_freq_table[i].index = i;
437 }
438 pxa255_turbo_freq_table[i].frequency = CPUFREQ_TABLE_END;
439
Marc Zyngier65587f72008-11-04 13:33:25 +0100440 pxa255_turbo_table = !!pxa255_turbo_table;
441
Robert Jarzmik592eb992008-05-07 20:39:06 +0100442 /* Generate the pxa27x cpufreq_frequency_table struct */
443 for (i = 0; i < NUM_PXA27x_FREQS; i++) {
444 freq = pxa27x_freqs[i].khz;
445 if (freq > pxa27x_maxfreq)
446 break;
447 pxa27x_freq_table[i].frequency = freq;
448 pxa27x_freq_table[i].index = i;
449 }
450 pxa27x_freq_table[i].frequency = CPUFREQ_TABLE_END;
451
452 /*
453 * Set the policy's minimum and maximum frequencies from the tables
454 * just constructed. This sets cpuinfo.mxx_freq, min and max.
455 */
Marc Zyngier65587f72008-11-04 13:33:25 +0100456 if (cpu_is_pxa25x()) {
457 find_freq_tables(&pxa255_freq_table, &pxa255_freqs);
458 pr_info("PXA255 cpufreq using %s frequency table\n",
459 pxa255_turbo_table ? "turbo" : "run");
460 cpufreq_frequency_table_cpuinfo(policy, pxa255_freq_table);
461 }
Robert Jarzmik592eb992008-05-07 20:39:06 +0100462 else if (cpu_is_pxa27x())
463 cpufreq_frequency_table_cpuinfo(policy, pxa27x_freq_table);
464
Russell King9e2697f2007-12-14 13:30:14 +0000465 printk(KERN_INFO "PXA CPU frequency change support initialized\n");
466
467 return 0;
468}
469
470static struct cpufreq_driver pxa_cpufreq_driver = {
471 .verify = pxa_verify_policy,
472 .target = pxa_set_target,
473 .init = pxa_cpufreq_init,
Holger Schurigea833f02008-02-11 16:53:15 +0100474 .get = pxa_cpufreq_get,
Robert Jarzmik592eb992008-05-07 20:39:06 +0100475 .name = "PXA2xx",
Russell King9e2697f2007-12-14 13:30:14 +0000476};
477
478static int __init pxa_cpu_init(void)
479{
480 int ret = -ENODEV;
Robert Jarzmik592eb992008-05-07 20:39:06 +0100481 if (cpu_is_pxa25x() || cpu_is_pxa27x())
Russell King9e2697f2007-12-14 13:30:14 +0000482 ret = cpufreq_register_driver(&pxa_cpufreq_driver);
483 return ret;
484}
485
486static void __exit pxa_cpu_exit(void)
487{
Robert Jarzmik592eb992008-05-07 20:39:06 +0100488 cpufreq_unregister_driver(&pxa_cpufreq_driver);
Russell King9e2697f2007-12-14 13:30:14 +0000489}
490
491
Robert Jarzmik36793892008-05-07 20:36:34 +0100492MODULE_AUTHOR("Intrinsyc Software Inc.");
493MODULE_DESCRIPTION("CPU frequency changing driver for the PXA architecture");
Russell King9e2697f2007-12-14 13:30:14 +0000494MODULE_LICENSE("GPL");
495module_init(pxa_cpu_init);
496module_exit(pxa_cpu_exit);