Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2014 Advanced Micro Devices, Inc. |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | */ |
| 23 | #include "drmP.h" |
| 24 | #include "amdgpu.h" |
| 25 | #include "amdgpu_pm.h" |
| 26 | #include "amdgpu_i2c.h" |
| 27 | #include "vid.h" |
| 28 | #include "atom.h" |
| 29 | #include "amdgpu_atombios.h" |
| 30 | #include "atombios_crtc.h" |
| 31 | #include "atombios_encoders.h" |
| 32 | #include "amdgpu_pll.h" |
| 33 | #include "amdgpu_connectors.h" |
| 34 | |
| 35 | #include "dce/dce_11_0_d.h" |
| 36 | #include "dce/dce_11_0_sh_mask.h" |
| 37 | #include "dce/dce_11_0_enum.h" |
| 38 | #include "oss/oss_3_0_d.h" |
| 39 | #include "oss/oss_3_0_sh_mask.h" |
| 40 | #include "gmc/gmc_8_1_d.h" |
| 41 | #include "gmc/gmc_8_1_sh_mask.h" |
| 42 | |
| 43 | static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev); |
| 44 | static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev); |
| 45 | |
| 46 | static const u32 crtc_offsets[] = |
| 47 | { |
| 48 | CRTC0_REGISTER_OFFSET, |
| 49 | CRTC1_REGISTER_OFFSET, |
| 50 | CRTC2_REGISTER_OFFSET, |
| 51 | CRTC3_REGISTER_OFFSET, |
| 52 | CRTC4_REGISTER_OFFSET, |
| 53 | CRTC5_REGISTER_OFFSET, |
| 54 | CRTC6_REGISTER_OFFSET |
| 55 | }; |
| 56 | |
| 57 | static const u32 hpd_offsets[] = |
| 58 | { |
| 59 | HPD0_REGISTER_OFFSET, |
| 60 | HPD1_REGISTER_OFFSET, |
| 61 | HPD2_REGISTER_OFFSET, |
| 62 | HPD3_REGISTER_OFFSET, |
| 63 | HPD4_REGISTER_OFFSET, |
| 64 | HPD5_REGISTER_OFFSET |
| 65 | }; |
| 66 | |
| 67 | static const uint32_t dig_offsets[] = { |
| 68 | DIG0_REGISTER_OFFSET, |
| 69 | DIG1_REGISTER_OFFSET, |
| 70 | DIG2_REGISTER_OFFSET, |
| 71 | DIG3_REGISTER_OFFSET, |
| 72 | DIG4_REGISTER_OFFSET, |
| 73 | DIG5_REGISTER_OFFSET, |
| 74 | DIG6_REGISTER_OFFSET, |
| 75 | DIG7_REGISTER_OFFSET, |
| 76 | DIG8_REGISTER_OFFSET |
| 77 | }; |
| 78 | |
| 79 | static const struct { |
| 80 | uint32_t reg; |
| 81 | uint32_t vblank; |
| 82 | uint32_t vline; |
| 83 | uint32_t hpd; |
| 84 | |
| 85 | } interrupt_status_offsets[] = { { |
| 86 | .reg = mmDISP_INTERRUPT_STATUS, |
| 87 | .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK, |
| 88 | .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK, |
| 89 | .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK |
| 90 | }, { |
| 91 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE, |
| 92 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK, |
| 93 | .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK, |
| 94 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK |
| 95 | }, { |
| 96 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2, |
| 97 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK, |
| 98 | .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK, |
| 99 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK |
| 100 | }, { |
| 101 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3, |
| 102 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK, |
| 103 | .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK, |
| 104 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK |
| 105 | }, { |
| 106 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4, |
| 107 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK, |
| 108 | .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK, |
| 109 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK |
| 110 | }, { |
| 111 | .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5, |
| 112 | .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK, |
| 113 | .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK, |
| 114 | .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK |
| 115 | } }; |
| 116 | |
| 117 | static const u32 cz_golden_settings_a11[] = |
| 118 | { |
| 119 | mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000, |
| 120 | mmFBC_MISC, 0x1f311fff, 0x14300000, |
| 121 | }; |
| 122 | |
Alex Deucher | 5732a94 | 2015-06-09 13:51:25 -0400 | [diff] [blame] | 123 | static const u32 cz_mgcg_cgcg_init[] = |
| 124 | { |
| 125 | mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, |
| 126 | mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, |
| 127 | }; |
| 128 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 129 | static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) |
| 130 | { |
| 131 | switch (adev->asic_type) { |
| 132 | case CHIP_CARRIZO: |
| 133 | amdgpu_program_register_sequence(adev, |
Alex Deucher | 5732a94 | 2015-06-09 13:51:25 -0400 | [diff] [blame] | 134 | cz_mgcg_cgcg_init, |
| 135 | (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); |
| 136 | amdgpu_program_register_sequence(adev, |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 137 | cz_golden_settings_a11, |
| 138 | (const u32)ARRAY_SIZE(cz_golden_settings_a11)); |
| 139 | break; |
| 140 | default: |
| 141 | break; |
| 142 | } |
| 143 | } |
| 144 | |
| 145 | static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev, |
| 146 | u32 block_offset, u32 reg) |
| 147 | { |
| 148 | unsigned long flags; |
| 149 | u32 r; |
| 150 | |
| 151 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); |
| 152 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
| 153 | r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset); |
| 154 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); |
| 155 | |
| 156 | return r; |
| 157 | } |
| 158 | |
| 159 | static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev, |
| 160 | u32 block_offset, u32 reg, u32 v) |
| 161 | { |
| 162 | unsigned long flags; |
| 163 | |
| 164 | spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags); |
| 165 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
| 166 | WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v); |
| 167 | spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags); |
| 168 | } |
| 169 | |
| 170 | static bool dce_v11_0_is_in_vblank(struct amdgpu_device *adev, int crtc) |
| 171 | { |
| 172 | if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & |
| 173 | CRTC_V_BLANK_START_END__CRTC_V_BLANK_START_MASK) |
| 174 | return true; |
| 175 | else |
| 176 | return false; |
| 177 | } |
| 178 | |
| 179 | static bool dce_v11_0_is_counter_moving(struct amdgpu_device *adev, int crtc) |
| 180 | { |
| 181 | u32 pos1, pos2; |
| 182 | |
| 183 | pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| 184 | pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| 185 | |
| 186 | if (pos1 != pos2) |
| 187 | return true; |
| 188 | else |
| 189 | return false; |
| 190 | } |
| 191 | |
| 192 | /** |
| 193 | * dce_v11_0_vblank_wait - vblank wait asic callback. |
| 194 | * |
| 195 | * @adev: amdgpu_device pointer |
| 196 | * @crtc: crtc to wait for vblank on |
| 197 | * |
| 198 | * Wait for vblank on the requested crtc (evergreen+). |
| 199 | */ |
| 200 | static void dce_v11_0_vblank_wait(struct amdgpu_device *adev, int crtc) |
| 201 | { |
| 202 | unsigned i = 0; |
| 203 | |
| 204 | if (crtc >= adev->mode_info.num_crtc) |
| 205 | return; |
| 206 | |
| 207 | if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK)) |
| 208 | return; |
| 209 | |
| 210 | /* depending on when we hit vblank, we may be close to active; if so, |
| 211 | * wait for another frame. |
| 212 | */ |
| 213 | while (dce_v11_0_is_in_vblank(adev, crtc)) { |
| 214 | if (i++ % 100 == 0) { |
| 215 | if (!dce_v11_0_is_counter_moving(adev, crtc)) |
| 216 | break; |
| 217 | } |
| 218 | } |
| 219 | |
| 220 | while (!dce_v11_0_is_in_vblank(adev, crtc)) { |
| 221 | if (i++ % 100 == 0) { |
| 222 | if (!dce_v11_0_is_counter_moving(adev, crtc)) |
| 223 | break; |
| 224 | } |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc) |
| 229 | { |
| 230 | if (crtc >= adev->mode_info.num_crtc) |
| 231 | return 0; |
| 232 | else |
| 233 | return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); |
| 234 | } |
| 235 | |
| 236 | /** |
| 237 | * dce_v11_0_page_flip - pageflip callback. |
| 238 | * |
| 239 | * @adev: amdgpu_device pointer |
| 240 | * @crtc_id: crtc to cleanup pageflip on |
| 241 | * @crtc_base: new address of the crtc (GPU MC address) |
| 242 | * |
| 243 | * Does the actual pageflip (evergreen+). |
| 244 | * During vblank we take the crtc lock and wait for the update_pending |
| 245 | * bit to go high, when it does, we release the lock, and allow the |
| 246 | * double buffered update to take place. |
| 247 | * Returns the current update pending status. |
| 248 | */ |
| 249 | static void dce_v11_0_page_flip(struct amdgpu_device *adev, |
| 250 | int crtc_id, u64 crtc_base) |
| 251 | { |
| 252 | struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; |
| 253 | u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset); |
| 254 | int i; |
| 255 | |
| 256 | /* Lock the graphics update lock */ |
| 257 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); |
| 258 | WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); |
| 259 | |
| 260 | /* update the scanout addresses */ |
| 261 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, |
| 262 | upper_32_bits(crtc_base)); |
| 263 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, |
| 264 | lower_32_bits(crtc_base)); |
| 265 | |
| 266 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, |
| 267 | upper_32_bits(crtc_base)); |
| 268 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, |
| 269 | lower_32_bits(crtc_base)); |
| 270 | |
| 271 | /* Wait for update_pending to go high. */ |
| 272 | for (i = 0; i < adev->usec_timeout; i++) { |
| 273 | if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) & |
| 274 | GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) |
| 275 | break; |
| 276 | udelay(1); |
| 277 | } |
| 278 | DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n"); |
| 279 | |
| 280 | /* Unlock the lock, so double-buffering can take place inside vblank */ |
| 281 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); |
| 282 | WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp); |
| 283 | } |
| 284 | |
| 285 | static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, |
| 286 | u32 *vbl, u32 *position) |
| 287 | { |
| 288 | if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) |
| 289 | return -EINVAL; |
| 290 | |
| 291 | *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]); |
| 292 | *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]); |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | /** |
| 298 | * dce_v11_0_hpd_sense - hpd sense callback. |
| 299 | * |
| 300 | * @adev: amdgpu_device pointer |
| 301 | * @hpd: hpd (hotplug detect) pin |
| 302 | * |
| 303 | * Checks if a digital monitor is connected (evergreen+). |
| 304 | * Returns true if connected, false if not connected. |
| 305 | */ |
| 306 | static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev, |
| 307 | enum amdgpu_hpd_id hpd) |
| 308 | { |
| 309 | int idx; |
| 310 | bool connected = false; |
| 311 | |
| 312 | switch (hpd) { |
| 313 | case AMDGPU_HPD_1: |
| 314 | idx = 0; |
| 315 | break; |
| 316 | case AMDGPU_HPD_2: |
| 317 | idx = 1; |
| 318 | break; |
| 319 | case AMDGPU_HPD_3: |
| 320 | idx = 2; |
| 321 | break; |
| 322 | case AMDGPU_HPD_4: |
| 323 | idx = 3; |
| 324 | break; |
| 325 | case AMDGPU_HPD_5: |
| 326 | idx = 4; |
| 327 | break; |
| 328 | case AMDGPU_HPD_6: |
| 329 | idx = 5; |
| 330 | break; |
| 331 | default: |
| 332 | return connected; |
| 333 | } |
| 334 | |
| 335 | if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[idx]) & |
| 336 | DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK) |
| 337 | connected = true; |
| 338 | |
| 339 | return connected; |
| 340 | } |
| 341 | |
| 342 | /** |
| 343 | * dce_v11_0_hpd_set_polarity - hpd set polarity callback. |
| 344 | * |
| 345 | * @adev: amdgpu_device pointer |
| 346 | * @hpd: hpd (hotplug detect) pin |
| 347 | * |
| 348 | * Set the polarity of the hpd pin (evergreen+). |
| 349 | */ |
| 350 | static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev, |
| 351 | enum amdgpu_hpd_id hpd) |
| 352 | { |
| 353 | u32 tmp; |
| 354 | bool connected = dce_v11_0_hpd_sense(adev, hpd); |
| 355 | int idx; |
| 356 | |
| 357 | switch (hpd) { |
| 358 | case AMDGPU_HPD_1: |
| 359 | idx = 0; |
| 360 | break; |
| 361 | case AMDGPU_HPD_2: |
| 362 | idx = 1; |
| 363 | break; |
| 364 | case AMDGPU_HPD_3: |
| 365 | idx = 2; |
| 366 | break; |
| 367 | case AMDGPU_HPD_4: |
| 368 | idx = 3; |
| 369 | break; |
| 370 | case AMDGPU_HPD_5: |
| 371 | idx = 4; |
| 372 | break; |
| 373 | case AMDGPU_HPD_6: |
| 374 | idx = 5; |
| 375 | break; |
| 376 | default: |
| 377 | return; |
| 378 | } |
| 379 | |
| 380 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx]); |
| 381 | if (connected) |
| 382 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0); |
| 383 | else |
| 384 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1); |
| 385 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[idx], tmp); |
| 386 | } |
| 387 | |
| 388 | /** |
| 389 | * dce_v11_0_hpd_init - hpd setup callback. |
| 390 | * |
| 391 | * @adev: amdgpu_device pointer |
| 392 | * |
| 393 | * Setup the hpd pins used by the card (evergreen+). |
| 394 | * Enable the pin, set the polarity, and enable the hpd interrupts. |
| 395 | */ |
| 396 | static void dce_v11_0_hpd_init(struct amdgpu_device *adev) |
| 397 | { |
| 398 | struct drm_device *dev = adev->ddev; |
| 399 | struct drm_connector *connector; |
| 400 | u32 tmp; |
| 401 | int idx; |
| 402 | |
| 403 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 404 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); |
| 405 | |
| 406 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP || |
| 407 | connector->connector_type == DRM_MODE_CONNECTOR_LVDS) { |
| 408 | /* don't try to enable hpd on eDP or LVDS avoid breaking the |
| 409 | * aux dp channel on imac and help (but not completely fix) |
| 410 | * https://bugzilla.redhat.com/show_bug.cgi?id=726143 |
| 411 | * also avoid interrupt storms during dpms. |
| 412 | */ |
| 413 | continue; |
| 414 | } |
| 415 | |
| 416 | switch (amdgpu_connector->hpd.hpd) { |
| 417 | case AMDGPU_HPD_1: |
| 418 | idx = 0; |
| 419 | break; |
| 420 | case AMDGPU_HPD_2: |
| 421 | idx = 1; |
| 422 | break; |
| 423 | case AMDGPU_HPD_3: |
| 424 | idx = 2; |
| 425 | break; |
| 426 | case AMDGPU_HPD_4: |
| 427 | idx = 3; |
| 428 | break; |
| 429 | case AMDGPU_HPD_5: |
| 430 | idx = 4; |
| 431 | break; |
| 432 | case AMDGPU_HPD_6: |
| 433 | idx = 5; |
| 434 | break; |
| 435 | default: |
| 436 | continue; |
| 437 | } |
| 438 | |
| 439 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); |
| 440 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1); |
| 441 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); |
| 442 | |
| 443 | tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx]); |
| 444 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, |
| 445 | DC_HPD_CONNECT_INT_DELAY, |
| 446 | AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS); |
| 447 | tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL, |
| 448 | DC_HPD_DISCONNECT_INT_DELAY, |
| 449 | AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS); |
| 450 | WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[idx], tmp); |
| 451 | |
| 452 | dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); |
| 453 | amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); |
| 454 | } |
| 455 | } |
| 456 | |
| 457 | /** |
| 458 | * dce_v11_0_hpd_fini - hpd tear down callback. |
| 459 | * |
| 460 | * @adev: amdgpu_device pointer |
| 461 | * |
| 462 | * Tear down the hpd pins used by the card (evergreen+). |
| 463 | * Disable the hpd interrupts. |
| 464 | */ |
| 465 | static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) |
| 466 | { |
| 467 | struct drm_device *dev = adev->ddev; |
| 468 | struct drm_connector *connector; |
| 469 | u32 tmp; |
| 470 | int idx; |
| 471 | |
| 472 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { |
| 473 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); |
| 474 | |
| 475 | switch (amdgpu_connector->hpd.hpd) { |
| 476 | case AMDGPU_HPD_1: |
| 477 | idx = 0; |
| 478 | break; |
| 479 | case AMDGPU_HPD_2: |
| 480 | idx = 1; |
| 481 | break; |
| 482 | case AMDGPU_HPD_3: |
| 483 | idx = 2; |
| 484 | break; |
| 485 | case AMDGPU_HPD_4: |
| 486 | idx = 3; |
| 487 | break; |
| 488 | case AMDGPU_HPD_5: |
| 489 | idx = 4; |
| 490 | break; |
| 491 | case AMDGPU_HPD_6: |
| 492 | idx = 5; |
| 493 | break; |
| 494 | default: |
| 495 | continue; |
| 496 | } |
| 497 | |
| 498 | tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[idx]); |
| 499 | tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0); |
| 500 | WREG32(mmDC_HPD_CONTROL + hpd_offsets[idx], tmp); |
| 501 | |
| 502 | amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); |
| 503 | } |
| 504 | } |
| 505 | |
| 506 | static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) |
| 507 | { |
| 508 | return mmDC_GPIO_HPD_A; |
| 509 | } |
| 510 | |
| 511 | static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev) |
| 512 | { |
| 513 | u32 crtc_hung = 0; |
| 514 | u32 crtc_status[6]; |
| 515 | u32 i, j, tmp; |
| 516 | |
| 517 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 518 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); |
| 519 | if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) { |
| 520 | crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); |
| 521 | crtc_hung |= (1 << i); |
| 522 | } |
| 523 | } |
| 524 | |
| 525 | for (j = 0; j < 10; j++) { |
| 526 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 527 | if (crtc_hung & (1 << i)) { |
| 528 | tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]); |
| 529 | if (tmp != crtc_status[i]) |
| 530 | crtc_hung &= ~(1 << i); |
| 531 | } |
| 532 | } |
| 533 | if (crtc_hung == 0) |
| 534 | return false; |
| 535 | udelay(100); |
| 536 | } |
| 537 | |
| 538 | return true; |
| 539 | } |
| 540 | |
| 541 | static void dce_v11_0_stop_mc_access(struct amdgpu_device *adev, |
| 542 | struct amdgpu_mode_mc_save *save) |
| 543 | { |
| 544 | u32 crtc_enabled, tmp; |
| 545 | int i; |
| 546 | |
| 547 | save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL); |
| 548 | save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL); |
| 549 | |
| 550 | /* disable VGA render */ |
| 551 | tmp = RREG32(mmVGA_RENDER_CONTROL); |
| 552 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); |
| 553 | WREG32(mmVGA_RENDER_CONTROL, tmp); |
| 554 | |
| 555 | /* blank the display controllers */ |
| 556 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 557 | crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), |
| 558 | CRTC_CONTROL, CRTC_MASTER_EN); |
| 559 | if (crtc_enabled) { |
| 560 | #if 0 |
| 561 | u32 frame_count; |
| 562 | int j; |
| 563 | |
| 564 | save->crtc_enabled[i] = true; |
| 565 | tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); |
| 566 | if (REG_GET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN) == 0) { |
| 567 | amdgpu_display_vblank_wait(adev, i); |
| 568 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| 569 | tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 1); |
| 570 | WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); |
| 571 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| 572 | } |
| 573 | /* wait for the next frame */ |
| 574 | frame_count = amdgpu_display_vblank_get_counter(adev, i); |
| 575 | for (j = 0; j < adev->usec_timeout; j++) { |
| 576 | if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) |
| 577 | break; |
| 578 | udelay(1); |
| 579 | } |
| 580 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); |
| 581 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK) == 0) { |
| 582 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1); |
| 583 | WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); |
| 584 | } |
| 585 | tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
| 586 | if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK) == 0) { |
| 587 | tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 1); |
| 588 | WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
| 589 | } |
| 590 | #else |
| 591 | /* XXX this is a hack to avoid strange behavior with EFI on certain systems */ |
| 592 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| 593 | tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); |
| 594 | tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0); |
| 595 | WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); |
| 596 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| 597 | save->crtc_enabled[i] = false; |
| 598 | /* ***** */ |
| 599 | #endif |
| 600 | } else { |
| 601 | save->crtc_enabled[i] = false; |
| 602 | } |
| 603 | } |
| 604 | } |
| 605 | |
| 606 | static void dce_v11_0_resume_mc_access(struct amdgpu_device *adev, |
| 607 | struct amdgpu_mode_mc_save *save) |
| 608 | { |
| 609 | u32 tmp, frame_count; |
| 610 | int i, j; |
| 611 | |
| 612 | /* update crtc base addresses */ |
| 613 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 614 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], |
| 615 | upper_32_bits(adev->mc.vram_start)); |
| 616 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i], |
| 617 | upper_32_bits(adev->mc.vram_start)); |
| 618 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i], |
| 619 | (u32)adev->mc.vram_start); |
| 620 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], |
| 621 | (u32)adev->mc.vram_start); |
| 622 | |
| 623 | if (save->crtc_enabled[i]) { |
| 624 | tmp = RREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i]); |
| 625 | if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE) != 3) { |
| 626 | tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_MODE, MASTER_UPDATE_MODE, 3); |
| 627 | WREG32(mmCRTC_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); |
| 628 | } |
| 629 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); |
| 630 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK)) { |
| 631 | tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0); |
| 632 | WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp); |
| 633 | } |
| 634 | tmp = RREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i]); |
| 635 | if (REG_GET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK)) { |
| 636 | tmp = REG_SET_FIELD(tmp, CRTC_MASTER_UPDATE_LOCK, MASTER_UPDATE_LOCK, 0); |
| 637 | WREG32(mmCRTC_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); |
| 638 | } |
| 639 | for (j = 0; j < adev->usec_timeout; j++) { |
| 640 | tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); |
| 641 | if (REG_GET_FIELD(tmp, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING) == 0) |
| 642 | break; |
| 643 | udelay(1); |
| 644 | } |
| 645 | tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]); |
| 646 | tmp = REG_SET_FIELD(tmp, CRTC_BLANK_CONTROL, CRTC_BLANK_DATA_EN, 0); |
| 647 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1); |
| 648 | WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp); |
| 649 | WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0); |
| 650 | /* wait for the next frame */ |
| 651 | frame_count = amdgpu_display_vblank_get_counter(adev, i); |
| 652 | for (j = 0; j < adev->usec_timeout; j++) { |
| 653 | if (amdgpu_display_vblank_get_counter(adev, i) != frame_count) |
| 654 | break; |
| 655 | udelay(1); |
| 656 | } |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start)); |
| 661 | WREG32(mmVGA_MEMORY_BASE_ADDRESS, lower_32_bits(adev->mc.vram_start)); |
| 662 | |
| 663 | /* Unlock vga access */ |
| 664 | WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control); |
| 665 | mdelay(1); |
| 666 | WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control); |
| 667 | } |
| 668 | |
| 669 | static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev, |
| 670 | bool render) |
| 671 | { |
| 672 | u32 tmp; |
| 673 | |
| 674 | /* Lockout access through VGA aperture*/ |
| 675 | tmp = RREG32(mmVGA_HDP_CONTROL); |
| 676 | if (render) |
| 677 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0); |
| 678 | else |
| 679 | tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1); |
| 680 | WREG32(mmVGA_HDP_CONTROL, tmp); |
| 681 | |
| 682 | /* disable VGA render */ |
| 683 | tmp = RREG32(mmVGA_RENDER_CONTROL); |
| 684 | if (render) |
| 685 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1); |
| 686 | else |
| 687 | tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0); |
| 688 | WREG32(mmVGA_RENDER_CONTROL, tmp); |
| 689 | } |
| 690 | |
| 691 | static void dce_v11_0_program_fmt(struct drm_encoder *encoder) |
| 692 | { |
| 693 | struct drm_device *dev = encoder->dev; |
| 694 | struct amdgpu_device *adev = dev->dev_private; |
| 695 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 696 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); |
| 697 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); |
| 698 | int bpc = 0; |
| 699 | u32 tmp = 0; |
| 700 | enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE; |
| 701 | |
| 702 | if (connector) { |
| 703 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); |
| 704 | bpc = amdgpu_connector_get_monitor_bpc(connector); |
| 705 | dither = amdgpu_connector->dither; |
| 706 | } |
| 707 | |
| 708 | /* LVDS/eDP FMT is set up by atom */ |
| 709 | if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT) |
| 710 | return; |
| 711 | |
| 712 | /* not needed for analog */ |
| 713 | if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) || |
| 714 | (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2)) |
| 715 | return; |
| 716 | |
| 717 | if (bpc == 0) |
| 718 | return; |
| 719 | |
| 720 | switch (bpc) { |
| 721 | case 6: |
| 722 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { |
| 723 | /* XXX sort out optimal dither settings */ |
| 724 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); |
| 725 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); |
| 726 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); |
| 727 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); |
| 728 | } else { |
| 729 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); |
| 730 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); |
| 731 | } |
| 732 | break; |
| 733 | case 8: |
| 734 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { |
| 735 | /* XXX sort out optimal dither settings */ |
| 736 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); |
| 737 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); |
| 738 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); |
| 739 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); |
| 740 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1); |
| 741 | } else { |
| 742 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); |
| 743 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1); |
| 744 | } |
| 745 | break; |
| 746 | case 10: |
| 747 | if (dither == AMDGPU_FMT_DITHER_ENABLE) { |
| 748 | /* XXX sort out optimal dither settings */ |
| 749 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); |
| 750 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); |
| 751 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); |
| 752 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); |
| 753 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2); |
| 754 | } else { |
| 755 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); |
| 756 | tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2); |
| 757 | } |
| 758 | break; |
| 759 | default: |
| 760 | /* not needed */ |
| 761 | break; |
| 762 | } |
| 763 | |
| 764 | WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 765 | } |
| 766 | |
| 767 | |
| 768 | /* display watermark setup */ |
| 769 | /** |
| 770 | * dce_v11_0_line_buffer_adjust - Set up the line buffer |
| 771 | * |
| 772 | * @adev: amdgpu_device pointer |
| 773 | * @amdgpu_crtc: the selected display controller |
| 774 | * @mode: the current display mode on the selected display |
| 775 | * controller |
| 776 | * |
| 777 | * Setup up the line buffer allocation for |
| 778 | * the selected display controller (CIK). |
| 779 | * Returns the line buffer size in pixels. |
| 780 | */ |
| 781 | static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev, |
| 782 | struct amdgpu_crtc *amdgpu_crtc, |
| 783 | struct drm_display_mode *mode) |
| 784 | { |
| 785 | u32 tmp, buffer_alloc, i, mem_cfg; |
| 786 | u32 pipe_offset = amdgpu_crtc->crtc_id; |
| 787 | /* |
| 788 | * Line Buffer Setup |
| 789 | * There are 6 line buffers, one for each display controllers. |
| 790 | * There are 3 partitions per LB. Select the number of partitions |
| 791 | * to enable based on the display width. For display widths larger |
| 792 | * than 4096, you need use to use 2 display controllers and combine |
| 793 | * them using the stereo blender. |
| 794 | */ |
| 795 | if (amdgpu_crtc->base.enabled && mode) { |
| 796 | if (mode->crtc_hdisplay < 1920) { |
| 797 | mem_cfg = 1; |
| 798 | buffer_alloc = 2; |
| 799 | } else if (mode->crtc_hdisplay < 2560) { |
| 800 | mem_cfg = 2; |
| 801 | buffer_alloc = 2; |
| 802 | } else if (mode->crtc_hdisplay < 4096) { |
| 803 | mem_cfg = 0; |
| 804 | buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; |
| 805 | } else { |
| 806 | DRM_DEBUG_KMS("Mode too big for LB!\n"); |
| 807 | mem_cfg = 0; |
| 808 | buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; |
| 809 | } |
| 810 | } else { |
| 811 | mem_cfg = 1; |
| 812 | buffer_alloc = 0; |
| 813 | } |
| 814 | |
| 815 | tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset); |
| 816 | tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg); |
| 817 | WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp); |
| 818 | |
| 819 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); |
| 820 | tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc); |
| 821 | WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp); |
| 822 | |
| 823 | for (i = 0; i < adev->usec_timeout; i++) { |
| 824 | tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset); |
| 825 | if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED)) |
| 826 | break; |
| 827 | udelay(1); |
| 828 | } |
| 829 | |
| 830 | if (amdgpu_crtc->base.enabled && mode) { |
| 831 | switch (mem_cfg) { |
| 832 | case 0: |
| 833 | default: |
| 834 | return 4096 * 2; |
| 835 | case 1: |
| 836 | return 1920 * 2; |
| 837 | case 2: |
| 838 | return 2560 * 2; |
| 839 | } |
| 840 | } |
| 841 | |
| 842 | /* controller not enabled, so no lb used */ |
| 843 | return 0; |
| 844 | } |
| 845 | |
| 846 | /** |
| 847 | * cik_get_number_of_dram_channels - get the number of dram channels |
| 848 | * |
| 849 | * @adev: amdgpu_device pointer |
| 850 | * |
| 851 | * Look up the number of video ram channels (CIK). |
| 852 | * Used for display watermark bandwidth calculations |
| 853 | * Returns the number of dram channels |
| 854 | */ |
| 855 | static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev) |
| 856 | { |
| 857 | u32 tmp = RREG32(mmMC_SHARED_CHMAP); |
| 858 | |
| 859 | switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) { |
| 860 | case 0: |
| 861 | default: |
| 862 | return 1; |
| 863 | case 1: |
| 864 | return 2; |
| 865 | case 2: |
| 866 | return 4; |
| 867 | case 3: |
| 868 | return 8; |
| 869 | case 4: |
| 870 | return 3; |
| 871 | case 5: |
| 872 | return 6; |
| 873 | case 6: |
| 874 | return 10; |
| 875 | case 7: |
| 876 | return 12; |
| 877 | case 8: |
| 878 | return 16; |
| 879 | } |
| 880 | } |
| 881 | |
| 882 | struct dce10_wm_params { |
| 883 | u32 dram_channels; /* number of dram channels */ |
| 884 | u32 yclk; /* bandwidth per dram data pin in kHz */ |
| 885 | u32 sclk; /* engine clock in kHz */ |
| 886 | u32 disp_clk; /* display clock in kHz */ |
| 887 | u32 src_width; /* viewport width */ |
| 888 | u32 active_time; /* active display time in ns */ |
| 889 | u32 blank_time; /* blank time in ns */ |
| 890 | bool interlaced; /* mode is interlaced */ |
| 891 | fixed20_12 vsc; /* vertical scale ratio */ |
| 892 | u32 num_heads; /* number of active crtcs */ |
| 893 | u32 bytes_per_pixel; /* bytes per pixel display + overlay */ |
| 894 | u32 lb_size; /* line buffer allocated to pipe */ |
| 895 | u32 vtaps; /* vertical scaler taps */ |
| 896 | }; |
| 897 | |
| 898 | /** |
| 899 | * dce_v11_0_dram_bandwidth - get the dram bandwidth |
| 900 | * |
| 901 | * @wm: watermark calculation data |
| 902 | * |
| 903 | * Calculate the raw dram bandwidth (CIK). |
| 904 | * Used for display watermark bandwidth calculations |
| 905 | * Returns the dram bandwidth in MBytes/s |
| 906 | */ |
| 907 | static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) |
| 908 | { |
| 909 | /* Calculate raw DRAM Bandwidth */ |
| 910 | fixed20_12 dram_efficiency; /* 0.7 */ |
| 911 | fixed20_12 yclk, dram_channels, bandwidth; |
| 912 | fixed20_12 a; |
| 913 | |
| 914 | a.full = dfixed_const(1000); |
| 915 | yclk.full = dfixed_const(wm->yclk); |
| 916 | yclk.full = dfixed_div(yclk, a); |
| 917 | dram_channels.full = dfixed_const(wm->dram_channels * 4); |
| 918 | a.full = dfixed_const(10); |
| 919 | dram_efficiency.full = dfixed_const(7); |
| 920 | dram_efficiency.full = dfixed_div(dram_efficiency, a); |
| 921 | bandwidth.full = dfixed_mul(dram_channels, yclk); |
| 922 | bandwidth.full = dfixed_mul(bandwidth, dram_efficiency); |
| 923 | |
| 924 | return dfixed_trunc(bandwidth); |
| 925 | } |
| 926 | |
| 927 | /** |
| 928 | * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display |
| 929 | * |
| 930 | * @wm: watermark calculation data |
| 931 | * |
| 932 | * Calculate the dram bandwidth used for display (CIK). |
| 933 | * Used for display watermark bandwidth calculations |
| 934 | * Returns the dram bandwidth for display in MBytes/s |
| 935 | */ |
| 936 | static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) |
| 937 | { |
| 938 | /* Calculate DRAM Bandwidth and the part allocated to display. */ |
| 939 | fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */ |
| 940 | fixed20_12 yclk, dram_channels, bandwidth; |
| 941 | fixed20_12 a; |
| 942 | |
| 943 | a.full = dfixed_const(1000); |
| 944 | yclk.full = dfixed_const(wm->yclk); |
| 945 | yclk.full = dfixed_div(yclk, a); |
| 946 | dram_channels.full = dfixed_const(wm->dram_channels * 4); |
| 947 | a.full = dfixed_const(10); |
| 948 | disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */ |
| 949 | disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a); |
| 950 | bandwidth.full = dfixed_mul(dram_channels, yclk); |
| 951 | bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation); |
| 952 | |
| 953 | return dfixed_trunc(bandwidth); |
| 954 | } |
| 955 | |
| 956 | /** |
| 957 | * dce_v11_0_data_return_bandwidth - get the data return bandwidth |
| 958 | * |
| 959 | * @wm: watermark calculation data |
| 960 | * |
| 961 | * Calculate the data return bandwidth used for display (CIK). |
| 962 | * Used for display watermark bandwidth calculations |
| 963 | * Returns the data return bandwidth in MBytes/s |
| 964 | */ |
| 965 | static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) |
| 966 | { |
| 967 | /* Calculate the display Data return Bandwidth */ |
| 968 | fixed20_12 return_efficiency; /* 0.8 */ |
| 969 | fixed20_12 sclk, bandwidth; |
| 970 | fixed20_12 a; |
| 971 | |
| 972 | a.full = dfixed_const(1000); |
| 973 | sclk.full = dfixed_const(wm->sclk); |
| 974 | sclk.full = dfixed_div(sclk, a); |
| 975 | a.full = dfixed_const(10); |
| 976 | return_efficiency.full = dfixed_const(8); |
| 977 | return_efficiency.full = dfixed_div(return_efficiency, a); |
| 978 | a.full = dfixed_const(32); |
| 979 | bandwidth.full = dfixed_mul(a, sclk); |
| 980 | bandwidth.full = dfixed_mul(bandwidth, return_efficiency); |
| 981 | |
| 982 | return dfixed_trunc(bandwidth); |
| 983 | } |
| 984 | |
| 985 | /** |
| 986 | * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth |
| 987 | * |
| 988 | * @wm: watermark calculation data |
| 989 | * |
| 990 | * Calculate the dmif bandwidth used for display (CIK). |
| 991 | * Used for display watermark bandwidth calculations |
| 992 | * Returns the dmif bandwidth in MBytes/s |
| 993 | */ |
| 994 | static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) |
| 995 | { |
| 996 | /* Calculate the DMIF Request Bandwidth */ |
| 997 | fixed20_12 disp_clk_request_efficiency; /* 0.8 */ |
| 998 | fixed20_12 disp_clk, bandwidth; |
| 999 | fixed20_12 a, b; |
| 1000 | |
| 1001 | a.full = dfixed_const(1000); |
| 1002 | disp_clk.full = dfixed_const(wm->disp_clk); |
| 1003 | disp_clk.full = dfixed_div(disp_clk, a); |
| 1004 | a.full = dfixed_const(32); |
| 1005 | b.full = dfixed_mul(a, disp_clk); |
| 1006 | |
| 1007 | a.full = dfixed_const(10); |
| 1008 | disp_clk_request_efficiency.full = dfixed_const(8); |
| 1009 | disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a); |
| 1010 | |
| 1011 | bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency); |
| 1012 | |
| 1013 | return dfixed_trunc(bandwidth); |
| 1014 | } |
| 1015 | |
| 1016 | /** |
| 1017 | * dce_v11_0_available_bandwidth - get the min available bandwidth |
| 1018 | * |
| 1019 | * @wm: watermark calculation data |
| 1020 | * |
| 1021 | * Calculate the min available bandwidth used for display (CIK). |
| 1022 | * Used for display watermark bandwidth calculations |
| 1023 | * Returns the min available bandwidth in MBytes/s |
| 1024 | */ |
| 1025 | static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) |
| 1026 | { |
| 1027 | /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */ |
| 1028 | u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); |
| 1029 | u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); |
| 1030 | u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); |
| 1031 | |
| 1032 | return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth)); |
| 1033 | } |
| 1034 | |
| 1035 | /** |
| 1036 | * dce_v11_0_average_bandwidth - get the average available bandwidth |
| 1037 | * |
| 1038 | * @wm: watermark calculation data |
| 1039 | * |
| 1040 | * Calculate the average available bandwidth used for display (CIK). |
| 1041 | * Used for display watermark bandwidth calculations |
| 1042 | * Returns the average available bandwidth in MBytes/s |
| 1043 | */ |
| 1044 | static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) |
| 1045 | { |
| 1046 | /* Calculate the display mode Average Bandwidth |
| 1047 | * DisplayMode should contain the source and destination dimensions, |
| 1048 | * timing, etc. |
| 1049 | */ |
| 1050 | fixed20_12 bpp; |
| 1051 | fixed20_12 line_time; |
| 1052 | fixed20_12 src_width; |
| 1053 | fixed20_12 bandwidth; |
| 1054 | fixed20_12 a; |
| 1055 | |
| 1056 | a.full = dfixed_const(1000); |
| 1057 | line_time.full = dfixed_const(wm->active_time + wm->blank_time); |
| 1058 | line_time.full = dfixed_div(line_time, a); |
| 1059 | bpp.full = dfixed_const(wm->bytes_per_pixel); |
| 1060 | src_width.full = dfixed_const(wm->src_width); |
| 1061 | bandwidth.full = dfixed_mul(src_width, bpp); |
| 1062 | bandwidth.full = dfixed_mul(bandwidth, wm->vsc); |
| 1063 | bandwidth.full = dfixed_div(bandwidth, line_time); |
| 1064 | |
| 1065 | return dfixed_trunc(bandwidth); |
| 1066 | } |
| 1067 | |
| 1068 | /** |
| 1069 | * dce_v11_0_latency_watermark - get the latency watermark |
| 1070 | * |
| 1071 | * @wm: watermark calculation data |
| 1072 | * |
| 1073 | * Calculate the latency watermark (CIK). |
| 1074 | * Used for display watermark bandwidth calculations |
| 1075 | * Returns the latency watermark in ns |
| 1076 | */ |
| 1077 | static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) |
| 1078 | { |
| 1079 | /* First calculate the latency in ns */ |
| 1080 | u32 mc_latency = 2000; /* 2000 ns. */ |
| 1081 | u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); |
| 1082 | u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth; |
| 1083 | u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth; |
| 1084 | u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ |
| 1085 | u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + |
| 1086 | (wm->num_heads * cursor_line_pair_return_time); |
| 1087 | u32 latency = mc_latency + other_heads_data_return_time + dc_latency; |
| 1088 | u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time; |
| 1089 | u32 tmp, dmif_size = 12288; |
| 1090 | fixed20_12 a, b, c; |
| 1091 | |
| 1092 | if (wm->num_heads == 0) |
| 1093 | return 0; |
| 1094 | |
| 1095 | a.full = dfixed_const(2); |
| 1096 | b.full = dfixed_const(1); |
| 1097 | if ((wm->vsc.full > a.full) || |
| 1098 | ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || |
| 1099 | (wm->vtaps >= 5) || |
| 1100 | ((wm->vsc.full >= a.full) && wm->interlaced)) |
| 1101 | max_src_lines_per_dst_line = 4; |
| 1102 | else |
| 1103 | max_src_lines_per_dst_line = 2; |
| 1104 | |
| 1105 | a.full = dfixed_const(available_bandwidth); |
| 1106 | b.full = dfixed_const(wm->num_heads); |
| 1107 | a.full = dfixed_div(a, b); |
| 1108 | |
| 1109 | b.full = dfixed_const(mc_latency + 512); |
| 1110 | c.full = dfixed_const(wm->disp_clk); |
| 1111 | b.full = dfixed_div(b, c); |
| 1112 | |
| 1113 | c.full = dfixed_const(dmif_size); |
| 1114 | b.full = dfixed_div(c, b); |
| 1115 | |
| 1116 | tmp = min(dfixed_trunc(a), dfixed_trunc(b)); |
| 1117 | |
| 1118 | b.full = dfixed_const(1000); |
| 1119 | c.full = dfixed_const(wm->disp_clk); |
| 1120 | b.full = dfixed_div(c, b); |
| 1121 | c.full = dfixed_const(wm->bytes_per_pixel); |
| 1122 | b.full = dfixed_mul(b, c); |
| 1123 | |
| 1124 | lb_fill_bw = min(tmp, dfixed_trunc(b)); |
| 1125 | |
| 1126 | a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); |
| 1127 | b.full = dfixed_const(1000); |
| 1128 | c.full = dfixed_const(lb_fill_bw); |
| 1129 | b.full = dfixed_div(c, b); |
| 1130 | a.full = dfixed_div(a, b); |
| 1131 | line_fill_time = dfixed_trunc(a); |
| 1132 | |
| 1133 | if (line_fill_time < wm->active_time) |
| 1134 | return latency; |
| 1135 | else |
| 1136 | return latency + (line_fill_time - wm->active_time); |
| 1137 | |
| 1138 | } |
| 1139 | |
| 1140 | /** |
| 1141 | * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check |
| 1142 | * average and available dram bandwidth |
| 1143 | * |
| 1144 | * @wm: watermark calculation data |
| 1145 | * |
| 1146 | * Check if the display average bandwidth fits in the display |
| 1147 | * dram bandwidth (CIK). |
| 1148 | * Used for display watermark bandwidth calculations |
| 1149 | * Returns true if the display fits, false if not. |
| 1150 | */ |
| 1151 | static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) |
| 1152 | { |
| 1153 | if (dce_v11_0_average_bandwidth(wm) <= |
| 1154 | (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) |
| 1155 | return true; |
| 1156 | else |
| 1157 | return false; |
| 1158 | } |
| 1159 | |
| 1160 | /** |
| 1161 | * dce_v11_0_average_bandwidth_vs_available_bandwidth - check |
| 1162 | * average and available bandwidth |
| 1163 | * |
| 1164 | * @wm: watermark calculation data |
| 1165 | * |
| 1166 | * Check if the display average bandwidth fits in the display |
| 1167 | * available bandwidth (CIK). |
| 1168 | * Used for display watermark bandwidth calculations |
| 1169 | * Returns true if the display fits, false if not. |
| 1170 | */ |
| 1171 | static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) |
| 1172 | { |
| 1173 | if (dce_v11_0_average_bandwidth(wm) <= |
| 1174 | (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) |
| 1175 | return true; |
| 1176 | else |
| 1177 | return false; |
| 1178 | } |
| 1179 | |
| 1180 | /** |
| 1181 | * dce_v11_0_check_latency_hiding - check latency hiding |
| 1182 | * |
| 1183 | * @wm: watermark calculation data |
| 1184 | * |
| 1185 | * Check latency hiding (CIK). |
| 1186 | * Used for display watermark bandwidth calculations |
| 1187 | * Returns true if the display fits, false if not. |
| 1188 | */ |
| 1189 | static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) |
| 1190 | { |
| 1191 | u32 lb_partitions = wm->lb_size / wm->src_width; |
| 1192 | u32 line_time = wm->active_time + wm->blank_time; |
| 1193 | u32 latency_tolerant_lines; |
| 1194 | u32 latency_hiding; |
| 1195 | fixed20_12 a; |
| 1196 | |
| 1197 | a.full = dfixed_const(1); |
| 1198 | if (wm->vsc.full > a.full) |
| 1199 | latency_tolerant_lines = 1; |
| 1200 | else { |
| 1201 | if (lb_partitions <= (wm->vtaps + 1)) |
| 1202 | latency_tolerant_lines = 1; |
| 1203 | else |
| 1204 | latency_tolerant_lines = 2; |
| 1205 | } |
| 1206 | |
| 1207 | latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); |
| 1208 | |
| 1209 | if (dce_v11_0_latency_watermark(wm) <= latency_hiding) |
| 1210 | return true; |
| 1211 | else |
| 1212 | return false; |
| 1213 | } |
| 1214 | |
| 1215 | /** |
| 1216 | * dce_v11_0_program_watermarks - program display watermarks |
| 1217 | * |
| 1218 | * @adev: amdgpu_device pointer |
| 1219 | * @amdgpu_crtc: the selected display controller |
| 1220 | * @lb_size: line buffer size |
| 1221 | * @num_heads: number of display controllers in use |
| 1222 | * |
| 1223 | * Calculate and program the display watermarks for the |
| 1224 | * selected display controller (CIK). |
| 1225 | */ |
| 1226 | static void dce_v11_0_program_watermarks(struct amdgpu_device *adev, |
| 1227 | struct amdgpu_crtc *amdgpu_crtc, |
| 1228 | u32 lb_size, u32 num_heads) |
| 1229 | { |
| 1230 | struct drm_display_mode *mode = &amdgpu_crtc->base.mode; |
| 1231 | struct dce10_wm_params wm_low, wm_high; |
| 1232 | u32 pixel_period; |
| 1233 | u32 line_time = 0; |
| 1234 | u32 latency_watermark_a = 0, latency_watermark_b = 0; |
| 1235 | u32 tmp, wm_mask; |
| 1236 | |
| 1237 | if (amdgpu_crtc->base.enabled && num_heads && mode) { |
| 1238 | pixel_period = 1000000 / (u32)mode->clock; |
| 1239 | line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535); |
| 1240 | |
| 1241 | /* watermark for high clocks */ |
| 1242 | if (adev->pm.dpm_enabled) { |
| 1243 | wm_high.yclk = |
| 1244 | amdgpu_dpm_get_mclk(adev, false) * 10; |
| 1245 | wm_high.sclk = |
| 1246 | amdgpu_dpm_get_sclk(adev, false) * 10; |
| 1247 | } else { |
| 1248 | wm_high.yclk = adev->pm.current_mclk * 10; |
| 1249 | wm_high.sclk = adev->pm.current_sclk * 10; |
| 1250 | } |
| 1251 | |
| 1252 | wm_high.disp_clk = mode->clock; |
| 1253 | wm_high.src_width = mode->crtc_hdisplay; |
| 1254 | wm_high.active_time = mode->crtc_hdisplay * pixel_period; |
| 1255 | wm_high.blank_time = line_time - wm_high.active_time; |
| 1256 | wm_high.interlaced = false; |
| 1257 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1258 | wm_high.interlaced = true; |
| 1259 | wm_high.vsc = amdgpu_crtc->vsc; |
| 1260 | wm_high.vtaps = 1; |
| 1261 | if (amdgpu_crtc->rmx_type != RMX_OFF) |
| 1262 | wm_high.vtaps = 2; |
| 1263 | wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */ |
| 1264 | wm_high.lb_size = lb_size; |
| 1265 | wm_high.dram_channels = cik_get_number_of_dram_channels(adev); |
| 1266 | wm_high.num_heads = num_heads; |
| 1267 | |
| 1268 | /* set for high clocks */ |
| 1269 | latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535); |
| 1270 | |
| 1271 | /* possibly force display priority to high */ |
| 1272 | /* should really do this at mode validation time... */ |
| 1273 | if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) || |
| 1274 | !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) || |
| 1275 | !dce_v11_0_check_latency_hiding(&wm_high) || |
| 1276 | (adev->mode_info.disp_priority == 2)) { |
| 1277 | DRM_DEBUG_KMS("force priority to high\n"); |
| 1278 | } |
| 1279 | |
| 1280 | /* watermark for low clocks */ |
| 1281 | if (adev->pm.dpm_enabled) { |
| 1282 | wm_low.yclk = |
| 1283 | amdgpu_dpm_get_mclk(adev, true) * 10; |
| 1284 | wm_low.sclk = |
| 1285 | amdgpu_dpm_get_sclk(adev, true) * 10; |
| 1286 | } else { |
| 1287 | wm_low.yclk = adev->pm.current_mclk * 10; |
| 1288 | wm_low.sclk = adev->pm.current_sclk * 10; |
| 1289 | } |
| 1290 | |
| 1291 | wm_low.disp_clk = mode->clock; |
| 1292 | wm_low.src_width = mode->crtc_hdisplay; |
| 1293 | wm_low.active_time = mode->crtc_hdisplay * pixel_period; |
| 1294 | wm_low.blank_time = line_time - wm_low.active_time; |
| 1295 | wm_low.interlaced = false; |
| 1296 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1297 | wm_low.interlaced = true; |
| 1298 | wm_low.vsc = amdgpu_crtc->vsc; |
| 1299 | wm_low.vtaps = 1; |
| 1300 | if (amdgpu_crtc->rmx_type != RMX_OFF) |
| 1301 | wm_low.vtaps = 2; |
| 1302 | wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */ |
| 1303 | wm_low.lb_size = lb_size; |
| 1304 | wm_low.dram_channels = cik_get_number_of_dram_channels(adev); |
| 1305 | wm_low.num_heads = num_heads; |
| 1306 | |
| 1307 | /* set for low clocks */ |
| 1308 | latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535); |
| 1309 | |
| 1310 | /* possibly force display priority to high */ |
| 1311 | /* should really do this at mode validation time... */ |
| 1312 | if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) || |
| 1313 | !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) || |
| 1314 | !dce_v11_0_check_latency_hiding(&wm_low) || |
| 1315 | (adev->mode_info.disp_priority == 2)) { |
| 1316 | DRM_DEBUG_KMS("force priority to high\n"); |
| 1317 | } |
| 1318 | } |
| 1319 | |
| 1320 | /* select wm A */ |
| 1321 | wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset); |
| 1322 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1); |
| 1323 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 1324 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); |
| 1325 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); |
| 1326 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); |
| 1327 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 1328 | /* select wm B */ |
| 1329 | tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2); |
| 1330 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 1331 | tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); |
| 1332 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a); |
| 1333 | tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time); |
| 1334 | WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 1335 | /* restore original selection */ |
| 1336 | WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask); |
| 1337 | |
| 1338 | /* save values for DPM */ |
| 1339 | amdgpu_crtc->line_time = line_time; |
| 1340 | amdgpu_crtc->wm_high = latency_watermark_a; |
| 1341 | amdgpu_crtc->wm_low = latency_watermark_b; |
| 1342 | } |
| 1343 | |
| 1344 | /** |
| 1345 | * dce_v11_0_bandwidth_update - program display watermarks |
| 1346 | * |
| 1347 | * @adev: amdgpu_device pointer |
| 1348 | * |
| 1349 | * Calculate and program the display watermarks and line |
| 1350 | * buffer allocation (CIK). |
| 1351 | */ |
| 1352 | static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev) |
| 1353 | { |
| 1354 | struct drm_display_mode *mode = NULL; |
| 1355 | u32 num_heads = 0, lb_size; |
| 1356 | int i; |
| 1357 | |
| 1358 | amdgpu_update_display_priority(adev); |
| 1359 | |
| 1360 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 1361 | if (adev->mode_info.crtcs[i]->base.enabled) |
| 1362 | num_heads++; |
| 1363 | } |
| 1364 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 1365 | mode = &adev->mode_info.crtcs[i]->base.mode; |
| 1366 | lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode); |
| 1367 | dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i], |
| 1368 | lb_size, num_heads); |
| 1369 | } |
| 1370 | } |
| 1371 | |
| 1372 | static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev) |
| 1373 | { |
| 1374 | int i; |
| 1375 | u32 offset, tmp; |
| 1376 | |
| 1377 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1378 | offset = adev->mode_info.audio.pin[i].offset; |
| 1379 | tmp = RREG32_AUDIO_ENDPT(offset, |
| 1380 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); |
| 1381 | if (((tmp & |
| 1382 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >> |
| 1383 | AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1) |
| 1384 | adev->mode_info.audio.pin[i].connected = false; |
| 1385 | else |
| 1386 | adev->mode_info.audio.pin[i].connected = true; |
| 1387 | } |
| 1388 | } |
| 1389 | |
| 1390 | static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev) |
| 1391 | { |
| 1392 | int i; |
| 1393 | |
| 1394 | dce_v11_0_audio_get_connected_pins(adev); |
| 1395 | |
| 1396 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1397 | if (adev->mode_info.audio.pin[i].connected) |
| 1398 | return &adev->mode_info.audio.pin[i]; |
| 1399 | } |
| 1400 | DRM_ERROR("No connected audio pins found!\n"); |
| 1401 | return NULL; |
| 1402 | } |
| 1403 | |
| 1404 | static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder) |
| 1405 | { |
| 1406 | struct amdgpu_device *adev = encoder->dev->dev_private; |
| 1407 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1408 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1409 | u32 tmp; |
| 1410 | |
| 1411 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1412 | return; |
| 1413 | |
| 1414 | tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset); |
| 1415 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id); |
| 1416 | WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp); |
| 1417 | } |
| 1418 | |
| 1419 | static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, |
| 1420 | struct drm_display_mode *mode) |
| 1421 | { |
| 1422 | struct amdgpu_device *adev = encoder->dev->dev_private; |
| 1423 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1424 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1425 | struct drm_connector *connector; |
| 1426 | struct amdgpu_connector *amdgpu_connector = NULL; |
| 1427 | u32 tmp; |
| 1428 | int interlace = 0; |
| 1429 | |
| 1430 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1431 | return; |
| 1432 | |
| 1433 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 1434 | if (connector->encoder == encoder) { |
| 1435 | amdgpu_connector = to_amdgpu_connector(connector); |
| 1436 | break; |
| 1437 | } |
| 1438 | } |
| 1439 | |
| 1440 | if (!amdgpu_connector) { |
| 1441 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 1442 | return; |
| 1443 | } |
| 1444 | |
| 1445 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 1446 | interlace = 1; |
| 1447 | if (connector->latency_present[interlace]) { |
| 1448 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
| 1449 | VIDEO_LIPSYNC, connector->video_latency[interlace]); |
| 1450 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
| 1451 | AUDIO_LIPSYNC, connector->audio_latency[interlace]); |
| 1452 | } else { |
| 1453 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
| 1454 | VIDEO_LIPSYNC, 0); |
| 1455 | tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, |
| 1456 | AUDIO_LIPSYNC, 0); |
| 1457 | } |
| 1458 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, |
| 1459 | ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); |
| 1460 | } |
| 1461 | |
| 1462 | static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder) |
| 1463 | { |
| 1464 | struct amdgpu_device *adev = encoder->dev->dev_private; |
| 1465 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1466 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1467 | struct drm_connector *connector; |
| 1468 | struct amdgpu_connector *amdgpu_connector = NULL; |
| 1469 | u32 tmp; |
| 1470 | u8 *sadb = NULL; |
| 1471 | int sad_count; |
| 1472 | |
| 1473 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1474 | return; |
| 1475 | |
| 1476 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 1477 | if (connector->encoder == encoder) { |
| 1478 | amdgpu_connector = to_amdgpu_connector(connector); |
| 1479 | break; |
| 1480 | } |
| 1481 | } |
| 1482 | |
| 1483 | if (!amdgpu_connector) { |
| 1484 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 1485 | return; |
| 1486 | } |
| 1487 | |
| 1488 | sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb); |
| 1489 | if (sad_count < 0) { |
| 1490 | DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count); |
| 1491 | sad_count = 0; |
| 1492 | } |
| 1493 | |
| 1494 | /* program the speaker allocation */ |
| 1495 | tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset, |
| 1496 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
| 1497 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
| 1498 | DP_CONNECTION, 0); |
| 1499 | /* set HDMI mode */ |
| 1500 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
| 1501 | HDMI_CONNECTION, 1); |
| 1502 | if (sad_count) |
| 1503 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
| 1504 | SPEAKER_ALLOCATION, sadb[0]); |
| 1505 | else |
| 1506 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, |
| 1507 | SPEAKER_ALLOCATION, 5); /* stereo */ |
| 1508 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, |
| 1509 | ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
| 1510 | |
| 1511 | kfree(sadb); |
| 1512 | } |
| 1513 | |
| 1514 | static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) |
| 1515 | { |
| 1516 | struct amdgpu_device *adev = encoder->dev->dev_private; |
| 1517 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1518 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1519 | struct drm_connector *connector; |
| 1520 | struct amdgpu_connector *amdgpu_connector = NULL; |
| 1521 | struct cea_sad *sads; |
| 1522 | int i, sad_count; |
| 1523 | |
| 1524 | static const u16 eld_reg_to_type[][2] = { |
| 1525 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
| 1526 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
| 1527 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
| 1528 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
| 1529 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
| 1530 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
| 1531 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
| 1532 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
| 1533 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
| 1534 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
| 1535 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
| 1536 | { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
| 1537 | }; |
| 1538 | |
| 1539 | if (!dig || !dig->afmt || !dig->afmt->pin) |
| 1540 | return; |
| 1541 | |
| 1542 | list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) { |
| 1543 | if (connector->encoder == encoder) { |
| 1544 | amdgpu_connector = to_amdgpu_connector(connector); |
| 1545 | break; |
| 1546 | } |
| 1547 | } |
| 1548 | |
| 1549 | if (!amdgpu_connector) { |
| 1550 | DRM_ERROR("Couldn't find encoder's connector\n"); |
| 1551 | return; |
| 1552 | } |
| 1553 | |
| 1554 | sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads); |
| 1555 | if (sad_count <= 0) { |
| 1556 | DRM_ERROR("Couldn't read SADs: %d\n", sad_count); |
| 1557 | return; |
| 1558 | } |
| 1559 | BUG_ON(!sads); |
| 1560 | |
| 1561 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
| 1562 | u32 tmp = 0; |
| 1563 | u8 stereo_freqs = 0; |
| 1564 | int max_channels = -1; |
| 1565 | int j; |
| 1566 | |
| 1567 | for (j = 0; j < sad_count; j++) { |
| 1568 | struct cea_sad *sad = &sads[j]; |
| 1569 | |
| 1570 | if (sad->format == eld_reg_to_type[i][1]) { |
| 1571 | if (sad->channels > max_channels) { |
| 1572 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
| 1573 | MAX_CHANNELS, sad->channels); |
| 1574 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
| 1575 | DESCRIPTOR_BYTE_2, sad->byte2); |
| 1576 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
| 1577 | SUPPORTED_FREQUENCIES, sad->freq); |
| 1578 | max_channels = sad->channels; |
| 1579 | } |
| 1580 | |
| 1581 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
| 1582 | stereo_freqs |= sad->freq; |
| 1583 | else |
| 1584 | break; |
| 1585 | } |
| 1586 | } |
| 1587 | |
| 1588 | tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, |
| 1589 | SUPPORTED_FREQUENCIES_STEREO, stereo_freqs); |
| 1590 | WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp); |
| 1591 | } |
| 1592 | |
| 1593 | kfree(sads); |
| 1594 | } |
| 1595 | |
| 1596 | static void dce_v11_0_audio_enable(struct amdgpu_device *adev, |
| 1597 | struct amdgpu_audio_pin *pin, |
| 1598 | bool enable) |
| 1599 | { |
| 1600 | if (!pin) |
| 1601 | return; |
| 1602 | |
| 1603 | WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
| 1604 | enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0); |
| 1605 | } |
| 1606 | |
| 1607 | static const u32 pin_offsets[] = |
| 1608 | { |
| 1609 | AUD0_REGISTER_OFFSET, |
| 1610 | AUD1_REGISTER_OFFSET, |
| 1611 | AUD2_REGISTER_OFFSET, |
| 1612 | AUD3_REGISTER_OFFSET, |
| 1613 | AUD4_REGISTER_OFFSET, |
| 1614 | AUD5_REGISTER_OFFSET, |
| 1615 | AUD6_REGISTER_OFFSET, |
| 1616 | }; |
| 1617 | |
| 1618 | static int dce_v11_0_audio_init(struct amdgpu_device *adev) |
| 1619 | { |
| 1620 | int i; |
| 1621 | |
| 1622 | if (!amdgpu_audio) |
| 1623 | return 0; |
| 1624 | |
| 1625 | adev->mode_info.audio.enabled = true; |
| 1626 | |
| 1627 | adev->mode_info.audio.num_pins = 7; |
| 1628 | |
| 1629 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 1630 | adev->mode_info.audio.pin[i].channels = -1; |
| 1631 | adev->mode_info.audio.pin[i].rate = -1; |
| 1632 | adev->mode_info.audio.pin[i].bits_per_sample = -1; |
| 1633 | adev->mode_info.audio.pin[i].status_bits = 0; |
| 1634 | adev->mode_info.audio.pin[i].category_code = 0; |
| 1635 | adev->mode_info.audio.pin[i].connected = false; |
| 1636 | adev->mode_info.audio.pin[i].offset = pin_offsets[i]; |
| 1637 | adev->mode_info.audio.pin[i].id = i; |
| 1638 | /* disable audio. it will be set up later */ |
| 1639 | /* XXX remove once we switch to ip funcs */ |
| 1640 | dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); |
| 1641 | } |
| 1642 | |
| 1643 | return 0; |
| 1644 | } |
| 1645 | |
| 1646 | static void dce_v11_0_audio_fini(struct amdgpu_device *adev) |
| 1647 | { |
| 1648 | int i; |
| 1649 | |
| 1650 | if (!adev->mode_info.audio.enabled) |
| 1651 | return; |
| 1652 | |
| 1653 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) |
| 1654 | dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); |
| 1655 | |
| 1656 | adev->mode_info.audio.enabled = false; |
| 1657 | } |
| 1658 | |
| 1659 | /* |
| 1660 | * update the N and CTS parameters for a given pixel clock rate |
| 1661 | */ |
| 1662 | static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock) |
| 1663 | { |
| 1664 | struct drm_device *dev = encoder->dev; |
| 1665 | struct amdgpu_device *adev = dev->dev_private; |
| 1666 | struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock); |
| 1667 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1668 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1669 | u32 tmp; |
| 1670 | |
| 1671 | tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset); |
| 1672 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz); |
| 1673 | WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp); |
| 1674 | tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset); |
| 1675 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz); |
| 1676 | WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp); |
| 1677 | |
| 1678 | tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset); |
| 1679 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz); |
| 1680 | WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp); |
| 1681 | tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset); |
| 1682 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz); |
| 1683 | WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp); |
| 1684 | |
| 1685 | tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); |
| 1686 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz); |
| 1687 | WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); |
| 1688 | tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset); |
| 1689 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz); |
| 1690 | WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp); |
| 1691 | |
| 1692 | } |
| 1693 | |
| 1694 | /* |
| 1695 | * build a HDMI Video Info Frame |
| 1696 | */ |
| 1697 | static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder, |
| 1698 | void *buffer, size_t size) |
| 1699 | { |
| 1700 | struct drm_device *dev = encoder->dev; |
| 1701 | struct amdgpu_device *adev = dev->dev_private; |
| 1702 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1703 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1704 | uint8_t *frame = buffer + 3; |
| 1705 | uint8_t *header = buffer; |
| 1706 | |
| 1707 | WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset, |
| 1708 | frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24)); |
| 1709 | WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset, |
| 1710 | frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24)); |
| 1711 | WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset, |
| 1712 | frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24)); |
| 1713 | WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset, |
| 1714 | frame[0xC] | (frame[0xD] << 8) | (header[1] << 24)); |
| 1715 | } |
| 1716 | |
| 1717 | static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock) |
| 1718 | { |
| 1719 | struct drm_device *dev = encoder->dev; |
| 1720 | struct amdgpu_device *adev = dev->dev_private; |
| 1721 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1722 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1723 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); |
| 1724 | u32 dto_phase = 24 * 1000; |
| 1725 | u32 dto_modulo = clock; |
| 1726 | u32 tmp; |
| 1727 | |
| 1728 | if (!dig || !dig->afmt) |
| 1729 | return; |
| 1730 | |
| 1731 | /* XXX two dtos; generally use dto0 for hdmi */ |
| 1732 | /* Express [24MHz / target pixel clock] as an exact rational |
| 1733 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
| 1734 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
| 1735 | */ |
| 1736 | tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE); |
| 1737 | tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, |
| 1738 | amdgpu_crtc->crtc_id); |
| 1739 | WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp); |
| 1740 | WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase); |
| 1741 | WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo); |
| 1742 | } |
| 1743 | |
| 1744 | /* |
| 1745 | * update the info frames with the data from the current display mode |
| 1746 | */ |
| 1747 | static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, |
| 1748 | struct drm_display_mode *mode) |
| 1749 | { |
| 1750 | struct drm_device *dev = encoder->dev; |
| 1751 | struct amdgpu_device *adev = dev->dev_private; |
| 1752 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1753 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1754 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); |
| 1755 | u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE]; |
| 1756 | struct hdmi_avi_infoframe frame; |
| 1757 | ssize_t err; |
| 1758 | u32 tmp; |
| 1759 | int bpc = 8; |
| 1760 | |
| 1761 | if (!dig || !dig->afmt) |
| 1762 | return; |
| 1763 | |
| 1764 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 1765 | if (!dig->afmt->enabled) |
| 1766 | return; |
| 1767 | |
| 1768 | /* hdmi deep color mode general control packets setup, if bpc > 8 */ |
| 1769 | if (encoder->crtc) { |
| 1770 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc); |
| 1771 | bpc = amdgpu_crtc->bpc; |
| 1772 | } |
| 1773 | |
| 1774 | /* disable audio prior to setting up hw */ |
| 1775 | dig->afmt->pin = dce_v11_0_audio_get_pin(adev); |
| 1776 | dce_v11_0_audio_enable(adev, dig->afmt->pin, false); |
| 1777 | |
| 1778 | dce_v11_0_audio_set_dto(encoder, mode->clock); |
| 1779 | |
| 1780 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); |
| 1781 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); |
| 1782 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */ |
| 1783 | |
| 1784 | WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000); |
| 1785 | |
| 1786 | tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset); |
| 1787 | switch (bpc) { |
| 1788 | case 0: |
| 1789 | case 6: |
| 1790 | case 8: |
| 1791 | case 16: |
| 1792 | default: |
| 1793 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0); |
| 1794 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); |
| 1795 | DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n", |
| 1796 | connector->name, bpc); |
| 1797 | break; |
| 1798 | case 10: |
| 1799 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); |
| 1800 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1); |
| 1801 | DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n", |
| 1802 | connector->name); |
| 1803 | break; |
| 1804 | case 12: |
| 1805 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1); |
| 1806 | tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2); |
| 1807 | DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n", |
| 1808 | connector->name); |
| 1809 | break; |
| 1810 | } |
| 1811 | WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp); |
| 1812 | |
| 1813 | tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset); |
| 1814 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */ |
| 1815 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */ |
| 1816 | tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */ |
| 1817 | WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); |
| 1818 | |
| 1819 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); |
| 1820 | /* enable audio info frames (frames won't be set until audio is enabled) */ |
| 1821 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); |
| 1822 | /* required for audio info values to be updated */ |
| 1823 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1); |
| 1824 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); |
| 1825 | |
| 1826 | tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset); |
| 1827 | /* required for audio info values to be updated */ |
| 1828 | tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); |
| 1829 | WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); |
| 1830 | |
| 1831 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); |
| 1832 | /* anything other than 0 */ |
| 1833 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2); |
| 1834 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); |
| 1835 | |
| 1836 | WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */ |
| 1837 | |
| 1838 | tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset); |
| 1839 | /* set the default audio delay */ |
| 1840 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1); |
| 1841 | /* should be suffient for all audio modes and small enough for all hblanks */ |
| 1842 | tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3); |
| 1843 | WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); |
| 1844 | |
| 1845 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); |
| 1846 | /* allow 60958 channel status fields to be updated */ |
| 1847 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); |
| 1848 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); |
| 1849 | |
| 1850 | tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset); |
| 1851 | if (bpc > 8) |
| 1852 | /* clear SW CTS value */ |
| 1853 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0); |
| 1854 | else |
| 1855 | /* select SW CTS value */ |
| 1856 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1); |
| 1857 | /* allow hw to sent ACR packets when required */ |
| 1858 | tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1); |
| 1859 | WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp); |
| 1860 | |
| 1861 | dce_v11_0_afmt_update_ACR(encoder, mode->clock); |
| 1862 | |
| 1863 | tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset); |
| 1864 | tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1); |
| 1865 | WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp); |
| 1866 | |
| 1867 | tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset); |
| 1868 | tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); |
| 1869 | WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp); |
| 1870 | |
| 1871 | tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset); |
| 1872 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3); |
| 1873 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4); |
| 1874 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5); |
| 1875 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6); |
| 1876 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7); |
| 1877 | tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8); |
| 1878 | WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp); |
| 1879 | |
| 1880 | dce_v11_0_audio_write_speaker_allocation(encoder); |
| 1881 | |
| 1882 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, |
| 1883 | (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT)); |
| 1884 | |
| 1885 | dce_v11_0_afmt_audio_select_pin(encoder); |
| 1886 | dce_v11_0_audio_write_sad_regs(encoder); |
| 1887 | dce_v11_0_audio_write_latency_fields(encoder, mode); |
| 1888 | |
| 1889 | err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); |
| 1890 | if (err < 0) { |
| 1891 | DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); |
| 1892 | return; |
| 1893 | } |
| 1894 | |
| 1895 | err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); |
| 1896 | if (err < 0) { |
| 1897 | DRM_ERROR("failed to pack AVI infoframe: %zd\n", err); |
| 1898 | return; |
| 1899 | } |
| 1900 | |
| 1901 | dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer)); |
| 1902 | |
| 1903 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset); |
| 1904 | /* enable AVI info frames */ |
| 1905 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1); |
| 1906 | /* required for audio info values to be updated */ |
| 1907 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1); |
| 1908 | WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp); |
| 1909 | |
| 1910 | tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset); |
| 1911 | tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2); |
| 1912 | WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp); |
| 1913 | |
| 1914 | tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset); |
| 1915 | /* send audio packets */ |
| 1916 | tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1); |
| 1917 | WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp); |
| 1918 | |
| 1919 | WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF); |
| 1920 | WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF); |
| 1921 | WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001); |
| 1922 | WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001); |
| 1923 | |
| 1924 | /* enable audio after to setting up hw */ |
| 1925 | dce_v11_0_audio_enable(adev, dig->afmt->pin, true); |
| 1926 | } |
| 1927 | |
| 1928 | static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable) |
| 1929 | { |
| 1930 | struct drm_device *dev = encoder->dev; |
| 1931 | struct amdgpu_device *adev = dev->dev_private; |
| 1932 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 1933 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 1934 | |
| 1935 | if (!dig || !dig->afmt) |
| 1936 | return; |
| 1937 | |
| 1938 | /* Silent, r600_hdmi_enable will raise WARN for us */ |
| 1939 | if (enable && dig->afmt->enabled) |
| 1940 | return; |
| 1941 | if (!enable && !dig->afmt->enabled) |
| 1942 | return; |
| 1943 | |
| 1944 | if (!enable && dig->afmt->pin) { |
| 1945 | dce_v11_0_audio_enable(adev, dig->afmt->pin, false); |
| 1946 | dig->afmt->pin = NULL; |
| 1947 | } |
| 1948 | |
| 1949 | dig->afmt->enabled = enable; |
| 1950 | |
| 1951 | DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n", |
| 1952 | enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id); |
| 1953 | } |
| 1954 | |
| 1955 | static void dce_v11_0_afmt_init(struct amdgpu_device *adev) |
| 1956 | { |
| 1957 | int i; |
| 1958 | |
| 1959 | for (i = 0; i < adev->mode_info.num_dig; i++) |
| 1960 | adev->mode_info.afmt[i] = NULL; |
| 1961 | |
| 1962 | /* DCE11 has audio blocks tied to DIG encoders */ |
| 1963 | for (i = 0; i < adev->mode_info.num_dig; i++) { |
| 1964 | adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL); |
| 1965 | if (adev->mode_info.afmt[i]) { |
| 1966 | adev->mode_info.afmt[i]->offset = dig_offsets[i]; |
| 1967 | adev->mode_info.afmt[i]->id = i; |
| 1968 | } |
| 1969 | } |
| 1970 | } |
| 1971 | |
| 1972 | static void dce_v11_0_afmt_fini(struct amdgpu_device *adev) |
| 1973 | { |
| 1974 | int i; |
| 1975 | |
| 1976 | for (i = 0; i < adev->mode_info.num_dig; i++) { |
| 1977 | kfree(adev->mode_info.afmt[i]); |
| 1978 | adev->mode_info.afmt[i] = NULL; |
| 1979 | } |
| 1980 | } |
| 1981 | |
| 1982 | static const u32 vga_control_regs[6] = |
| 1983 | { |
| 1984 | mmD1VGA_CONTROL, |
| 1985 | mmD2VGA_CONTROL, |
| 1986 | mmD3VGA_CONTROL, |
| 1987 | mmD4VGA_CONTROL, |
| 1988 | mmD5VGA_CONTROL, |
| 1989 | mmD6VGA_CONTROL, |
| 1990 | }; |
| 1991 | |
| 1992 | static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable) |
| 1993 | { |
| 1994 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 1995 | struct drm_device *dev = crtc->dev; |
| 1996 | struct amdgpu_device *adev = dev->dev_private; |
| 1997 | u32 vga_control; |
| 1998 | |
| 1999 | vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1; |
| 2000 | if (enable) |
| 2001 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1); |
| 2002 | else |
| 2003 | WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control); |
| 2004 | } |
| 2005 | |
| 2006 | static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable) |
| 2007 | { |
| 2008 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2009 | struct drm_device *dev = crtc->dev; |
| 2010 | struct amdgpu_device *adev = dev->dev_private; |
| 2011 | |
| 2012 | if (enable) |
| 2013 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1); |
| 2014 | else |
| 2015 | WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0); |
| 2016 | } |
| 2017 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2018 | static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, |
| 2019 | struct drm_framebuffer *fb, |
| 2020 | int x, int y, int atomic) |
| 2021 | { |
| 2022 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2023 | struct drm_device *dev = crtc->dev; |
| 2024 | struct amdgpu_device *adev = dev->dev_private; |
| 2025 | struct amdgpu_framebuffer *amdgpu_fb; |
| 2026 | struct drm_framebuffer *target_fb; |
| 2027 | struct drm_gem_object *obj; |
| 2028 | struct amdgpu_bo *rbo; |
| 2029 | uint64_t fb_location, tiling_flags; |
| 2030 | uint32_t fb_format, fb_pitch_pixels; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2031 | u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE); |
Marek Olšák | fbd76d5 | 2015-05-14 23:48:26 +0200 | [diff] [blame] | 2032 | u32 pipe_config; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2033 | u32 tmp, viewport_w, viewport_h; |
| 2034 | int r; |
| 2035 | bool bypass_lut = false; |
| 2036 | |
| 2037 | /* no fb bound */ |
| 2038 | if (!atomic && !crtc->primary->fb) { |
| 2039 | DRM_DEBUG_KMS("No FB bound\n"); |
| 2040 | return 0; |
| 2041 | } |
| 2042 | |
| 2043 | if (atomic) { |
| 2044 | amdgpu_fb = to_amdgpu_framebuffer(fb); |
| 2045 | target_fb = fb; |
| 2046 | } |
| 2047 | else { |
| 2048 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); |
| 2049 | target_fb = crtc->primary->fb; |
| 2050 | } |
| 2051 | |
| 2052 | /* If atomic, assume fb object is pinned & idle & fenced and |
| 2053 | * just update base pointers |
| 2054 | */ |
| 2055 | obj = amdgpu_fb->obj; |
| 2056 | rbo = gem_to_amdgpu_bo(obj); |
| 2057 | r = amdgpu_bo_reserve(rbo, false); |
| 2058 | if (unlikely(r != 0)) |
| 2059 | return r; |
| 2060 | |
| 2061 | if (atomic) |
| 2062 | fb_location = amdgpu_bo_gpu_offset(rbo); |
| 2063 | else { |
| 2064 | r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location); |
| 2065 | if (unlikely(r != 0)) { |
| 2066 | amdgpu_bo_unreserve(rbo); |
| 2067 | return -EINVAL; |
| 2068 | } |
| 2069 | } |
| 2070 | |
| 2071 | amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); |
| 2072 | amdgpu_bo_unreserve(rbo); |
| 2073 | |
Marek Olšák | fbd76d5 | 2015-05-14 23:48:26 +0200 | [diff] [blame] | 2074 | pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); |
| 2075 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2076 | switch (target_fb->pixel_format) { |
| 2077 | case DRM_FORMAT_C8: |
| 2078 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); |
| 2079 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); |
| 2080 | break; |
| 2081 | case DRM_FORMAT_XRGB4444: |
| 2082 | case DRM_FORMAT_ARGB4444: |
| 2083 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); |
| 2084 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2); |
| 2085 | #ifdef __BIG_ENDIAN |
| 2086 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2087 | ENDIAN_8IN16); |
| 2088 | #endif |
| 2089 | break; |
| 2090 | case DRM_FORMAT_XRGB1555: |
| 2091 | case DRM_FORMAT_ARGB1555: |
| 2092 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); |
| 2093 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); |
| 2094 | #ifdef __BIG_ENDIAN |
| 2095 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2096 | ENDIAN_8IN16); |
| 2097 | #endif |
| 2098 | break; |
| 2099 | case DRM_FORMAT_BGRX5551: |
| 2100 | case DRM_FORMAT_BGRA5551: |
| 2101 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); |
| 2102 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5); |
| 2103 | #ifdef __BIG_ENDIAN |
| 2104 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2105 | ENDIAN_8IN16); |
| 2106 | #endif |
| 2107 | break; |
| 2108 | case DRM_FORMAT_RGB565: |
| 2109 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1); |
| 2110 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); |
| 2111 | #ifdef __BIG_ENDIAN |
| 2112 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2113 | ENDIAN_8IN16); |
| 2114 | #endif |
| 2115 | break; |
| 2116 | case DRM_FORMAT_XRGB8888: |
| 2117 | case DRM_FORMAT_ARGB8888: |
| 2118 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); |
| 2119 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); |
| 2120 | #ifdef __BIG_ENDIAN |
| 2121 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2122 | ENDIAN_8IN32); |
| 2123 | #endif |
| 2124 | break; |
| 2125 | case DRM_FORMAT_XRGB2101010: |
| 2126 | case DRM_FORMAT_ARGB2101010: |
| 2127 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); |
| 2128 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1); |
| 2129 | #ifdef __BIG_ENDIAN |
| 2130 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2131 | ENDIAN_8IN32); |
| 2132 | #endif |
| 2133 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
| 2134 | bypass_lut = true; |
| 2135 | break; |
| 2136 | case DRM_FORMAT_BGRX1010102: |
| 2137 | case DRM_FORMAT_BGRA1010102: |
| 2138 | fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); |
| 2139 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4); |
| 2140 | #ifdef __BIG_ENDIAN |
| 2141 | fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, |
| 2142 | ENDIAN_8IN32); |
| 2143 | #endif |
| 2144 | /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ |
| 2145 | bypass_lut = true; |
| 2146 | break; |
| 2147 | default: |
| 2148 | DRM_ERROR("Unsupported screen format %s\n", |
| 2149 | drm_get_format_name(target_fb->pixel_format)); |
| 2150 | return -EINVAL; |
| 2151 | } |
| 2152 | |
Marek Olšák | fbd76d5 | 2015-05-14 23:48:26 +0200 | [diff] [blame] | 2153 | if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { |
| 2154 | unsigned bankw, bankh, mtaspect, tile_split, num_banks; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2155 | |
Marek Olšák | fbd76d5 | 2015-05-14 23:48:26 +0200 | [diff] [blame] | 2156 | bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); |
| 2157 | bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); |
| 2158 | mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); |
| 2159 | tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); |
| 2160 | num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2161 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2162 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks); |
| 2163 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, |
| 2164 | ARRAY_2D_TILED_THIN1); |
| 2165 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT, |
| 2166 | tile_split); |
| 2167 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw); |
| 2168 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh); |
| 2169 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, |
| 2170 | mtaspect); |
| 2171 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, |
| 2172 | ADDR_SURF_MICRO_TILING_DISPLAY); |
Marek Olšák | fbd76d5 | 2015-05-14 23:48:26 +0200 | [diff] [blame] | 2173 | } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2174 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE, |
| 2175 | ARRAY_1D_TILED_THIN1); |
| 2176 | } |
| 2177 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2178 | fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG, |
| 2179 | pipe_config); |
| 2180 | |
| 2181 | dce_v11_0_vga_enable(crtc, false); |
| 2182 | |
| 2183 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, |
| 2184 | upper_32_bits(fb_location)); |
| 2185 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, |
| 2186 | upper_32_bits(fb_location)); |
| 2187 | WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, |
| 2188 | (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK); |
| 2189 | WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, |
| 2190 | (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK); |
| 2191 | WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); |
| 2192 | WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap); |
| 2193 | |
| 2194 | /* |
| 2195 | * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT |
| 2196 | * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to |
| 2197 | * retain the full precision throughout the pipeline. |
| 2198 | */ |
| 2199 | tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset); |
| 2200 | if (bypass_lut) |
| 2201 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1); |
| 2202 | else |
| 2203 | tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0); |
| 2204 | WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp); |
| 2205 | |
| 2206 | if (bypass_lut) |
| 2207 | DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n"); |
| 2208 | |
| 2209 | WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0); |
| 2210 | WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0); |
| 2211 | WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0); |
| 2212 | WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0); |
| 2213 | WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); |
| 2214 | WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); |
| 2215 | |
| 2216 | fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); |
| 2217 | WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); |
| 2218 | |
| 2219 | dce_v11_0_grph_enable(crtc, true); |
| 2220 | |
| 2221 | WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset, |
| 2222 | target_fb->height); |
| 2223 | |
| 2224 | x &= ~3; |
| 2225 | y &= ~1; |
| 2226 | WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset, |
| 2227 | (x << 16) | y); |
| 2228 | viewport_w = crtc->mode.hdisplay; |
| 2229 | viewport_h = (crtc->mode.vdisplay + 1) & ~1; |
| 2230 | WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset, |
| 2231 | (viewport_w << 16) | viewport_h); |
| 2232 | |
| 2233 | /* pageflip setup */ |
| 2234 | /* make sure flip is at vb rather than hb */ |
| 2235 | tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset); |
| 2236 | tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL, |
| 2237 | GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0); |
| 2238 | WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2239 | |
| 2240 | /* set pageflip to happen only at start of vblank interval (front porch) */ |
| 2241 | WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 3); |
| 2242 | |
| 2243 | if (!atomic && fb && fb != crtc->primary->fb) { |
| 2244 | amdgpu_fb = to_amdgpu_framebuffer(fb); |
| 2245 | rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); |
| 2246 | r = amdgpu_bo_reserve(rbo, false); |
| 2247 | if (unlikely(r != 0)) |
| 2248 | return r; |
| 2249 | amdgpu_bo_unpin(rbo); |
| 2250 | amdgpu_bo_unreserve(rbo); |
| 2251 | } |
| 2252 | |
| 2253 | /* Bytes per pixel may have changed */ |
| 2254 | dce_v11_0_bandwidth_update(adev); |
| 2255 | |
| 2256 | return 0; |
| 2257 | } |
| 2258 | |
| 2259 | static void dce_v11_0_set_interleave(struct drm_crtc *crtc, |
| 2260 | struct drm_display_mode *mode) |
| 2261 | { |
| 2262 | struct drm_device *dev = crtc->dev; |
| 2263 | struct amdgpu_device *adev = dev->dev_private; |
| 2264 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2265 | u32 tmp; |
| 2266 | |
| 2267 | tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset); |
| 2268 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 2269 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1); |
| 2270 | else |
| 2271 | tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0); |
| 2272 | WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp); |
| 2273 | } |
| 2274 | |
| 2275 | static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc) |
| 2276 | { |
| 2277 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2278 | struct drm_device *dev = crtc->dev; |
| 2279 | struct amdgpu_device *adev = dev->dev_private; |
| 2280 | int i; |
| 2281 | u32 tmp; |
| 2282 | |
| 2283 | DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id); |
| 2284 | |
| 2285 | tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); |
| 2286 | tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0); |
| 2287 | WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2288 | |
| 2289 | tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset); |
| 2290 | tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1); |
| 2291 | WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2292 | |
| 2293 | tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset); |
| 2294 | tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0); |
| 2295 | WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2296 | |
| 2297 | WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0); |
| 2298 | |
| 2299 | WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0); |
| 2300 | WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0); |
| 2301 | WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0); |
| 2302 | |
| 2303 | WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff); |
| 2304 | WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff); |
| 2305 | WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff); |
| 2306 | |
| 2307 | WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0); |
| 2308 | WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007); |
| 2309 | |
| 2310 | WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0); |
| 2311 | for (i = 0; i < 256; i++) { |
| 2312 | WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset, |
| 2313 | (amdgpu_crtc->lut_r[i] << 20) | |
| 2314 | (amdgpu_crtc->lut_g[i] << 10) | |
| 2315 | (amdgpu_crtc->lut_b[i] << 0)); |
| 2316 | } |
| 2317 | |
| 2318 | tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset); |
| 2319 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0); |
| 2320 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0); |
| 2321 | tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0); |
| 2322 | WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2323 | |
| 2324 | tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset); |
| 2325 | tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0); |
| 2326 | WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2327 | |
| 2328 | tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset); |
| 2329 | tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0); |
| 2330 | WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2331 | |
| 2332 | tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset); |
| 2333 | tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0); |
| 2334 | WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2335 | |
| 2336 | /* XXX match this to the depth of the crtc fmt block, move to modeset? */ |
| 2337 | WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0); |
| 2338 | /* XXX this only needs to be programmed once per crtc at startup, |
| 2339 | * not sure where the best place for it is |
| 2340 | */ |
| 2341 | tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset); |
| 2342 | tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1); |
| 2343 | WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2344 | } |
| 2345 | |
| 2346 | static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder) |
| 2347 | { |
| 2348 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 2349 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 2350 | |
| 2351 | switch (amdgpu_encoder->encoder_id) { |
| 2352 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 2353 | if (dig->linkb) |
| 2354 | return 1; |
| 2355 | else |
| 2356 | return 0; |
| 2357 | break; |
| 2358 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 2359 | if (dig->linkb) |
| 2360 | return 3; |
| 2361 | else |
| 2362 | return 2; |
| 2363 | break; |
| 2364 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 2365 | if (dig->linkb) |
| 2366 | return 5; |
| 2367 | else |
| 2368 | return 4; |
| 2369 | break; |
| 2370 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 2371 | return 6; |
| 2372 | break; |
| 2373 | default: |
| 2374 | DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id); |
| 2375 | return 0; |
| 2376 | } |
| 2377 | } |
| 2378 | |
| 2379 | /** |
| 2380 | * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc. |
| 2381 | * |
| 2382 | * @crtc: drm crtc |
| 2383 | * |
| 2384 | * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors |
| 2385 | * a single PPLL can be used for all DP crtcs/encoders. For non-DP |
| 2386 | * monitors a dedicated PPLL must be used. If a particular board has |
| 2387 | * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming |
| 2388 | * as there is no need to program the PLL itself. If we are not able to |
| 2389 | * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to |
| 2390 | * avoid messing up an existing monitor. |
| 2391 | * |
| 2392 | * Asic specific PLL information |
| 2393 | * |
| 2394 | * DCE 10.x |
| 2395 | * Tonga |
| 2396 | * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) |
| 2397 | * CI |
| 2398 | * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC |
| 2399 | * |
| 2400 | */ |
| 2401 | static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) |
| 2402 | { |
| 2403 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2404 | struct drm_device *dev = crtc->dev; |
| 2405 | struct amdgpu_device *adev = dev->dev_private; |
| 2406 | u32 pll_in_use; |
| 2407 | int pll; |
| 2408 | |
| 2409 | if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) { |
| 2410 | if (adev->clock.dp_extclk) |
| 2411 | /* skip PPLL programming if using ext clock */ |
| 2412 | return ATOM_PPLL_INVALID; |
| 2413 | else { |
| 2414 | /* use the same PPLL for all DP monitors */ |
| 2415 | pll = amdgpu_pll_get_shared_dp_ppll(crtc); |
| 2416 | if (pll != ATOM_PPLL_INVALID) |
| 2417 | return pll; |
| 2418 | } |
| 2419 | } else { |
| 2420 | /* use the same PPLL for all monitors with the same clock */ |
| 2421 | pll = amdgpu_pll_get_shared_nondp_ppll(crtc); |
| 2422 | if (pll != ATOM_PPLL_INVALID) |
| 2423 | return pll; |
| 2424 | } |
| 2425 | |
| 2426 | /* XXX need to determine what plls are available on each DCE11 part */ |
| 2427 | pll_in_use = amdgpu_pll_get_use_mask(crtc); |
| 2428 | if (adev->asic_type == CHIP_CARRIZO) { |
| 2429 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
| 2430 | return ATOM_PPLL1; |
| 2431 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
| 2432 | return ATOM_PPLL0; |
| 2433 | DRM_ERROR("unable to allocate a PPLL\n"); |
| 2434 | return ATOM_PPLL_INVALID; |
| 2435 | } else { |
| 2436 | if (!(pll_in_use & (1 << ATOM_PPLL2))) |
| 2437 | return ATOM_PPLL2; |
| 2438 | if (!(pll_in_use & (1 << ATOM_PPLL1))) |
| 2439 | return ATOM_PPLL1; |
| 2440 | if (!(pll_in_use & (1 << ATOM_PPLL0))) |
| 2441 | return ATOM_PPLL0; |
| 2442 | DRM_ERROR("unable to allocate a PPLL\n"); |
| 2443 | return ATOM_PPLL_INVALID; |
| 2444 | } |
| 2445 | return ATOM_PPLL_INVALID; |
| 2446 | } |
| 2447 | |
| 2448 | static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock) |
| 2449 | { |
| 2450 | struct amdgpu_device *adev = crtc->dev->dev_private; |
| 2451 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2452 | uint32_t cur_lock; |
| 2453 | |
| 2454 | cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset); |
| 2455 | if (lock) |
| 2456 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1); |
| 2457 | else |
| 2458 | cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0); |
| 2459 | WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock); |
| 2460 | } |
| 2461 | |
| 2462 | static void dce_v11_0_hide_cursor(struct drm_crtc *crtc) |
| 2463 | { |
| 2464 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2465 | struct amdgpu_device *adev = crtc->dev->dev_private; |
| 2466 | u32 tmp; |
| 2467 | |
| 2468 | tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); |
| 2469 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0); |
| 2470 | WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2471 | } |
| 2472 | |
| 2473 | static void dce_v11_0_show_cursor(struct drm_crtc *crtc) |
| 2474 | { |
| 2475 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2476 | struct amdgpu_device *adev = crtc->dev->dev_private; |
| 2477 | u32 tmp; |
| 2478 | |
| 2479 | tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset); |
| 2480 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1); |
| 2481 | tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2); |
| 2482 | WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp); |
| 2483 | } |
| 2484 | |
| 2485 | static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj, |
| 2486 | uint64_t gpu_addr) |
| 2487 | { |
| 2488 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2489 | struct amdgpu_device *adev = crtc->dev->dev_private; |
| 2490 | |
| 2491 | WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, |
| 2492 | upper_32_bits(gpu_addr)); |
| 2493 | WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset, |
| 2494 | lower_32_bits(gpu_addr)); |
| 2495 | } |
| 2496 | |
| 2497 | static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc, |
| 2498 | int x, int y) |
| 2499 | { |
| 2500 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2501 | struct amdgpu_device *adev = crtc->dev->dev_private; |
| 2502 | int xorigin = 0, yorigin = 0; |
| 2503 | |
| 2504 | /* avivo cursor are offset into the total surface */ |
| 2505 | x += crtc->x; |
| 2506 | y += crtc->y; |
| 2507 | DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); |
| 2508 | |
| 2509 | if (x < 0) { |
| 2510 | xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); |
| 2511 | x = 0; |
| 2512 | } |
| 2513 | if (y < 0) { |
| 2514 | yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); |
| 2515 | y = 0; |
| 2516 | } |
| 2517 | |
| 2518 | dce_v11_0_lock_cursor(crtc, true); |
| 2519 | WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y); |
| 2520 | WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin); |
| 2521 | WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset, |
| 2522 | ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1)); |
| 2523 | dce_v11_0_lock_cursor(crtc, false); |
| 2524 | |
| 2525 | return 0; |
| 2526 | } |
| 2527 | |
| 2528 | static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc, |
| 2529 | struct drm_file *file_priv, |
| 2530 | uint32_t handle, |
| 2531 | uint32_t width, |
| 2532 | uint32_t height) |
| 2533 | { |
| 2534 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2535 | struct drm_gem_object *obj; |
| 2536 | struct amdgpu_bo *robj; |
| 2537 | uint64_t gpu_addr; |
| 2538 | int ret; |
| 2539 | |
| 2540 | if (!handle) { |
| 2541 | /* turn off cursor */ |
| 2542 | dce_v11_0_hide_cursor(crtc); |
| 2543 | obj = NULL; |
| 2544 | goto unpin; |
| 2545 | } |
| 2546 | |
| 2547 | if ((width > amdgpu_crtc->max_cursor_width) || |
| 2548 | (height > amdgpu_crtc->max_cursor_height)) { |
| 2549 | DRM_ERROR("bad cursor width or height %d x %d\n", width, height); |
| 2550 | return -EINVAL; |
| 2551 | } |
| 2552 | |
| 2553 | obj = drm_gem_object_lookup(crtc->dev, file_priv, handle); |
| 2554 | if (!obj) { |
| 2555 | DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id); |
| 2556 | return -ENOENT; |
| 2557 | } |
| 2558 | |
| 2559 | robj = gem_to_amdgpu_bo(obj); |
| 2560 | ret = amdgpu_bo_reserve(robj, false); |
| 2561 | if (unlikely(ret != 0)) |
| 2562 | goto fail; |
| 2563 | ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM, |
Chunming Zhou | 7e5a547 | 2015-04-24 17:37:30 +0800 | [diff] [blame] | 2564 | 0, 0, &gpu_addr); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2565 | amdgpu_bo_unreserve(robj); |
| 2566 | if (ret) |
| 2567 | goto fail; |
| 2568 | |
| 2569 | amdgpu_crtc->cursor_width = width; |
| 2570 | amdgpu_crtc->cursor_height = height; |
| 2571 | |
| 2572 | dce_v11_0_lock_cursor(crtc, true); |
| 2573 | dce_v11_0_set_cursor(crtc, obj, gpu_addr); |
| 2574 | dce_v11_0_show_cursor(crtc); |
| 2575 | dce_v11_0_lock_cursor(crtc, false); |
| 2576 | |
| 2577 | unpin: |
| 2578 | if (amdgpu_crtc->cursor_bo) { |
| 2579 | robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); |
| 2580 | ret = amdgpu_bo_reserve(robj, false); |
| 2581 | if (likely(ret == 0)) { |
| 2582 | amdgpu_bo_unpin(robj); |
| 2583 | amdgpu_bo_unreserve(robj); |
| 2584 | } |
| 2585 | drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo); |
| 2586 | } |
| 2587 | |
| 2588 | amdgpu_crtc->cursor_bo = obj; |
| 2589 | return 0; |
| 2590 | fail: |
| 2591 | drm_gem_object_unreference_unlocked(obj); |
| 2592 | |
| 2593 | return ret; |
| 2594 | } |
| 2595 | |
| 2596 | static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
| 2597 | u16 *blue, uint32_t start, uint32_t size) |
| 2598 | { |
| 2599 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2600 | int end = (start + size > 256) ? 256 : start + size, i; |
| 2601 | |
| 2602 | /* userspace palettes are always correct as is */ |
| 2603 | for (i = start; i < end; i++) { |
| 2604 | amdgpu_crtc->lut_r[i] = red[i] >> 6; |
| 2605 | amdgpu_crtc->lut_g[i] = green[i] >> 6; |
| 2606 | amdgpu_crtc->lut_b[i] = blue[i] >> 6; |
| 2607 | } |
| 2608 | dce_v11_0_crtc_load_lut(crtc); |
| 2609 | } |
| 2610 | |
| 2611 | static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) |
| 2612 | { |
| 2613 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2614 | |
| 2615 | drm_crtc_cleanup(crtc); |
| 2616 | destroy_workqueue(amdgpu_crtc->pflip_queue); |
| 2617 | kfree(amdgpu_crtc); |
| 2618 | } |
| 2619 | |
| 2620 | static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { |
| 2621 | .cursor_set = dce_v11_0_crtc_cursor_set, |
| 2622 | .cursor_move = dce_v11_0_crtc_cursor_move, |
| 2623 | .gamma_set = dce_v11_0_crtc_gamma_set, |
| 2624 | .set_config = amdgpu_crtc_set_config, |
| 2625 | .destroy = dce_v11_0_crtc_destroy, |
| 2626 | .page_flip = amdgpu_crtc_page_flip, |
| 2627 | }; |
| 2628 | |
| 2629 | static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) |
| 2630 | { |
| 2631 | struct drm_device *dev = crtc->dev; |
| 2632 | struct amdgpu_device *adev = dev->dev_private; |
| 2633 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2634 | |
| 2635 | switch (mode) { |
| 2636 | case DRM_MODE_DPMS_ON: |
| 2637 | amdgpu_crtc->enabled = true; |
| 2638 | amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE); |
| 2639 | dce_v11_0_vga_enable(crtc, true); |
| 2640 | amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE); |
| 2641 | dce_v11_0_vga_enable(crtc, false); |
| 2642 | drm_vblank_post_modeset(dev, amdgpu_crtc->crtc_id); |
| 2643 | dce_v11_0_crtc_load_lut(crtc); |
| 2644 | break; |
| 2645 | case DRM_MODE_DPMS_STANDBY: |
| 2646 | case DRM_MODE_DPMS_SUSPEND: |
| 2647 | case DRM_MODE_DPMS_OFF: |
| 2648 | drm_vblank_pre_modeset(dev, amdgpu_crtc->crtc_id); |
| 2649 | if (amdgpu_crtc->enabled) { |
| 2650 | dce_v11_0_vga_enable(crtc, true); |
| 2651 | amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE); |
| 2652 | dce_v11_0_vga_enable(crtc, false); |
| 2653 | } |
| 2654 | amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE); |
| 2655 | amdgpu_crtc->enabled = false; |
| 2656 | break; |
| 2657 | } |
| 2658 | /* adjust pm to dpms */ |
| 2659 | amdgpu_pm_compute_clocks(adev); |
| 2660 | } |
| 2661 | |
| 2662 | static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc) |
| 2663 | { |
| 2664 | /* disable crtc pair power gating before programming */ |
| 2665 | amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE); |
| 2666 | amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE); |
| 2667 | dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 2668 | } |
| 2669 | |
| 2670 | static void dce_v11_0_crtc_commit(struct drm_crtc *crtc) |
| 2671 | { |
| 2672 | dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
| 2673 | amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE); |
| 2674 | } |
| 2675 | |
| 2676 | static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) |
| 2677 | { |
| 2678 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2679 | struct drm_device *dev = crtc->dev; |
| 2680 | struct amdgpu_device *adev = dev->dev_private; |
| 2681 | struct amdgpu_atom_ss ss; |
| 2682 | int i; |
| 2683 | |
| 2684 | dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
| 2685 | if (crtc->primary->fb) { |
| 2686 | int r; |
| 2687 | struct amdgpu_framebuffer *amdgpu_fb; |
| 2688 | struct amdgpu_bo *rbo; |
| 2689 | |
| 2690 | amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); |
| 2691 | rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); |
| 2692 | r = amdgpu_bo_reserve(rbo, false); |
| 2693 | if (unlikely(r)) |
| 2694 | DRM_ERROR("failed to reserve rbo before unpin\n"); |
| 2695 | else { |
| 2696 | amdgpu_bo_unpin(rbo); |
| 2697 | amdgpu_bo_unreserve(rbo); |
| 2698 | } |
| 2699 | } |
| 2700 | /* disable the GRPH */ |
| 2701 | dce_v11_0_grph_enable(crtc, false); |
| 2702 | |
| 2703 | amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE); |
| 2704 | |
| 2705 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 2706 | if (adev->mode_info.crtcs[i] && |
| 2707 | adev->mode_info.crtcs[i]->enabled && |
| 2708 | i != amdgpu_crtc->crtc_id && |
| 2709 | amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) { |
| 2710 | /* one other crtc is using this pll don't turn |
| 2711 | * off the pll |
| 2712 | */ |
| 2713 | goto done; |
| 2714 | } |
| 2715 | } |
| 2716 | |
| 2717 | switch (amdgpu_crtc->pll_id) { |
| 2718 | case ATOM_PPLL0: |
| 2719 | case ATOM_PPLL1: |
| 2720 | case ATOM_PPLL2: |
| 2721 | /* disable the ppll */ |
| 2722 | amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id, |
| 2723 | 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); |
| 2724 | break; |
| 2725 | default: |
| 2726 | break; |
| 2727 | } |
| 2728 | done: |
| 2729 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; |
| 2730 | amdgpu_crtc->adjusted_clock = 0; |
| 2731 | amdgpu_crtc->encoder = NULL; |
| 2732 | amdgpu_crtc->connector = NULL; |
| 2733 | } |
| 2734 | |
| 2735 | static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, |
| 2736 | struct drm_display_mode *mode, |
| 2737 | struct drm_display_mode *adjusted_mode, |
| 2738 | int x, int y, struct drm_framebuffer *old_fb) |
| 2739 | { |
| 2740 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2741 | |
| 2742 | if (!amdgpu_crtc->adjusted_clock) |
| 2743 | return -EINVAL; |
| 2744 | |
| 2745 | amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode); |
| 2746 | amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode); |
| 2747 | dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); |
| 2748 | amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode); |
| 2749 | amdgpu_atombios_crtc_scaler_setup(crtc); |
| 2750 | /* update the hw version fpr dpm */ |
| 2751 | amdgpu_crtc->hw_mode = *adjusted_mode; |
| 2752 | |
| 2753 | return 0; |
| 2754 | } |
| 2755 | |
| 2756 | static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc, |
| 2757 | const struct drm_display_mode *mode, |
| 2758 | struct drm_display_mode *adjusted_mode) |
| 2759 | { |
| 2760 | struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); |
| 2761 | struct drm_device *dev = crtc->dev; |
| 2762 | struct drm_encoder *encoder; |
| 2763 | |
| 2764 | /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */ |
| 2765 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2766 | if (encoder->crtc == crtc) { |
| 2767 | amdgpu_crtc->encoder = encoder; |
| 2768 | amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder); |
| 2769 | break; |
| 2770 | } |
| 2771 | } |
| 2772 | if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) { |
| 2773 | amdgpu_crtc->encoder = NULL; |
| 2774 | amdgpu_crtc->connector = NULL; |
| 2775 | return false; |
| 2776 | } |
| 2777 | if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
| 2778 | return false; |
| 2779 | if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode)) |
| 2780 | return false; |
| 2781 | /* pick pll */ |
| 2782 | amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc); |
| 2783 | /* if we can't get a PPLL for a non-DP encoder, fail */ |
| 2784 | if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) && |
| 2785 | !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) |
| 2786 | return false; |
| 2787 | |
| 2788 | return true; |
| 2789 | } |
| 2790 | |
| 2791 | static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
| 2792 | struct drm_framebuffer *old_fb) |
| 2793 | { |
| 2794 | return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0); |
| 2795 | } |
| 2796 | |
| 2797 | static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc, |
| 2798 | struct drm_framebuffer *fb, |
| 2799 | int x, int y, enum mode_set_atomic state) |
| 2800 | { |
| 2801 | return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1); |
| 2802 | } |
| 2803 | |
| 2804 | static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { |
| 2805 | .dpms = dce_v11_0_crtc_dpms, |
| 2806 | .mode_fixup = dce_v11_0_crtc_mode_fixup, |
| 2807 | .mode_set = dce_v11_0_crtc_mode_set, |
| 2808 | .mode_set_base = dce_v11_0_crtc_set_base, |
| 2809 | .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic, |
| 2810 | .prepare = dce_v11_0_crtc_prepare, |
| 2811 | .commit = dce_v11_0_crtc_commit, |
| 2812 | .load_lut = dce_v11_0_crtc_load_lut, |
| 2813 | .disable = dce_v11_0_crtc_disable, |
| 2814 | }; |
| 2815 | |
| 2816 | static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) |
| 2817 | { |
| 2818 | struct amdgpu_crtc *amdgpu_crtc; |
| 2819 | int i; |
| 2820 | |
| 2821 | amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) + |
| 2822 | (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL); |
| 2823 | if (amdgpu_crtc == NULL) |
| 2824 | return -ENOMEM; |
| 2825 | |
| 2826 | drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs); |
| 2827 | |
| 2828 | drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256); |
| 2829 | amdgpu_crtc->crtc_id = index; |
| 2830 | amdgpu_crtc->pflip_queue = create_singlethread_workqueue("amdgpu-pageflip-queue"); |
| 2831 | adev->mode_info.crtcs[index] = amdgpu_crtc; |
| 2832 | |
| 2833 | amdgpu_crtc->max_cursor_width = 128; |
| 2834 | amdgpu_crtc->max_cursor_height = 128; |
| 2835 | adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width; |
| 2836 | adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height; |
| 2837 | |
| 2838 | for (i = 0; i < 256; i++) { |
| 2839 | amdgpu_crtc->lut_r[i] = i << 2; |
| 2840 | amdgpu_crtc->lut_g[i] = i << 2; |
| 2841 | amdgpu_crtc->lut_b[i] = i << 2; |
| 2842 | } |
| 2843 | |
| 2844 | switch (amdgpu_crtc->crtc_id) { |
| 2845 | case 0: |
| 2846 | default: |
| 2847 | amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET; |
| 2848 | break; |
| 2849 | case 1: |
| 2850 | amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET; |
| 2851 | break; |
| 2852 | case 2: |
| 2853 | amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET; |
| 2854 | break; |
| 2855 | case 3: |
| 2856 | amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET; |
| 2857 | break; |
| 2858 | case 4: |
| 2859 | amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET; |
| 2860 | break; |
| 2861 | case 5: |
| 2862 | amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET; |
| 2863 | break; |
| 2864 | } |
| 2865 | |
| 2866 | amdgpu_crtc->pll_id = ATOM_PPLL_INVALID; |
| 2867 | amdgpu_crtc->adjusted_clock = 0; |
| 2868 | amdgpu_crtc->encoder = NULL; |
| 2869 | amdgpu_crtc->connector = NULL; |
| 2870 | drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs); |
| 2871 | |
| 2872 | return 0; |
| 2873 | } |
| 2874 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2875 | static int dce_v11_0_early_init(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2876 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2877 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2878 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2879 | adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; |
| 2880 | adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; |
| 2881 | |
| 2882 | dce_v11_0_set_display_funcs(adev); |
| 2883 | dce_v11_0_set_irq_funcs(adev); |
| 2884 | |
| 2885 | switch (adev->asic_type) { |
| 2886 | case CHIP_CARRIZO: |
| 2887 | adev->mode_info.num_crtc = 4; |
| 2888 | adev->mode_info.num_hpd = 6; |
| 2889 | adev->mode_info.num_dig = 9; |
| 2890 | break; |
| 2891 | default: |
| 2892 | /* FIXME: not supported yet */ |
| 2893 | return -EINVAL; |
| 2894 | } |
| 2895 | |
| 2896 | return 0; |
| 2897 | } |
| 2898 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2899 | static int dce_v11_0_sw_init(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2900 | { |
| 2901 | int r, i; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2902 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2903 | |
| 2904 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 2905 | r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq); |
| 2906 | if (r) |
| 2907 | return r; |
| 2908 | } |
| 2909 | |
| 2910 | for (i = 8; i < 20; i += 2) { |
| 2911 | r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq); |
| 2912 | if (r) |
| 2913 | return r; |
| 2914 | } |
| 2915 | |
| 2916 | /* HPD hotplug */ |
| 2917 | r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq); |
| 2918 | if (r) |
| 2919 | return r; |
| 2920 | |
| 2921 | adev->mode_info.mode_config_initialized = true; |
| 2922 | |
| 2923 | adev->ddev->mode_config.funcs = &amdgpu_mode_funcs; |
| 2924 | |
| 2925 | adev->ddev->mode_config.max_width = 16384; |
| 2926 | adev->ddev->mode_config.max_height = 16384; |
| 2927 | |
| 2928 | adev->ddev->mode_config.preferred_depth = 24; |
| 2929 | adev->ddev->mode_config.prefer_shadow = 1; |
| 2930 | |
| 2931 | adev->ddev->mode_config.fb_base = adev->mc.aper_base; |
| 2932 | |
| 2933 | r = amdgpu_modeset_create_props(adev); |
| 2934 | if (r) |
| 2935 | return r; |
| 2936 | |
| 2937 | adev->ddev->mode_config.max_width = 16384; |
| 2938 | adev->ddev->mode_config.max_height = 16384; |
| 2939 | |
| 2940 | /* allocate crtcs */ |
| 2941 | for (i = 0; i < adev->mode_info.num_crtc; i++) { |
| 2942 | r = dce_v11_0_crtc_init(adev, i); |
| 2943 | if (r) |
| 2944 | return r; |
| 2945 | } |
| 2946 | |
| 2947 | if (amdgpu_atombios_get_connector_info_from_object_table(adev)) |
| 2948 | amdgpu_print_display_setup(adev->ddev); |
| 2949 | else |
| 2950 | return -EINVAL; |
| 2951 | |
| 2952 | /* setup afmt */ |
| 2953 | dce_v11_0_afmt_init(adev); |
| 2954 | |
| 2955 | r = dce_v11_0_audio_init(adev); |
| 2956 | if (r) |
| 2957 | return r; |
| 2958 | |
| 2959 | drm_kms_helper_poll_init(adev->ddev); |
| 2960 | |
| 2961 | return r; |
| 2962 | } |
| 2963 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2964 | static int dce_v11_0_sw_fini(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2965 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2966 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 2967 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2968 | kfree(adev->mode_info.bios_hardcoded_edid); |
| 2969 | |
| 2970 | drm_kms_helper_poll_fini(adev->ddev); |
| 2971 | |
| 2972 | dce_v11_0_audio_fini(adev); |
| 2973 | |
| 2974 | dce_v11_0_afmt_fini(adev); |
| 2975 | |
| 2976 | adev->mode_info.mode_config_initialized = false; |
| 2977 | |
| 2978 | return 0; |
| 2979 | } |
| 2980 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2981 | static int dce_v11_0_hw_init(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2982 | { |
| 2983 | int i; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 2984 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 2985 | |
| 2986 | dce_v11_0_init_golden_registers(adev); |
| 2987 | |
| 2988 | /* init dig PHYs, disp eng pll */ |
| 2989 | amdgpu_atombios_encoder_init_dig(adev); |
| 2990 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); |
| 2991 | |
| 2992 | /* initialize hpd */ |
| 2993 | dce_v11_0_hpd_init(adev); |
| 2994 | |
| 2995 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 2996 | dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); |
| 2997 | } |
| 2998 | |
| 2999 | return 0; |
| 3000 | } |
| 3001 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3002 | static int dce_v11_0_hw_fini(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3003 | { |
| 3004 | int i; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3005 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3006 | |
| 3007 | dce_v11_0_hpd_fini(adev); |
| 3008 | |
| 3009 | for (i = 0; i < adev->mode_info.audio.num_pins; i++) { |
| 3010 | dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false); |
| 3011 | } |
| 3012 | |
| 3013 | return 0; |
| 3014 | } |
| 3015 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3016 | static int dce_v11_0_suspend(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3017 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3018 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3019 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3020 | amdgpu_atombios_scratch_regs_save(adev); |
| 3021 | |
| 3022 | dce_v11_0_hpd_fini(adev); |
| 3023 | |
| 3024 | return 0; |
| 3025 | } |
| 3026 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3027 | static int dce_v11_0_resume(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3028 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3029 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3030 | |
| 3031 | dce_v11_0_init_golden_registers(adev); |
| 3032 | |
| 3033 | amdgpu_atombios_scratch_regs_restore(adev); |
| 3034 | |
| 3035 | /* init dig PHYs, disp eng pll */ |
| 3036 | amdgpu_atombios_crtc_powergate_init(adev); |
| 3037 | amdgpu_atombios_encoder_init_dig(adev); |
| 3038 | amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk); |
| 3039 | /* turn on the BL */ |
| 3040 | if (adev->mode_info.bl_encoder) { |
| 3041 | u8 bl_level = amdgpu_display_backlight_get_level(adev, |
| 3042 | adev->mode_info.bl_encoder); |
| 3043 | amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder, |
| 3044 | bl_level); |
| 3045 | } |
| 3046 | |
| 3047 | /* initialize hpd */ |
| 3048 | dce_v11_0_hpd_init(adev); |
| 3049 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3050 | return 0; |
| 3051 | } |
| 3052 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3053 | static bool dce_v11_0_is_idle(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3054 | { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3055 | return true; |
| 3056 | } |
| 3057 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3058 | static int dce_v11_0_wait_for_idle(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3059 | { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3060 | return 0; |
| 3061 | } |
| 3062 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3063 | static void dce_v11_0_print_status(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3064 | { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3065 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
| 3066 | |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3067 | dev_info(adev->dev, "DCE 10.x registers\n"); |
| 3068 | /* XXX todo */ |
| 3069 | } |
| 3070 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3071 | static int dce_v11_0_soft_reset(void *handle) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3072 | { |
| 3073 | u32 srbm_soft_reset = 0, tmp; |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3074 | struct amdgpu_device *adev = (struct amdgpu_device *)handle; |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3075 | |
| 3076 | if (dce_v11_0_is_display_hung(adev)) |
| 3077 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; |
| 3078 | |
| 3079 | if (srbm_soft_reset) { |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3080 | dce_v11_0_print_status((void *)adev); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3081 | |
| 3082 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 3083 | tmp |= srbm_soft_reset; |
| 3084 | dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); |
| 3085 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 3086 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 3087 | |
| 3088 | udelay(50); |
| 3089 | |
| 3090 | tmp &= ~srbm_soft_reset; |
| 3091 | WREG32(mmSRBM_SOFT_RESET, tmp); |
| 3092 | tmp = RREG32(mmSRBM_SOFT_RESET); |
| 3093 | |
| 3094 | /* Wait a little for things to settle down */ |
| 3095 | udelay(50); |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3096 | dce_v11_0_print_status((void *)adev); |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3097 | } |
| 3098 | return 0; |
| 3099 | } |
| 3100 | |
| 3101 | static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev, |
| 3102 | int crtc, |
| 3103 | enum amdgpu_interrupt_state state) |
| 3104 | { |
| 3105 | u32 lb_interrupt_mask; |
| 3106 | |
| 3107 | if (crtc >= adev->mode_info.num_crtc) { |
| 3108 | DRM_DEBUG("invalid crtc %d\n", crtc); |
| 3109 | return; |
| 3110 | } |
| 3111 | |
| 3112 | switch (state) { |
| 3113 | case AMDGPU_IRQ_STATE_DISABLE: |
| 3114 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); |
| 3115 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, |
| 3116 | VBLANK_INTERRUPT_MASK, 0); |
| 3117 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); |
| 3118 | break; |
| 3119 | case AMDGPU_IRQ_STATE_ENABLE: |
| 3120 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); |
| 3121 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, |
| 3122 | VBLANK_INTERRUPT_MASK, 1); |
| 3123 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); |
| 3124 | break; |
| 3125 | default: |
| 3126 | break; |
| 3127 | } |
| 3128 | } |
| 3129 | |
| 3130 | static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev, |
| 3131 | int crtc, |
| 3132 | enum amdgpu_interrupt_state state) |
| 3133 | { |
| 3134 | u32 lb_interrupt_mask; |
| 3135 | |
| 3136 | if (crtc >= adev->mode_info.num_crtc) { |
| 3137 | DRM_DEBUG("invalid crtc %d\n", crtc); |
| 3138 | return; |
| 3139 | } |
| 3140 | |
| 3141 | switch (state) { |
| 3142 | case AMDGPU_IRQ_STATE_DISABLE: |
| 3143 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); |
| 3144 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, |
| 3145 | VLINE_INTERRUPT_MASK, 0); |
| 3146 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); |
| 3147 | break; |
| 3148 | case AMDGPU_IRQ_STATE_ENABLE: |
| 3149 | lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]); |
| 3150 | lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK, |
| 3151 | VLINE_INTERRUPT_MASK, 1); |
| 3152 | WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask); |
| 3153 | break; |
| 3154 | default: |
| 3155 | break; |
| 3156 | } |
| 3157 | } |
| 3158 | |
| 3159 | static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev, |
| 3160 | struct amdgpu_irq_src *source, |
| 3161 | unsigned hpd, |
| 3162 | enum amdgpu_interrupt_state state) |
| 3163 | { |
| 3164 | u32 tmp; |
| 3165 | |
| 3166 | if (hpd >= adev->mode_info.num_hpd) { |
| 3167 | DRM_DEBUG("invalid hdp %d\n", hpd); |
| 3168 | return 0; |
| 3169 | } |
| 3170 | |
| 3171 | switch (state) { |
| 3172 | case AMDGPU_IRQ_STATE_DISABLE: |
| 3173 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); |
| 3174 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0); |
| 3175 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); |
| 3176 | break; |
| 3177 | case AMDGPU_IRQ_STATE_ENABLE: |
| 3178 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); |
| 3179 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1); |
| 3180 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); |
| 3181 | break; |
| 3182 | default: |
| 3183 | break; |
| 3184 | } |
| 3185 | |
| 3186 | return 0; |
| 3187 | } |
| 3188 | |
| 3189 | static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev, |
| 3190 | struct amdgpu_irq_src *source, |
| 3191 | unsigned type, |
| 3192 | enum amdgpu_interrupt_state state) |
| 3193 | { |
| 3194 | switch (type) { |
| 3195 | case AMDGPU_CRTC_IRQ_VBLANK1: |
| 3196 | dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state); |
| 3197 | break; |
| 3198 | case AMDGPU_CRTC_IRQ_VBLANK2: |
| 3199 | dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state); |
| 3200 | break; |
| 3201 | case AMDGPU_CRTC_IRQ_VBLANK3: |
| 3202 | dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state); |
| 3203 | break; |
| 3204 | case AMDGPU_CRTC_IRQ_VBLANK4: |
| 3205 | dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state); |
| 3206 | break; |
| 3207 | case AMDGPU_CRTC_IRQ_VBLANK5: |
| 3208 | dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state); |
| 3209 | break; |
| 3210 | case AMDGPU_CRTC_IRQ_VBLANK6: |
| 3211 | dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state); |
| 3212 | break; |
| 3213 | case AMDGPU_CRTC_IRQ_VLINE1: |
| 3214 | dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state); |
| 3215 | break; |
| 3216 | case AMDGPU_CRTC_IRQ_VLINE2: |
| 3217 | dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state); |
| 3218 | break; |
| 3219 | case AMDGPU_CRTC_IRQ_VLINE3: |
| 3220 | dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state); |
| 3221 | break; |
| 3222 | case AMDGPU_CRTC_IRQ_VLINE4: |
| 3223 | dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state); |
| 3224 | break; |
| 3225 | case AMDGPU_CRTC_IRQ_VLINE5: |
| 3226 | dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state); |
| 3227 | break; |
| 3228 | case AMDGPU_CRTC_IRQ_VLINE6: |
| 3229 | dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state); |
| 3230 | break; |
| 3231 | default: |
| 3232 | break; |
| 3233 | } |
| 3234 | return 0; |
| 3235 | } |
| 3236 | |
| 3237 | static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev, |
| 3238 | struct amdgpu_irq_src *src, |
| 3239 | unsigned type, |
| 3240 | enum amdgpu_interrupt_state state) |
| 3241 | { |
| 3242 | u32 reg, reg_block; |
| 3243 | /* now deal with page flip IRQ */ |
| 3244 | switch (type) { |
| 3245 | case AMDGPU_PAGEFLIP_IRQ_D1: |
| 3246 | reg_block = CRTC0_REGISTER_OFFSET; |
| 3247 | break; |
| 3248 | case AMDGPU_PAGEFLIP_IRQ_D2: |
| 3249 | reg_block = CRTC1_REGISTER_OFFSET; |
| 3250 | break; |
| 3251 | case AMDGPU_PAGEFLIP_IRQ_D3: |
| 3252 | reg_block = CRTC2_REGISTER_OFFSET; |
| 3253 | break; |
| 3254 | case AMDGPU_PAGEFLIP_IRQ_D4: |
| 3255 | reg_block = CRTC3_REGISTER_OFFSET; |
| 3256 | break; |
| 3257 | case AMDGPU_PAGEFLIP_IRQ_D5: |
| 3258 | reg_block = CRTC4_REGISTER_OFFSET; |
| 3259 | break; |
| 3260 | case AMDGPU_PAGEFLIP_IRQ_D6: |
| 3261 | reg_block = CRTC5_REGISTER_OFFSET; |
| 3262 | break; |
| 3263 | default: |
| 3264 | DRM_ERROR("invalid pageflip crtc %d\n", type); |
| 3265 | return -EINVAL; |
| 3266 | } |
| 3267 | |
| 3268 | reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block); |
| 3269 | if (state == AMDGPU_IRQ_STATE_DISABLE) |
| 3270 | WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); |
| 3271 | else |
| 3272 | WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK); |
| 3273 | |
| 3274 | return 0; |
| 3275 | } |
| 3276 | |
| 3277 | static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev, |
| 3278 | struct amdgpu_irq_src *source, |
| 3279 | struct amdgpu_iv_entry *entry) |
| 3280 | { |
| 3281 | int reg_block; |
| 3282 | unsigned long flags; |
| 3283 | unsigned crtc_id; |
| 3284 | struct amdgpu_crtc *amdgpu_crtc; |
| 3285 | struct amdgpu_flip_work *works; |
| 3286 | |
| 3287 | crtc_id = (entry->src_id - 8) >> 1; |
| 3288 | amdgpu_crtc = adev->mode_info.crtcs[crtc_id]; |
| 3289 | |
| 3290 | /* ack the interrupt */ |
| 3291 | switch(crtc_id){ |
| 3292 | case AMDGPU_PAGEFLIP_IRQ_D1: |
| 3293 | reg_block = CRTC0_REGISTER_OFFSET; |
| 3294 | break; |
| 3295 | case AMDGPU_PAGEFLIP_IRQ_D2: |
| 3296 | reg_block = CRTC1_REGISTER_OFFSET; |
| 3297 | break; |
| 3298 | case AMDGPU_PAGEFLIP_IRQ_D3: |
| 3299 | reg_block = CRTC2_REGISTER_OFFSET; |
| 3300 | break; |
| 3301 | case AMDGPU_PAGEFLIP_IRQ_D4: |
| 3302 | reg_block = CRTC3_REGISTER_OFFSET; |
| 3303 | break; |
| 3304 | case AMDGPU_PAGEFLIP_IRQ_D5: |
| 3305 | reg_block = CRTC4_REGISTER_OFFSET; |
| 3306 | break; |
| 3307 | case AMDGPU_PAGEFLIP_IRQ_D6: |
| 3308 | reg_block = CRTC5_REGISTER_OFFSET; |
| 3309 | break; |
| 3310 | default: |
| 3311 | DRM_ERROR("invalid pageflip crtc %d\n", crtc_id); |
| 3312 | return -EINVAL; |
| 3313 | } |
| 3314 | |
| 3315 | if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK) |
| 3316 | WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK); |
| 3317 | |
| 3318 | /* IRQ could occur when in initial stage */ |
| 3319 | if(amdgpu_crtc == NULL) |
| 3320 | return 0; |
| 3321 | |
| 3322 | spin_lock_irqsave(&adev->ddev->event_lock, flags); |
| 3323 | works = amdgpu_crtc->pflip_works; |
| 3324 | if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ |
| 3325 | DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != " |
| 3326 | "AMDGPU_FLIP_SUBMITTED(%d)\n", |
| 3327 | amdgpu_crtc->pflip_status, |
| 3328 | AMDGPU_FLIP_SUBMITTED); |
| 3329 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); |
| 3330 | return 0; |
| 3331 | } |
| 3332 | |
| 3333 | /* page flip completed. clean up */ |
| 3334 | amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; |
| 3335 | amdgpu_crtc->pflip_works = NULL; |
| 3336 | |
| 3337 | /* wakeup usersapce */ |
| 3338 | if(works->event) |
| 3339 | drm_send_vblank_event(adev->ddev, crtc_id, works->event); |
| 3340 | |
| 3341 | spin_unlock_irqrestore(&adev->ddev->event_lock, flags); |
| 3342 | |
| 3343 | drm_vblank_put(adev->ddev, amdgpu_crtc->crtc_id); |
| 3344 | amdgpu_irq_put(adev, &adev->pageflip_irq, crtc_id); |
| 3345 | queue_work(amdgpu_crtc->pflip_queue, &works->unpin_work); |
| 3346 | |
| 3347 | return 0; |
| 3348 | } |
| 3349 | |
| 3350 | static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev, |
| 3351 | int hpd) |
| 3352 | { |
| 3353 | u32 tmp; |
| 3354 | |
| 3355 | if (hpd >= adev->mode_info.num_hpd) { |
| 3356 | DRM_DEBUG("invalid hdp %d\n", hpd); |
| 3357 | return; |
| 3358 | } |
| 3359 | |
| 3360 | tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]); |
| 3361 | tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1); |
| 3362 | WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp); |
| 3363 | } |
| 3364 | |
| 3365 | static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev, |
| 3366 | int crtc) |
| 3367 | { |
| 3368 | u32 tmp; |
| 3369 | |
| 3370 | if (crtc >= adev->mode_info.num_crtc) { |
| 3371 | DRM_DEBUG("invalid crtc %d\n", crtc); |
| 3372 | return; |
| 3373 | } |
| 3374 | |
| 3375 | tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]); |
| 3376 | tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1); |
| 3377 | WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp); |
| 3378 | } |
| 3379 | |
| 3380 | static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev, |
| 3381 | int crtc) |
| 3382 | { |
| 3383 | u32 tmp; |
| 3384 | |
| 3385 | if (crtc >= adev->mode_info.num_crtc) { |
| 3386 | DRM_DEBUG("invalid crtc %d\n", crtc); |
| 3387 | return; |
| 3388 | } |
| 3389 | |
| 3390 | tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]); |
| 3391 | tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1); |
| 3392 | WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp); |
| 3393 | } |
| 3394 | |
| 3395 | static int dce_v11_0_crtc_irq(struct amdgpu_device *adev, |
| 3396 | struct amdgpu_irq_src *source, |
| 3397 | struct amdgpu_iv_entry *entry) |
| 3398 | { |
| 3399 | unsigned crtc = entry->src_id - 1; |
| 3400 | uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); |
| 3401 | unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc); |
| 3402 | |
| 3403 | switch (entry->src_data) { |
| 3404 | case 0: /* vblank */ |
| 3405 | if (disp_int & interrupt_status_offsets[crtc].vblank) { |
| 3406 | dce_v11_0_crtc_vblank_int_ack(adev, crtc); |
| 3407 | if (amdgpu_irq_enabled(adev, source, irq_type)) { |
| 3408 | drm_handle_vblank(adev->ddev, crtc); |
| 3409 | } |
| 3410 | DRM_DEBUG("IH: D%d vblank\n", crtc + 1); |
| 3411 | } |
| 3412 | break; |
| 3413 | case 1: /* vline */ |
| 3414 | if (disp_int & interrupt_status_offsets[crtc].vline) { |
| 3415 | dce_v11_0_crtc_vline_int_ack(adev, crtc); |
| 3416 | DRM_DEBUG("IH: D%d vline\n", crtc + 1); |
| 3417 | } |
| 3418 | break; |
| 3419 | default: |
| 3420 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); |
| 3421 | break; |
| 3422 | } |
| 3423 | |
| 3424 | return 0; |
| 3425 | } |
| 3426 | |
| 3427 | static int dce_v11_0_hpd_irq(struct amdgpu_device *adev, |
| 3428 | struct amdgpu_irq_src *source, |
| 3429 | struct amdgpu_iv_entry *entry) |
| 3430 | { |
| 3431 | uint32_t disp_int, mask; |
| 3432 | unsigned hpd; |
| 3433 | |
| 3434 | if (entry->src_data >= adev->mode_info.num_hpd) { |
| 3435 | DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data); |
| 3436 | return 0; |
| 3437 | } |
| 3438 | |
| 3439 | hpd = entry->src_data; |
| 3440 | disp_int = RREG32(interrupt_status_offsets[hpd].reg); |
| 3441 | mask = interrupt_status_offsets[hpd].hpd; |
| 3442 | |
| 3443 | if (disp_int & mask) { |
| 3444 | dce_v11_0_hpd_int_ack(adev, hpd); |
| 3445 | schedule_work(&adev->hotplug_work); |
| 3446 | DRM_DEBUG("IH: HPD%d\n", hpd + 1); |
| 3447 | } |
| 3448 | |
| 3449 | return 0; |
| 3450 | } |
| 3451 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3452 | static int dce_v11_0_set_clockgating_state(void *handle, |
| 3453 | enum amd_clockgating_state state) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3454 | { |
| 3455 | return 0; |
| 3456 | } |
| 3457 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3458 | static int dce_v11_0_set_powergating_state(void *handle, |
| 3459 | enum amd_powergating_state state) |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3460 | { |
| 3461 | return 0; |
| 3462 | } |
| 3463 | |
yanyang1 | 5fc3aee | 2015-05-22 14:39:35 -0400 | [diff] [blame] | 3464 | const struct amd_ip_funcs dce_v11_0_ip_funcs = { |
Alex Deucher | aaa36a976 | 2015-04-20 17:31:14 -0400 | [diff] [blame] | 3465 | .early_init = dce_v11_0_early_init, |
| 3466 | .late_init = NULL, |
| 3467 | .sw_init = dce_v11_0_sw_init, |
| 3468 | .sw_fini = dce_v11_0_sw_fini, |
| 3469 | .hw_init = dce_v11_0_hw_init, |
| 3470 | .hw_fini = dce_v11_0_hw_fini, |
| 3471 | .suspend = dce_v11_0_suspend, |
| 3472 | .resume = dce_v11_0_resume, |
| 3473 | .is_idle = dce_v11_0_is_idle, |
| 3474 | .wait_for_idle = dce_v11_0_wait_for_idle, |
| 3475 | .soft_reset = dce_v11_0_soft_reset, |
| 3476 | .print_status = dce_v11_0_print_status, |
| 3477 | .set_clockgating_state = dce_v11_0_set_clockgating_state, |
| 3478 | .set_powergating_state = dce_v11_0_set_powergating_state, |
| 3479 | }; |
| 3480 | |
| 3481 | static void |
| 3482 | dce_v11_0_encoder_mode_set(struct drm_encoder *encoder, |
| 3483 | struct drm_display_mode *mode, |
| 3484 | struct drm_display_mode *adjusted_mode) |
| 3485 | { |
| 3486 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 3487 | |
| 3488 | amdgpu_encoder->pixel_clock = adjusted_mode->clock; |
| 3489 | |
| 3490 | /* need to call this here rather than in prepare() since we need some crtc info */ |
| 3491 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 3492 | |
| 3493 | /* set scaler clears this on some chips */ |
| 3494 | dce_v11_0_set_interleave(encoder->crtc, mode); |
| 3495 | |
| 3496 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { |
| 3497 | dce_v11_0_afmt_enable(encoder, true); |
| 3498 | dce_v11_0_afmt_setmode(encoder, adjusted_mode); |
| 3499 | } |
| 3500 | } |
| 3501 | |
| 3502 | static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder) |
| 3503 | { |
| 3504 | struct amdgpu_device *adev = encoder->dev->dev_private; |
| 3505 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 3506 | struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder); |
| 3507 | |
| 3508 | if ((amdgpu_encoder->active_device & |
| 3509 | (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) || |
| 3510 | (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != |
| 3511 | ENCODER_OBJECT_ID_NONE)) { |
| 3512 | struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; |
| 3513 | if (dig) { |
| 3514 | dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder); |
| 3515 | if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) |
| 3516 | dig->afmt = adev->mode_info.afmt[dig->dig_encoder]; |
| 3517 | } |
| 3518 | } |
| 3519 | |
| 3520 | amdgpu_atombios_scratch_regs_lock(adev, true); |
| 3521 | |
| 3522 | if (connector) { |
| 3523 | struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); |
| 3524 | |
| 3525 | /* select the clock/data port if it uses a router */ |
| 3526 | if (amdgpu_connector->router.cd_valid) |
| 3527 | amdgpu_i2c_router_select_cd_port(amdgpu_connector); |
| 3528 | |
| 3529 | /* turn eDP panel on for mode set */ |
| 3530 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
| 3531 | amdgpu_atombios_encoder_set_edp_panel_power(connector, |
| 3532 | ATOM_TRANSMITTER_ACTION_POWER_ON); |
| 3533 | } |
| 3534 | |
| 3535 | /* this is needed for the pll/ss setup to work correctly in some cases */ |
| 3536 | amdgpu_atombios_encoder_set_crtc_source(encoder); |
| 3537 | /* set up the FMT blocks */ |
| 3538 | dce_v11_0_program_fmt(encoder); |
| 3539 | } |
| 3540 | |
| 3541 | static void dce_v11_0_encoder_commit(struct drm_encoder *encoder) |
| 3542 | { |
| 3543 | struct drm_device *dev = encoder->dev; |
| 3544 | struct amdgpu_device *adev = dev->dev_private; |
| 3545 | |
| 3546 | /* need to call this here as we need the crtc set up */ |
| 3547 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON); |
| 3548 | amdgpu_atombios_scratch_regs_lock(adev, false); |
| 3549 | } |
| 3550 | |
| 3551 | static void dce_v11_0_encoder_disable(struct drm_encoder *encoder) |
| 3552 | { |
| 3553 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 3554 | struct amdgpu_encoder_atom_dig *dig; |
| 3555 | |
| 3556 | amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 3557 | |
| 3558 | if (amdgpu_atombios_encoder_is_digital(encoder)) { |
| 3559 | if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) |
| 3560 | dce_v11_0_afmt_enable(encoder, false); |
| 3561 | dig = amdgpu_encoder->enc_priv; |
| 3562 | dig->dig_encoder = -1; |
| 3563 | } |
| 3564 | amdgpu_encoder->active_device = 0; |
| 3565 | } |
| 3566 | |
| 3567 | /* these are handled by the primary encoders */ |
| 3568 | static void dce_v11_0_ext_prepare(struct drm_encoder *encoder) |
| 3569 | { |
| 3570 | |
| 3571 | } |
| 3572 | |
| 3573 | static void dce_v11_0_ext_commit(struct drm_encoder *encoder) |
| 3574 | { |
| 3575 | |
| 3576 | } |
| 3577 | |
| 3578 | static void |
| 3579 | dce_v11_0_ext_mode_set(struct drm_encoder *encoder, |
| 3580 | struct drm_display_mode *mode, |
| 3581 | struct drm_display_mode *adjusted_mode) |
| 3582 | { |
| 3583 | |
| 3584 | } |
| 3585 | |
| 3586 | static void dce_v11_0_ext_disable(struct drm_encoder *encoder) |
| 3587 | { |
| 3588 | |
| 3589 | } |
| 3590 | |
| 3591 | static void |
| 3592 | dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode) |
| 3593 | { |
| 3594 | |
| 3595 | } |
| 3596 | |
| 3597 | static bool dce_v11_0_ext_mode_fixup(struct drm_encoder *encoder, |
| 3598 | const struct drm_display_mode *mode, |
| 3599 | struct drm_display_mode *adjusted_mode) |
| 3600 | { |
| 3601 | return true; |
| 3602 | } |
| 3603 | |
| 3604 | static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = { |
| 3605 | .dpms = dce_v11_0_ext_dpms, |
| 3606 | .mode_fixup = dce_v11_0_ext_mode_fixup, |
| 3607 | .prepare = dce_v11_0_ext_prepare, |
| 3608 | .mode_set = dce_v11_0_ext_mode_set, |
| 3609 | .commit = dce_v11_0_ext_commit, |
| 3610 | .disable = dce_v11_0_ext_disable, |
| 3611 | /* no detect for TMDS/LVDS yet */ |
| 3612 | }; |
| 3613 | |
| 3614 | static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = { |
| 3615 | .dpms = amdgpu_atombios_encoder_dpms, |
| 3616 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, |
| 3617 | .prepare = dce_v11_0_encoder_prepare, |
| 3618 | .mode_set = dce_v11_0_encoder_mode_set, |
| 3619 | .commit = dce_v11_0_encoder_commit, |
| 3620 | .disable = dce_v11_0_encoder_disable, |
| 3621 | .detect = amdgpu_atombios_encoder_dig_detect, |
| 3622 | }; |
| 3623 | |
| 3624 | static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = { |
| 3625 | .dpms = amdgpu_atombios_encoder_dpms, |
| 3626 | .mode_fixup = amdgpu_atombios_encoder_mode_fixup, |
| 3627 | .prepare = dce_v11_0_encoder_prepare, |
| 3628 | .mode_set = dce_v11_0_encoder_mode_set, |
| 3629 | .commit = dce_v11_0_encoder_commit, |
| 3630 | .detect = amdgpu_atombios_encoder_dac_detect, |
| 3631 | }; |
| 3632 | |
| 3633 | static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder) |
| 3634 | { |
| 3635 | struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 3636 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 3637 | amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder); |
| 3638 | kfree(amdgpu_encoder->enc_priv); |
| 3639 | drm_encoder_cleanup(encoder); |
| 3640 | kfree(amdgpu_encoder); |
| 3641 | } |
| 3642 | |
| 3643 | static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = { |
| 3644 | .destroy = dce_v11_0_encoder_destroy, |
| 3645 | }; |
| 3646 | |
| 3647 | static void dce_v11_0_encoder_add(struct amdgpu_device *adev, |
| 3648 | uint32_t encoder_enum, |
| 3649 | uint32_t supported_device, |
| 3650 | u16 caps) |
| 3651 | { |
| 3652 | struct drm_device *dev = adev->ddev; |
| 3653 | struct drm_encoder *encoder; |
| 3654 | struct amdgpu_encoder *amdgpu_encoder; |
| 3655 | |
| 3656 | /* see if we already added it */ |
| 3657 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 3658 | amdgpu_encoder = to_amdgpu_encoder(encoder); |
| 3659 | if (amdgpu_encoder->encoder_enum == encoder_enum) { |
| 3660 | amdgpu_encoder->devices |= supported_device; |
| 3661 | return; |
| 3662 | } |
| 3663 | |
| 3664 | } |
| 3665 | |
| 3666 | /* add a new one */ |
| 3667 | amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL); |
| 3668 | if (!amdgpu_encoder) |
| 3669 | return; |
| 3670 | |
| 3671 | encoder = &amdgpu_encoder->base; |
| 3672 | switch (adev->mode_info.num_crtc) { |
| 3673 | case 1: |
| 3674 | encoder->possible_crtcs = 0x1; |
| 3675 | break; |
| 3676 | case 2: |
| 3677 | default: |
| 3678 | encoder->possible_crtcs = 0x3; |
| 3679 | break; |
| 3680 | case 4: |
| 3681 | encoder->possible_crtcs = 0xf; |
| 3682 | break; |
| 3683 | case 6: |
| 3684 | encoder->possible_crtcs = 0x3f; |
| 3685 | break; |
| 3686 | } |
| 3687 | |
| 3688 | amdgpu_encoder->enc_priv = NULL; |
| 3689 | |
| 3690 | amdgpu_encoder->encoder_enum = encoder_enum; |
| 3691 | amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; |
| 3692 | amdgpu_encoder->devices = supported_device; |
| 3693 | amdgpu_encoder->rmx_type = RMX_OFF; |
| 3694 | amdgpu_encoder->underscan_type = UNDERSCAN_OFF; |
| 3695 | amdgpu_encoder->is_ext_encoder = false; |
| 3696 | amdgpu_encoder->caps = caps; |
| 3697 | |
| 3698 | switch (amdgpu_encoder->encoder_id) { |
| 3699 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1: |
| 3700 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2: |
| 3701 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3702 | DRM_MODE_ENCODER_DAC); |
| 3703 | drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs); |
| 3704 | break; |
| 3705 | case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: |
| 3706 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY: |
| 3707 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1: |
| 3708 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2: |
| 3709 | case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3: |
| 3710 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 3711 | amdgpu_encoder->rmx_type = RMX_FULL; |
| 3712 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3713 | DRM_MODE_ENCODER_LVDS); |
| 3714 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder); |
| 3715 | } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { |
| 3716 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3717 | DRM_MODE_ENCODER_DAC); |
| 3718 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); |
| 3719 | } else { |
| 3720 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3721 | DRM_MODE_ENCODER_TMDS); |
| 3722 | amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder); |
| 3723 | } |
| 3724 | drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs); |
| 3725 | break; |
| 3726 | case ENCODER_OBJECT_ID_SI170B: |
| 3727 | case ENCODER_OBJECT_ID_CH7303: |
| 3728 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOA: |
| 3729 | case ENCODER_OBJECT_ID_EXTERNAL_SDVOB: |
| 3730 | case ENCODER_OBJECT_ID_TITFP513: |
| 3731 | case ENCODER_OBJECT_ID_VT1623: |
| 3732 | case ENCODER_OBJECT_ID_HDMI_SI1930: |
| 3733 | case ENCODER_OBJECT_ID_TRAVIS: |
| 3734 | case ENCODER_OBJECT_ID_NUTMEG: |
| 3735 | /* these are handled by the primary encoders */ |
| 3736 | amdgpu_encoder->is_ext_encoder = true; |
| 3737 | if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) |
| 3738 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3739 | DRM_MODE_ENCODER_LVDS); |
| 3740 | else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) |
| 3741 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3742 | DRM_MODE_ENCODER_DAC); |
| 3743 | else |
| 3744 | drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs, |
| 3745 | DRM_MODE_ENCODER_TMDS); |
| 3746 | drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs); |
| 3747 | break; |
| 3748 | } |
| 3749 | } |
| 3750 | |
| 3751 | static const struct amdgpu_display_funcs dce_v11_0_display_funcs = { |
| 3752 | .set_vga_render_state = &dce_v11_0_set_vga_render_state, |
| 3753 | .bandwidth_update = &dce_v11_0_bandwidth_update, |
| 3754 | .vblank_get_counter = &dce_v11_0_vblank_get_counter, |
| 3755 | .vblank_wait = &dce_v11_0_vblank_wait, |
| 3756 | .is_display_hung = &dce_v11_0_is_display_hung, |
| 3757 | .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level, |
| 3758 | .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level, |
| 3759 | .hpd_sense = &dce_v11_0_hpd_sense, |
| 3760 | .hpd_set_polarity = &dce_v11_0_hpd_set_polarity, |
| 3761 | .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg, |
| 3762 | .page_flip = &dce_v11_0_page_flip, |
| 3763 | .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos, |
| 3764 | .add_encoder = &dce_v11_0_encoder_add, |
| 3765 | .add_connector = &amdgpu_connector_add, |
| 3766 | .stop_mc_access = &dce_v11_0_stop_mc_access, |
| 3767 | .resume_mc_access = &dce_v11_0_resume_mc_access, |
| 3768 | }; |
| 3769 | |
| 3770 | static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev) |
| 3771 | { |
| 3772 | if (adev->mode_info.funcs == NULL) |
| 3773 | adev->mode_info.funcs = &dce_v11_0_display_funcs; |
| 3774 | } |
| 3775 | |
| 3776 | static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = { |
| 3777 | .set = dce_v11_0_set_crtc_irq_state, |
| 3778 | .process = dce_v11_0_crtc_irq, |
| 3779 | }; |
| 3780 | |
| 3781 | static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = { |
| 3782 | .set = dce_v11_0_set_pageflip_irq_state, |
| 3783 | .process = dce_v11_0_pageflip_irq, |
| 3784 | }; |
| 3785 | |
| 3786 | static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = { |
| 3787 | .set = dce_v11_0_set_hpd_irq_state, |
| 3788 | .process = dce_v11_0_hpd_irq, |
| 3789 | }; |
| 3790 | |
| 3791 | static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev) |
| 3792 | { |
| 3793 | adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST; |
| 3794 | adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs; |
| 3795 | |
| 3796 | adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST; |
| 3797 | adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs; |
| 3798 | |
| 3799 | adev->hpd_irq.num_types = AMDGPU_HPD_LAST; |
| 3800 | adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs; |
| 3801 | } |