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Linus Torvalds1da177e2005-04-16 15:20:36 -07001#ifndef __LINUX_UHCI_HCD_H
2#define __LINUX_UHCI_HCD_H
3
4#include <linux/list.h>
5#include <linux/usb.h>
6
7#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8#define PIPE_DEVEP_MASK 0x0007ff00
9
Alan Stern8b262bd2005-09-26 16:31:15 -040010
Linus Torvalds1da177e2005-04-16 15:20:36 -070011/*
12 * Universal Host Controller Interface data structures and defines
13 */
14
15/* Command register */
16#define USBCMD 0
17#define USBCMD_RS 0x0001 /* Run/Stop */
18#define USBCMD_HCRESET 0x0002 /* Host reset */
19#define USBCMD_GRESET 0x0004 /* Global reset */
20#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
21#define USBCMD_FGR 0x0010 /* Force Global Resume */
22#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
23#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
24#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
25
26/* Status register */
27#define USBSTS 2
28#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
29#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
30#define USBSTS_RD 0x0004 /* Resume Detect */
Alan Sterndccf4a42005-12-17 17:58:46 -050031#define USBSTS_HSE 0x0008 /* Host System Error: PCI problems */
32#define USBSTS_HCPE 0x0010 /* Host Controller Process Error:
33 * the schedule is buggy */
Linus Torvalds1da177e2005-04-16 15:20:36 -070034#define USBSTS_HCH 0x0020 /* HC Halted */
35
36/* Interrupt enable register */
37#define USBINTR 4
38#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
39#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
40#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
41#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
42
43#define USBFRNUM 6
44#define USBFLBASEADD 8
45#define USBSOF 12
Alan Sterna8bed8b2005-04-09 17:29:00 -040046#define USBSOF_DEFAULT 64 /* Frame length is exactly 1 ms */
Linus Torvalds1da177e2005-04-16 15:20:36 -070047
48/* USB port status and control registers */
49#define USBPORTSC1 16
50#define USBPORTSC2 18
Alan Sterndccf4a42005-12-17 17:58:46 -050051#define USBPORTSC_CCS 0x0001 /* Current Connect Status
52 * ("device present") */
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
54#define USBPORTSC_PE 0x0004 /* Port Enable */
55#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
56#define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
57#define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
58#define USBPORTSC_RD 0x0040 /* Resume Detect */
59#define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
60#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
61#define USBPORTSC_PR 0x0200 /* Port Reset */
62/* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
63#define USBPORTSC_OC 0x0400 /* Over Current condition */
64#define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
65#define USBPORTSC_SUSP 0x1000 /* Suspend */
66#define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
67#define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
68#define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
69
70/* Legacy support register */
71#define USBLEGSUP 0xc0
72#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
Alan Sterna8bed8b2005-04-09 17:29:00 -040073#define USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
74#define USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
Alan Sterndccf4a42005-12-17 17:58:46 -050076#define UHCI_PTR_BITS __constant_cpu_to_le32(0x000F)
77#define UHCI_PTR_TERM __constant_cpu_to_le32(0x0001)
78#define UHCI_PTR_QH __constant_cpu_to_le32(0x0002)
79#define UHCI_PTR_DEPTH __constant_cpu_to_le32(0x0004)
80#define UHCI_PTR_BREADTH __constant_cpu_to_le32(0x0000)
Linus Torvalds1da177e2005-04-16 15:20:36 -070081
82#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
83#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
Alan Sterndccf4a42005-12-17 17:58:46 -050084#define CAN_SCHEDULE_FRAMES 1000 /* how far in the future frames
85 * can be scheduled */
Alan Stern3ca2a322007-01-16 11:56:32 -050086#define MAX_PHASE 32 /* Periodic scheduling length */
Linus Torvalds1da177e2005-04-16 15:20:36 -070087
Alan Stern84afddd2006-05-12 11:35:45 -040088/* When no queues need Full-Speed Bandwidth Reclamation,
89 * delay this long before turning FSBR off */
Alan Sternc5e3b742006-06-05 12:28:57 -040090#define FSBR_OFF_DELAY msecs_to_jiffies(10)
Alan Stern84afddd2006-05-12 11:35:45 -040091
92/* If a queue hasn't advanced after this much time, assume it is stuck */
93#define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
94
Linus Torvalds1da177e2005-04-16 15:20:36 -070095
Alan Stern8b262bd2005-09-26 16:31:15 -040096/*
97 * Queue Headers
98 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070099
100/*
Alan Sterndccf4a42005-12-17 17:58:46 -0500101 * One role of a QH is to hold a queue of TDs for some endpoint. One QH goes
102 * with each endpoint, and qh->element (updated by the HC) is either:
103 * - the next unprocessed TD in the endpoint's queue, or
104 * - UHCI_PTR_TERM (when there's no more traffic for this endpoint).
Linus Torvalds1da177e2005-04-16 15:20:36 -0700105 *
106 * The other role of a QH is to serve as a "skeleton" framelist entry, so we
107 * can easily splice a QH for some endpoint into the schedule at the right
108 * place. Then qh->element is UHCI_PTR_TERM.
109 *
Alan Sterndccf4a42005-12-17 17:58:46 -0500110 * In the schedule, qh->link maintains a list of QHs seen by the HC:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111 * skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
Alan Sterndccf4a42005-12-17 17:58:46 -0500112 *
113 * qh->node is the software equivalent of qh->link. The differences
114 * are that the software list is doubly-linked and QHs in the UNLINKING
115 * state are on the software list but not the hardware schedule.
116 *
117 * For bookkeeping purposes we maintain QHs even for Isochronous endpoints,
118 * but they never get added to the hardware schedule.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119 */
Alan Sterndccf4a42005-12-17 17:58:46 -0500120#define QH_STATE_IDLE 1 /* QH is not being used */
121#define QH_STATE_UNLINKING 2 /* QH has been removed from the
122 * schedule but the hardware may
123 * still be using it */
124#define QH_STATE_ACTIVE 3 /* QH is on the schedule */
125
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126struct uhci_qh {
127 /* Hardware fields */
Alan Sterndccf4a42005-12-17 17:58:46 -0500128 __le32 link; /* Next QH in the schedule */
129 __le32 element; /* Queue element (TD) pointer */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130
131 /* Software fields */
Alan Stern28b93252007-02-19 15:51:51 -0500132 dma_addr_t dma_handle;
133
Alan Sterndccf4a42005-12-17 17:58:46 -0500134 struct list_head node; /* Node in the list of QHs */
135 struct usb_host_endpoint *hep; /* Endpoint information */
136 struct usb_device *udev;
137 struct list_head queue; /* Queue of urbps for this QH */
Alan Sternaf0bb592005-12-17 18:00:12 -0500138 struct uhci_td *dummy_td; /* Dummy TD to end the queue */
Alan Stern59e29ed2006-05-12 11:19:19 -0400139 struct uhci_td *post_td; /* Last TD completed */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700140
Alan Sternc8155cc2006-05-19 16:52:35 -0400141 struct usb_iso_packet_descriptor *iso_packet_desc;
142 /* Next urb->iso_frame_desc entry */
Alan Stern84afddd2006-05-12 11:35:45 -0400143 unsigned long advance_jiffies; /* Time of last queue advance */
Alan Sterndccf4a42005-12-17 17:58:46 -0500144 unsigned int unlink_frame; /* When the QH was unlinked */
Alan Sterncaf38272006-05-19 16:44:55 -0400145 unsigned int period; /* For Interrupt and Isochronous QHs */
Alan Stern3ca2a322007-01-16 11:56:32 -0500146 short phase; /* Between 0 and period-1 */
147 short load; /* Periodic time requirement, in us */
Alan Sternc8155cc2006-05-19 16:52:35 -0400148 unsigned int iso_frame; /* Frame # for iso_packet_desc */
Alan Sterncaf38272006-05-19 16:44:55 -0400149
Alan Sterndccf4a42005-12-17 17:58:46 -0500150 int state; /* QH_STATE_xxx; see above */
Alan Stern4de7d2c2006-05-05 16:26:58 -0400151 int type; /* Queue type (control, bulk, etc) */
Alan Stern17230ac2007-02-19 15:52:45 -0500152 int skel; /* Skeleton queue number */
Alan Stern0ed8fee2005-12-17 18:02:38 -0500153
154 unsigned int initial_toggle:1; /* Endpoint's current toggle value */
155 unsigned int needs_fixup:1; /* Must fix the TD toggle values */
Alan Stern59e29ed2006-05-12 11:19:19 -0400156 unsigned int is_stopped:1; /* Queue was stopped by error/unlink */
Alan Stern84afddd2006-05-12 11:35:45 -0400157 unsigned int wait_expired:1; /* QH_WAIT_TIMEOUT has expired */
Alan Stern3ca2a322007-01-16 11:56:32 -0500158 unsigned int bandwidth_reserved:1; /* Periodic bandwidth has
159 * been allocated */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700160} __attribute__((aligned(16)));
161
162/*
163 * We need a special accessor for the element pointer because it is
Alan Stern8b262bd2005-09-26 16:31:15 -0400164 * subject to asynchronous updates by the controller.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165 */
Alan Sterndccf4a42005-12-17 17:58:46 -0500166static inline __le32 qh_element(struct uhci_qh *qh) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700167 __le32 element = qh->element;
168
169 barrier();
170 return element;
171}
172
Alan Stern28b93252007-02-19 15:51:51 -0500173#define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle))
174
Alan Stern8b262bd2005-09-26 16:31:15 -0400175
176/*
177 * Transfer Descriptors
178 */
179
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180/*
181 * for TD <status>:
182 */
183#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
184#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
185#define TD_CTRL_C_ERR_SHIFT 27
186#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
187#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
188#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
189#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
190#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
191#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
192#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
193#define TD_CTRL_NAK (1 << 19) /* NAK Received */
194#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
195#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
196#define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
197
198#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
Alan Sterndccf4a42005-12-17 17:58:46 -0500199 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
200 TD_CTRL_BITSTUFF)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700201
202#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
203#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
Alan Sterndccf4a42005-12-17 17:58:46 -0500204#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
205 TD_CTRL_ACTLEN_MASK) /* 1-based */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700206
207/*
208 * for TD <info>: (a.k.a. Token)
209 */
210#define td_token(td) le32_to_cpu((td)->token)
211#define TD_TOKEN_DEVADDR_SHIFT 8
212#define TD_TOKEN_TOGGLE_SHIFT 19
213#define TD_TOKEN_TOGGLE (1 << 19)
214#define TD_TOKEN_EXPLEN_SHIFT 21
Alan Sterndccf4a42005-12-17 17:58:46 -0500215#define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n-1 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700216#define TD_TOKEN_PID_MASK 0xFF
217
Alan Sternfa346562005-11-30 11:57:51 -0500218#define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
219 TD_TOKEN_EXPLEN_SHIFT)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220
Alan Sternfa346562005-11-30 11:57:51 -0500221#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
222 1) & TD_TOKEN_EXPLEN_MASK)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
224#define uhci_endpoint(token) (((token) >> 15) & 0xf)
225#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
226#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
227#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
228#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
229#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
230
231/*
232 * The documentation says "4 words for hardware, 4 words for software".
233 *
234 * That's silly, the hardware doesn't care. The hardware only cares that
235 * the hardware words are 16-byte aligned, and we can have any amount of
Alan Stern8b262bd2005-09-26 16:31:15 -0400236 * sw space after the TD entry.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237 *
238 * td->link points to either another TD (not necessarily for the same urb or
Alan Sterndccf4a42005-12-17 17:58:46 -0500239 * even the same endpoint), or nothing (PTR_TERM), or a QH.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 */
241struct uhci_td {
242 /* Hardware fields */
243 __le32 link;
244 __le32 status;
245 __le32 token;
246 __le32 buffer;
247
248 /* Software fields */
249 dma_addr_t dma_handle;
250
Alan Stern8b262bd2005-09-26 16:31:15 -0400251 struct list_head list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700252
253 int frame; /* for iso: what frame? */
Alan Stern8b262bd2005-09-26 16:31:15 -0400254 struct list_head fl_list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255} __attribute__((aligned(16)));
256
257/*
258 * We need a special accessor for the control/status word because it is
Alan Stern8b262bd2005-09-26 16:31:15 -0400259 * subject to asynchronous updates by the controller.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700260 */
Alan Sterndccf4a42005-12-17 17:58:46 -0500261static inline u32 td_status(struct uhci_td *td) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700262 __le32 status = td->status;
263
264 barrier();
265 return le32_to_cpu(status);
266}
267
Alan Stern28b93252007-02-19 15:51:51 -0500268#define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle))
269
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270
271/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400272 * Skeleton Queue Headers
273 */
274
275/*
Alan Sterndccf4a42005-12-17 17:58:46 -0500276 * The UHCI driver uses QHs with Interrupt, Control and Bulk URBs for
277 * automatic queuing. To make it easy to insert entries into the schedule,
Alan Stern17230ac2007-02-19 15:52:45 -0500278 * we have a skeleton of QHs for each predefined Interrupt latency.
279 * Asynchronous QHs (low-speed control, full-speed control, and bulk)
280 * go onto the period-1 interrupt list, since they all get accessed on
281 * every frame.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282 *
Alan Stern17230ac2007-02-19 15:52:45 -0500283 * When we want to add a new QH, we add it to the list starting from the
284 * appropriate skeleton QH. For instance, the schedule can look like this:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285 *
286 * skel int128 QH
287 * dev 1 interrupt QH
288 * dev 5 interrupt QH
289 * skel int64 QH
290 * skel int32 QH
291 * ...
Alan Stern17230ac2007-02-19 15:52:45 -0500292 * skel int1 + async QH
293 * dev 5 low-speed control QH
Linus Torvalds1da177e2005-04-16 15:20:36 -0700294 * dev 1 bulk QH
295 * dev 2 bulk QH
Linus Torvalds1da177e2005-04-16 15:20:36 -0700296 *
Alan Stern17230ac2007-02-19 15:52:45 -0500297 * There is a special terminating QH used to keep full-speed bandwidth
298 * reclamation active when no full-speed control or bulk QHs are linked
299 * into the schedule. It has an inactive TD (to work around a PIIX bug,
300 * see the Intel errata) and it points back to itself.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301 *
Alan Stern17230ac2007-02-19 15:52:45 -0500302 * There's a special skeleton QH for Isochronous QHs which never appears
303 * on the schedule. Isochronous TDs go on the schedule before the
Alan Sterndccf4a42005-12-17 17:58:46 -0500304 * the skeleton QHs. The hardware accesses them directly rather than
305 * through their QH, which is used only for bookkeeping purposes.
306 * While the UHCI spec doesn't forbid the use of QHs for Isochronous,
307 * it doesn't use them either. And the spec says that queues never
308 * advance on an error completion status, which makes them totally
309 * unsuitable for Isochronous transfers.
Alan Stern17230ac2007-02-19 15:52:45 -0500310 *
311 * There's also a special skeleton QH used for QHs which are in the process
312 * of unlinking and so may still be in use by the hardware. It too never
313 * appears on the schedule.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700314 */
315
Alan Stern17230ac2007-02-19 15:52:45 -0500316#define UHCI_NUM_SKELQH 11
317#define SKEL_UNLINK 0
318#define skel_unlink_qh skelqh[SKEL_UNLINK]
319#define SKEL_ISO 1
320#define skel_iso_qh skelqh[SKEL_ISO]
321 /* int128, int64, ..., int1 = 2, 3, ..., 9 */
322#define SKEL_INDEX(exponent) (9 - exponent)
323#define SKEL_ASYNC 9
324#define skel_async_qh skelqh[SKEL_ASYNC]
325#define SKEL_TERM 10
326#define skel_term_qh skelqh[SKEL_TERM]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327
Alan Stern17230ac2007-02-19 15:52:45 -0500328/* The following entries refer to sublists of skel_async_qh */
329#define SKEL_LS_CONTROL 20
330#define SKEL_FS_CONTROL 21
331#define SKEL_FSBR SKEL_FS_CONTROL
332#define SKEL_BULK 22
Alan Stern8b262bd2005-09-26 16:31:15 -0400333
Linus Torvalds1da177e2005-04-16 15:20:36 -0700334/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400335 * The UHCI controller and root hub
336 */
337
338/*
339 * States for the root hub:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700340 *
341 * To prevent "bouncing" in the presence of electrical noise,
Alan Sternc8f4fe42005-04-09 17:27:32 -0400342 * when there are no devices attached we delay for 1 second in the
343 * RUNNING_NODEVS state before switching to the AUTO_STOPPED state.
344 *
345 * (Note that the AUTO_STOPPED state won't be necessary once the hub
346 * driver learns to autosuspend.)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700347 */
Alan Sternc8f4fe42005-04-09 17:27:32 -0400348enum uhci_rh_state {
Alan Stern6c1b4452005-04-21 16:04:58 -0400349 /* In the following states the HC must be halted.
Alan Stern8b262bd2005-09-26 16:31:15 -0400350 * These two must come first. */
Alan Stern6c1b4452005-04-21 16:04:58 -0400351 UHCI_RH_RESET,
Alan Sternc8f4fe42005-04-09 17:27:32 -0400352 UHCI_RH_SUSPENDED,
Alan Sterna8bed8b2005-04-09 17:29:00 -0400353
Alan Sternc8f4fe42005-04-09 17:27:32 -0400354 UHCI_RH_AUTO_STOPPED,
355 UHCI_RH_RESUMING,
356
Alan Stern6c1b4452005-04-21 16:04:58 -0400357 /* In this state the HC changes from running to halted,
358 * so it can legally appear either way. */
Alan Sternc8f4fe42005-04-09 17:27:32 -0400359 UHCI_RH_SUSPENDING,
360
Alan Stern6c1b4452005-04-21 16:04:58 -0400361 /* In the following states it's an error if the HC is halted.
Alan Stern8b262bd2005-09-26 16:31:15 -0400362 * These two must come last. */
Alan Sternc8f4fe42005-04-09 17:27:32 -0400363 UHCI_RH_RUNNING, /* The normal state */
364 UHCI_RH_RUNNING_NODEVS, /* Running with no devices attached */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365};
366
367/*
Alan Stern8b262bd2005-09-26 16:31:15 -0400368 * The full UHCI controller information:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369 */
370struct uhci_hcd {
371
372 /* debugfs */
373 struct dentry *dentry;
374
375 /* Grabbed from PCI */
376 unsigned long io_addr;
377
378 struct dma_pool *qh_pool;
379 struct dma_pool *td_pool;
380
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
Alan Stern687f5f32005-11-30 17:16:19 -0500382 struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QHs */
Alan Stern0ed8fee2005-12-17 18:02:38 -0500383 struct uhci_qh *next_qh; /* Next QH to scan */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700384
385 spinlock_t lock;
Alan Sterna1d59ce2005-09-16 14:22:51 -0400386
Alan Sterndccf4a42005-12-17 17:58:46 -0500387 dma_addr_t frame_dma_handle; /* Hardware frame list */
Alan Stern8b262bd2005-09-26 16:31:15 -0400388 __le32 *frame;
Alan Sterndccf4a42005-12-17 17:58:46 -0500389 void **frame_cpu; /* CPU's frame list */
Alan Sterna1d59ce2005-09-16 14:22:51 -0400390
Alan Sternc8f4fe42005-04-09 17:27:32 -0400391 enum uhci_rh_state rh_state;
392 unsigned long auto_stop_time; /* When to AUTO_STOP */
393
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 unsigned int frame_number; /* As of last check */
395 unsigned int is_stopped;
396#define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
Alan Sternc8155cc2006-05-19 16:52:35 -0400397 unsigned int last_iso_frame; /* Frame of last scan */
398 unsigned int cur_iso_frame; /* Frame for current scan */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700399
400 unsigned int scan_in_progress:1; /* Schedule scan is running */
401 unsigned int need_rescan:1; /* Redo the schedule scan */
Alan Sterne323de42006-06-05 12:21:30 -0400402 unsigned int dead:1; /* Controller has died */
Alan Sternd8f12ab2008-04-22 10:49:15 -0400403 unsigned int RD_enable:1; /* Suspended root hub with
404 Resume-Detect interrupts
405 enabled */
Alan Stern8d402e12005-12-17 18:03:37 -0500406 unsigned int is_initialized:1; /* Data structure is usable */
Alan Stern84afddd2006-05-12 11:35:45 -0400407 unsigned int fsbr_is_on:1; /* FSBR is turned on */
Alan Sternc5e3b742006-06-05 12:28:57 -0400408 unsigned int fsbr_is_wanted:1; /* Does any URB want FSBR? */
409 unsigned int fsbr_expiring:1; /* FSBR is timing out */
410
411 struct timer_list fsbr_timer; /* For turning off FBSR */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413 /* Support for port suspend/resume/reset */
414 unsigned long port_c_suspend; /* Bit-arrays of ports */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700415 unsigned long resuming_ports;
416 unsigned long ports_timeout; /* Time to stop signalling */
417
Alan Sterndccf4a42005-12-17 17:58:46 -0500418 struct list_head idle_qh_list; /* Where the idle QHs live */
419
Alan Stern1f09df82005-09-05 13:59:51 -0400420 int rh_numports; /* Number of root-hub ports */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700421
422 wait_queue_head_t waitqh; /* endpoint_disable waiters */
Alan Sterndccf4a42005-12-17 17:58:46 -0500423 int num_waiting; /* Number of waiters */
Alan Stern3ca2a322007-01-16 11:56:32 -0500424
425 int total_load; /* Sum of array values */
426 short load[MAX_PHASE]; /* Periodic allocations */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700427};
428
429/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
430static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
431{
432 return (struct uhci_hcd *) (hcd->hcd_priv);
433}
434static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
435{
436 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
437}
438
439#define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
440
Alan Sternc4334722006-05-19 16:34:57 -0400441/* Utility macro for comparing frame numbers */
442#define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
443
Alan Stern8b262bd2005-09-26 16:31:15 -0400444
445/*
446 * Private per-URB data
447 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700448struct urb_priv {
Alan Sterndccf4a42005-12-17 17:58:46 -0500449 struct list_head node; /* Node in the QH's urbp list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700450
451 struct urb *urb;
452
453 struct uhci_qh *qh; /* QH for this URB */
Alan Stern8b262bd2005-09-26 16:31:15 -0400454 struct list_head td_list;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455
Alan Stern84afddd2006-05-12 11:35:45 -0400456 unsigned fsbr:1; /* URB wants FSBR */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700457};
458
Alan Stern8b262bd2005-09-26 16:31:15 -0400459
Alan Sternc8f4fe42005-04-09 17:27:32 -0400460/* Some special IDs */
461
462#define PCI_VENDOR_ID_GENESYS 0x17a0
463#define PCI_DEVICE_ID_GL880S_UHCI 0x8083
Alan Sternc8f4fe42005-04-09 17:27:32 -0400464
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465#endif