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Michael Buesch61e115a2007-09-18 15:12:50 -04001#ifndef LINUX_SSB_REGS_H_
2#define LINUX_SSB_REGS_H_
3
4
5/* SiliconBackplane Address Map.
6 * All regions may not exist on all chips.
7 */
8#define SSB_SDRAM_BASE 0x00000000U /* Physical SDRAM */
9#define SSB_PCI_MEM 0x08000000U /* Host Mode sb2pcitranslation0 (64 MB) */
10#define SSB_PCI_CFG 0x0c000000U /* Host Mode sb2pcitranslation1 (64 MB) */
11#define SSB_SDRAM_SWAPPED 0x10000000U /* Byteswapped Physical SDRAM */
12#define SSB_ENUM_BASE 0x18000000U /* Enumeration space base */
13#define SSB_ENUM_LIMIT 0x18010000U /* Enumeration space limit */
14
15#define SSB_FLASH2 0x1c000000U /* Flash Region 2 (region 1 shadowed here) */
16#define SSB_FLASH2_SZ 0x02000000U /* Size of Flash Region 2 */
17
18#define SSB_EXTIF_BASE 0x1f000000U /* External Interface region base address */
19#define SSB_FLASH1 0x1fc00000U /* Flash Region 1 */
20#define SSB_FLASH1_SZ 0x00400000U /* Size of Flash Region 1 */
21
22#define SSB_PCI_DMA 0x40000000U /* Client Mode sb2pcitranslation2 (1 GB) */
23#define SSB_PCI_DMA_SZ 0x40000000U /* Client Mode sb2pcitranslation2 size in bytes */
24#define SSB_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
25#define SSB_PCIE_DMA_H32 0x80000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
26#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
27#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
28
29
30/* Enumeration space constants */
31#define SSB_CORE_SIZE 0x1000 /* Size of a core MMIO area */
32#define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
33
34
35/* mips address */
36#define SSB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
37
38
39/* SSB PCI config space registers. */
40#define SSB_PMCSR 0x44
41#define SSB_PE 0x100
42#define SSB_BAR0_WIN 0x80 /* Backplane address space 0 */
43#define SSB_BAR1_WIN 0x84 /* Backplane address space 1 */
44#define SSB_SPROMCTL 0x88 /* SPROM control */
45#define SSB_SPROMCTL_WE 0x10 /* SPROM write enable */
46#define SSB_BAR1_CONTROL 0x8c /* Address space 1 burst control */
47#define SSB_PCI_IRQS 0x90 /* PCI interrupts */
48#define SSB_PCI_IRQMASK 0x94 /* PCI IRQ control and mask (pcirev >= 6 only) */
49#define SSB_BACKPLANE_IRQS 0x98 /* Backplane Interrupts */
50#define SSB_GPIO_IN 0xB0 /* GPIO Input (pcirev >= 3 only) */
51#define SSB_GPIO_OUT 0xB4 /* GPIO Output (pcirev >= 3 only) */
52#define SSB_GPIO_OUT_ENABLE 0xB8 /* GPIO Output Enable/Disable (pcirev >= 3 only) */
53#define SSB_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
54#define SSB_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
55#define SSB_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
56#define SSB_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
57
58
59#define SSB_BAR0_MAX_RETRIES 50
60
61/* Silicon backplane configuration register definitions */
62#define SSB_IPSFLAG 0x0F08
63#define SSB_IPSFLAG_IRQ1 0x0000003F /* which sbflags get routed to mips interrupt 1 */
64#define SSB_IPSFLAG_IRQ1_SHIFT 0
65#define SSB_IPSFLAG_IRQ2 0x00003F00 /* which sbflags get routed to mips interrupt 2 */
66#define SSB_IPSFLAG_IRQ2_SHIFT 8
67#define SSB_IPSFLAG_IRQ3 0x003F0000 /* which sbflags get routed to mips interrupt 3 */
68#define SSB_IPSFLAG_IRQ3_SHIFT 16
69#define SSB_IPSFLAG_IRQ4 0x3F000000 /* which sbflags get routed to mips interrupt 4 */
70#define SSB_IPSFLAG_IRQ4_SHIFT 24
71#define SSB_TPSFLAG 0x0F18
72#define SSB_TPSFLAG_BPFLAG 0x0000003F /* Backplane flag # */
73#define SSB_TPSFLAG_ALWAYSIRQ 0x00000040 /* IRQ is always sent on the Backplane */
74#define SSB_TMERRLOGA 0x0F48
75#define SSB_TMERRLOG 0x0F50
76#define SSB_ADMATCH3 0x0F60
77#define SSB_ADMATCH2 0x0F68
78#define SSB_ADMATCH1 0x0F70
79#define SSB_IMSTATE 0x0F90 /* SB Initiator Agent State */
80#define SSB_IMSTATE_PC 0x0000000f /* Pipe Count */
81#define SSB_IMSTATE_AP_MASK 0x00000030 /* Arbitration Priority */
82#define SSB_IMSTATE_AP_BOTH 0x00000000 /* Use both timeslices and token */
83#define SSB_IMSTATE_AP_TS 0x00000010 /* Use timeslices only */
84#define SSB_IMSTATE_AP_TK 0x00000020 /* Use token only */
85#define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
86#define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
87#define SSB_IMSTATE_TO 0x00040000 /* Timeout */
Rafał Miłeckib1a1bcf2011-02-17 01:50:50 +010088#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
89#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
Michael Buesch61e115a2007-09-18 15:12:50 -040090#define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
91#define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
92#define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
93#define SSB_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
94#define SSB_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
95#define SSB_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
96#define SSB_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
97#define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
98#define SSB_TMSLOW 0x0F98 /* SB Target State Low */
99#define SSB_TMSLOW_RESET 0x00000001 /* Reset */
Rafał Miłecki04ad1fb2011-04-23 19:30:29 +0200100#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
Michael Buesch61e115a2007-09-18 15:12:50 -0400101#define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
102#define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
103#define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
104#define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
105#define SSB_TMSLOW_BE 0x80000000 /* BIST Enable */
106#define SSB_TMSHIGH 0x0F9C /* SB Target State High */
107#define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
108#define SSB_TMSHIGH_INT 0x00000002 /* Interrupt */
109#define SSB_TMSHIGH_BUSY 0x00000004 /* Busy */
110#define SSB_TMSHIGH_TO 0x00000020 /* Timeout. Backplane rev >= 2.3 only */
111#define SSB_TMSHIGH_COREFL 0x1FFF0000 /* Core specific flags */
112#define SSB_TMSHIGH_COREFL_SHIFT 16
113#define SSB_TMSHIGH_DMA64 0x10000000 /* 64bit DMA supported */
114#define SSB_TMSHIGH_GCR 0x20000000 /* Gated Clock Request */
115#define SSB_TMSHIGH_BISTF 0x40000000 /* BIST Failed */
116#define SSB_TMSHIGH_BISTD 0x80000000 /* BIST Done */
117#define SSB_BWA0 0x0FA0
118#define SSB_IMCFGLO 0x0FA8
119#define SSB_IMCFGLO_SERTO 0x00000007 /* Service timeout */
120#define SSB_IMCFGLO_REQTO 0x00000070 /* Request timeout */
121#define SSB_IMCFGLO_REQTO_SHIFT 4
122#define SSB_IMCFGLO_CONNID 0x00FF0000 /* Connection ID */
123#define SSB_IMCFGLO_CONNID_SHIFT 16
124#define SSB_IMCFGHI 0x0FAC
125#define SSB_ADMATCH0 0x0FB0
126#define SSB_TMCFGLO 0x0FB8
127#define SSB_TMCFGHI 0x0FBC
128#define SSB_BCONFIG 0x0FC0
129#define SSB_BSTATE 0x0FC8
130#define SSB_ACTCFG 0x0FD8
131#define SSB_FLAGST 0x0FE8
132#define SSB_IDLOW 0x0FF8
133#define SSB_IDLOW_CFGSP 0x00000003 /* Config Space */
134#define SSB_IDLOW_ADDRNGE 0x00000038 /* Address Ranges supported */
135#define SSB_IDLOW_ADDRNGE_SHIFT 3
136#define SSB_IDLOW_SYNC 0x00000040
137#define SSB_IDLOW_INITIATOR 0x00000080
138#define SSB_IDLOW_MIBL 0x00000F00 /* Minimum Backplane latency */
139#define SSB_IDLOW_MIBL_SHIFT 8
140#define SSB_IDLOW_MABL 0x0000F000 /* Maximum Backplane latency */
141#define SSB_IDLOW_MABL_SHIFT 12
142#define SSB_IDLOW_TIF 0x00010000 /* This Initiator is first */
143#define SSB_IDLOW_CCW 0x000C0000 /* Cycle counter width */
144#define SSB_IDLOW_CCW_SHIFT 18
145#define SSB_IDLOW_TPT 0x00F00000 /* Target ports */
146#define SSB_IDLOW_TPT_SHIFT 20
147#define SSB_IDLOW_INITP 0x0F000000 /* Initiator ports */
148#define SSB_IDLOW_INITP_SHIFT 24
149#define SSB_IDLOW_SSBREV 0xF0000000 /* Sonics Backplane Revision code */
150#define SSB_IDLOW_SSBREV_22 0x00000000 /* <= 2.2 */
151#define SSB_IDLOW_SSBREV_23 0x10000000 /* 2.3 */
Larry Fingerc272ef42007-11-09 16:56:25 -0600152#define SSB_IDLOW_SSBREV_24 0x40000000 /* ?? Found in BCM4328 */
153#define SSB_IDLOW_SSBREV_25 0x50000000 /* ?? Not Found yet */
154#define SSB_IDLOW_SSBREV_26 0x60000000 /* ?? Found in some BCM4311/2 */
155#define SSB_IDLOW_SSBREV_27 0x70000000 /* ?? Found in some BCM4311/2 */
Michael Buesch61e115a2007-09-18 15:12:50 -0400156#define SSB_IDHIGH 0x0FFC /* SB Identification High */
157#define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
158#define SSB_IDHIGH_CC 0x00008FF0 /* Core Code */
159#define SSB_IDHIGH_CC_SHIFT 4
160#define SSB_IDHIGH_RCHI 0x00007000 /* Revision Code (high part) */
161#define SSB_IDHIGH_RCHI_SHIFT 8 /* yes, shift 8 is right */
162#define SSB_IDHIGH_VC 0xFFFF0000 /* Vendor Code */
163#define SSB_IDHIGH_VC_SHIFT 16
164
165/* SPROM shadow area. If not otherwise noted, fields are
166 * two bytes wide. Note that the SPROM can _only_ be read
Gábor Stefanikf6790562009-08-10 21:23:08 +0200167 * in two-byte quantities.
Michael Buesch61e115a2007-09-18 15:12:50 -0400168 */
169#define SSB_SPROMSIZE_WORDS 64
170#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
Larry Fingerc272ef42007-11-09 16:56:25 -0600171#define SSB_SPROMSIZE_WORDS_R123 64
172#define SSB_SPROMSIZE_WORDS_R4 220
173#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
174#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
Rafał Miłecki78e578c2013-05-13 22:07:53 +0200175#define SSB_SPROMSIZE_WORDS_R10 230
Rafał Miłeckiea2db492010-03-31 21:59:21 +0200176#define SSB_SPROM_BASE1 0x1000
177#define SSB_SPROM_BASE31 0x0800
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200178#define SSB_SPROM_REVISION 0x007E
Michael Buesch61e115a2007-09-18 15:12:50 -0400179#define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
180#define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
181#define SSB_SPROM_REVISION_CRC_SHIFT 8
Larry Fingerd3c319f2007-11-09 16:58:20 -0600182
Michael Buesch61e115a2007-09-18 15:12:50 -0400183/* SPROM Revision 1 */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200184#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
185#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
186#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
187#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
188#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
189#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
190#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
Michael Buesch61e115a2007-09-18 15:12:50 -0400191#define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
192#define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
193#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
194#define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
195#define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200196#define SSB_SPROM1_BINF 0x005C /* Board info */
Michael Buesch61e115a2007-09-18 15:12:50 -0400197#define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
198#define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
199#define SSB_SPROM1_BINF_CCODE_SHIFT 8
Michael Buesche861b982007-12-22 21:51:30 +0100200#define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
201#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
202#define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
203#define SSB_SPROM1_BINF_ANTA_SHIFT 14
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200204#define SSB_SPROM1_PA0B0 0x005E
205#define SSB_SPROM1_PA0B1 0x0060
206#define SSB_SPROM1_PA0B2 0x0062
207#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
Michael Buesch61e115a2007-09-18 15:12:50 -0400208#define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
209#define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
210#define SSB_SPROM1_GPIOA_P1_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200211#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
Michael Buesch61e115a2007-09-18 15:12:50 -0400212#define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
213#define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
214#define SSB_SPROM1_GPIOB_P3_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200215#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
Michael Buesch61e115a2007-09-18 15:12:50 -0400216#define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
217#define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
218#define SSB_SPROM1_MAXPWR_A_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200219#define SSB_SPROM1_PA1B0 0x006A
220#define SSB_SPROM1_PA1B1 0x006C
221#define SSB_SPROM1_PA1B2 0x006E
222#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
Michael Buesch61e115a2007-09-18 15:12:50 -0400223#define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
224#define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
225#define SSB_SPROM1_ITSSI_A_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200226#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
227#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
Michael Buesche861b982007-12-22 21:51:30 +0100228#define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
229#define SSB_SPROM1_AGAIN_BG_SHIFT 0
230#define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
231#define SSB_SPROM1_AGAIN_A_SHIFT 8
Hauke Mehrtensbf7d4202012-04-29 02:04:10 +0200232#define SSB_SPROM1_CCODE 0x0076
Larry Fingerd3c319f2007-11-09 16:58:20 -0600233
Michael Buesch61e115a2007-09-18 15:12:50 -0400234/* SPROM Revision 2 (inherits from rev 1) */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200235#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
236#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
Michael Buesch61e115a2007-09-18 15:12:50 -0400237#define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
238#define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
239#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200240#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
241#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
242#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
243#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
244#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
245#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
246#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
Michael Buesch61e115a2007-09-18 15:12:50 -0400247#define SSB_SPROM2_OPO_VALUE 0x00FF
248#define SSB_SPROM2_OPO_UNUSED 0xFF00
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200249#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
Larry Fingerd3c319f2007-11-09 16:58:20 -0600250
Larry Fingerc272ef42007-11-09 16:56:25 -0600251/* SPROM Revision 3 (inherits most data from rev 2) */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200252#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
253#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
254#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
255#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
Michael Buesch61e115a2007-09-18 15:12:50 -0400256#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
257#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
258#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
259#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
Rafał Miłecki5af55422010-03-31 22:54:19 +0200260#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200261#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
Michael Buesch61e115a2007-09-18 15:12:50 -0400262#define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
263#define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
264#define SSB_SPROM3_CCKPO_2M_SHIFT 4
265#define SSB_SPROM3_CCKPO_55M 0x0F00 /* 5.5M Rate PO */
266#define SSB_SPROM3_CCKPO_55M_SHIFT 8
267#define SSB_SPROM3_CCKPO_11M 0xF000 /* 11M Rate PO */
268#define SSB_SPROM3_CCKPO_11M_SHIFT 12
269#define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
Larry Fingerd3c319f2007-11-09 16:58:20 -0600270
Michael Buesche861b982007-12-22 21:51:30 +0100271/* SPROM Revision 4 */
Hauke Mehrtens673335c2012-04-29 02:04:11 +0200272#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
Rafał Miłecki5af55422010-03-31 22:54:19 +0200273#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
274#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
Rafał Miłecki6d1d4ea2011-02-08 23:32:17 +0100275#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
276#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200277#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
Rafał Miłecki5af55422010-03-31 22:54:19 +0200278#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
279#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
280#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
281#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
282#define SSB_SPROM4_GPIOA_P1_SHIFT 8
283#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
284#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
285#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
286#define SSB_SPROM4_GPIOB_P3_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200287#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
Larry Fingerac82fab2007-11-09 16:54:45 -0600288#define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
289#define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
290#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
291#define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
292#define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
Hauke Mehrtens12bef782013-03-21 16:26:19 +0100293#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
294#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
295#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
296#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
297#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200298#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
Michael Buesche861b982007-12-22 21:51:30 +0100299#define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
300#define SSB_SPROM4_AGAIN0_SHIFT 0
301#define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
302#define SSB_SPROM4_AGAIN1_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200303#define SSB_SPROM4_AGAIN23 0x0060
Michael Buesche861b982007-12-22 21:51:30 +0100304#define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
305#define SSB_SPROM4_AGAIN2_SHIFT 0
306#define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
307#define SSB_SPROM4_AGAIN3_SHIFT 8
Rafał Miłecki172c69a2010-11-28 10:39:35 +0100308#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
309#define SSB_SPROM4_TXPID2G0 0x00FF
310#define SSB_SPROM4_TXPID2G0_SHIFT 0
311#define SSB_SPROM4_TXPID2G1 0xFF00
312#define SSB_SPROM4_TXPID2G1_SHIFT 8
313#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
314#define SSB_SPROM4_TXPID2G2 0x00FF
315#define SSB_SPROM4_TXPID2G2_SHIFT 0
316#define SSB_SPROM4_TXPID2G3 0xFF00
317#define SSB_SPROM4_TXPID2G3_SHIFT 8
318#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
319#define SSB_SPROM4_TXPID5G0 0x00FF
320#define SSB_SPROM4_TXPID5G0_SHIFT 0
321#define SSB_SPROM4_TXPID5G1 0xFF00
322#define SSB_SPROM4_TXPID5G1_SHIFT 8
323#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
324#define SSB_SPROM4_TXPID5G2 0x00FF
325#define SSB_SPROM4_TXPID5G2_SHIFT 0
326#define SSB_SPROM4_TXPID5G3 0xFF00
327#define SSB_SPROM4_TXPID5G3_SHIFT 8
328#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
329#define SSB_SPROM4_TXPID5GL0 0x00FF
330#define SSB_SPROM4_TXPID5GL0_SHIFT 0
331#define SSB_SPROM4_TXPID5GL1 0xFF00
332#define SSB_SPROM4_TXPID5GL1_SHIFT 8
333#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
334#define SSB_SPROM4_TXPID5GL2 0x00FF
335#define SSB_SPROM4_TXPID5GL2_SHIFT 0
336#define SSB_SPROM4_TXPID5GL3 0xFF00
337#define SSB_SPROM4_TXPID5GL3_SHIFT 8
338#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
339#define SSB_SPROM4_TXPID5GH0 0x00FF
340#define SSB_SPROM4_TXPID5GH0_SHIFT 0
341#define SSB_SPROM4_TXPID5GH1 0xFF00
342#define SSB_SPROM4_TXPID5GH1_SHIFT 8
343#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
344#define SSB_SPROM4_TXPID5GH2 0x00FF
345#define SSB_SPROM4_TXPID5GH2_SHIFT 0
346#define SSB_SPROM4_TXPID5GH3 0xFF00
347#define SSB_SPROM4_TXPID5GH3_SHIFT 8
Rafał Miłecki6ad59342014-07-15 16:18:57 +0200348
349/* There are 4 blocks with power info sharing the same layout */
350#define SSB_SPROM4_PWR_INFO_CORE0 0x0080
351#define SSB_SPROM4_PWR_INFO_CORE1 0x00AE
352#define SSB_SPROM4_PWR_INFO_CORE2 0x00DC
353#define SSB_SPROM4_PWR_INFO_CORE3 0x010A
354
355#define SSB_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */
356#define SSB_SPROM4_2G_MAXP 0x00FF
357#define SSB_SPROM4_2G_ITSSI 0xFF00
358#define SSB_SPROM4_2G_ITSSI_SHIFT 8
359#define SSB_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */
360#define SSB_SPROM4_2G_PA_1 0x04
361#define SSB_SPROM4_2G_PA_2 0x06
362#define SSB_SPROM4_2G_PA_3 0x08
363#define SSB_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */
364#define SSB_SPROM4_5G_MAXP 0x00FF
365#define SSB_SPROM4_5G_ITSSI 0xFF00
366#define SSB_SPROM4_5G_ITSSI_SHIFT 8
367#define SSB_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */
368#define SSB_SPROM4_5GH_MAXP 0x00FF
369#define SSB_SPROM4_5GL_MAXP 0xFF00
370#define SSB_SPROM4_5GL_MAXP_SHIFT 8
371#define SSB_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */
372#define SSB_SPROM4_5G_PA_1 0x10
373#define SSB_SPROM4_5G_PA_2 0x12
374#define SSB_SPROM4_5G_PA_3 0x14
375#define SSB_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */
376#define SSB_SPROM4_5GL_PA_1 0x18
377#define SSB_SPROM4_5GL_PA_2 0x1A
378#define SSB_SPROM4_5GL_PA_3 0x1C
379#define SSB_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */
380#define SSB_SPROM4_5GH_PA_1 0x20
381#define SSB_SPROM4_5GH_PA_2 0x22
382#define SSB_SPROM4_5GH_PA_3 0x24
383
384/* TODO: Make it deprecated */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200385#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
Larry Fingerd3c319f2007-11-09 16:58:20 -0600386#define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
387#define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
388#define SSB_SPROM4_ITSSI_BG_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200389#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
Larry Fingerd3c319f2007-11-09 16:58:20 -0600390#define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
391#define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
392#define SSB_SPROM4_ITSSI_A_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200393#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
394#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
395#define SSB_SPROM4_PA0B2 0x0086
396#define SSB_SPROM4_PA1B0 0x008E
397#define SSB_SPROM4_PA1B1 0x0090
398#define SSB_SPROM4_PA1B2 0x0092
Michael Buesch61e115a2007-09-18 15:12:50 -0400399
Larry Finger095f6952008-08-19 12:50:31 -0500400/* SPROM Revision 5 (inherits most data from rev 4) */
Rafał Miłecki5af55422010-03-31 22:54:19 +0200401#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200402#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
403#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
Rafał Miłecki6d1d4ea2011-02-08 23:32:17 +0100404#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
405#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200406#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200407#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
Larry Finger095f6952008-08-19 12:50:31 -0500408#define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
409#define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
410#define SSB_SPROM5_GPIOA_P1_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200411#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
Larry Finger095f6952008-08-19 12:50:31 -0500412#define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
413#define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
414#define SSB_SPROM5_GPIOB_P3_SHIFT 8
415
Michael Buesch6b1c7c62008-12-25 00:39:28 +0100416/* SPROM Revision 8 */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200417#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
418#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
419#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
420#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
421#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
422#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
423#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
Rafał Miłecki5af55422010-03-31 22:54:19 +0200424#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
425#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
426#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
427#define SSB_SPROM8_GPIOA_P1_SHIFT 8
428#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
429#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
430#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
431#define SSB_SPROM8_GPIOB_P3_SHIFT 8
Hauke Mehrtense2da4bd2012-04-29 02:04:13 +0200432#define SSB_SPROM8_LEDDC 0x009A
433#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
434#define SSB_SPROM8_LEDDC_ON_SHIFT 8
435#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
436#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200437#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
Rafał Miłecki5af55422010-03-31 22:54:19 +0200438#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
439#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
440#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
441#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200442#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
Michael Buesch6b1c7c62008-12-25 00:39:28 +0100443#define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
444#define SSB_SPROM8_AGAIN0_SHIFT 0
445#define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
446#define SSB_SPROM8_AGAIN1_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200447#define SSB_SPROM8_AGAIN23 0x00A0
Michael Buesch6b1c7c62008-12-25 00:39:28 +0100448#define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
449#define SSB_SPROM8_AGAIN2_SHIFT 0
450#define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
451#define SSB_SPROM8_AGAIN3_SHIFT 8
Hauke Mehrtense2da4bd2012-04-29 02:04:13 +0200452#define SSB_SPROM8_TXRXC 0x00A2
453#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
454#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
455#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
456#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
457#define SSB_SPROM8_TXRXC_SWITCH 0xff00
458#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200459#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200460#define SSB_SPROM8_RSSISMF2G 0x000F
461#define SSB_SPROM8_RSSISMC2G 0x00F0
462#define SSB_SPROM8_RSSISMC2G_SHIFT 4
463#define SSB_SPROM8_RSSISAV2G 0x0700
464#define SSB_SPROM8_RSSISAV2G_SHIFT 8
465#define SSB_SPROM8_BXA2G 0x1800
466#define SSB_SPROM8_BXA2G_SHIFT 11
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200467#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200468#define SSB_SPROM8_RSSISMF5G 0x000F
469#define SSB_SPROM8_RSSISMC5G 0x00F0
470#define SSB_SPROM8_RSSISMC5G_SHIFT 4
471#define SSB_SPROM8_RSSISAV5G 0x0700
472#define SSB_SPROM8_RSSISAV5G_SHIFT 8
473#define SSB_SPROM8_BXA5G 0x1800
474#define SSB_SPROM8_BXA5G_SHIFT 11
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200475#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200476#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
477#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
478#define SSB_SPROM8_TRI5G_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200479#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200480#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
481#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
482#define SSB_SPROM8_TRI5GH_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200483#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200484#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
Hauke Mehrtense2da4bd2012-04-29 02:04:13 +0200485#define SSB_SPROM8_RXPO2G_SHIFT 0
Gábor Stefanikf6790562009-08-10 21:23:08 +0200486#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
487#define SSB_SPROM8_RXPO5G_SHIFT 8
Rafał Miłecki8a5ac6e2011-12-08 18:02:21 +0100488#define SSB_SPROM8_FEM2G 0x00AE
489#define SSB_SPROM8_FEM5G 0x00B0
490#define SSB_SROM8_FEM_TSSIPOS 0x0001
491#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
492#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
493#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
494#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
495#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
496#define SSB_SROM8_FEM_TR_ISO 0x0700
497#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
498#define SSB_SROM8_FEM_ANTSWLUT 0xF800
499#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
500#define SSB_SPROM8_THERMAL 0x00B2
Hauke Mehrtense2da4bd2012-04-29 02:04:13 +0200501#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
502#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
503#define SSB_SPROM8_THERMAL_TRESH 0xff00
504#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
505/* Temp sense related entries */
506#define SSB_SPROM8_RAWTS 0x00B4
507#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
508#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
509#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
510#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
511#define SSB_SPROM8_OPT_CORRX 0x00B6
512#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
513#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
514#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
515#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
516#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
517#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
518/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
519#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
520#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
521#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
522#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
523#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
524#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
525#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
Piotr Haber7583fe72012-11-08 09:47:27 +0100526#define SSB_SPROM8_TEMPDELTA 0x00BC
Hauke Mehrtense2da4bd2012-04-29 02:04:13 +0200527#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
528#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
529#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
530#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
531#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
532#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
Rafał Miłeckib0f70292012-01-02 08:41:23 +0100533
534/* There are 4 blocks with power info sharing the same layout */
535#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
536#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
537#define SSB_SROM8_PWR_INFO_CORE2 0x0100
538#define SSB_SROM8_PWR_INFO_CORE3 0x0120
539
540#define SSB_SROM8_2G_MAXP_ITSSI 0x00
541#define SSB_SPROM8_2G_MAXP 0x00FF
542#define SSB_SPROM8_2G_ITSSI 0xFF00
543#define SSB_SPROM8_2G_ITSSI_SHIFT 8
544#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
545#define SSB_SROM8_2G_PA_1 0x04
546#define SSB_SROM8_2G_PA_2 0x06
547#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
548#define SSB_SPROM8_5G_MAXP 0x00FF
549#define SSB_SPROM8_5G_ITSSI 0xFF00
550#define SSB_SPROM8_5G_ITSSI_SHIFT 8
551#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
552#define SSB_SPROM8_5GH_MAXP 0x00FF
553#define SSB_SPROM8_5GL_MAXP 0xFF00
554#define SSB_SPROM8_5GL_MAXP_SHIFT 8
555#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
556#define SSB_SROM8_5G_PA_1 0x0E
557#define SSB_SROM8_5G_PA_2 0x10
558#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
559#define SSB_SROM8_5GL_PA_1 0x14
560#define SSB_SROM8_5GL_PA_2 0x16
561#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
562#define SSB_SROM8_5GH_PA_1 0x1A
563#define SSB_SROM8_5GH_PA_2 0x1C
564
565/* TODO: Make it deprecated */
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200566#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200567#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
Michael Buesch6b1c7c62008-12-25 00:39:28 +0100568#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
569#define SSB_SPROM8_ITSSI_BG_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200570#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
571#define SSB_SPROM8_PA0B1 0x00C4
572#define SSB_SPROM8_PA0B2 0x00C6
573#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200574#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
Michael Buesch6b1c7c62008-12-25 00:39:28 +0100575#define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
576#define SSB_SPROM8_ITSSI_A_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200577#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
Gábor Stefanikf6790562009-08-10 21:23:08 +0200578#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
579#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
580#define SSB_SPROM8_MAXP_AL_SHIFT 8
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200581#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
582#define SSB_SPROM8_PA1B1 0x00CE
583#define SSB_SPROM8_PA1B2 0x00D0
584#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
585#define SSB_SPROM8_PA1LOB1 0x00D4
586#define SSB_SPROM8_PA1LOB2 0x00D6
587#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
588#define SSB_SPROM8_PA1HIB1 0x00DA
589#define SSB_SPROM8_PA1HIB2 0x00DC
Rafał Miłeckib0f70292012-01-02 08:41:23 +0100590
Rafał Miłecki0a182fd2010-03-31 22:54:18 +0200591#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
592#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
593#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
594#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
595#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
Larry Finger095f6952008-08-19 12:50:31 -0500596
Hauke Mehrtense2da4bd2012-04-29 02:04:13 +0200597#define SSB_SPROM8_2G_MCSPO 0x0152
598#define SSB_SPROM8_5G_MCSPO 0x0162
599#define SSB_SPROM8_5GL_MCSPO 0x0172
600#define SSB_SPROM8_5GH_MCSPO 0x0182
601
602#define SSB_SPROM8_CDDPO 0x0192
603#define SSB_SPROM8_STBCPO 0x0194
604#define SSB_SPROM8_BW40PO 0x0196
605#define SSB_SPROM8_BWDUPPO 0x0198
606
Rafał Miłecki454496f2011-07-23 11:10:11 +0200607/* Values for boardflags_lo read from SPROM */
608#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
609#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
610#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
611#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
612#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
613#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
614#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
615#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
616#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
617#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
618#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
619#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
620#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
621#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
622#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
623#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
624
625/* Values for boardflags_hi read from SPROM */
626#define SSB_BFH_NOPA 0x0001 /* has no PA */
627#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
628#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
629#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
630#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
631#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
632#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
633
634/* Values for boardflags2_lo read from SPROM */
635#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
636#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
637#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
638#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
639#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
640#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
641#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
642#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
643#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
644#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
645#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
646
Michael Buesch61e115a2007-09-18 15:12:50 -0400647/* Values for SSB_SPROM1_BINF_CCODE */
648enum {
649 SSB_SPROM1CCODE_WORLD = 0,
650 SSB_SPROM1CCODE_THAILAND,
651 SSB_SPROM1CCODE_ISRAEL,
652 SSB_SPROM1CCODE_JORDAN,
653 SSB_SPROM1CCODE_CHINA,
654 SSB_SPROM1CCODE_JAPAN,
655 SSB_SPROM1CCODE_USA_CANADA_ANZ,
656 SSB_SPROM1CCODE_EUROPE,
657 SSB_SPROM1CCODE_USA_LOW,
658 SSB_SPROM1CCODE_JAPAN_HIGH,
659 SSB_SPROM1CCODE_ALL,
660 SSB_SPROM1CCODE_NONE,
661};
662
663/* Address-Match values and masks (SSB_ADMATCHxxx) */
664#define SSB_ADM_TYPE 0x00000003 /* Address type */
665#define SSB_ADM_TYPE0 0
666#define SSB_ADM_TYPE1 1
667#define SSB_ADM_TYPE2 2
668#define SSB_ADM_AD64 0x00000004
669#define SSB_ADM_SZ0 0x000000F8 /* Type0 size */
670#define SSB_ADM_SZ0_SHIFT 3
671#define SSB_ADM_SZ1 0x000001F8 /* Type1 size */
672#define SSB_ADM_SZ1_SHIFT 3
673#define SSB_ADM_SZ2 0x000001F8 /* Type2 size */
674#define SSB_ADM_SZ2_SHIFT 3
675#define SSB_ADM_EN 0x00000400 /* Enable */
676#define SSB_ADM_NEG 0x00000800 /* Negative decode */
677#define SSB_ADM_BASE0 0xFFFFFF00 /* Type0 base address */
678#define SSB_ADM_BASE0_SHIFT 8
679#define SSB_ADM_BASE1 0xFFFFF000 /* Type1 base address for the core */
680#define SSB_ADM_BASE1_SHIFT 12
681#define SSB_ADM_BASE2 0xFFFF0000 /* Type2 base address for the core */
682#define SSB_ADM_BASE2_SHIFT 16
683
684
685#endif /* LINUX_SSB_REGS_H_ */