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Bryan Wu1394f032007-05-06 14:50:22 -07001/*
Michael Hennerichcfefe3c2008-02-09 04:12:37 +08002 * File: arch/blackfin/mach-common/ints-priority.c
Bryan Wu1394f032007-05-06 14:50:22 -07003 *
Simon Arlottd2d50aa2007-06-11 15:31:30 +08004 * Description: Set up the interrupt priorities
Bryan Wu1394f032007-05-06 14:50:22 -07005 *
6 * Modified:
7 * 1996 Roman Zippel
8 * 1999 D. Jeff Dionne <jeff@uclinux.org>
9 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
10 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
11 * 2003 Metrowerks/Motorola
12 * 2003 Bas Vermeulen <bas@buyways.nl>
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080013 * Copyright 2004-2008 Analog Devices Inc.
Bryan Wu1394f032007-05-06 14:50:22 -070014 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, see the file COPYING, or write
29 * to the Free Software Foundation, Inc.,
30 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
31 */
32
33#include <linux/module.h>
34#include <linux/kernel_stat.h>
35#include <linux/seq_file.h>
36#include <linux/irq.h>
Yi Li6a01f232009-01-07 23:14:39 +080037#ifdef CONFIG_IPIPE
38#include <linux/ipipe.h>
39#endif
Bryan Wu1394f032007-05-06 14:50:22 -070040#ifdef CONFIG_KGDB
41#include <linux/kgdb.h>
42#endif
43#include <asm/traps.h>
44#include <asm/blackfin.h>
45#include <asm/gpio.h>
46#include <asm/irq_handler.h>
47
Mike Frysinger7beb7432008-11-18 17:48:22 +080048#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
49
Bryan Wu1394f032007-05-06 14:50:22 -070050#ifdef BF537_FAMILY
51# define BF537_GENERIC_ERROR_INT_DEMUX
52#else
53# undef BF537_GENERIC_ERROR_INT_DEMUX
54#endif
55
56/*
57 * NOTES:
58 * - we have separated the physical Hardware interrupt from the
59 * levels that the LINUX kernel sees (see the description in irq.h)
60 * -
61 */
62
Graf Yang6b3087c2009-01-07 23:14:39 +080063#ifndef CONFIG_SMP
Mike Frysingera99bbcc2007-10-22 00:19:31 +080064/* Initialize this to an actual value to force it into the .data
65 * section so that we know it is properly initialized at entry into
66 * the kernel but before bss is initialized to zero (which is where
67 * it would live otherwise). The 0x1f magic represents the IRQs we
68 * cannot actually mask out in hardware.
69 */
Mike Frysinger40059782008-11-18 17:48:22 +080070unsigned long bfin_irq_flags = 0x1f;
71EXPORT_SYMBOL(bfin_irq_flags);
Graf Yang6b3087c2009-01-07 23:14:39 +080072#endif
Bryan Wu1394f032007-05-06 14:50:22 -070073
74/* The number of spurious interrupts */
75atomic_t num_spurious;
76
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080077#ifdef CONFIG_PM
78unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
Michael Hennerich4a88d0c2008-08-05 17:38:41 +080079unsigned vr_wakeup;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +080080#endif
81
Bryan Wu1394f032007-05-06 14:50:22 -070082struct ivgx {
Michael Hennerich464abc52008-02-25 13:50:20 +080083 /* irq number for request_irq, available in mach-bf5xx/irq.h */
Roy Huang24a07a12007-07-12 22:41:45 +080084 unsigned int irqno;
Bryan Wu1394f032007-05-06 14:50:22 -070085 /* corresponding bit in the SIC_ISR register */
Roy Huang24a07a12007-07-12 22:41:45 +080086 unsigned int isrflag;
Bryan Wu1394f032007-05-06 14:50:22 -070087} ivg_table[NR_PERI_INTS];
88
89struct ivg_slice {
90 /* position of first irq in ivg_table for given ivg */
91 struct ivgx *ifirst;
92 struct ivgx *istop;
93} ivg7_13[IVG13 - IVG7 + 1];
94
Bryan Wu1394f032007-05-06 14:50:22 -070095
96/*
97 * Search SIC_IAR and fill tables with the irqvalues
98 * and their positions in the SIC_ISR register.
99 */
100static void __init search_IAR(void)
101{
102 unsigned ivg, irq_pos = 0;
103 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
104 int irqn;
105
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800106 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
Bryan Wu1394f032007-05-06 14:50:22 -0700107
108 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
109 int iar_shift = (irqn & 7) * 4;
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800110 if (ivg == (0xf &
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800111#if defined(CONFIG_BF52x) || defined(CONFIG_BF538) \
112 || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800113 bfin_read32((unsigned long *)SIC_IAR0 +
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800114 ((irqn % 32) >> 3) + ((irqn / 32) *
115 ((SIC_IAR4 - SIC_IAR0) / 4))) >> iar_shift)) {
Michael Hennerich59003142007-10-21 16:54:27 +0800116#else
117 bfin_read32((unsigned long *)SIC_IAR0 +
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800118 (irqn >> 3)) >> iar_shift)) {
Michael Hennerich59003142007-10-21 16:54:27 +0800119#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700120 ivg_table[irq_pos].irqno = IVG7 + irqn;
Roy Huang24a07a12007-07-12 22:41:45 +0800121 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
Bryan Wu1394f032007-05-06 14:50:22 -0700122 ivg7_13[ivg].istop++;
123 irq_pos++;
124 }
125 }
126 }
127}
128
129/*
Michael Hennerich464abc52008-02-25 13:50:20 +0800130 * This is for core internal IRQs
Bryan Wu1394f032007-05-06 14:50:22 -0700131 */
132
Michael Hennerich464abc52008-02-25 13:50:20 +0800133static void bfin_ack_noop(unsigned int irq)
Bryan Wu1394f032007-05-06 14:50:22 -0700134{
135 /* Dummy function. */
136}
137
138static void bfin_core_mask_irq(unsigned int irq)
139{
Mike Frysinger40059782008-11-18 17:48:22 +0800140 bfin_irq_flags &= ~(1 << irq);
Yi Li6a01f232009-01-07 23:14:39 +0800141 if (!irqs_disabled_hw())
142 local_irq_enable_hw();
Bryan Wu1394f032007-05-06 14:50:22 -0700143}
144
145static void bfin_core_unmask_irq(unsigned int irq)
146{
Mike Frysinger40059782008-11-18 17:48:22 +0800147 bfin_irq_flags |= 1 << irq;
Bryan Wu1394f032007-05-06 14:50:22 -0700148 /*
149 * If interrupts are enabled, IMASK must contain the same value
Mike Frysinger40059782008-11-18 17:48:22 +0800150 * as bfin_irq_flags. Make sure that invariant holds. If interrupts
Bryan Wu1394f032007-05-06 14:50:22 -0700151 * are currently disabled we need not do anything; one of the
152 * callers will take care of setting IMASK to the proper value
153 * when reenabling interrupts.
Mike Frysinger40059782008-11-18 17:48:22 +0800154 * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
Bryan Wu1394f032007-05-06 14:50:22 -0700155 * what we need.
156 */
Yi Li6a01f232009-01-07 23:14:39 +0800157 if (!irqs_disabled_hw())
158 local_irq_enable_hw();
Bryan Wu1394f032007-05-06 14:50:22 -0700159 return;
160}
161
162static void bfin_internal_mask_irq(unsigned int irq)
163{
Michael Hennerich59003142007-10-21 16:54:27 +0800164#ifdef CONFIG_BF53x
Bryan Wu1394f032007-05-06 14:50:22 -0700165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
Michael Hennerich464abc52008-02-25 13:50:20 +0800166 ~(1 << SIC_SYSIRQ(irq)));
Roy Huang24a07a12007-07-12 22:41:45 +0800167#else
168 unsigned mask_bank, mask_bit;
Michael Hennerich464abc52008-02-25 13:50:20 +0800169 mask_bank = SIC_SYSIRQ(irq) / 32;
170 mask_bit = SIC_SYSIRQ(irq) % 32;
Bryan Wuc04d66b2007-07-12 17:26:31 +0800171 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
172 ~(1 << mask_bit));
Graf Yang6b3087c2009-01-07 23:14:39 +0800173#ifdef CONFIG_SMP
174 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
175 ~(1 << mask_bit));
176#endif
Roy Huang24a07a12007-07-12 22:41:45 +0800177#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700178}
179
180static void bfin_internal_unmask_irq(unsigned int irq)
181{
Michael Hennerich59003142007-10-21 16:54:27 +0800182#ifdef CONFIG_BF53x
Bryan Wu1394f032007-05-06 14:50:22 -0700183 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
Michael Hennerich464abc52008-02-25 13:50:20 +0800184 (1 << SIC_SYSIRQ(irq)));
Roy Huang24a07a12007-07-12 22:41:45 +0800185#else
186 unsigned mask_bank, mask_bit;
Michael Hennerich464abc52008-02-25 13:50:20 +0800187 mask_bank = SIC_SYSIRQ(irq) / 32;
188 mask_bit = SIC_SYSIRQ(irq) % 32;
Bryan Wuc04d66b2007-07-12 17:26:31 +0800189 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
190 (1 << mask_bit));
Graf Yang6b3087c2009-01-07 23:14:39 +0800191#ifdef CONFIG_SMP
192 bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) |
193 (1 << mask_bit));
194#endif
Roy Huang24a07a12007-07-12 22:41:45 +0800195#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700196}
197
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800198#ifdef CONFIG_PM
199int bfin_internal_set_wake(unsigned int irq, unsigned int state)
200{
Michael Hennerich8d022372008-11-18 17:48:22 +0800201 u32 bank, bit, wakeup = 0;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800202 unsigned long flags;
Michael Hennerich464abc52008-02-25 13:50:20 +0800203 bank = SIC_SYSIRQ(irq) / 32;
204 bit = SIC_SYSIRQ(irq) % 32;
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800205
Michael Hennerich4a88d0c2008-08-05 17:38:41 +0800206 switch (irq) {
207#ifdef IRQ_RTC
208 case IRQ_RTC:
209 wakeup |= WAKE;
210 break;
211#endif
212#ifdef IRQ_CAN0_RX
213 case IRQ_CAN0_RX:
214 wakeup |= CANWE;
215 break;
216#endif
217#ifdef IRQ_CAN1_RX
218 case IRQ_CAN1_RX:
219 wakeup |= CANWE;
220 break;
221#endif
222#ifdef IRQ_USB_INT0
223 case IRQ_USB_INT0:
224 wakeup |= USBWE;
225 break;
226#endif
227#ifdef IRQ_KEY
228 case IRQ_KEY:
229 wakeup |= KPADWE;
230 break;
231#endif
Michael Hennerichd310fb42008-08-28 17:32:01 +0800232#ifdef CONFIG_BF54x
Michael Hennerich4a88d0c2008-08-05 17:38:41 +0800233 case IRQ_CNT:
234 wakeup |= ROTWE;
235 break;
236#endif
237 default:
238 break;
239 }
240
Yi Li6a01f232009-01-07 23:14:39 +0800241 local_irq_save_hw(flags);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800242
Michael Hennerich4a88d0c2008-08-05 17:38:41 +0800243 if (state) {
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800244 bfin_sic_iwr[bank] |= (1 << bit);
Michael Hennerich4a88d0c2008-08-05 17:38:41 +0800245 vr_wakeup |= wakeup;
246
247 } else {
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800248 bfin_sic_iwr[bank] &= ~(1 << bit);
Michael Hennerich4a88d0c2008-08-05 17:38:41 +0800249 vr_wakeup &= ~wakeup;
250 }
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800251
Yi Li6a01f232009-01-07 23:14:39 +0800252 local_irq_restore_hw(flags);
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800253
254 return 0;
255}
256#endif
257
Bryan Wu1394f032007-05-06 14:50:22 -0700258static struct irq_chip bfin_core_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800259 .name = "CORE",
Michael Hennerich464abc52008-02-25 13:50:20 +0800260 .ack = bfin_ack_noop,
Bryan Wu1394f032007-05-06 14:50:22 -0700261 .mask = bfin_core_mask_irq,
262 .unmask = bfin_core_unmask_irq,
263};
264
265static struct irq_chip bfin_internal_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800266 .name = "INTN",
Michael Hennerich464abc52008-02-25 13:50:20 +0800267 .ack = bfin_ack_noop,
Bryan Wu1394f032007-05-06 14:50:22 -0700268 .mask = bfin_internal_mask_irq,
269 .unmask = bfin_internal_unmask_irq,
Michael Hennerichce3b7bb2008-02-25 13:48:47 +0800270 .mask_ack = bfin_internal_mask_irq,
271 .disable = bfin_internal_mask_irq,
272 .enable = bfin_internal_unmask_irq,
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800273#ifdef CONFIG_PM
274 .set_wake = bfin_internal_set_wake,
275#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700276};
277
Yi Li6a01f232009-01-07 23:14:39 +0800278static void bfin_handle_irq(unsigned irq)
279{
280#ifdef CONFIG_IPIPE
281 struct pt_regs regs; /* Contents not used. */
282 ipipe_trace_irq_entry(irq);
283 __ipipe_handle_irq(irq, &regs);
284 ipipe_trace_irq_exit(irq);
285#else /* !CONFIG_IPIPE */
286 struct irq_desc *desc = irq_desc + irq;
287 desc->handle_irq(irq, desc);
288#endif /* !CONFIG_IPIPE */
289}
290
Bryan Wu1394f032007-05-06 14:50:22 -0700291#ifdef BF537_GENERIC_ERROR_INT_DEMUX
292static int error_int_mask;
293
Bryan Wu1394f032007-05-06 14:50:22 -0700294static void bfin_generic_error_mask_irq(unsigned int irq)
295{
296 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
297
Michael Hennerich464abc52008-02-25 13:50:20 +0800298 if (!error_int_mask)
299 bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
Bryan Wu1394f032007-05-06 14:50:22 -0700300}
301
302static void bfin_generic_error_unmask_irq(unsigned int irq)
303{
Michael Hennerich464abc52008-02-25 13:50:20 +0800304 bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
Bryan Wu1394f032007-05-06 14:50:22 -0700305 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
306}
307
308static struct irq_chip bfin_generic_error_irqchip = {
Graf Yang763e63c2008-10-08 17:08:15 +0800309 .name = "ERROR",
Michael Hennerich464abc52008-02-25 13:50:20 +0800310 .ack = bfin_ack_noop,
311 .mask_ack = bfin_generic_error_mask_irq,
Bryan Wu1394f032007-05-06 14:50:22 -0700312 .mask = bfin_generic_error_mask_irq,
313 .unmask = bfin_generic_error_unmask_irq,
314};
315
316static void bfin_demux_error_irq(unsigned int int_err_irq,
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800317 struct irq_desc *inta_desc)
Bryan Wu1394f032007-05-06 14:50:22 -0700318{
319 int irq = 0;
320
Bryan Wu1394f032007-05-06 14:50:22 -0700321#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
322 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
323 irq = IRQ_MAC_ERROR;
324 else
325#endif
326 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
327 irq = IRQ_SPORT0_ERROR;
328 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
329 irq = IRQ_SPORT1_ERROR;
330 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
331 irq = IRQ_PPI_ERROR;
332 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
333 irq = IRQ_CAN_ERROR;
334 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
335 irq = IRQ_SPI_ERROR;
336 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
337 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
338 irq = IRQ_UART0_ERROR;
339 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
340 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
341 irq = IRQ_UART1_ERROR;
342
343 if (irq) {
Yi Li6a01f232009-01-07 23:14:39 +0800344 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
345 bfin_handle_irq(irq);
346 else {
Bryan Wu1394f032007-05-06 14:50:22 -0700347
348 switch (irq) {
349 case IRQ_PPI_ERROR:
350 bfin_write_PPI_STATUS(PPI_ERR_MASK);
351 break;
352#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
353 case IRQ_MAC_ERROR:
354 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
355 break;
356#endif
357 case IRQ_SPORT0_ERROR:
358 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
359 break;
360
361 case IRQ_SPORT1_ERROR:
362 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
363 break;
364
365 case IRQ_CAN_ERROR:
366 bfin_write_CAN_GIS(CAN_ERR_MASK);
367 break;
368
369 case IRQ_SPI_ERROR:
370 bfin_write_SPI_STAT(SPI_ERR_MASK);
371 break;
372
373 default:
374 break;
375 }
376
377 pr_debug("IRQ %d:"
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800378 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
379 irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700380 }
381 } else
382 printk(KERN_ERR
383 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
384 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
Harvey Harrisonb85d8582008-04-23 09:39:01 +0800385 __func__, __FILE__, __LINE__);
Bryan Wu1394f032007-05-06 14:50:22 -0700386
Bryan Wu1394f032007-05-06 14:50:22 -0700387}
388#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
389
Graf Yangbfd15112008-10-08 18:02:44 +0800390static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
391{
Yi Li6a01f232009-01-07 23:14:39 +0800392#ifdef CONFIG_IPIPE
393 _set_irq_handler(irq, handle_edge_irq);
394#else
Graf Yangbfd15112008-10-08 18:02:44 +0800395 struct irq_desc *desc = irq_desc + irq;
396 /* May not call generic set_irq_handler() due to spinlock
397 recursion. */
398 desc->handle_irq = handle;
Yi Li6a01f232009-01-07 23:14:39 +0800399#endif
Graf Yangbfd15112008-10-08 18:02:44 +0800400}
401
Michael Hennerich8d022372008-11-18 17:48:22 +0800402static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800403extern void bfin_gpio_irq_prepare(unsigned gpio);
Michael Hennerich6fce6a82007-12-24 16:56:12 +0800404
Michael Hennerich8d022372008-11-18 17:48:22 +0800405#if !defined(CONFIG_BF54x)
406
Bryan Wu1394f032007-05-06 14:50:22 -0700407static void bfin_gpio_ack_irq(unsigned int irq)
408{
Michael Hennerich8d022372008-11-18 17:48:22 +0800409 /* AFAIK ack_irq in case mask_ack is provided
410 * get's only called for edge sense irqs
411 */
412 set_gpio_data(irq_to_gpio(irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700413}
414
415static void bfin_gpio_mask_ack_irq(unsigned int irq)
416{
Michael Hennerich8d022372008-11-18 17:48:22 +0800417 struct irq_desc *desc = irq_desc + irq;
418 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700419
Michael Hennerich8d022372008-11-18 17:48:22 +0800420 if (desc->handle_irq == handle_edge_irq)
Bryan Wu1394f032007-05-06 14:50:22 -0700421 set_gpio_data(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700422
423 set_gpio_maska(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700424}
425
426static void bfin_gpio_mask_irq(unsigned int irq)
427{
Michael Hennerich8d022372008-11-18 17:48:22 +0800428 set_gpio_maska(irq_to_gpio(irq), 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700429}
430
431static void bfin_gpio_unmask_irq(unsigned int irq)
432{
Michael Hennerich8d022372008-11-18 17:48:22 +0800433 set_gpio_maska(irq_to_gpio(irq), 1);
Bryan Wu1394f032007-05-06 14:50:22 -0700434}
435
436static unsigned int bfin_gpio_irq_startup(unsigned int irq)
437{
Michael Hennerich8d022372008-11-18 17:48:22 +0800438 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700439
Michael Hennerich8d022372008-11-18 17:48:22 +0800440 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800441 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700442
Bryan Wu1394f032007-05-06 14:50:22 -0700443 bfin_gpio_unmask_irq(irq);
444
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800445 return 0;
Bryan Wu1394f032007-05-06 14:50:22 -0700446}
447
448static void bfin_gpio_irq_shutdown(unsigned int irq)
449{
Graf Yang30af6d42008-11-18 17:48:21 +0800450 u32 gpionr = irq_to_gpio(irq);
451
Bryan Wu1394f032007-05-06 14:50:22 -0700452 bfin_gpio_mask_irq(irq);
Graf Yang30af6d42008-11-18 17:48:21 +0800453 __clear_bit(gpionr, gpio_enabled);
Graf Yang9570ff42009-01-07 23:14:38 +0800454 bfin_gpio_irq_free(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700455}
456
457static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
458{
Graf Yang8eb3e3b2008-11-18 17:48:22 +0800459 int ret;
460 char buf[16];
Michael Hennerich8d022372008-11-18 17:48:22 +0800461 u32 gpionr = irq_to_gpio(irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700462
463 if (type == IRQ_TYPE_PROBE) {
464 /* only probe unenabled GPIO interrupt lines */
Michael Hennerich8d022372008-11-18 17:48:22 +0800465 if (__test_bit(gpionr, gpio_enabled))
Bryan Wu1394f032007-05-06 14:50:22 -0700466 return 0;
467 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
468 }
469
470 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800471 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
Michael Hennerich8d022372008-11-18 17:48:22 +0800472
Graf Yang9570ff42009-01-07 23:14:38 +0800473 snprintf(buf, 16, "gpio-irq%d", irq);
474 ret = bfin_gpio_irq_request(gpionr, buf);
475 if (ret)
476 return ret;
477
Michael Hennerich8d022372008-11-18 17:48:22 +0800478 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800479 bfin_gpio_irq_prepare(gpionr);
Bryan Wu1394f032007-05-06 14:50:22 -0700480
Bryan Wu1394f032007-05-06 14:50:22 -0700481 } else {
Michael Hennerich8d022372008-11-18 17:48:22 +0800482 __clear_bit(gpionr, gpio_enabled);
Bryan Wu1394f032007-05-06 14:50:22 -0700483 return 0;
484 }
485
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800486 set_gpio_inen(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700487 set_gpio_dir(gpionr, 0);
Bryan Wu1394f032007-05-06 14:50:22 -0700488
489 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
490 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
491 set_gpio_both(gpionr, 1);
492 else
493 set_gpio_both(gpionr, 0);
494
495 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
496 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
497 else
498 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
499
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800500 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
501 set_gpio_edge(gpionr, 1);
502 set_gpio_inen(gpionr, 1);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800503 set_gpio_data(gpionr, 0);
504
505 } else {
506 set_gpio_edge(gpionr, 0);
Michael Hennerichf1bceb42008-02-02 16:17:52 +0800507 set_gpio_inen(gpionr, 1);
508 }
509
Bryan Wu1394f032007-05-06 14:50:22 -0700510 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
Graf Yangbfd15112008-10-08 18:02:44 +0800511 bfin_set_irq_handler(irq, handle_edge_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700512 else
Graf Yangbfd15112008-10-08 18:02:44 +0800513 bfin_set_irq_handler(irq, handle_level_irq);
Bryan Wu1394f032007-05-06 14:50:22 -0700514
515 return 0;
516}
517
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800518#ifdef CONFIG_PM
519int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
520{
521 unsigned gpio = irq_to_gpio(irq);
522
523 if (state)
524 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
525 else
526 gpio_pm_wakeup_free(gpio);
527
528 return 0;
529}
530#endif
531
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800532static void bfin_demux_gpio_irq(unsigned int inta_irq,
533 struct irq_desc *desc)
Bryan Wu1394f032007-05-06 14:50:22 -0700534{
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800535 unsigned int i, gpio, mask, irq, search = 0;
Bryan Wu1394f032007-05-06 14:50:22 -0700536
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800537 switch (inta_irq) {
538#if defined(CONFIG_BF53x)
539 case IRQ_PROG_INTA:
540 irq = IRQ_PF0;
541 search = 1;
542 break;
543# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
544 case IRQ_MAC_RX:
545 irq = IRQ_PH0;
546 break;
547# endif
Michael Hennerichdc26aec2008-11-18 17:48:22 +0800548#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
549 case IRQ_PORTF_INTA:
550 irq = IRQ_PF0;
551 break;
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800552#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800553 case IRQ_PORTF_INTA:
554 irq = IRQ_PF0;
555 break;
556 case IRQ_PORTG_INTA:
557 irq = IRQ_PG0;
558 break;
559 case IRQ_PORTH_INTA:
560 irq = IRQ_PH0;
561 break;
562#elif defined(CONFIG_BF561)
563 case IRQ_PROG0_INTA:
564 irq = IRQ_PF0;
565 break;
566 case IRQ_PROG1_INTA:
567 irq = IRQ_PF16;
568 break;
569 case IRQ_PROG2_INTA:
570 irq = IRQ_PF32;
571 break;
572#endif
573 default:
574 BUG();
575 return;
Bryan Wu1394f032007-05-06 14:50:22 -0700576 }
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800577
578 if (search) {
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800579 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800580 irq += i;
581
Michael Hennerich8d022372008-11-18 17:48:22 +0800582 mask = get_gpiop_data(i) & get_gpiop_maska(i);
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800583
584 while (mask) {
Yi Li6a01f232009-01-07 23:14:39 +0800585 if (mask & 1)
586 bfin_handle_irq(irq);
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800587 irq++;
588 mask >>= 1;
589 }
590 }
591 } else {
592 gpio = irq_to_gpio(irq);
Michael Hennerich8d022372008-11-18 17:48:22 +0800593 mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800594
595 do {
Yi Li6a01f232009-01-07 23:14:39 +0800596 if (mask & 1)
597 bfin_handle_irq(irq);
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800598 irq++;
599 mask >>= 1;
600 } while (mask);
601 }
602
Bryan Wu1394f032007-05-06 14:50:22 -0700603}
604
Mike Frysingera055b2b2007-11-15 21:12:32 +0800605#else /* CONFIG_BF54x */
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800606
607#define NR_PINT_SYS_IRQS 4
608#define NR_PINT_BITS 32
609#define NR_PINTS 160
610#define IRQ_NOT_AVAIL 0xFF
611
612#define PINT_2_BANK(x) ((x) >> 5)
613#define PINT_2_BIT(x) ((x) & 0x1F)
614#define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
615
616static unsigned char irq2pint_lut[NR_PINTS];
Michael Henneriche3f23002007-07-12 16:39:29 +0800617static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800618
619struct pin_int_t {
620 unsigned int mask_set;
621 unsigned int mask_clear;
622 unsigned int request;
623 unsigned int assign;
624 unsigned int edge_set;
625 unsigned int edge_clear;
626 unsigned int invert_set;
627 unsigned int invert_clear;
628 unsigned int pinstate;
629 unsigned int latch;
630};
631
632static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
633 (struct pin_int_t *)PINT0_MASK_SET,
634 (struct pin_int_t *)PINT1_MASK_SET,
635 (struct pin_int_t *)PINT2_MASK_SET,
636 (struct pin_int_t *)PINT3_MASK_SET,
637};
638
Michael Hennerich8d022372008-11-18 17:48:22 +0800639inline unsigned int get_irq_base(u32 bank, u8 bmap)
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800640{
Michael Hennerich8d022372008-11-18 17:48:22 +0800641 unsigned int irq_base;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800642
643 if (bank < 2) { /*PA-PB */
644 irq_base = IRQ_PA0 + bmap * 16;
645 } else { /*PC-PJ */
646 irq_base = IRQ_PC0 + bmap * 16;
647 }
648
649 return irq_base;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800650}
651
652 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
653void init_pint_lut(void)
654{
655 u16 bank, bit, irq_base, bit_pos;
656 u32 pint_assign;
657 u8 bmap;
658
659 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
660
661 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
662
663 pint_assign = pint[bank]->assign;
664
665 for (bit = 0; bit < NR_PINT_BITS; bit++) {
666
667 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
668
669 irq_base = get_irq_base(bank, bmap);
670
671 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
672 bit_pos = bit + bank * NR_PINT_BITS;
673
Michael Henneriche3f23002007-07-12 16:39:29 +0800674 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800675 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800676 }
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800677 }
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800678}
679
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800680static void bfin_gpio_ack_irq(unsigned int irq)
681{
Michael Hennerich8d022372008-11-18 17:48:22 +0800682 struct irq_desc *desc = irq_desc + irq;
683 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Hennerich8baf5602007-12-24 18:51:34 +0800684 u32 pintbit = PINT_BIT(pint_val);
Michael Hennerich8d022372008-11-18 17:48:22 +0800685 u32 bank = PINT_2_BANK(pint_val);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800686
Michael Hennerich8d022372008-11-18 17:48:22 +0800687 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
Michael Hennerich8baf5602007-12-24 18:51:34 +0800688 if (pint[bank]->invert_set & pintbit)
689 pint[bank]->invert_clear = pintbit;
690 else
691 pint[bank]->invert_set = pintbit;
692 }
693 pint[bank]->request = pintbit;
694
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800695}
696
697static void bfin_gpio_mask_ack_irq(unsigned int irq)
698{
Michael Hennerich8d022372008-11-18 17:48:22 +0800699 struct irq_desc *desc = irq_desc + irq;
700 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Henneriche3f23002007-07-12 16:39:29 +0800701 u32 pintbit = PINT_BIT(pint_val);
Michael Hennerich8d022372008-11-18 17:48:22 +0800702 u32 bank = PINT_2_BANK(pint_val);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800703
Michael Hennerich8d022372008-11-18 17:48:22 +0800704 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
Michael Hennerich8baf5602007-12-24 18:51:34 +0800705 if (pint[bank]->invert_set & pintbit)
706 pint[bank]->invert_clear = pintbit;
707 else
708 pint[bank]->invert_set = pintbit;
709 }
710
Michael Henneriche3f23002007-07-12 16:39:29 +0800711 pint[bank]->request = pintbit;
712 pint[bank]->mask_clear = pintbit;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800713}
714
715static void bfin_gpio_mask_irq(unsigned int irq)
716{
Michael Hennerich8d022372008-11-18 17:48:22 +0800717 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800718
719 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800720}
721
722static void bfin_gpio_unmask_irq(unsigned int irq)
723{
Michael Hennerich8d022372008-11-18 17:48:22 +0800724 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Henneriche3f23002007-07-12 16:39:29 +0800725 u32 pintbit = PINT_BIT(pint_val);
Michael Hennerich8d022372008-11-18 17:48:22 +0800726 u32 bank = PINT_2_BANK(pint_val);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800727
Michael Henneriche3f23002007-07-12 16:39:29 +0800728 pint[bank]->request = pintbit;
729 pint[bank]->mask_set = pintbit;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800730}
731
732static unsigned int bfin_gpio_irq_startup(unsigned int irq)
733{
Michael Hennerich8d022372008-11-18 17:48:22 +0800734 u32 gpionr = irq_to_gpio(irq);
735 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800736
Michael Hennerich50e163c2007-07-24 16:17:28 +0800737 if (pint_val == IRQ_NOT_AVAIL) {
738 printk(KERN_ERR
739 "GPIO IRQ %d :Not in PINT Assign table "
740 "Reconfigure Interrupt to Port Assignemt\n", irq);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800741 return -ENODEV;
Michael Hennerich50e163c2007-07-24 16:17:28 +0800742 }
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800743
Michael Hennerich8d022372008-11-18 17:48:22 +0800744 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800745 bfin_gpio_irq_prepare(gpionr);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800746
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800747 bfin_gpio_unmask_irq(irq);
748
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800749 return 0;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800750}
751
752static void bfin_gpio_irq_shutdown(unsigned int irq)
753{
Michael Hennerich8d022372008-11-18 17:48:22 +0800754 u32 gpionr = irq_to_gpio(irq);
Michael Hennerich8baf5602007-12-24 18:51:34 +0800755
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800756 bfin_gpio_mask_irq(irq);
Michael Hennerich8d022372008-11-18 17:48:22 +0800757 __clear_bit(gpionr, gpio_enabled);
Graf Yang9570ff42009-01-07 23:14:38 +0800758 bfin_gpio_irq_free(gpionr);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800759}
760
761static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
762{
Graf Yang8eb3e3b2008-11-18 17:48:22 +0800763 int ret;
764 char buf[16];
Michael Hennerich8d022372008-11-18 17:48:22 +0800765 u32 gpionr = irq_to_gpio(irq);
766 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Henneriche3f23002007-07-12 16:39:29 +0800767 u32 pintbit = PINT_BIT(pint_val);
Michael Hennerich8d022372008-11-18 17:48:22 +0800768 u32 bank = PINT_2_BANK(pint_val);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800769
770 if (pint_val == IRQ_NOT_AVAIL)
771 return -ENODEV;
772
773 if (type == IRQ_TYPE_PROBE) {
774 /* only probe unenabled GPIO interrupt lines */
Michael Hennerich8d022372008-11-18 17:48:22 +0800775 if (__test_bit(gpionr, gpio_enabled))
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800776 return 0;
777 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
778 }
779
780 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
781 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
Graf Yang9570ff42009-01-07 23:14:38 +0800782
783 snprintf(buf, 16, "gpio-irq%d", irq);
784 ret = bfin_gpio_irq_request(gpionr, buf);
785 if (ret)
786 return ret;
787
Michael Hennerich8d022372008-11-18 17:48:22 +0800788 if (__test_and_set_bit(gpionr, gpio_enabled))
Michael Hennerichaffee2b2008-04-24 08:10:10 +0800789 bfin_gpio_irq_prepare(gpionr);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800790
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800791 } else {
Michael Hennerich8d022372008-11-18 17:48:22 +0800792 __clear_bit(gpionr, gpio_enabled);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800793 return 0;
794 }
795
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800796 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
Michael Henneriche3f23002007-07-12 16:39:29 +0800797 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800798 else
Michael Hennerich8baf5602007-12-24 18:51:34 +0800799 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800800
Michael Hennerich8baf5602007-12-24 18:51:34 +0800801 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
802 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
Michael Hennerich8baf5602007-12-24 18:51:34 +0800803 if (gpio_get_value(gpionr))
804 pint[bank]->invert_set = pintbit;
805 else
806 pint[bank]->invert_clear = pintbit;
Michael Hennerich8baf5602007-12-24 18:51:34 +0800807 }
808
809 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
810 pint[bank]->edge_set = pintbit;
Graf Yangbfd15112008-10-08 18:02:44 +0800811 bfin_set_irq_handler(irq, handle_edge_irq);
Michael Hennerich8baf5602007-12-24 18:51:34 +0800812 } else {
813 pint[bank]->edge_clear = pintbit;
Graf Yangbfd15112008-10-08 18:02:44 +0800814 bfin_set_irq_handler(irq, handle_level_irq);
Michael Hennerich8baf5602007-12-24 18:51:34 +0800815 }
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800816
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800817 return 0;
818}
819
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800820#ifdef CONFIG_PM
821u32 pint_saved_masks[NR_PINT_SYS_IRQS];
822u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
823
824int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
825{
826 u32 pint_irq;
Michael Hennerich8d022372008-11-18 17:48:22 +0800827 u32 pint_val = irq2pint_lut[irq - SYS_IRQS];
Michael Hennerichcfefe3c2008-02-09 04:12:37 +0800828 u32 bank = PINT_2_BANK(pint_val);
829 u32 pintbit = PINT_BIT(pint_val);
830
831 switch (bank) {
832 case 0:
833 pint_irq = IRQ_PINT0;
834 break;
835 case 2:
836 pint_irq = IRQ_PINT2;
837 break;
838 case 3:
839 pint_irq = IRQ_PINT3;
840 break;
841 case 1:
842 pint_irq = IRQ_PINT1;
843 break;
844 default:
845 return -EINVAL;
846 }
847
848 bfin_internal_set_wake(pint_irq, state);
849
850 if (state)
851 pint_wakeup_masks[bank] |= pintbit;
852 else
853 pint_wakeup_masks[bank] &= ~pintbit;
854
855 return 0;
856}
857
858u32 bfin_pm_setup(void)
859{
860 u32 val, i;
861
862 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
863 val = pint[i]->mask_clear;
864 pint_saved_masks[i] = val;
865 if (val ^ pint_wakeup_masks[i]) {
866 pint[i]->mask_clear = val;
867 pint[i]->mask_set = pint_wakeup_masks[i];
868 }
869 }
870
871 return 0;
872}
873
874void bfin_pm_restore(void)
875{
876 u32 i, val;
877
878 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
879 val = pint_saved_masks[i];
880 if (val ^ pint_wakeup_masks[i]) {
881 pint[i]->mask_clear = pint[i]->mask_clear;
882 pint[i]->mask_set = val;
883 }
884 }
885}
886#endif
887
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800888static void bfin_demux_gpio_irq(unsigned int inta_irq,
889 struct irq_desc *desc)
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800890{
Michael Hennerich8d022372008-11-18 17:48:22 +0800891 u32 bank, pint_val;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800892 u32 request, irq;
893
Michael Hennerich2c4f8292008-02-09 04:11:14 +0800894 switch (inta_irq) {
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800895 case IRQ_PINT0:
896 bank = 0;
897 break;
898 case IRQ_PINT2:
899 bank = 2;
900 break;
901 case IRQ_PINT3:
902 bank = 3;
903 break;
904 case IRQ_PINT1:
905 bank = 1;
906 break;
Michael Henneriche3f23002007-07-12 16:39:29 +0800907 default:
908 return;
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800909 }
910
911 pint_val = bank * NR_PINT_BITS;
912
913 request = pint[bank]->request;
914
915 while (request) {
916 if (request & 1) {
Michael Henneriche3f23002007-07-12 16:39:29 +0800917 irq = pint2irq_lut[pint_val] + SYS_IRQS;
Yi Li6a01f232009-01-07 23:14:39 +0800918 bfin_handle_irq(irq);
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800919 }
920 pint_val++;
921 request >>= 1;
922 }
923
924}
Mike Frysingera055b2b2007-11-15 21:12:32 +0800925#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700926
Michael Hennerich8d022372008-11-18 17:48:22 +0800927static struct irq_chip bfin_gpio_irqchip = {
928 .name = "GPIO",
929 .ack = bfin_gpio_ack_irq,
930 .mask = bfin_gpio_mask_irq,
931 .mask_ack = bfin_gpio_mask_ack_irq,
932 .unmask = bfin_gpio_unmask_irq,
933 .disable = bfin_gpio_mask_irq,
934 .enable = bfin_gpio_unmask_irq,
935 .set_type = bfin_gpio_irq_type,
936 .startup = bfin_gpio_irq_startup,
937 .shutdown = bfin_gpio_irq_shutdown,
938#ifdef CONFIG_PM
939 .set_wake = bfin_gpio_set_wake,
940#endif
941};
942
Graf Yang6b3087c2009-01-07 23:14:39 +0800943void __cpuinit init_exception_vectors(void)
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800944{
Mike Frysingerf0b5d122007-08-05 17:03:59 +0800945 /* cannot program in software:
946 * evt0 - emulation (jtag)
947 * evt1 - reset
948 */
949 bfin_write_EVT2(evt_nmi);
Bernd Schmidt8be80ed2007-07-25 14:44:49 +0800950 bfin_write_EVT3(trap);
951 bfin_write_EVT5(evt_ivhw);
952 bfin_write_EVT6(evt_timer);
953 bfin_write_EVT7(evt_evt7);
954 bfin_write_EVT8(evt_evt8);
955 bfin_write_EVT9(evt_evt9);
956 bfin_write_EVT10(evt_evt10);
957 bfin_write_EVT11(evt_evt11);
958 bfin_write_EVT12(evt_evt12);
959 bfin_write_EVT13(evt_evt13);
960 bfin_write_EVT14(evt14_softirq);
961 bfin_write_EVT15(evt_system_call);
962 CSYNC();
963}
964
Bryan Wu1394f032007-05-06 14:50:22 -0700965/*
966 * This function should be called during kernel startup to initialize
967 * the BFin IRQ handling routines.
968 */
Michael Hennerich8d022372008-11-18 17:48:22 +0800969
Bryan Wu1394f032007-05-06 14:50:22 -0700970int __init init_arch_irq(void)
971{
972 int irq;
973 unsigned long ilat = 0;
974 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
Bryan Wu2f6f4bc2008-11-18 17:48:21 +0800975#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
976 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
Roy Huang24a07a12007-07-12 22:41:45 +0800977 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
978 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
Mike Frysingera055b2b2007-11-15 21:12:32 +0800979# ifdef CONFIG_BF54x
Michael Hennerich59003142007-10-21 16:54:27 +0800980 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
Mike Frysingera055b2b2007-11-15 21:12:32 +0800981# endif
Graf Yang6b3087c2009-01-07 23:14:39 +0800982# ifdef CONFIG_SMP
983 bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
984 bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
985# endif
Roy Huang24a07a12007-07-12 22:41:45 +0800986#else
Bryan Wu1394f032007-05-06 14:50:22 -0700987 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
Roy Huang24a07a12007-07-12 22:41:45 +0800988#endif
Bryan Wu1394f032007-05-06 14:50:22 -0700989
990 local_irq_disable();
991
Mike Frysingerd70536e2008-08-25 17:37:35 +0800992#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
Mike Frysinger95a86b52008-08-14 15:05:01 +0800993 /* Clear EMAC Interrupt Status bits so we can demux it later */
994 bfin_write_EMAC_SYSTAT(-1);
995#endif
996
Mike Frysingera055b2b2007-11-15 21:12:32 +0800997#ifdef CONFIG_BF54x
998# ifdef CONFIG_PINTx_REASSIGN
Michael Hennerich34e0fc82007-07-12 16:17:18 +0800999 pint[0]->assign = CONFIG_PINT0_ASSIGN;
1000 pint[1]->assign = CONFIG_PINT1_ASSIGN;
1001 pint[2]->assign = CONFIG_PINT2_ASSIGN;
1002 pint[3]->assign = CONFIG_PINT3_ASSIGN;
Mike Frysingera055b2b2007-11-15 21:12:32 +08001003# endif
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001004 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
1005 init_pint_lut();
1006#endif
1007
1008 for (irq = 0; irq <= SYS_IRQS; irq++) {
Bryan Wu1394f032007-05-06 14:50:22 -07001009 if (irq <= IRQ_CORETMR)
1010 set_irq_chip(irq, &bfin_core_irqchip);
1011 else
1012 set_irq_chip(irq, &bfin_internal_irqchip);
Bryan Wu1394f032007-05-06 14:50:22 -07001013
Michael Hennerich464abc52008-02-25 13:50:20 +08001014 switch (irq) {
Michael Hennerich59003142007-10-21 16:54:27 +08001015#if defined(CONFIG_BF53x)
Michael Hennerich464abc52008-02-25 13:50:20 +08001016 case IRQ_PROG_INTA:
Mike Frysingera055b2b2007-11-15 21:12:32 +08001017# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
Michael Hennerich464abc52008-02-25 13:50:20 +08001018 case IRQ_MAC_RX:
Mike Frysingera055b2b2007-11-15 21:12:32 +08001019# endif
Michael Hennerich59003142007-10-21 16:54:27 +08001020#elif defined(CONFIG_BF54x)
Michael Hennerich464abc52008-02-25 13:50:20 +08001021 case IRQ_PINT0:
1022 case IRQ_PINT1:
1023 case IRQ_PINT2:
1024 case IRQ_PINT3:
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001025#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
Michael Hennerich464abc52008-02-25 13:50:20 +08001026 case IRQ_PORTF_INTA:
1027 case IRQ_PORTG_INTA:
1028 case IRQ_PORTH_INTA:
Michael Hennerich2c4f8292008-02-09 04:11:14 +08001029#elif defined(CONFIG_BF561)
Michael Hennerich464abc52008-02-25 13:50:20 +08001030 case IRQ_PROG0_INTA:
1031 case IRQ_PROG1_INTA:
1032 case IRQ_PROG2_INTA:
Michael Hennerichdc26aec2008-11-18 17:48:22 +08001033#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
1034 case IRQ_PORTF_INTA:
Michael Hennerich59003142007-10-21 16:54:27 +08001035#endif
Michael Hennerichdc26aec2008-11-18 17:48:22 +08001036
Michael Hennerich464abc52008-02-25 13:50:20 +08001037 set_irq_chained_handler(irq,
1038 bfin_demux_gpio_irq);
1039 break;
Bryan Wu1394f032007-05-06 14:50:22 -07001040#ifdef BF537_GENERIC_ERROR_INT_DEMUX
Michael Hennerich464abc52008-02-25 13:50:20 +08001041 case IRQ_GENERIC_ERROR:
Yi Li6a01f232009-01-07 23:14:39 +08001042 set_irq_chained_handler(irq, bfin_demux_error_irq);
Michael Hennerich464abc52008-02-25 13:50:20 +08001043 break;
1044#endif
Yi Li6a01f232009-01-07 23:14:39 +08001045#if defined(CONFIG_TICK_SOURCE_SYSTMR0) || defined(CONFIG_IPIPE)
Graf Yang6b3087c2009-01-07 23:14:39 +08001046 case IRQ_TIMER0:
1047 set_irq_handler(irq, handle_percpu_irq);
1048 break;
1049#endif
1050#ifdef CONFIG_SMP
1051 case IRQ_SUPPLE_0:
1052 case IRQ_SUPPLE_1:
1053 set_irq_handler(irq, handle_percpu_irq);
1054 break;
1055#endif
Michael Hennerich464abc52008-02-25 13:50:20 +08001056 default:
Yi Li6a01f232009-01-07 23:14:39 +08001057#ifdef CONFIG_IPIPE
1058 /*
1059 * We want internal interrupt sources to be masked, because
1060 * ISRs may trigger interrupts recursively (e.g. DMA), but
1061 * interrupts are _not_ masked at CPU level. So let's handle
1062 * them as level interrupts.
1063 */
1064 set_irq_handler(irq, handle_level_irq);
1065#else /* !CONFIG_IPIPE */
Michael Hennerich464abc52008-02-25 13:50:20 +08001066 set_irq_handler(irq, handle_simple_irq);
Yi Li6a01f232009-01-07 23:14:39 +08001067#endif /* !CONFIG_IPIPE */
Michael Hennerich464abc52008-02-25 13:50:20 +08001068 break;
Bryan Wu1394f032007-05-06 14:50:22 -07001069 }
Bryan Wu1394f032007-05-06 14:50:22 -07001070 }
Michael Hennerich464abc52008-02-25 13:50:20 +08001071
Bryan Wu1394f032007-05-06 14:50:22 -07001072#ifdef BF537_GENERIC_ERROR_INT_DEMUX
Michael Hennerich464abc52008-02-25 13:50:20 +08001073 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
1074 set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
1075 handle_level_irq);
Bryan Wu1394f032007-05-06 14:50:22 -07001076#endif
1077
Michael Hennerich464abc52008-02-25 13:50:20 +08001078 /* if configured as edge, then will be changed to do_edge_IRQ */
1079 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
1080 set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
1081 handle_level_irq);
Michael Hennerich2c4f8292008-02-09 04:11:14 +08001082
Mike Frysingera055b2b2007-11-15 21:12:32 +08001083
Bryan Wu1394f032007-05-06 14:50:22 -07001084 bfin_write_IMASK(0);
1085 CSYNC();
1086 ilat = bfin_read_ILAT();
1087 CSYNC();
1088 bfin_write_ILAT(ilat);
1089 CSYNC();
1090
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001091 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
Mike Frysinger40059782008-11-18 17:48:22 +08001092 /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
Bryan Wu1394f032007-05-06 14:50:22 -07001093 * local_irq_enable()
1094 */
1095 program_IAR();
1096 /* Therefore it's better to setup IARs before interrupts enabled */
1097 search_IAR();
1098
1099 /* Enable interrupts IVG7-15 */
Mike Frysinger40059782008-11-18 17:48:22 +08001100 bfin_irq_flags |= IMASK_IVG15 |
Bryan Wu1394f032007-05-06 14:50:22 -07001101 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001102 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
Bryan Wu1394f032007-05-06 14:50:22 -07001103
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001104#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1105 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
Michael Hennerich56f5f592008-08-06 17:55:32 +08001106 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001107#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1108 /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
Michael Hennerich55546ac2008-08-13 17:41:13 +08001109 * will screw up the bootrom as it relies on MDMA0/1 waking it
1110 * up from IDLE instructions. See this report for more info:
1111 * http://blackfin.uclinux.org/gf/tracker/4323
1112 */
Mike Frysingerb7e11292008-11-18 17:48:22 +08001113 if (ANOMALY_05000435)
1114 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1115 else
1116 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
Michael Hennerich55546ac2008-08-13 17:41:13 +08001117#else
Michael Hennerich56f5f592008-08-06 17:55:32 +08001118 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
Michael Hennerich55546ac2008-08-13 17:41:13 +08001119#endif
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001120# ifdef CONFIG_BF54x
Michael Hennerich56f5f592008-08-06 17:55:32 +08001121 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001122# endif
1123#else
Michael Hennerich56f5f592008-08-06 17:55:32 +08001124 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
Michael Hennerichfe9ec9b2008-02-25 12:04:57 +08001125#endif
1126
Yi Li6a01f232009-01-07 23:14:39 +08001127#ifdef CONFIG_IPIPE
1128 for (irq = 0; irq < NR_IRQS; irq++) {
1129 struct irq_desc *desc = irq_desc + irq;
1130 desc->ic_prio = __ipipe_get_irq_priority(irq);
1131 desc->thr_prio = __ipipe_get_irqthread_priority(irq);
1132 }
1133#endif /* CONFIG_IPIPE */
1134
Bryan Wu1394f032007-05-06 14:50:22 -07001135 return 0;
1136}
1137
1138#ifdef CONFIG_DO_IRQ_L1
Mike Frysingera055b2b2007-11-15 21:12:32 +08001139__attribute__((l1_text))
Bryan Wu1394f032007-05-06 14:50:22 -07001140#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001141void do_irq(int vec, struct pt_regs *fp)
1142{
1143 if (vec == EVT_IVTMR_P) {
1144 vec = IRQ_CORETMR;
1145 } else {
1146 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1147 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
Bryan Wu2f6f4bc2008-11-18 17:48:21 +08001148#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
1149 || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
Roy Huang24a07a12007-07-12 22:41:45 +08001150 unsigned long sic_status[3];
Bryan Wu1394f032007-05-06 14:50:22 -07001151
Graf Yang6b3087c2009-01-07 23:14:39 +08001152 if (smp_processor_id()) {
1153#ifdef CONFIG_SMP
1154 /* This will be optimized out in UP mode. */
1155 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1156 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1157#endif
1158 } else {
1159 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1160 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1161 }
Michael Hennerich59003142007-10-21 16:54:27 +08001162#ifdef CONFIG_BF54x
Michael Hennerich4fb45242007-10-21 16:53:53 +08001163 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
Michael Hennerich59003142007-10-21 16:54:27 +08001164#endif
Mike Frysinger1f83b8f2007-07-12 22:58:21 +08001165 for (;; ivg++) {
Roy Huang24a07a12007-07-12 22:41:45 +08001166 if (ivg >= ivg_stop) {
1167 atomic_inc(&num_spurious);
1168 return;
1169 }
Michael Hennerich34e0fc82007-07-12 16:17:18 +08001170 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
Roy Huang24a07a12007-07-12 22:41:45 +08001171 break;
1172 }
1173#else
1174 unsigned long sic_status;
Michael Hennerich464abc52008-02-25 13:50:20 +08001175
Bryan Wu1394f032007-05-06 14:50:22 -07001176 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1177
1178 for (;; ivg++) {
1179 if (ivg >= ivg_stop) {
1180 atomic_inc(&num_spurious);
1181 return;
1182 } else if (sic_status & ivg->isrflag)
1183 break;
1184 }
Roy Huang24a07a12007-07-12 22:41:45 +08001185#endif
Bryan Wu1394f032007-05-06 14:50:22 -07001186 vec = ivg->irqno;
1187 }
1188 asm_do_IRQ(vec, fp);
Bryan Wu1394f032007-05-06 14:50:22 -07001189}
Yi Li6a01f232009-01-07 23:14:39 +08001190
1191#ifdef CONFIG_IPIPE
1192
1193int __ipipe_get_irq_priority(unsigned irq)
1194{
1195 int ient, prio;
1196
1197 if (irq <= IRQ_CORETMR)
1198 return irq;
1199
1200 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1201 struct ivgx *ivg = ivg_table + ient;
1202 if (ivg->irqno == irq) {
1203 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1204 if (ivg7_13[prio].ifirst <= ivg &&
1205 ivg7_13[prio].istop > ivg)
1206 return IVG7 + prio;
1207 }
1208 }
1209 }
1210
1211 return IVG15;
1212}
1213
1214int __ipipe_get_irqthread_priority(unsigned irq)
1215{
1216 int ient, prio;
1217 int demux_irq;
1218
1219 /* The returned priority value is rescaled to [0..IVG13+1]
1220 * with 0 being the lowest effective priority level. */
1221
1222 if (irq <= IRQ_CORETMR)
1223 return IVG13 - irq + 1;
1224
1225 /* GPIO IRQs are given the priority of the demux
1226 * interrupt. */
1227 if (IS_GPIOIRQ(irq)) {
1228#if defined(CONFIG_BF54x)
1229 u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
1230 demux_irq = (bank == 0 ? IRQ_PINT0 :
1231 bank == 1 ? IRQ_PINT1 :
1232 bank == 2 ? IRQ_PINT2 :
1233 IRQ_PINT3);
1234#elif defined(CONFIG_BF561)
1235 demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
1236 irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
1237 IRQ_PROG0_INTA);
1238#elif defined(CONFIG_BF52x)
1239 demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
1240 irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
1241 IRQ_PORTF_INTA);
1242#else
1243 demux_irq = irq;
1244#endif
1245 return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
1246 }
1247
1248 /* The GPIO demux interrupt is given a lower priority
1249 * than the GPIO IRQs, so that its threaded handler
1250 * unmasks the interrupt line after the decoded IRQs
1251 * have been processed. */
1252 prio = PRIO_GPIODEMUX(irq);
1253 /* demux irq? */
1254 if (prio != -1)
1255 return IVG13 - prio;
1256
1257 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1258 struct ivgx *ivg = ivg_table + ient;
1259 if (ivg->irqno == irq) {
1260 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1261 if (ivg7_13[prio].ifirst <= ivg &&
1262 ivg7_13[prio].istop > ivg)
1263 return IVG7 - prio;
1264 }
1265 }
1266 }
1267
1268 return 0;
1269}
1270
1271/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1272#ifdef CONFIG_DO_IRQ_L1
1273__attribute__((l1_text))
1274#endif
1275asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1276{
1277 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1278 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1279 int irq;
1280
1281 if (likely(vec == EVT_IVTMR_P)) {
1282 irq = IRQ_CORETMR;
1283 goto handle_irq;
1284 }
1285
1286 SSYNC();
1287
1288#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1289 {
1290 unsigned long sic_status[3];
1291
1292 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1293 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1294#ifdef CONFIG_BF54x
1295 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1296#endif
1297 for (;; ivg++) {
1298 if (ivg >= ivg_stop) {
1299 atomic_inc(&num_spurious);
1300 return 0;
1301 }
1302 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1303 break;
1304 }
1305 }
1306#else
1307 {
1308 unsigned long sic_status;
1309
1310 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1311
1312 for (;; ivg++) {
1313 if (ivg >= ivg_stop) {
1314 atomic_inc(&num_spurious);
1315 return 0;
1316 } else if (sic_status & ivg->isrflag)
1317 break;
1318 }
1319 }
1320#endif
1321
1322 irq = ivg->irqno;
1323
1324 if (irq == IRQ_SYSTMR) {
1325 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1326 /* This is basically what we need from the register frame. */
1327 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1328 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1329 if (!ipipe_root_domain_p)
1330 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1331 else
1332 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1333 }
1334
1335handle_irq:
1336
1337 ipipe_trace_irq_entry(irq);
1338 __ipipe_handle_irq(irq, regs);
1339 ipipe_trace_irq_exit(irq);
1340
1341 if (ipipe_root_domain_p)
1342 return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status));
1343
1344 return 0;
1345}
1346
1347#endif /* CONFIG_IPIPE */