blob: 55cdd804cdbac0b078ea4e6ddbcd59d35813b989 [file] [log] [blame]
David Lanzendörfer3cbcb1602014-05-12 14:04:48 +02001* Allwinner sunxi MMC controller
2
3The highspeed MMC host controller on Allwinner SoCs provides an interface
4for MMC, SD and SDIO types of memory cards.
5
6Supported maximum speeds are the ones of the eMMC standard 4.5 as well
7as the speed of SD standard 3.0.
8Absolute maximum transfer rate is 200MB/s
9
10Required properties:
Hans de Goedeb4656462016-07-30 16:25:47 +020011 - compatible : should be one of:
12 * "allwinner,sun4i-a10-mmc"
13 * "allwinner,sun5i-a13-mmc"
14 * "allwinner,sun7i-a20-mmc"
15 * "allwinner,sun9i-a80-mmc"
Icenowy Zheng3d254b52016-08-05 04:57:14 +020016 * "allwinner,sun50i-a64-mmc"
David Lanzendörfer3cbcb1602014-05-12 14:04:48 +020017 - reg : mmc controller base registers
Maxime Ripard6c09bb82014-07-12 12:01:33 +020018 - clocks : a list with 4 phandle + clock specifier pairs
19 - clock-names : must contain "ahb", "mmc", "output" and "sample"
David Lanzendörfer3cbcb1602014-05-12 14:04:48 +020020 - interrupts : mmc controller interrupt
21
22Optional properties:
23 - resets : phandle + reset specifier pair
24 - reset-names : must contain "ahb"
25 - for cd, bus-width and additional generic mmc parameters
26 please refer to mmc.txt within this directory
27
28Examples:
29 - Within .dtsi:
30 mmc0: mmc@01c0f000 {
31 compatible = "allwinner,sun5i-a13-mmc";
32 reg = <0x01c0f000 0x1000>;
Maxime Ripard6c09bb82014-07-12 12:01:33 +020033 clocks = <&ahb_gates 8>, <&mmc0_clk>, <&mmc0_output_clk>, <&mmc0_sample_clk>;
34 clock-names = "ahb", "mod", "output", "sample";
David Lanzendörfer3cbcb1602014-05-12 14:04:48 +020035 interrupts = <0 32 4>;
36 status = "disabled";
37 };
38
39 - Within dts:
40 mmc0: mmc@01c0f000 {
41 pinctrl-names = "default", "default";
42 pinctrl-0 = <&mmc0_pins_a>;
43 pinctrl-1 = <&mmc0_cd_pin_reference_design>;
44 bus-width = <4>;
45 cd-gpios = <&pio 7 1 0>; /* PH1 */
46 cd-inverted;
47 status = "okay";
48 };