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Alek Du8bf02612009-09-22 16:46:36 -07001/* langwell_gpio.c Moorestown platform Langwell chip GPIO driver
2 * Copyright (c) 2008 - 2009, Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
16 */
17
18/* Supports:
19 * Moorestown platform Langwell chip.
Alek Du8081c842010-05-26 14:42:25 -070020 * Medfield platform Penwell chip.
Alan Cox72b43792010-10-27 15:33:23 -070021 * Whitney point.
Alek Du8bf02612009-09-22 16:46:36 -070022 */
23
24#include <linux/module.h>
25#include <linux/pci.h>
Alan Cox72b43792010-10-27 15:33:23 -070026#include <linux/platform_device.h>
Alek Du8bf02612009-09-22 16:46:36 -070027#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/stddef.h>
30#include <linux/interrupt.h>
31#include <linux/init.h>
32#include <linux/irq.h>
33#include <linux/io.h>
34#include <linux/gpio.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090035#include <linux/slab.h>
Alek Du8bf02612009-09-22 16:46:36 -070036
Alek Du8081c842010-05-26 14:42:25 -070037/*
38 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
39 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
40 * registers to control them, so we only define the order here instead of a
41 * structure, to get a bit offset for a pin (use GPDR as an example):
42 *
43 * nreg = ngpio / 32;
44 * reg = offset / 32;
45 * bit = offset % 32;
46 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
47 *
48 * so the bit of reg_addr is to control pin offset's GPDR feature
49*/
50
51enum GPIO_REG {
52 GPLR = 0, /* pin level read-only */
53 GPDR, /* pin direction */
54 GPSR, /* pin set */
55 GPCR, /* pin clear */
56 GRER, /* rising edge detect */
57 GFER, /* falling edge detect */
58 GEDR, /* edge detect result */
Alek Du8bf02612009-09-22 16:46:36 -070059};
60
61struct lnw_gpio {
62 struct gpio_chip chip;
Alek Du8081c842010-05-26 14:42:25 -070063 void *reg_base;
Alek Du8bf02612009-09-22 16:46:36 -070064 spinlock_t lock;
65 unsigned irq_base;
66};
67
Alek Du8081c842010-05-26 14:42:25 -070068static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
69 enum GPIO_REG reg_type)
Alek Du8bf02612009-09-22 16:46:36 -070070{
71 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
Alek Du8081c842010-05-26 14:42:25 -070072 unsigned nreg = chip->ngpio / 32;
Alek Du8bf02612009-09-22 16:46:36 -070073 u8 reg = offset / 32;
Alek Du8081c842010-05-26 14:42:25 -070074 void __iomem *ptr;
Alek Du8bf02612009-09-22 16:46:36 -070075
Alek Du8081c842010-05-26 14:42:25 -070076 ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
77 return ptr;
78}
79
80static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
81{
82 void __iomem *gplr = gpio_reg(chip, offset, GPLR);
83
Alek Du8bf02612009-09-22 16:46:36 -070084 return readl(gplr) & BIT(offset % 32);
85}
86
87static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
88{
Alek Du8bf02612009-09-22 16:46:36 -070089 void __iomem *gpsr, *gpcr;
90
91 if (value) {
Alek Du8081c842010-05-26 14:42:25 -070092 gpsr = gpio_reg(chip, offset, GPSR);
Alek Du8bf02612009-09-22 16:46:36 -070093 writel(BIT(offset % 32), gpsr);
94 } else {
Alek Du8081c842010-05-26 14:42:25 -070095 gpcr = gpio_reg(chip, offset, GPCR);
Alek Du8bf02612009-09-22 16:46:36 -070096 writel(BIT(offset % 32), gpcr);
97 }
98}
99
100static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
101{
102 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
Alek Du8081c842010-05-26 14:42:25 -0700103 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700104 u32 value;
105 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700106
Alek Du8bf02612009-09-22 16:46:36 -0700107 spin_lock_irqsave(&lnw->lock, flags);
108 value = readl(gpdr);
109 value &= ~BIT(offset % 32);
110 writel(value, gpdr);
111 spin_unlock_irqrestore(&lnw->lock, flags);
112 return 0;
113}
114
115static int lnw_gpio_direction_output(struct gpio_chip *chip,
116 unsigned offset, int value)
117{
118 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
Alek Du8081c842010-05-26 14:42:25 -0700119 void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
Alek Du8bf02612009-09-22 16:46:36 -0700120 unsigned long flags;
Alek Du8bf02612009-09-22 16:46:36 -0700121
122 lnw_gpio_set(chip, offset, value);
Alek Du8bf02612009-09-22 16:46:36 -0700123 spin_lock_irqsave(&lnw->lock, flags);
124 value = readl(gpdr);
125 value |= BIT(offset % 32);;
126 writel(value, gpdr);
127 spin_unlock_irqrestore(&lnw->lock, flags);
128 return 0;
129}
130
131static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
132{
133 struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
134 return lnw->irq_base + offset;
135}
136
137static int lnw_irq_type(unsigned irq, unsigned type)
138{
139 struct lnw_gpio *lnw = get_irq_chip_data(irq);
140 u32 gpio = irq - lnw->irq_base;
Alek Du8bf02612009-09-22 16:46:36 -0700141 unsigned long flags;
142 u32 value;
Alek Du8081c842010-05-26 14:42:25 -0700143 void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
144 void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
Alek Du8bf02612009-09-22 16:46:36 -0700145
Roel Kluin4efec622009-12-15 16:46:18 -0800146 if (gpio >= lnw->chip.ngpio)
Alek Du8bf02612009-09-22 16:46:36 -0700147 return -EINVAL;
148 spin_lock_irqsave(&lnw->lock, flags);
149 if (type & IRQ_TYPE_EDGE_RISING)
150 value = readl(grer) | BIT(gpio % 32);
151 else
152 value = readl(grer) & (~BIT(gpio % 32));
153 writel(value, grer);
154
155 if (type & IRQ_TYPE_EDGE_FALLING)
156 value = readl(gfer) | BIT(gpio % 32);
157 else
158 value = readl(gfer) & (~BIT(gpio % 32));
159 writel(value, gfer);
160 spin_unlock_irqrestore(&lnw->lock, flags);
161
162 return 0;
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700163}
Alek Du8bf02612009-09-22 16:46:36 -0700164
165static void lnw_irq_unmask(unsigned irq)
166{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700167}
Alek Du8bf02612009-09-22 16:46:36 -0700168
169static void lnw_irq_mask(unsigned irq)
170{
Andrew Mortonfd0574c2010-10-27 15:33:22 -0700171}
Alek Du8bf02612009-09-22 16:46:36 -0700172
173static struct irq_chip lnw_irqchip = {
174 .name = "LNW-GPIO",
175 .mask = lnw_irq_mask,
176 .unmask = lnw_irq_unmask,
177 .set_type = lnw_irq_type,
178};
179
Alek Du8081c842010-05-26 14:42:25 -0700180static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
181 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
Alek Du8bf02612009-09-22 16:46:36 -0700184 { 0, }
185};
186MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
187
188static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
189{
190 struct lnw_gpio *lnw = (struct lnw_gpio *)get_irq_data(irq);
Alek Du8081c842010-05-26 14:42:25 -0700191 u32 base, gpio;
Alek Du8bf02612009-09-22 16:46:36 -0700192 void __iomem *gedr;
193 u32 gedr_v;
194
195 /* check GPIO controller to check which pin triggered the interrupt */
Alek Du8081c842010-05-26 14:42:25 -0700196 for (base = 0; base < lnw->chip.ngpio; base += 32) {
197 gedr = gpio_reg(&lnw->chip, base, GEDR);
Alek Du8bf02612009-09-22 16:46:36 -0700198 gedr_v = readl(gedr);
199 if (!gedr_v)
200 continue;
Alek Du8081c842010-05-26 14:42:25 -0700201 for (gpio = base; gpio < base + 32; gpio++)
Alek Du8bf02612009-09-22 16:46:36 -0700202 if (gedr_v & BIT(gpio % 32)) {
203 pr_debug("pin %d triggered\n", gpio);
204 generic_handle_irq(lnw->irq_base + gpio);
205 }
Alek Du8bf02612009-09-22 16:46:36 -0700206 /* clear the edge detect status bit */
207 writel(gedr_v, gedr);
208 }
209 desc->chip->eoi(irq);
210}
211
212static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
213 const struct pci_device_id *id)
214{
215 void *base;
216 int i;
217 resource_size_t start, len;
218 struct lnw_gpio *lnw;
219 u32 irq_base;
220 u32 gpio_base;
221 int retval = 0;
222
223 retval = pci_enable_device(pdev);
224 if (retval)
225 goto done;
226
227 retval = pci_request_regions(pdev, "langwell_gpio");
228 if (retval) {
229 dev_err(&pdev->dev, "error requesting resources\n");
230 goto err2;
231 }
232 /* get the irq_base from bar1 */
233 start = pci_resource_start(pdev, 1);
234 len = pci_resource_len(pdev, 1);
235 base = ioremap_nocache(start, len);
236 if (!base) {
237 dev_err(&pdev->dev, "error mapping bar1\n");
238 goto err3;
239 }
240 irq_base = *(u32 *)base;
241 gpio_base = *((u32 *)base + 1);
242 /* release the IO mapping, since we already get the info from bar1 */
243 iounmap(base);
244 /* get the register base from bar0 */
245 start = pci_resource_start(pdev, 0);
246 len = pci_resource_len(pdev, 0);
247 base = ioremap_nocache(start, len);
248 if (!base) {
249 dev_err(&pdev->dev, "error mapping bar0\n");
250 retval = -EFAULT;
251 goto err3;
252 }
253
254 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
255 if (!lnw) {
256 dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
257 retval = -ENOMEM;
258 goto err4;
259 }
260 lnw->reg_base = base;
261 lnw->irq_base = irq_base;
262 lnw->chip.label = dev_name(&pdev->dev);
263 lnw->chip.direction_input = lnw_gpio_direction_input;
264 lnw->chip.direction_output = lnw_gpio_direction_output;
265 lnw->chip.get = lnw_gpio_get;
266 lnw->chip.set = lnw_gpio_set;
267 lnw->chip.to_irq = lnw_gpio_to_irq;
268 lnw->chip.base = gpio_base;
Alek Du8081c842010-05-26 14:42:25 -0700269 lnw->chip.ngpio = id->driver_data;
Alek Du8bf02612009-09-22 16:46:36 -0700270 lnw->chip.can_sleep = 0;
271 pci_set_drvdata(pdev, lnw);
272 retval = gpiochip_add(&lnw->chip);
273 if (retval) {
274 dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
275 goto err5;
276 }
277 set_irq_data(pdev->irq, lnw);
278 set_irq_chained_handler(pdev->irq, lnw_irq_handler);
279 for (i = 0; i < lnw->chip.ngpio; i++) {
280 set_irq_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
281 handle_simple_irq, "demux");
282 set_irq_chip_data(i + lnw->irq_base, lnw);
283 }
284
285 spin_lock_init(&lnw->lock);
286 goto done;
287err5:
288 kfree(lnw);
289err4:
290 iounmap(base);
291err3:
292 pci_release_regions(pdev);
293err2:
294 pci_disable_device(pdev);
295done:
296 return retval;
297}
298
299static struct pci_driver lnw_gpio_driver = {
300 .name = "langwell_gpio",
301 .id_table = lnw_gpio_ids,
302 .probe = lnw_gpio_probe,
303};
304
Alan Cox72b43792010-10-27 15:33:23 -0700305
306static int __devinit wp_gpio_probe(struct platform_device *pdev)
307{
308 struct lnw_gpio *lnw;
309 struct gpio_chip *gc;
310 struct resource *rc;
311 int retval = 0;
312
313 rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
314 if (!rc)
315 return -EINVAL;
316
317 lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
318 if (!lnw) {
319 dev_err(&pdev->dev,
320 "can't allocate whitneypoint_gpio chip data\n");
321 return -ENOMEM;
322 }
323 lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
324 if (lnw->reg_base == NULL) {
325 retval = -EINVAL;
326 goto err_kmalloc;
327 }
328 spin_lock_init(&lnw->lock);
329 gc = &lnw->chip;
330 gc->label = dev_name(&pdev->dev);
331 gc->owner = THIS_MODULE;
332 gc->direction_input = lnw_gpio_direction_input;
333 gc->direction_output = lnw_gpio_direction_output;
334 gc->get = lnw_gpio_get;
335 gc->set = lnw_gpio_set;
336 gc->to_irq = NULL;
337 gc->base = 0;
338 gc->ngpio = 64;
339 gc->can_sleep = 0;
340 retval = gpiochip_add(gc);
341 if (retval) {
342 dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
343 retval);
344 goto err_ioremap;
345 }
346 platform_set_drvdata(pdev, lnw);
347 return 0;
348err_ioremap:
349 iounmap(lnw->reg_base);
350err_kmalloc:
351 kfree(lnw);
352 return retval;
353}
354
355static int __devexit wp_gpio_remove(struct platform_device *pdev)
356{
357 struct lnw_gpio *lnw = platform_get_drvdata(pdev);
358 int err;
359 err = gpiochip_remove(&lnw->chip);
360 if (err)
361 dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
362 iounmap(lnw->reg_base);
363 kfree(lnw);
364 platform_set_drvdata(pdev, NULL);
365 return 0;
366}
367
368static struct platform_driver wp_gpio_driver = {
369 .probe = wp_gpio_probe,
370 .remove = __devexit_p(wp_gpio_remove),
371 .driver = {
372 .name = "wp_gpio",
373 .owner = THIS_MODULE,
374 },
375};
376
Alek Du8bf02612009-09-22 16:46:36 -0700377static int __init lnw_gpio_init(void)
378{
Alan Cox72b43792010-10-27 15:33:23 -0700379 int ret;
380 ret = pci_register_driver(&lnw_gpio_driver);
381 if (ret < 0)
382 return ret;
383 ret = platform_driver_register(&wp_gpio_driver);
384 if (ret < 0)
385 pci_unregister_driver(&lnw_gpio_driver);
386 return ret;
Alek Du8bf02612009-09-22 16:46:36 -0700387}
388
389device_initcall(lnw_gpio_init);