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gerrit-public.fairphone.software / kernel / msm-4.9 / 6ab3d5624e172c553004ecc862bfeac16d9d68b7 / . / arch / m32r / lib / ashxdi3.S
blob: 107594b65d58315059fd86f0cfe02c284cb6fc95 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]1/*
2 * linux/arch/m32r/lib/ashxdi3.S
3 *
4 * Copyright (C) 2001,2002 Hiroyuki Kondo, and Hirokazu Takata
5 *
6 */
7/* $Id$ */
8
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]9
10;
11; input (r0,r1) src
12; input r2 shift val
13; r3 scratch
14; output (r0,r1)
15;
16
17#ifdef CONFIG_ISA_DUAL_ISSUE
18
19#ifndef __LITTLE_ENDIAN__
20
21 .text
22 .align 4
23 .globl __ashrdi3
24__ashrdi3:
25 cmpz r2 || ldi r3, #32
26 jc r14 || cmpu r2, r3
27 bc 1f
28 ; case 32 =< shift
29 mv r1, r0 || srai r0, #31
30 addi r2, #-32
31 sra r1, r2
32 jmp r14
33 .fillinsn
341: ; case shift <32
35 mv r3, r0 || srl r1, r2
36 sra r0, r2 || neg r2, r2
37 sll r3, r2
38 or r1, r3 || jmp r14
39
40 .align 4
41 .globl __ashldi3
42 .globl __lshldi3
43__ashldi3:
44__lshldi3:
45 cmpz r2 || ldi r3, #32
46 jc r14 || cmpu r2, r3
47 bc 1f
48 ; case 32 =< shift
49 mv r0, r1 || addi r2, #-32
50 sll r0, r2 || ldi r1, #0
51 jmp r14
52 .fillinsn
531: ; case shift <32
54 mv r3, r1 || sll r0, r2
55 sll r1, r2 || neg r2, r2
56 srl r3, r2
57 or r0, r3 || jmp r14
58
59 .align 4
60 .globl __lshrdi3
61__lshrdi3:
62 cmpz r2 || ldi r3, #32
63 jc r14 || cmpu r2, r3
64 bc 1f
65 ; case 32 =< shift
66 mv r1, r0 || addi r2, #-32
67 ldi r0, #0 || srl r1, r2
68 jmp r14
69 .fillinsn
701: ; case shift <32
71 mv r3, r0 || srl r1, r2
72 srl r0, r2 || neg r2, r2
73 sll r3, r2
74 or r1, r3 || jmp r14
75
76#else /* LITTLE_ENDIAN */
77
78 .text
79 .align 4
80 .globl __ashrdi3
81__ashrdi3:
82 cmpz r2 || ldi r3, #32
83 jc r14 || cmpu r2, r3
84 bc 1f
85 ; case 32 =< shift
86 mv r0, r1 || srai r1, #31
87 addi r2, #-32
88 sra r0, r2
89 jmp r14
90 .fillinsn
911: ; case shift <32
92 mv r3, r1 || srl r0, r2
93 sra r1, r2 || neg r2, r2
94 sll r3, r2
95 or r0, r3 || jmp r14
96
97 .align 4
98 .globl __ashldi3
99 .globl __lshldi3
100__ashldi3:
101__lshldi3:
102 cmpz r2 || ldi r3, #32
103 jc r14 || cmpu r2, r3
104 bc 1f
105 ; case 32 =< shift
106 mv r1, r0 || addi r2, #-32
107 sll r1, r2 || ldi r0, #0
108 jmp r14
109 .fillinsn
1101: ; case shift <32
111 mv r3, r0 || sll r1, r2
112 sll r0, r2 || neg r2, r2
113 srl r3, r2
114 or r1, r3 || jmp r14
115
116 .align 4
117 .globl __lshrdi3
118__lshrdi3:
119 cmpz r2 || ldi r3, #32
120 jc r14 || cmpu r2, r3
121 bc 1f
122 ; case 32 =< shift
123 mv r0, r1 || addi r2, #-32
124 ldi r1, #0 || srl r0, r2
125 jmp r14
126 .fillinsn
1271: ; case shift <32
128 mv r3, r1 || srl r0, r2
129 srl r1, r2 || neg r2, r2
130 sll r3, r2
131 or r0, r3 || jmp r14
132
133#endif
134
135#else /* not CONFIG_ISA_DUAL_ISSUE */
136
137#ifndef __LITTLE_ENDIAN__
138
139 .text
140 .align 4
141 .globl __ashrdi3
142__ashrdi3:
143 beqz r2, 2f
144 cmpui r2, #32
145 bc 1f
146 ; case 32 =< shift
147 mv r1, r0
148 srai r0, #31
149 addi r2, #-32
150 sra r1, r2
151 jmp r14
152 .fillinsn
1531: ; case shift <32
154 mv r3, r0
155 srl r1, r2
156 sra r0, r2
157 neg r2, r2
158 sll r3, r2
159 or r1, r3
160 .fillinsn
1612:
162 jmp r14
163
164 .align 4
165 .globl __ashldi3
166 .globl __lshldi3
167__ashldi3:
168__lshldi3:
169 beqz r2, 2f
170 cmpui r2, #32
171 bc 1f
172 ; case 32 =< shift
173 mv r0, r1
174 addi r2, #-32
175 sll r0, r2
176 ldi r1, #0
177 jmp r14
178 .fillinsn
1791: ; case shift <32
180 mv r3, r1
181 sll r0, r2
182 sll r1, r2
183 neg r2, r2
184 srl r3, r2
185 or r0, r3
186 .fillinsn
1872:
188 jmp r14
189
190 .align 4
191 .globl __lshrdi3
192__lshrdi3:
193 beqz r2, 2f
194 cmpui r2, #32
195 bc 1f
196 ; case 32 =< shift
197 mv r1, r0
198 ldi r0, #0
199 addi r2, #-32
200 srl r1, r2
201 jmp r14
202 .fillinsn
2031: ; case shift <32
204 mv r3, r0
205 srl r1, r2
206 srl r0, r2
207 neg r2, r2
208 sll r3, r2
209 or r1, r3
210 .fillinsn
2112:
212 jmp r14
213
214#else
215
216 .text
217 .align 4
218 .globl __ashrdi3
219__ashrdi3:
220 beqz r2, 2f
221 cmpui r2, #32
222 bc 1f
223 ; case 32 =< shift
224 mv r0, r1
225 srai r1, #31
226 addi r2, #-32
227 sra r0, r2
228 jmp r14
229 .fillinsn
2301: ; case shift <32
231 mv r3, r1
232 srl r0, r2
233 sra r1, r2
234 neg r2, r2
235 sll r3, r2
236 or r0, r3
237 .fillinsn
2382:
239 jmp r14
240
241 .align 4
242 .globl __ashldi3
243 .globl __lshldi3
244__ashldi3:
245__lshldi3:
246 beqz r2, 2f
247 cmpui r2, #32
248 bc 1f
249 ; case 32 =< shift
250 mv r1, r0
251 addi r2, #-32
252 sll r1, r2
253 ldi r0, #0
254 jmp r14
255 .fillinsn
2561: ; case shift <32
257 mv r3, r0
258 sll r1, r2
259 sll r0, r2
260 neg r2, r2
261 srl r3, r2
262 or r1, r3
263 .fillinsn
2642:
265 jmp r14
266
267 .align 4
268 .globl __lshrdi3
269__lshrdi3:
270 beqz r2, 2f
271 cmpui r2, #32
272 bc 1f
273 ; case 32 =< shift
274 mv r0, r1
275 ldi r1, #0
276 addi r2, #-32
277 srl r0, r2
278 jmp r14
279 .fillinsn
2801: ; case shift <32
281 mv r3, r1
282 srl r0, r2
283 srl r1, r2
284 neg r2, r2
285 sll r3, r2
286 or r0, r3
287 .fillinsn
2882:
289 jmp r14
290
291#endif
292
293#endif /* not CONFIG_ISA_DUAL_ISSUE */
294
295 .end
296