blob: 8fbfe2483ffdd12c20683e50194877c1a1ac85ca [file] [log] [blame]
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001/*
2 * Copyright (C) 2009 Texas Instruments.
Brian Niebuhr43abb112010-10-06 18:34:47 +05303 * Copyright (C) 2010 EF Johnson Technologies
Sandeep Paulraj358934a2009-12-16 22:02:18 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/module.h>
24#include <linux/delay.h>
25#include <linux/platform_device.h>
26#include <linux/err.h>
27#include <linux/clk.h>
Matt Porter048177c2012-08-22 21:09:36 -040028#include <linux/dmaengine.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000029#include <linux/dma-mapping.h>
Matt Porter048177c2012-08-22 21:09:36 -040030#include <linux/edma.h>
Murali Karicheriaae71472012-12-11 16:20:39 -050031#include <linux/of.h>
32#include <linux/of_device.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000033#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090035#include <linux/slab.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000036
Arnd Bergmannec2a0832012-08-24 15:11:34 +020037#include <linux/platform_data/spi-davinci.h>
Sandeep Paulraj358934a2009-12-16 22:02:18 +000038
39#define SPI_NO_RESOURCE ((resource_size_t)-1)
40
41#define SPI_MAX_CHIPSELECT 2
42
43#define CS_DEFAULT 0xFF
44
Sandeep Paulraj358934a2009-12-16 22:02:18 +000045#define SPIFMT_PHASE_MASK BIT(16)
46#define SPIFMT_POLARITY_MASK BIT(17)
47#define SPIFMT_DISTIMER_MASK BIT(18)
48#define SPIFMT_SHIFTDIR_MASK BIT(20)
49#define SPIFMT_WAITENA_MASK BIT(21)
50#define SPIFMT_PARITYENA_MASK BIT(22)
51#define SPIFMT_ODD_PARITY_MASK BIT(23)
52#define SPIFMT_WDELAY_MASK 0x3f000000u
53#define SPIFMT_WDELAY_SHIFT 24
Brian Niebuhr7fe00922010-08-13 13:27:23 +053054#define SPIFMT_PRESCALE_SHIFT 8
Sandeep Paulraj358934a2009-12-16 22:02:18 +000055
Sandeep Paulraj358934a2009-12-16 22:02:18 +000056/* SPIPC0 */
57#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
58#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
59#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
60#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000061
62#define SPIINT_MASKALL 0x0101035F
Brian Niebuhre0d205e2010-09-02 16:52:06 +053063#define SPIINT_MASKINT 0x0000015F
64#define SPI_INTLVL_1 0x000001FF
65#define SPI_INTLVL_0 0x00000000
Sandeep Paulraj358934a2009-12-16 22:02:18 +000066
Brian Niebuhrcfbc5d12010-08-12 12:27:33 +053067/* SPIDAT1 (upper 16 bit defines) */
68#define SPIDAT1_CSHOLD_MASK BIT(12)
69
70/* SPIGCR1 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +000071#define SPIGCR1_CLKMOD_MASK BIT(1)
72#define SPIGCR1_MASTER_MASK BIT(0)
Brian Niebuhr3f27b572010-10-06 18:25:43 +053073#define SPIGCR1_POWERDOWN_MASK BIT(8)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000074#define SPIGCR1_LOOPBACK_MASK BIT(16)
Sekhar Nori8e206f12010-08-20 16:20:49 +053075#define SPIGCR1_SPIENA_MASK BIT(24)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000076
77/* SPIBUF */
78#define SPIBUF_TXFULL_MASK BIT(29)
79#define SPIBUF_RXEMPTY_MASK BIT(31)
80
Brian Niebuhr7abbf232010-08-19 15:07:38 +053081/* SPIDELAY */
82#define SPIDELAY_C2TDELAY_SHIFT 24
83#define SPIDELAY_C2TDELAY_MASK (0xFF << SPIDELAY_C2TDELAY_SHIFT)
84#define SPIDELAY_T2CDELAY_SHIFT 16
85#define SPIDELAY_T2CDELAY_MASK (0xFF << SPIDELAY_T2CDELAY_SHIFT)
86#define SPIDELAY_T2EDELAY_SHIFT 8
87#define SPIDELAY_T2EDELAY_MASK (0xFF << SPIDELAY_T2EDELAY_SHIFT)
88#define SPIDELAY_C2EDELAY_SHIFT 0
89#define SPIDELAY_C2EDELAY_MASK 0xFF
90
Sandeep Paulraj358934a2009-12-16 22:02:18 +000091/* Error Masks */
92#define SPIFLG_DLEN_ERR_MASK BIT(0)
93#define SPIFLG_TIMEOUT_MASK BIT(1)
94#define SPIFLG_PARERR_MASK BIT(2)
95#define SPIFLG_DESYNC_MASK BIT(3)
96#define SPIFLG_BITERR_MASK BIT(4)
97#define SPIFLG_OVRRUN_MASK BIT(6)
Sandeep Paulraj358934a2009-12-16 22:02:18 +000098#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
Brian Niebuhr839c9962010-08-23 16:39:19 +053099#define SPIFLG_ERROR_MASK (SPIFLG_DLEN_ERR_MASK \
100 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
101 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
102 | SPIFLG_OVRRUN_MASK)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000103
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000104#define SPIINT_DMA_REQ_EN BIT(16)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000105
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000106/* SPI Controller registers */
107#define SPIGCR0 0x00
108#define SPIGCR1 0x04
109#define SPIINT 0x08
110#define SPILVL 0x0c
111#define SPIFLG 0x10
112#define SPIPC0 0x14
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000113#define SPIDAT1 0x3c
114#define SPIBUF 0x40
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000115#define SPIDELAY 0x48
116#define SPIDEF 0x4c
117#define SPIFMT0 0x50
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000118
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000119/* SPI Controller driver's private data. */
120struct davinci_spi {
121 struct spi_bitbang bitbang;
122 struct clk *clk;
123
124 u8 version;
125 resource_size_t pbase;
126 void __iomem *base;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530127 u32 irq;
128 struct completion done;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000129
130 const void *tx;
131 void *rx;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530132 int rcount;
133 int wcount;
Matt Porter048177c2012-08-22 21:09:36 -0400134
135 struct dma_chan *dma_rx;
136 struct dma_chan *dma_tx;
137 int dma_rx_chnum;
138 int dma_tx_chnum;
139
Murali Karicheriaae71472012-12-11 16:20:39 -0500140 struct davinci_spi_platform_data pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000141
142 void (*get_rx)(u32 rx_data, struct davinci_spi *);
143 u32 (*get_tx)(struct davinci_spi *);
144
Brian Niebuhrcda987e2010-08-19 16:16:28 +0530145 u8 bytes_per_word[SPI_MAX_CHIPSELECT];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000146};
147
Brian Niebuhr53a31b02010-08-16 15:05:51 +0530148static struct davinci_spi_config davinci_spi_default_cfg;
149
Sekhar Nori212d4b62010-10-11 10:41:39 +0530150static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000151{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530152 if (dspi->rx) {
153 u8 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530154 *rx++ = (u8)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530155 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530156 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000157}
158
Sekhar Nori212d4b62010-10-11 10:41:39 +0530159static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000160{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530161 if (dspi->rx) {
162 u16 *rx = dspi->rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530163 *rx++ = (u16)data;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530164 dspi->rx = rx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530165 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000166}
167
Sekhar Nori212d4b62010-10-11 10:41:39 +0530168static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000169{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530170 u32 data = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530171 if (dspi->tx) {
172 const u8 *tx = dspi->tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530173 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530174 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530175 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000176 return data;
177}
178
Sekhar Nori212d4b62010-10-11 10:41:39 +0530179static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000180{
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530181 u32 data = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530182 if (dspi->tx) {
183 const u16 *tx = dspi->tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530184 data = *tx++;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530185 dspi->tx = tx;
Brian Niebuhr53d454a2010-08-19 17:04:25 +0530186 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000187 return data;
188}
189
190static inline void set_io_bits(void __iomem *addr, u32 bits)
191{
192 u32 v = ioread32(addr);
193
194 v |= bits;
195 iowrite32(v, addr);
196}
197
198static inline void clear_io_bits(void __iomem *addr, u32 bits)
199{
200 u32 v = ioread32(addr);
201
202 v &= ~bits;
203 iowrite32(v, addr);
204}
205
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000206/*
207 * Interface to control the chip select signal
208 */
209static void davinci_spi_chipselect(struct spi_device *spi, int value)
210{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530211 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000212 struct davinci_spi_platform_data *pdata;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530213 u8 chip_sel = spi->chip_select;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530214 u16 spidat1 = CS_DEFAULT;
Brian Niebuhr23853972010-08-13 10:57:44 +0530215 bool gpio_chipsel = false;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000216
Sekhar Nori212d4b62010-10-11 10:41:39 +0530217 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500218 pdata = &dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000219
Brian Niebuhr23853972010-08-13 10:57:44 +0530220 if (pdata->chip_sel && chip_sel < pdata->num_chipselect &&
221 pdata->chip_sel[chip_sel] != SPI_INTERN_CS)
222 gpio_chipsel = true;
223
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000224 /*
225 * Board specific chip select logic decides the polarity and cs
226 * line for the controller
227 */
Brian Niebuhr23853972010-08-13 10:57:44 +0530228 if (gpio_chipsel) {
229 if (value == BITBANG_CS_ACTIVE)
230 gpio_set_value(pdata->chip_sel[chip_sel], 0);
231 else
232 gpio_set_value(pdata->chip_sel[chip_sel], 1);
233 } else {
234 if (value == BITBANG_CS_ACTIVE) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530235 spidat1 |= SPIDAT1_CSHOLD_MASK;
236 spidat1 &= ~(0x1 << chip_sel);
Brian Niebuhr23853972010-08-13 10:57:44 +0530237 }
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530238
Sekhar Nori212d4b62010-10-11 10:41:39 +0530239 iowrite16(spidat1, dspi->base + SPIDAT1 + 2);
Brian Niebuhr23853972010-08-13 10:57:44 +0530240 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000241}
242
243/**
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530244 * davinci_spi_get_prescale - Calculates the correct prescale value
245 * @maxspeed_hz: the maximum rate the SPI clock can run at
246 *
247 * This function calculates the prescale value that generates a clock rate
248 * less than or equal to the specified maximum.
249 *
250 * Returns: calculated prescale - 1 for easy programming into SPI registers
251 * or negative error number if valid prescalar cannot be updated.
252 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530253static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530254 u32 max_speed_hz)
255{
256 int ret;
257
Sekhar Nori212d4b62010-10-11 10:41:39 +0530258 ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530259
260 if (ret < 3 || ret > 256)
261 return -EINVAL;
262
263 return ret - 1;
264}
265
266/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000267 * davinci_spi_setup_transfer - This functions will determine transfer method
268 * @spi: spi device on which data transfer to be done
269 * @t: spi transfer in which transfer info is filled
270 *
271 * This function determines data transfer method (8/16/32 bit transfer).
272 * It will also set the SPI Clock Control register according to
273 * SPI slave device freq.
274 */
275static int davinci_spi_setup_transfer(struct spi_device *spi,
276 struct spi_transfer *t)
277{
278
Sekhar Nori212d4b62010-10-11 10:41:39 +0530279 struct davinci_spi *dspi;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530280 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000281 u8 bits_per_word = 0;
Brian Niebuhr25f33512010-08-19 12:15:22 +0530282 u32 hz = 0, spifmt = 0, prescale = 0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000283
Sekhar Nori212d4b62010-10-11 10:41:39 +0530284 dspi = spi_master_get_devdata(spi->master);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530285 spicfg = (struct davinci_spi_config *)spi->controller_data;
286 if (!spicfg)
287 spicfg = &davinci_spi_default_cfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000288
289 if (t) {
290 bits_per_word = t->bits_per_word;
291 hz = t->speed_hz;
292 }
293
294 /* if bits_per_word is not set then set it default */
295 if (!bits_per_word)
296 bits_per_word = spi->bits_per_word;
297
298 /*
299 * Assign function pointer to appropriate transfer method
300 * 8bit, 16bit or 32bit transfer
301 */
Stephen Warren24778be2013-05-21 20:36:35 -0600302 if (bits_per_word <= 8) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530303 dspi->get_rx = davinci_spi_rx_buf_u8;
304 dspi->get_tx = davinci_spi_tx_buf_u8;
305 dspi->bytes_per_word[spi->chip_select] = 1;
Stephen Warren24778be2013-05-21 20:36:35 -0600306 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530307 dspi->get_rx = davinci_spi_rx_buf_u16;
308 dspi->get_tx = davinci_spi_tx_buf_u16;
309 dspi->bytes_per_word[spi->chip_select] = 2;
Stephen Warren24778be2013-05-21 20:36:35 -0600310 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000311
312 if (!hz)
313 hz = spi->max_speed_hz;
314
Brian Niebuhr25f33512010-08-19 12:15:22 +0530315 /* Set up SPIFMTn register, unique to this chipselect. */
316
Sekhar Nori212d4b62010-10-11 10:41:39 +0530317 prescale = davinci_spi_get_prescale(dspi, hz);
Brian Niebuhr7fe00922010-08-13 13:27:23 +0530318 if (prescale < 0)
319 return prescale;
320
Brian Niebuhr25f33512010-08-19 12:15:22 +0530321 spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000322
Brian Niebuhr25f33512010-08-19 12:15:22 +0530323 if (spi->mode & SPI_LSB_FIRST)
324 spifmt |= SPIFMT_SHIFTDIR_MASK;
325
326 if (spi->mode & SPI_CPOL)
327 spifmt |= SPIFMT_POLARITY_MASK;
328
329 if (!(spi->mode & SPI_CPHA))
330 spifmt |= SPIFMT_PHASE_MASK;
331
332 /*
333 * Version 1 hardware supports two basic SPI modes:
334 * - Standard SPI mode uses 4 pins, with chipselect
335 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
336 * (distinct from SPI_3WIRE, with just one data wire;
337 * or similar variants without MOSI or without MISO)
338 *
339 * Version 2 hardware supports an optional handshaking signal,
340 * so it can support two more modes:
341 * - 5 pin SPI variant is standard SPI plus SPI_READY
342 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
343 */
344
Sekhar Nori212d4b62010-10-11 10:41:39 +0530345 if (dspi->version == SPI_VERSION_2) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530346
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530347 u32 delay = 0;
348
Brian Niebuhr25f33512010-08-19 12:15:22 +0530349 spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
350 & SPIFMT_WDELAY_MASK);
351
352 if (spicfg->odd_parity)
353 spifmt |= SPIFMT_ODD_PARITY_MASK;
354
355 if (spicfg->parity_enable)
356 spifmt |= SPIFMT_PARITYENA_MASK;
357
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530358 if (spicfg->timer_disable) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530359 spifmt |= SPIFMT_DISTIMER_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530360 } else {
361 delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
362 & SPIDELAY_C2TDELAY_MASK;
363 delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
364 & SPIDELAY_T2CDELAY_MASK;
365 }
Brian Niebuhr25f33512010-08-19 12:15:22 +0530366
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530367 if (spi->mode & SPI_READY) {
Brian Niebuhr25f33512010-08-19 12:15:22 +0530368 spifmt |= SPIFMT_WAITENA_MASK;
Brian Niebuhr7abbf232010-08-19 15:07:38 +0530369 delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
370 & SPIDELAY_T2EDELAY_MASK;
371 delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
372 & SPIDELAY_C2EDELAY_MASK;
373 }
374
Sekhar Nori212d4b62010-10-11 10:41:39 +0530375 iowrite32(delay, dspi->base + SPIDELAY);
Brian Niebuhr25f33512010-08-19 12:15:22 +0530376 }
377
Sekhar Nori212d4b62010-10-11 10:41:39 +0530378 iowrite32(spifmt, dspi->base + SPIFMT0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000379
380 return 0;
381}
382
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000383/**
384 * davinci_spi_setup - This functions will set default transfer method
385 * @spi: spi device on which data transfer to be done
386 *
387 * This functions sets the default transfer method.
388 */
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000389static int davinci_spi_setup(struct spi_device *spi)
390{
Brian Niebuhrb23a5d42010-09-24 18:53:32 +0530391 int retval = 0;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530392 struct davinci_spi *dspi;
Brian Niebuhrbe884712010-09-03 12:15:28 +0530393 struct davinci_spi_platform_data *pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000394
Sekhar Nori212d4b62010-10-11 10:41:39 +0530395 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500396 pdata = &dspi->pdata;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000397
398 /* if bits per word length is zero then set it default 8 */
399 if (!spi->bits_per_word)
400 spi->bits_per_word = 8;
401
Brian Niebuhrbe884712010-09-03 12:15:28 +0530402 if (!(spi->mode & SPI_NO_CS)) {
403 if ((pdata->chip_sel == NULL) ||
404 (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
Sekhar Nori212d4b62010-10-11 10:41:39 +0530405 set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530406
407 }
408
409 if (spi->mode & SPI_READY)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530410 set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530411
412 if (spi->mode & SPI_LOOP)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530413 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530414 else
Sekhar Nori212d4b62010-10-11 10:41:39 +0530415 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
Brian Niebuhrbe884712010-09-03 12:15:28 +0530416
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000417 return retval;
418}
419
Sekhar Nori212d4b62010-10-11 10:41:39 +0530420static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000421{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530422 struct device *sdev = dspi->bitbang.master->dev.parent;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000423
424 if (int_status & SPIFLG_TIMEOUT_MASK) {
425 dev_dbg(sdev, "SPI Time-out Error\n");
426 return -ETIMEDOUT;
427 }
428 if (int_status & SPIFLG_DESYNC_MASK) {
429 dev_dbg(sdev, "SPI Desynchronization Error\n");
430 return -EIO;
431 }
432 if (int_status & SPIFLG_BITERR_MASK) {
433 dev_dbg(sdev, "SPI Bit error\n");
434 return -EIO;
435 }
436
Sekhar Nori212d4b62010-10-11 10:41:39 +0530437 if (dspi->version == SPI_VERSION_2) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000438 if (int_status & SPIFLG_DLEN_ERR_MASK) {
439 dev_dbg(sdev, "SPI Data Length Error\n");
440 return -EIO;
441 }
442 if (int_status & SPIFLG_PARERR_MASK) {
443 dev_dbg(sdev, "SPI Parity Error\n");
444 return -EIO;
445 }
446 if (int_status & SPIFLG_OVRRUN_MASK) {
447 dev_dbg(sdev, "SPI Data Overrun error\n");
448 return -EIO;
449 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000450 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
451 dev_dbg(sdev, "SPI Buffer Init Active\n");
452 return -EBUSY;
453 }
454 }
455
456 return 0;
457}
458
459/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530460 * davinci_spi_process_events - check for and handle any SPI controller events
Sekhar Nori212d4b62010-10-11 10:41:39 +0530461 * @dspi: the controller data
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530462 *
463 * This function will check the SPIFLG register and handle any events that are
464 * detected there
465 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530466static int davinci_spi_process_events(struct davinci_spi *dspi)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530467{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530468 u32 buf, status, errors = 0, spidat1;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530469
Sekhar Nori212d4b62010-10-11 10:41:39 +0530470 buf = ioread32(dspi->base + SPIBUF);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530471
Sekhar Nori212d4b62010-10-11 10:41:39 +0530472 if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
473 dspi->get_rx(buf & 0xFFFF, dspi);
474 dspi->rcount--;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530475 }
476
Sekhar Nori212d4b62010-10-11 10:41:39 +0530477 status = ioread32(dspi->base + SPIFLG);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530478
479 if (unlikely(status & SPIFLG_ERROR_MASK)) {
480 errors = status & SPIFLG_ERROR_MASK;
481 goto out;
482 }
483
Sekhar Nori212d4b62010-10-11 10:41:39 +0530484 if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
485 spidat1 = ioread32(dspi->base + SPIDAT1);
486 dspi->wcount--;
487 spidat1 &= ~0xFFFF;
488 spidat1 |= 0xFFFF & dspi->get_tx(dspi);
489 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530490 }
491
492out:
493 return errors;
494}
495
Matt Porter048177c2012-08-22 21:09:36 -0400496static void davinci_spi_dma_rx_callback(void *data)
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530497{
Matt Porter048177c2012-08-22 21:09:36 -0400498 struct davinci_spi *dspi = (struct davinci_spi *)data;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530499
Matt Porter048177c2012-08-22 21:09:36 -0400500 dspi->rcount = 0;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530501
Matt Porter048177c2012-08-22 21:09:36 -0400502 if (!dspi->wcount && !dspi->rcount)
503 complete(&dspi->done);
504}
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530505
Matt Porter048177c2012-08-22 21:09:36 -0400506static void davinci_spi_dma_tx_callback(void *data)
507{
508 struct davinci_spi *dspi = (struct davinci_spi *)data;
509
510 dspi->wcount = 0;
511
512 if (!dspi->wcount && !dspi->rcount)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530513 complete(&dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530514}
515
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530516/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000517 * davinci_spi_bufs - functions which will handle transfer data
518 * @spi: spi device on which data transfer to be done
519 * @t: spi transfer in which transfer info is filled
520 *
521 * This function will put data to be transferred into data register
522 * of SPI controller and then wait until the completion will be marked
523 * by the IRQ Handler.
524 */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530525static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000526{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530527 struct davinci_spi *dspi;
Matt Porter048177c2012-08-22 21:09:36 -0400528 int data_type, ret = -ENOMEM;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530529 u32 tx_data, spidat1;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530530 u32 errors = 0;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530531 struct davinci_spi_config *spicfg;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000532 struct davinci_spi_platform_data *pdata;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530533 unsigned uninitialized_var(rx_buf_count);
Matt Porter048177c2012-08-22 21:09:36 -0400534 void *dummy_buf = NULL;
535 struct scatterlist sg_rx, sg_tx;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000536
Sekhar Nori212d4b62010-10-11 10:41:39 +0530537 dspi = spi_master_get_devdata(spi->master);
Murali Karicheriaae71472012-12-11 16:20:39 -0500538 pdata = &dspi->pdata;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530539 spicfg = (struct davinci_spi_config *)spi->controller_data;
540 if (!spicfg)
541 spicfg = &davinci_spi_default_cfg;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530542
543 /* convert len to words based on bits_per_word */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530544 data_type = dspi->bytes_per_word[spi->chip_select];
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000545
Sekhar Nori212d4b62010-10-11 10:41:39 +0530546 dspi->tx = t->tx_buf;
547 dspi->rx = t->rx_buf;
548 dspi->wcount = t->len / data_type;
549 dspi->rcount = dspi->wcount;
Brian Niebuhr7978b8c2010-08-13 10:11:03 +0530550
Sekhar Nori212d4b62010-10-11 10:41:39 +0530551 spidat1 = ioread32(dspi->base + SPIDAT1);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530552
Sekhar Nori212d4b62010-10-11 10:41:39 +0530553 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
554 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000555
Sekhar Nori212d4b62010-10-11 10:41:39 +0530556 INIT_COMPLETION(dspi->done);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530557
558 if (spicfg->io_type == SPI_IO_TYPE_INTR)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530559 set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530560
561 if (spicfg->io_type != SPI_IO_TYPE_DMA) {
562 /* start the transfer */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530563 dspi->wcount--;
564 tx_data = dspi->get_tx(dspi);
565 spidat1 &= 0xFFFF0000;
566 spidat1 |= tx_data & 0xFFFF;
567 iowrite32(spidat1, dspi->base + SPIDAT1);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530568 } else {
Matt Porter048177c2012-08-22 21:09:36 -0400569 struct dma_slave_config dma_rx_conf = {
570 .direction = DMA_DEV_TO_MEM,
571 .src_addr = (unsigned long)dspi->pbase + SPIBUF,
572 .src_addr_width = data_type,
573 .src_maxburst = 1,
574 };
575 struct dma_slave_config dma_tx_conf = {
576 .direction = DMA_MEM_TO_DEV,
577 .dst_addr = (unsigned long)dspi->pbase + SPIDAT1,
578 .dst_addr_width = data_type,
579 .dst_maxburst = 1,
580 };
581 struct dma_async_tx_descriptor *rxdesc;
582 struct dma_async_tx_descriptor *txdesc;
583 void *buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530584
Matt Porter048177c2012-08-22 21:09:36 -0400585 dummy_buf = kzalloc(t->len, GFP_KERNEL);
586 if (!dummy_buf)
587 goto err_alloc_dummy_buf;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530588
Matt Porter048177c2012-08-22 21:09:36 -0400589 dmaengine_slave_config(dspi->dma_rx, &dma_rx_conf);
590 dmaengine_slave_config(dspi->dma_tx, &dma_tx_conf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530591
Matt Porter048177c2012-08-22 21:09:36 -0400592 sg_init_table(&sg_rx, 1);
593 if (!t->rx_buf)
594 buf = dummy_buf;
Michael Williamsonb1178b22011-03-14 11:49:02 -0400595 else
Matt Porter048177c2012-08-22 21:09:36 -0400596 buf = t->rx_buf;
597 t->rx_dma = dma_map_single(&spi->dev, buf,
598 t->len, DMA_FROM_DEVICE);
599 if (!t->rx_dma) {
600 ret = -EFAULT;
601 goto err_rx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530602 }
Matt Porter048177c2012-08-22 21:09:36 -0400603 sg_dma_address(&sg_rx) = t->rx_dma;
604 sg_dma_len(&sg_rx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530605
Matt Porter048177c2012-08-22 21:09:36 -0400606 sg_init_table(&sg_tx, 1);
607 if (!t->tx_buf)
608 buf = dummy_buf;
609 else
610 buf = (void *)t->tx_buf;
611 t->tx_dma = dma_map_single(&spi->dev, buf,
Christian Eggers89c66ee2013-07-29 20:54:09 +0200612 t->len, DMA_TO_DEVICE);
Matt Porter048177c2012-08-22 21:09:36 -0400613 if (!t->tx_dma) {
614 ret = -EFAULT;
615 goto err_tx_map;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530616 }
Matt Porter048177c2012-08-22 21:09:36 -0400617 sg_dma_address(&sg_tx) = t->tx_dma;
618 sg_dma_len(&sg_tx) = t->len;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530619
Matt Porter048177c2012-08-22 21:09:36 -0400620 rxdesc = dmaengine_prep_slave_sg(dspi->dma_rx,
621 &sg_rx, 1, DMA_DEV_TO_MEM,
622 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
623 if (!rxdesc)
624 goto err_desc;
625
626 txdesc = dmaengine_prep_slave_sg(dspi->dma_tx,
627 &sg_tx, 1, DMA_MEM_TO_DEV,
628 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
629 if (!txdesc)
630 goto err_desc;
631
632 rxdesc->callback = davinci_spi_dma_rx_callback;
633 rxdesc->callback_param = (void *)dspi;
634 txdesc->callback = davinci_spi_dma_tx_callback;
635 txdesc->callback_param = (void *)dspi;
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530636
637 if (pdata->cshold_bug)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530638 iowrite16(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530639
Matt Porter048177c2012-08-22 21:09:36 -0400640 dmaengine_submit(rxdesc);
641 dmaengine_submit(txdesc);
642
643 dma_async_issue_pending(dspi->dma_rx);
644 dma_async_issue_pending(dspi->dma_tx);
645
Sekhar Nori212d4b62010-10-11 10:41:39 +0530646 set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530647 }
Brian Niebuhrcf90fe72010-08-20 17:02:49 +0530648
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530649 /* Wait for the transfer to complete */
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530650 if (spicfg->io_type != SPI_IO_TYPE_POLL) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530651 wait_for_completion_interruptible(&(dspi->done));
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530652 } else {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530653 while (dspi->rcount > 0 || dspi->wcount > 0) {
654 errors = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530655 if (errors)
656 break;
657 cpu_relax();
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000658 }
659 }
660
Sekhar Nori212d4b62010-10-11 10:41:39 +0530661 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530662 if (spicfg->io_type == SPI_IO_TYPE_DMA) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530663 clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
Matt Porter048177c2012-08-22 21:09:36 -0400664
665 dma_unmap_single(&spi->dev, t->rx_dma,
666 t->len, DMA_FROM_DEVICE);
667 dma_unmap_single(&spi->dev, t->tx_dma,
668 t->len, DMA_TO_DEVICE);
669 kfree(dummy_buf);
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530670 }
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530671
Sekhar Nori212d4b62010-10-11 10:41:39 +0530672 clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
673 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Brian Niebuhr3f27b572010-10-06 18:25:43 +0530674
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000675 /*
676 * Check for bit error, desync error,parity error,timeout error and
677 * receive overflow errors
678 */
Brian Niebuhr839c9962010-08-23 16:39:19 +0530679 if (errors) {
Sekhar Nori212d4b62010-10-11 10:41:39 +0530680 ret = davinci_spi_check_error(dspi, errors);
Brian Niebuhr839c9962010-08-23 16:39:19 +0530681 WARN(!ret, "%s: error reported but no error found!\n",
682 dev_name(&spi->dev));
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000683 return ret;
Brian Niebuhr839c9962010-08-23 16:39:19 +0530684 }
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000685
Sekhar Nori212d4b62010-10-11 10:41:39 +0530686 if (dspi->rcount != 0 || dspi->wcount != 0) {
Matt Porter048177c2012-08-22 21:09:36 -0400687 dev_err(&spi->dev, "SPI data transfer error\n");
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530688 return -EIO;
689 }
690
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000691 return t->len;
Matt Porter048177c2012-08-22 21:09:36 -0400692
693err_desc:
694 dma_unmap_single(&spi->dev, t->tx_dma, t->len, DMA_TO_DEVICE);
695err_tx_map:
696 dma_unmap_single(&spi->dev, t->rx_dma, t->len, DMA_FROM_DEVICE);
697err_rx_map:
698 kfree(dummy_buf);
699err_alloc_dummy_buf:
700 return ret;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000701}
702
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530703/**
Murali Karicheri32310aa2012-12-21 15:13:26 -0500704 * dummy_thread_fn - dummy thread function
705 * @irq: IRQ number for this SPI Master
706 * @context_data: structure for SPI Master controller davinci_spi
707 *
708 * This is to satisfy the request_threaded_irq() API so that the irq
709 * handler is called in interrupt context.
710 */
711static irqreturn_t dummy_thread_fn(s32 irq, void *data)
712{
713 return IRQ_HANDLED;
714}
715
716/**
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530717 * davinci_spi_irq - Interrupt handler for SPI Master Controller
718 * @irq: IRQ number for this SPI Master
719 * @context_data: structure for SPI Master controller davinci_spi
720 *
721 * ISR will determine that interrupt arrives either for READ or WRITE command.
722 * According to command it will do the appropriate action. It will check
723 * transfer length and if it is not zero then dispatch transfer command again.
724 * If transfer length is zero then it will indicate the COMPLETION so that
725 * davinci_spi_bufs function can go ahead.
726 */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530727static irqreturn_t davinci_spi_irq(s32 irq, void *data)
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530728{
Sekhar Nori212d4b62010-10-11 10:41:39 +0530729 struct davinci_spi *dspi = data;
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530730 int status;
731
Sekhar Nori212d4b62010-10-11 10:41:39 +0530732 status = davinci_spi_process_events(dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530733 if (unlikely(status != 0))
Sekhar Nori212d4b62010-10-11 10:41:39 +0530734 clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530735
Sekhar Nori212d4b62010-10-11 10:41:39 +0530736 if ((!dspi->rcount && !dspi->wcount) || status)
737 complete(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530738
739 return IRQ_HANDLED;
740}
741
Sekhar Nori212d4b62010-10-11 10:41:39 +0530742static int davinci_spi_request_dma(struct davinci_spi *dspi)
Sekhar Nori903ca252010-10-01 14:51:40 +0530743{
Matt Porter048177c2012-08-22 21:09:36 -0400744 dma_cap_mask_t mask;
745 struct device *sdev = dspi->bitbang.master->dev.parent;
Sekhar Nori903ca252010-10-01 14:51:40 +0530746 int r;
747
Matt Porter048177c2012-08-22 21:09:36 -0400748 dma_cap_zero(mask);
749 dma_cap_set(DMA_SLAVE, mask);
750
751 dspi->dma_rx = dma_request_channel(mask, edma_filter_fn,
752 &dspi->dma_rx_chnum);
753 if (!dspi->dma_rx) {
754 dev_err(sdev, "request RX DMA channel failed\n");
755 r = -ENODEV;
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530756 goto rx_dma_failed;
Sekhar Nori903ca252010-10-01 14:51:40 +0530757 }
758
Matt Porter048177c2012-08-22 21:09:36 -0400759 dspi->dma_tx = dma_request_channel(mask, edma_filter_fn,
760 &dspi->dma_tx_chnum);
761 if (!dspi->dma_tx) {
762 dev_err(sdev, "request TX DMA channel failed\n");
763 r = -ENODEV;
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530764 goto tx_dma_failed;
Sekhar Nori903ca252010-10-01 14:51:40 +0530765 }
766
767 return 0;
Matt Porter048177c2012-08-22 21:09:36 -0400768
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530769tx_dma_failed:
Matt Porter048177c2012-08-22 21:09:36 -0400770 dma_release_channel(dspi->dma_rx);
Brian Niebuhr523c37e2010-10-04 17:35:34 +0530771rx_dma_failed:
772 return r;
Sekhar Nori903ca252010-10-01 14:51:40 +0530773}
774
Murali Karicheriaae71472012-12-11 16:20:39 -0500775#if defined(CONFIG_OF)
776static const struct of_device_id davinci_spi_of_match[] = {
777 {
Manjunathappa, Prakash804413f2013-04-03 19:39:06 +0530778 .compatible = "ti,dm6441-spi",
Murali Karicheriaae71472012-12-11 16:20:39 -0500779 },
780 {
Manjunathappa, Prakash804413f2013-04-03 19:39:06 +0530781 .compatible = "ti,da830-spi",
Murali Karicheriaae71472012-12-11 16:20:39 -0500782 .data = (void *)SPI_VERSION_2,
783 },
784 { },
785};
Manjunathappa, Prakash0d2d0cc2013-02-25 16:14:07 +0530786MODULE_DEVICE_TABLE(of, davinci_spi_of_match);
Murali Karicheriaae71472012-12-11 16:20:39 -0500787
788/**
789 * spi_davinci_get_pdata - Get platform data from DTS binding
790 * @pdev: ptr to platform data
791 * @dspi: ptr to driver data
792 *
793 * Parses and populates pdata in dspi from device tree bindings.
794 *
795 * NOTE: Not all platform data params are supported currently.
796 */
797static int spi_davinci_get_pdata(struct platform_device *pdev,
798 struct davinci_spi *dspi)
799{
800 struct device_node *node = pdev->dev.of_node;
801 struct davinci_spi_platform_data *pdata;
802 unsigned int num_cs, intr_line = 0;
803 const struct of_device_id *match;
804
805 pdata = &dspi->pdata;
806
807 pdata->version = SPI_VERSION_1;
808 match = of_match_device(of_match_ptr(davinci_spi_of_match),
809 &pdev->dev);
810 if (!match)
811 return -ENODEV;
812
813 /* match data has the SPI version number for SPI_VERSION_2 */
814 if (match->data == (void *)SPI_VERSION_2)
815 pdata->version = SPI_VERSION_2;
816
817 /*
818 * default num_cs is 1 and all chipsel are internal to the chip
819 * indicated by chip_sel being NULL. GPIO based CS is not
820 * supported yet in DT bindings.
821 */
822 num_cs = 1;
823 of_property_read_u32(node, "num-cs", &num_cs);
824 pdata->num_chipselect = num_cs;
825 of_property_read_u32(node, "ti,davinci-spi-intr-line", &intr_line);
826 pdata->intr_line = intr_line;
827 return 0;
828}
829#else
830#define davinci_spi_of_match NULL
831static struct davinci_spi_platform_data
832 *spi_davinci_get_pdata(struct platform_device *pdev,
833 struct davinci_spi *dspi)
834{
835 return -ENODEV;
836}
837#endif
838
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000839/**
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000840 * davinci_spi_probe - probe function for SPI Master Controller
841 * @pdev: platform_device structure which contains plateform specific data
Brian Niebuhr035540f2010-10-06 18:32:40 +0530842 *
843 * According to Linux Device Model this function will be invoked by Linux
844 * with platform_device struct which contains the device specific info.
845 * This function will map the SPI controller's memory, register IRQ,
846 * Reset SPI controller and setting its registers to default value.
847 * It will invoke spi_bitbang_start to create work queue so that client driver
848 * can register transfer method to work queue.
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000849 */
Grant Likelyfd4a3192012-12-07 16:57:14 +0000850static int davinci_spi_probe(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000851{
852 struct spi_master *master;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530853 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000854 struct davinci_spi_platform_data *pdata;
855 struct resource *r, *mem;
856 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
857 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000858 int i = 0, ret = 0;
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530859 u32 spipc0;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000860
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000861 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
862 if (master == NULL) {
863 ret = -ENOMEM;
864 goto err;
865 }
866
Jingoo Han24b5a822013-05-23 19:20:40 +0900867 platform_set_drvdata(pdev, master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000868
Sekhar Nori212d4b62010-10-11 10:41:39 +0530869 dspi = spi_master_get_devdata(master);
870 if (dspi == NULL) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000871 ret = -ENOENT;
872 goto free_master;
873 }
874
Jingoo Han8074cf02013-07-30 16:58:59 +0900875 if (dev_get_platdata(&pdev->dev)) {
876 pdata = dev_get_platdata(&pdev->dev);
Murali Karicheriaae71472012-12-11 16:20:39 -0500877 dspi->pdata = *pdata;
878 } else {
879 /* update dspi pdata with that from the DT */
880 ret = spi_davinci_get_pdata(pdev, dspi);
881 if (ret < 0)
882 goto free_master;
883 }
884
885 /* pdata in dspi is now updated and point pdata to that */
886 pdata = &dspi->pdata;
887
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000888 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
889 if (r == NULL) {
890 ret = -ENOENT;
891 goto free_master;
892 }
893
Sekhar Nori212d4b62010-10-11 10:41:39 +0530894 dspi->pbase = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000895
Sekhar Nori0e0eae4d12010-10-08 14:04:22 +0530896 mem = request_mem_region(r->start, resource_size(r), pdev->name);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000897 if (mem == NULL) {
898 ret = -EBUSY;
899 goto free_master;
900 }
901
Sekhar Nori212d4b62010-10-11 10:41:39 +0530902 dspi->base = ioremap(r->start, resource_size(r));
903 if (dspi->base == NULL) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000904 ret = -ENOMEM;
905 goto release_region;
906 }
907
Sekhar Nori212d4b62010-10-11 10:41:39 +0530908 dspi->irq = platform_get_irq(pdev, 0);
909 if (dspi->irq <= 0) {
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530910 ret = -EINVAL;
911 goto unmap_io;
912 }
913
Murali Karicheri32310aa2012-12-21 15:13:26 -0500914 ret = request_threaded_irq(dspi->irq, davinci_spi_irq, dummy_thread_fn,
915 0, dev_name(&pdev->dev), dspi);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530916 if (ret)
917 goto unmap_io;
918
Sekhar Nori212d4b62010-10-11 10:41:39 +0530919 dspi->bitbang.master = spi_master_get(master);
920 if (dspi->bitbang.master == NULL) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000921 ret = -ENODEV;
Brian Niebuhrd3f71412010-09-29 12:31:54 +0530922 goto irq_free;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000923 }
924
Sekhar Nori212d4b62010-10-11 10:41:39 +0530925 dspi->clk = clk_get(&pdev->dev, NULL);
926 if (IS_ERR(dspi->clk)) {
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000927 ret = -ENODEV;
928 goto put_master;
929 }
Murali Karicheriaae71472012-12-11 16:20:39 -0500930 clk_prepare_enable(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000931
Murali Karicheriaae71472012-12-11 16:20:39 -0500932 master->dev.of_node = pdev->dev.of_node;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000933 master->bus_num = pdev->id;
934 master->num_chipselect = pdata->num_chipselect;
Stephen Warren24778be2013-05-21 20:36:35 -0600935 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000936 master->setup = davinci_spi_setup;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000937
Sekhar Nori212d4b62010-10-11 10:41:39 +0530938 dspi->bitbang.chipselect = davinci_spi_chipselect;
939 dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000940
Sekhar Nori212d4b62010-10-11 10:41:39 +0530941 dspi->version = pdata->version;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000942
Sekhar Nori212d4b62010-10-11 10:41:39 +0530943 dspi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
944 if (dspi->version == SPI_VERSION_2)
945 dspi->bitbang.flags |= SPI_READY;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000946
Sekhar Nori903ca252010-10-01 14:51:40 +0530947 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
948 if (r)
949 dma_rx_chan = r->start;
950 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
951 if (r)
952 dma_tx_chan = r->start;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000953
Sekhar Nori212d4b62010-10-11 10:41:39 +0530954 dspi->bitbang.txrx_bufs = davinci_spi_bufs;
Sekhar Nori903ca252010-10-01 14:51:40 +0530955 if (dma_rx_chan != SPI_NO_RESOURCE &&
Michael Williamson2e3e2a52011-02-08 07:59:55 -0500956 dma_tx_chan != SPI_NO_RESOURCE) {
Matt Porter048177c2012-08-22 21:09:36 -0400957 dspi->dma_rx_chnum = dma_rx_chan;
958 dspi->dma_tx_chnum = dma_tx_chan;
Brian Niebuhr96fd8812010-09-27 22:23:23 +0530959
Sekhar Nori212d4b62010-10-11 10:41:39 +0530960 ret = davinci_spi_request_dma(dspi);
Sekhar Nori903ca252010-10-01 14:51:40 +0530961 if (ret)
962 goto free_clk;
963
Brian Niebuhr87467bd2010-10-06 17:03:10 +0530964 dev_info(&pdev->dev, "DMA: supported\n");
965 dev_info(&pdev->dev, "DMA: RX channel: %d, TX channel: %d, "
966 "event queue: %d\n", dma_rx_chan, dma_tx_chan,
Michael Williamson2e3e2a52011-02-08 07:59:55 -0500967 pdata->dma_event_q);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000968 }
969
Sekhar Nori212d4b62010-10-11 10:41:39 +0530970 dspi->get_rx = davinci_spi_rx_buf_u8;
971 dspi->get_tx = davinci_spi_tx_buf_u8;
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000972
Sekhar Nori212d4b62010-10-11 10:41:39 +0530973 init_completion(&dspi->done);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530974
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000975 /* Reset In/OUT SPI module */
Sekhar Nori212d4b62010-10-11 10:41:39 +0530976 iowrite32(0, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000977 udelay(100);
Sekhar Nori212d4b62010-10-11 10:41:39 +0530978 iowrite32(1, dspi->base + SPIGCR0);
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000979
Brian Niebuhrbe884712010-09-03 12:15:28 +0530980 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530981 spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
Sekhar Nori212d4b62010-10-11 10:41:39 +0530982 iowrite32(spipc0, dspi->base + SPIPC0);
Brian Niebuhrf34bd4c2010-09-03 11:56:35 +0530983
Brian Niebuhr23853972010-08-13 10:57:44 +0530984 /* initialize chip selects */
985 if (pdata->chip_sel) {
986 for (i = 0; i < pdata->num_chipselect; i++) {
987 if (pdata->chip_sel[i] != SPI_INTERN_CS)
988 gpio_direction_output(pdata->chip_sel[i], 1);
989 }
990 }
991
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530992 if (pdata->intr_line)
Sekhar Nori212d4b62010-10-11 10:41:39 +0530993 iowrite32(SPI_INTLVL_1, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530994 else
Sekhar Nori212d4b62010-10-11 10:41:39 +0530995 iowrite32(SPI_INTLVL_0, dspi->base + SPILVL);
Brian Niebuhre0d205e2010-09-02 16:52:06 +0530996
Sekhar Nori212d4b62010-10-11 10:41:39 +0530997 iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
Brian Niebuhr843a7132010-08-12 12:49:05 +0530998
Sandeep Paulraj358934a2009-12-16 22:02:18 +0000999 /* master mode default */
Sekhar Nori212d4b62010-10-11 10:41:39 +05301000 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
1001 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1002 set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001003
Sekhar Nori212d4b62010-10-11 10:41:39 +05301004 ret = spi_bitbang_start(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001005 if (ret)
Sekhar Nori903ca252010-10-01 14:51:40 +05301006 goto free_dma;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001007
Sekhar Nori212d4b62010-10-11 10:41:39 +05301008 dev_info(&pdev->dev, "Controller at 0x%p\n", dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001009
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001010 return ret;
1011
Sekhar Nori903ca252010-10-01 14:51:40 +05301012free_dma:
Matt Porter048177c2012-08-22 21:09:36 -04001013 dma_release_channel(dspi->dma_rx);
1014 dma_release_channel(dspi->dma_tx);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001015free_clk:
Murali Karicheriaae71472012-12-11 16:20:39 -05001016 clk_disable_unprepare(dspi->clk);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301017 clk_put(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001018put_master:
1019 spi_master_put(master);
Brian Niebuhre0d205e2010-09-02 16:52:06 +05301020irq_free:
Sekhar Nori212d4b62010-10-11 10:41:39 +05301021 free_irq(dspi->irq, dspi);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001022unmap_io:
Sekhar Nori212d4b62010-10-11 10:41:39 +05301023 iounmap(dspi->base);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001024release_region:
Sekhar Nori212d4b62010-10-11 10:41:39 +05301025 release_mem_region(dspi->pbase, resource_size(r));
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001026free_master:
1027 kfree(master);
1028err:
1029 return ret;
1030}
1031
1032/**
1033 * davinci_spi_remove - remove function for SPI Master Controller
1034 * @pdev: platform_device structure which contains plateform specific data
1035 *
1036 * This function will do the reverse action of davinci_spi_probe function
1037 * It will free the IRQ and SPI controller's memory region.
1038 * It will also call spi_bitbang_stop to destroy the work queue which was
1039 * created by spi_bitbang_start.
1040 */
Grant Likelyfd4a3192012-12-07 16:57:14 +00001041static int davinci_spi_remove(struct platform_device *pdev)
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001042{
Sekhar Nori212d4b62010-10-11 10:41:39 +05301043 struct davinci_spi *dspi;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001044 struct spi_master *master;
Sekhar Nori0e0eae4d12010-10-08 14:04:22 +05301045 struct resource *r;
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001046
Jingoo Han24b5a822013-05-23 19:20:40 +09001047 master = platform_get_drvdata(pdev);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301048 dspi = spi_master_get_devdata(master);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001049
Sekhar Nori212d4b62010-10-11 10:41:39 +05301050 spi_bitbang_stop(&dspi->bitbang);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001051
Murali Karicheriaae71472012-12-11 16:20:39 -05001052 clk_disable_unprepare(dspi->clk);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301053 clk_put(dspi->clk);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001054 spi_master_put(master);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301055 free_irq(dspi->irq, dspi);
1056 iounmap(dspi->base);
Sekhar Nori0e0eae4d12010-10-08 14:04:22 +05301057 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Sekhar Nori212d4b62010-10-11 10:41:39 +05301058 release_mem_region(dspi->pbase, resource_size(r));
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001059
1060 return 0;
1061}
1062
1063static struct platform_driver davinci_spi_driver = {
Brian Niebuhrd8c174c2010-10-06 18:47:16 +05301064 .driver = {
1065 .name = "spi_davinci",
1066 .owner = THIS_MODULE,
Murali Karicheriaae71472012-12-11 16:20:39 -05001067 .of_match_table = davinci_spi_of_match,
Brian Niebuhrd8c174c2010-10-06 18:47:16 +05301068 },
Grant Likely940ab882011-10-05 11:29:49 -06001069 .probe = davinci_spi_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00001070 .remove = davinci_spi_remove,
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001071};
Grant Likely940ab882011-10-05 11:29:49 -06001072module_platform_driver(davinci_spi_driver);
Sandeep Paulraj358934a2009-12-16 22:02:18 +00001073
1074MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1075MODULE_LICENSE("GPL");