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Linus Walleijb43d65f2009-06-09 08:11:42 +01001/*
Linus Walleijb43d65f2009-06-09 08:11:42 +01002 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
3 *
Linus Walleijaeef9912012-09-26 16:48:36 +02004 * Copyright (C) 2008-2012 ST-Ericsson AB
Linus Walleijb43d65f2009-06-09 08:11:42 +01005 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
6 *
7 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 *
9 * Initial version inspired by:
10 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
11 * Initial adoption to PL022 by:
12 * Sachin Verma <sachin.verma@st.com>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 */
24
Linus Walleijb43d65f2009-06-09 08:11:42 +010025#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/device.h>
28#include <linux/ioport.h>
29#include <linux/errno.h>
30#include <linux/interrupt.h>
31#include <linux/spi/spi.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010032#include <linux/delay.h>
33#include <linux/clk.h>
34#include <linux/err.h>
35#include <linux/amba/bus.h>
36#include <linux/amba/pl022.h>
37#include <linux/io.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090038#include <linux/slab.h>
Linus Walleijb1b6b9a2010-09-29 17:31:35 +090039#include <linux/dmaengine.h>
40#include <linux/dma-mapping.h>
41#include <linux/scatterlist.h>
Rabin Vincentbcda6ff2011-06-16 10:14:40 +020042#include <linux/pm_runtime.h>
Roland Stiggef6f46de2012-08-22 15:49:17 +020043#include <linux/gpio.h>
Roland Stigge6d3952a2012-08-22 15:49:18 +020044#include <linux/of_gpio.h>
Patrice Chotard4f5e1b32012-09-19 14:23:46 +020045#include <linux/pinctrl/consumer.h>
Linus Walleijb43d65f2009-06-09 08:11:42 +010046
47/*
48 * This macro is used to define some register default values.
49 * reg is masked with mask, the OR:ed with an (again masked)
50 * val shifted sb steps to the left.
51 */
52#define SSP_WRITE_BITS(reg, val, mask, sb) \
53 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
54
55/*
56 * This macro is also used to define some default values.
57 * It will just shift val by sb steps to the left and mask
58 * the result with mask.
59 */
60#define GEN_MASK_BITS(val, mask, sb) \
61 (((val)<<(sb)) & (mask))
62
63#define DRIVE_TX 0
64#define DO_NOT_DRIVE_TX 1
65
66#define DO_NOT_QUEUE_DMA 0
67#define QUEUE_DMA 1
68
69#define RX_TRANSFER 1
70#define TX_TRANSFER 2
71
72/*
73 * Macros to access SSP Registers with their offsets
74 */
75#define SSP_CR0(r) (r + 0x000)
76#define SSP_CR1(r) (r + 0x004)
77#define SSP_DR(r) (r + 0x008)
78#define SSP_SR(r) (r + 0x00C)
79#define SSP_CPSR(r) (r + 0x010)
80#define SSP_IMSC(r) (r + 0x014)
81#define SSP_RIS(r) (r + 0x018)
82#define SSP_MIS(r) (r + 0x01C)
83#define SSP_ICR(r) (r + 0x020)
84#define SSP_DMACR(r) (r + 0x024)
85#define SSP_ITCR(r) (r + 0x080)
86#define SSP_ITIP(r) (r + 0x084)
87#define SSP_ITOP(r) (r + 0x088)
88#define SSP_TDR(r) (r + 0x08C)
89
90#define SSP_PID0(r) (r + 0xFE0)
91#define SSP_PID1(r) (r + 0xFE4)
92#define SSP_PID2(r) (r + 0xFE8)
93#define SSP_PID3(r) (r + 0xFEC)
94
95#define SSP_CID0(r) (r + 0xFF0)
96#define SSP_CID1(r) (r + 0xFF4)
97#define SSP_CID2(r) (r + 0xFF8)
98#define SSP_CID3(r) (r + 0xFFC)
99
100/*
101 * SSP Control Register 0 - SSP_CR0
102 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000103#define SSP_CR0_MASK_DSS (0x0FUL << 0)
104#define SSP_CR0_MASK_FRF (0x3UL << 4)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100105#define SSP_CR0_MASK_SPO (0x1UL << 6)
106#define SSP_CR0_MASK_SPH (0x1UL << 7)
107#define SSP_CR0_MASK_SCR (0xFFUL << 8)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000108
109/*
110 * The ST version of this block moves som bits
111 * in SSP_CR0 and extends it to 32 bits
112 */
113#define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
114#define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
115#define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
116#define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
117
Linus Walleijb43d65f2009-06-09 08:11:42 +0100118/*
119 * SSP Control Register 0 - SSP_CR1
120 */
121#define SSP_CR1_MASK_LBM (0x1UL << 0)
122#define SSP_CR1_MASK_SSE (0x1UL << 1)
123#define SSP_CR1_MASK_MS (0x1UL << 2)
124#define SSP_CR1_MASK_SOD (0x1UL << 3)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100125
126/*
Linus Walleij556f4ae2010-05-05 09:28:15 +0000127 * The ST version of this block adds some bits
128 * in SSP_CR1
Linus Walleijb43d65f2009-06-09 08:11:42 +0100129 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000130#define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
131#define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
132#define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
133#define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
134#define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
Linus Walleij781c7b12010-05-07 08:40:53 +0000135/* This one is only in the PL023 variant */
136#define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100137
138/*
139 * SSP Status Register - SSP_SR
140 */
141#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
142#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
143#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000144#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100145#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
146
147/*
148 * SSP Clock Prescale Register - SSP_CPSR
149 */
150#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
151
152/*
153 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
154 */
155#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
156#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
157#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
158#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
159
160/*
161 * SSP Raw Interrupt Status Register - SSP_RIS
162 */
163/* Receive Overrun Raw Interrupt status */
164#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
165/* Receive Timeout Raw Interrupt status */
166#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
167/* Receive FIFO Raw Interrupt status */
168#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
169/* Transmit FIFO Raw Interrupt status */
170#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
171
172/*
173 * SSP Masked Interrupt Status Register - SSP_MIS
174 */
175/* Receive Overrun Masked Interrupt status */
176#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
177/* Receive Timeout Masked Interrupt status */
178#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
179/* Receive FIFO Masked Interrupt status */
180#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
181/* Transmit FIFO Masked Interrupt status */
182#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
183
184/*
185 * SSP Interrupt Clear Register - SSP_ICR
186 */
187/* Receive Overrun Raw Clear Interrupt bit */
188#define SSP_ICR_MASK_RORIC (0x1UL << 0)
189/* Receive Timeout Clear Interrupt bit */
190#define SSP_ICR_MASK_RTIC (0x1UL << 1)
191
192/*
193 * SSP DMA Control Register - SSP_DMACR
194 */
195/* Receive DMA Enable bit */
196#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
197/* Transmit DMA Enable bit */
198#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
199
200/*
201 * SSP Integration Test control Register - SSP_ITCR
202 */
203#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
204#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
205
206/*
207 * SSP Integration Test Input Register - SSP_ITIP
208 */
209#define ITIP_MASK_SSPRXD (0x1UL << 0)
210#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
211#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
212#define ITIP_MASK_RXDMAC (0x1UL << 3)
213#define ITIP_MASK_TXDMAC (0x1UL << 4)
214#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
215
216/*
217 * SSP Integration Test output Register - SSP_ITOP
218 */
219#define ITOP_MASK_SSPTXD (0x1UL << 0)
220#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
221#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
222#define ITOP_MASK_SSPOEn (0x1UL << 3)
223#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
224#define ITOP_MASK_RORINTR (0x1UL << 5)
225#define ITOP_MASK_RTINTR (0x1UL << 6)
226#define ITOP_MASK_RXINTR (0x1UL << 7)
227#define ITOP_MASK_TXINTR (0x1UL << 8)
228#define ITOP_MASK_INTR (0x1UL << 9)
229#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
230#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
231#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
232#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
233
234/*
235 * SSP Test Data Register - SSP_TDR
236 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000237#define TDR_MASK_TESTDATA (0xFFFFFFFF)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100238
239/*
240 * Message State
241 * we use the spi_message.state (void *) pointer to
242 * hold a single state value, that's why all this
243 * (void *) casting is done here.
244 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000245#define STATE_START ((void *) 0)
246#define STATE_RUNNING ((void *) 1)
247#define STATE_DONE ((void *) 2)
248#define STATE_ERROR ((void *) -1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100249
250/*
Linus Walleijb43d65f2009-06-09 08:11:42 +0100251 * SSP State - Whether Enabled or Disabled
252 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000253#define SSP_DISABLED (0)
254#define SSP_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100255
256/*
257 * SSP DMA State - Whether DMA Enabled or Disabled
258 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000259#define SSP_DMA_DISABLED (0)
260#define SSP_DMA_ENABLED (1)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100261
262/*
263 * SSP Clock Defaults
264 */
Linus Walleij556f4ae2010-05-05 09:28:15 +0000265#define SSP_DEFAULT_CLKRATE 0x2
266#define SSP_DEFAULT_PRESCALE 0x40
Linus Walleijb43d65f2009-06-09 08:11:42 +0100267
268/*
269 * SSP Clock Parameter ranges
270 */
271#define CPSDVR_MIN 0x02
272#define CPSDVR_MAX 0xFE
273#define SCR_MIN 0x00
274#define SCR_MAX 0xFF
275
276/*
277 * SSP Interrupt related Macros
278 */
279#define DEFAULT_SSP_REG_IMSC 0x0UL
280#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
281#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
282
283#define CLEAR_ALL_INTERRUPTS 0x3
284
Magnus Templinga18c2662011-05-19 18:05:34 +0200285#define SPI_POLLING_TIMEOUT 1000
286
Linus Walleijb43d65f2009-06-09 08:11:42 +0100287/*
288 * The type of reading going on on this chip
289 */
290enum ssp_reading {
291 READING_NULL,
292 READING_U8,
293 READING_U16,
294 READING_U32
295};
296
297/**
298 * The type of writing going on on this chip
299 */
300enum ssp_writing {
301 WRITING_NULL,
302 WRITING_U8,
303 WRITING_U16,
304 WRITING_U32
305};
306
307/**
308 * struct vendor_data - vendor-specific config parameters
309 * for PL022 derivates
310 * @fifodepth: depth of FIFOs (both)
311 * @max_bpw: maximum number of bits per word
312 * @unidir: supports unidirection transfers
Linus Walleij556f4ae2010-05-05 09:28:15 +0000313 * @extended_cr: 32 bit wide control register 0 with extra
314 * features and extra features in CR1 as found in the ST variants
Linus Walleij781c7b12010-05-07 08:40:53 +0000315 * @pl023: supports a subset of the ST extensions called "PL023"
Linus Walleijb43d65f2009-06-09 08:11:42 +0100316 */
317struct vendor_data {
318 int fifodepth;
319 int max_bpw;
320 bool unidir;
Linus Walleij556f4ae2010-05-05 09:28:15 +0000321 bool extended_cr;
Linus Walleij781c7b12010-05-07 08:40:53 +0000322 bool pl023;
Philippe Langlais06fb01f2011-03-23 11:05:16 +0100323 bool loopback;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100324};
325
326/**
327 * struct pl022 - This is the private SSP driver data structure
328 * @adev: AMBA device model hookup
Linus Walleij12e8b322011-02-08 13:03:55 +0100329 * @vendor: vendor data for the IP block
330 * @phybase: the physical memory where the SSP device resides
331 * @virtbase: the virtual memory where the SSP is mapped
332 * @clk: outgoing clock "SPICLK" for the SPI bus
Linus Walleijb43d65f2009-06-09 08:11:42 +0100333 * @master: SPI framework hookup
334 * @master_info: controller-specific data from machine setup
Chris Blair14af60b2012-02-02 13:59:34 +0100335 * @kworker: thread struct for message pump
336 * @kworker_task: pointer to task for message pump kworker thread
337 * @pump_messages: work struct for scheduling work to the message pump
Linus Walleij12e8b322011-02-08 13:03:55 +0100338 * @queue_lock: spinlock to syncronise access to message queue
339 * @queue: message queue
Chris Blair14af60b2012-02-02 13:59:34 +0100340 * @busy: message pump is busy
341 * @running: message pump is running
Linus Walleijb43d65f2009-06-09 08:11:42 +0100342 * @pump_transfers: Tasklet used in Interrupt Transfer mode
343 * @cur_msg: Pointer to current spi_message being processed
344 * @cur_transfer: Pointer to current spi_transfer
345 * @cur_chip: pointer to current clients chip(assigned from controller_state)
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530346 * @next_msg_cs_active: the next message in the queue has been examined
347 * and it was found that it uses the same chip select as the previous
348 * message, so we left it active after the previous transfer, and it's
349 * active already.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100350 * @tx: current position in TX buffer to be read
351 * @tx_end: end position in TX buffer to be read
352 * @rx: current position in RX buffer to be written
353 * @rx_end: end position in RX buffer to be written
Linus Walleij12e8b322011-02-08 13:03:55 +0100354 * @read: the type of read currently going on
355 * @write: the type of write currently going on
356 * @exp_fifo_level: expected FIFO level
357 * @dma_rx_channel: optional channel for RX DMA
358 * @dma_tx_channel: optional channel for TX DMA
359 * @sgt_rx: scattertable for the RX transfer
360 * @sgt_tx: scattertable for the TX transfer
361 * @dummypage: a dummy page used for driving data on the bus with DMA
Roland Stiggef6f46de2012-08-22 15:49:17 +0200362 * @cur_cs: current chip select (gpio)
363 * @chipselects: list of chipselects (gpios)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100364 */
365struct pl022 {
366 struct amba_device *adev;
367 struct vendor_data *vendor;
368 resource_size_t phybase;
369 void __iomem *virtbase;
370 struct clk *clk;
371 struct spi_master *master;
372 struct pl022_ssp_controller *master_info;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100373 /* Message per-transfer pump */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100374 struct tasklet_struct pump_transfers;
375 struct spi_message *cur_msg;
376 struct spi_transfer *cur_transfer;
377 struct chip_data *cur_chip;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530378 bool next_msg_cs_active;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100379 void *tx;
380 void *tx_end;
381 void *rx;
382 void *rx_end;
383 enum ssp_reading read;
384 enum ssp_writing write;
Linus Walleijfc054752010-01-22 13:53:30 +0100385 u32 exp_fifo_level;
Linus Walleij083be3f2011-06-16 10:14:28 +0200386 enum ssp_rx_level_trig rx_lev_trig;
387 enum ssp_tx_level_trig tx_lev_trig;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900388 /* DMA settings */
389#ifdef CONFIG_DMA_ENGINE
390 struct dma_chan *dma_rx_channel;
391 struct dma_chan *dma_tx_channel;
392 struct sg_table sgt_rx;
393 struct sg_table sgt_tx;
394 char *dummypage;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100395 bool dma_running;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900396#endif
Roland Stiggef6f46de2012-08-22 15:49:17 +0200397 int cur_cs;
398 int *chipselects;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100399};
400
401/**
402 * struct chip_data - To maintain runtime state of SSP for each client chip
Linus Walleij556f4ae2010-05-05 09:28:15 +0000403 * @cr0: Value of control register CR0 of SSP - on later ST variants this
404 * register is 32 bits wide rather than just 16
Linus Walleijb43d65f2009-06-09 08:11:42 +0100405 * @cr1: Value of control register CR1 of SSP
406 * @dmacr: Value of DMA control Register of SSP
407 * @cpsr: Value of Clock prescale register
408 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
409 * @enable_dma: Whether to enable DMA or not
Linus Walleijb43d65f2009-06-09 08:11:42 +0100410 * @read: function ptr to be used to read when doing xfer for this chip
Linus Walleij12e8b322011-02-08 13:03:55 +0100411 * @write: function ptr to be used to write when doing xfer for this chip
Linus Walleijb43d65f2009-06-09 08:11:42 +0100412 * @cs_control: chip select callback provided by chip
413 * @xfer_type: polling/interrupt/DMA
414 *
415 * Runtime state of the SSP controller, maintained per chip,
416 * This would be set according to the current message that would be served
417 */
418struct chip_data {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000419 u32 cr0;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100420 u16 cr1;
421 u16 dmacr;
422 u16 cpsr;
423 u8 n_bytes;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900424 bool enable_dma;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100425 enum ssp_reading read;
426 enum ssp_writing write;
427 void (*cs_control) (u32 command);
428 int xfer_type;
429};
430
431/**
432 * null_cs_control - Dummy chip select function
433 * @command: select/delect the chip
434 *
435 * If no chip select function is provided by client this is used as dummy
436 * chip select
437 */
438static void null_cs_control(u32 command)
439{
440 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
441}
442
Roland Stiggef6f46de2012-08-22 15:49:17 +0200443static void pl022_cs_control(struct pl022 *pl022, u32 command)
444{
445 if (gpio_is_valid(pl022->cur_cs))
446 gpio_set_value(pl022->cur_cs, command);
447 else
448 pl022->cur_chip->cs_control(command);
449}
450
Linus Walleijb43d65f2009-06-09 08:11:42 +0100451/**
452 * giveback - current spi_message is over, schedule next message and call
453 * callback of this message. Assumes that caller already
454 * set message->status; dma and pio irqs are blocked
455 * @pl022: SSP driver private data structure
456 */
457static void giveback(struct pl022 *pl022)
458{
459 struct spi_transfer *last_transfer;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530460 pl022->next_msg_cs_active = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100461
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530462 last_transfer = list_entry(pl022->cur_msg->transfers.prev,
Linus Walleijb43d65f2009-06-09 08:11:42 +0100463 struct spi_transfer,
464 transfer_list);
465
466 /* Delay if requested before any change in chip select */
467 if (last_transfer->delay_usecs)
468 /*
469 * FIXME: This runs in interrupt context.
470 * Is this really smart?
471 */
472 udelay(last_transfer->delay_usecs);
473
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530474 if (!last_transfer->cs_change) {
Linus Walleijb43d65f2009-06-09 08:11:42 +0100475 struct spi_message *next_msg;
476
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530477 /*
478 * cs_change was not set. We can keep the chip select
479 * enabled if there is message in the queue and it is
480 * for the same spi device.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100481 *
482 * We cannot postpone this until pump_messages, because
483 * after calling msg->complete (below) the driver that
484 * sent the current message could be unloaded, which
485 * could invalidate the cs_control() callback...
486 */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100487 /* get a pointer to the next message, if any */
Linus Walleijffbbdd212012-02-22 10:05:38 +0100488 next_msg = spi_get_next_queued_message(pl022->master);
Linus Walleijb43d65f2009-06-09 08:11:42 +0100489
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530490 /*
491 * see if the next and current messages point
492 * to the same spi device.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100493 */
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530494 if (next_msg && next_msg->spi != pl022->cur_msg->spi)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100495 next_msg = NULL;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530496 if (!next_msg || pl022->cur_msg->state == STATE_ERROR)
Roland Stiggef6f46de2012-08-22 15:49:17 +0200497 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530498 else
499 pl022->next_msg_cs_active = true;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100500
Linus Walleijb43d65f2009-06-09 08:11:42 +0100501 }
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530502
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +0530503 pl022->cur_msg = NULL;
504 pl022->cur_transfer = NULL;
505 pl022->cur_chip = NULL;
Linus Walleijffbbdd212012-02-22 10:05:38 +0100506 spi_finalize_current_message(pl022->master);
Virupax Sadashivpetimathfd316942012-06-12 15:10:58 +0200507
508 /* disable the SPI/SSP operation */
509 writew((readw(SSP_CR1(pl022->virtbase)) &
510 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
511
Linus Walleijb43d65f2009-06-09 08:11:42 +0100512}
513
514/**
515 * flush - flush the FIFO to reach a clean state
516 * @pl022: SSP driver private data structure
517 */
518static int flush(struct pl022 *pl022)
519{
520 unsigned long limit = loops_per_jiffy << 1;
521
522 dev_dbg(&pl022->adev->dev, "flush\n");
523 do {
524 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
525 readw(SSP_DR(pl022->virtbase));
526 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
Linus Walleijfc054752010-01-22 13:53:30 +0100527
528 pl022->exp_fifo_level = 0;
529
Linus Walleijb43d65f2009-06-09 08:11:42 +0100530 return limit;
531}
532
533/**
534 * restore_state - Load configuration of current chip
535 * @pl022: SSP driver private data structure
536 */
537static void restore_state(struct pl022 *pl022)
538{
539 struct chip_data *chip = pl022->cur_chip;
540
Linus Walleij556f4ae2010-05-05 09:28:15 +0000541 if (pl022->vendor->extended_cr)
542 writel(chip->cr0, SSP_CR0(pl022->virtbase));
543 else
544 writew(chip->cr0, SSP_CR0(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +0100545 writew(chip->cr1, SSP_CR1(pl022->virtbase));
546 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
547 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
548 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
549 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
550}
551
Linus Walleijb43d65f2009-06-09 08:11:42 +0100552/*
553 * Default SSP Register Values
554 */
555#define DEFAULT_SSP_REG_CR0 ( \
556 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000557 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100558 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
Linus Walleijee2b8052009-08-15 15:12:05 +0100559 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000560 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
561)
562
563/* ST versions have slightly different bit layout */
564#define DEFAULT_SSP_REG_CR0_ST ( \
565 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
566 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
567 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
568 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
569 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
570 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
571 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100572)
573
Linus Walleij781c7b12010-05-07 08:40:53 +0000574/* The PL023 version is slightly different again */
575#define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
576 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
577 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
578 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
579 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
580)
581
Linus Walleijb43d65f2009-06-09 08:11:42 +0100582#define DEFAULT_SSP_REG_CR1 ( \
583 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
584 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
585 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000586 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100587)
588
Linus Walleij556f4ae2010-05-05 09:28:15 +0000589/* ST versions extend this register to use all 16 bits */
590#define DEFAULT_SSP_REG_CR1_ST ( \
591 DEFAULT_SSP_REG_CR1 | \
592 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
593 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
594 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
595 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
596 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
597)
598
Linus Walleij781c7b12010-05-07 08:40:53 +0000599/*
600 * The PL023 variant has further differences: no loopback mode, no microwire
601 * support, and a new clock feedback delay setting.
602 */
603#define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
604 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
605 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
606 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
607 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
608 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
609 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
610 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
611 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
612)
Linus Walleij556f4ae2010-05-05 09:28:15 +0000613
Linus Walleijb43d65f2009-06-09 08:11:42 +0100614#define DEFAULT_SSP_REG_CPSR ( \
Linus Walleij556f4ae2010-05-05 09:28:15 +0000615 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
Linus Walleijb43d65f2009-06-09 08:11:42 +0100616)
617
618#define DEFAULT_SSP_REG_DMACR (\
619 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
620 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
621)
622
Linus Walleij781c7b12010-05-07 08:40:53 +0000623/**
624 * load_ssp_default_config - Load default configuration for SSP
625 * @pl022: SSP driver private data structure
626 */
Linus Walleijb43d65f2009-06-09 08:11:42 +0100627static void load_ssp_default_config(struct pl022 *pl022)
628{
Linus Walleij781c7b12010-05-07 08:40:53 +0000629 if (pl022->vendor->pl023) {
630 writel(DEFAULT_SSP_REG_CR0_ST_PL023, SSP_CR0(pl022->virtbase));
631 writew(DEFAULT_SSP_REG_CR1_ST_PL023, SSP_CR1(pl022->virtbase));
632 } else if (pl022->vendor->extended_cr) {
Linus Walleij556f4ae2010-05-05 09:28:15 +0000633 writel(DEFAULT_SSP_REG_CR0_ST, SSP_CR0(pl022->virtbase));
634 writew(DEFAULT_SSP_REG_CR1_ST, SSP_CR1(pl022->virtbase));
635 } else {
636 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
637 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
638 }
Linus Walleijb43d65f2009-06-09 08:11:42 +0100639 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
640 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
641 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
642 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
643}
644
645/**
646 * This will write to TX and read from RX according to the parameters
647 * set in pl022.
648 */
649static void readwriter(struct pl022 *pl022)
650{
651
652 /*
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300653 * The FIFO depth is different between primecell variants.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100654 * I believe filling in too much in the FIFO might cause
655 * errons in 8bit wide transfers on ARM variants (just 8 words
656 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
657 *
Linus Walleijfc054752010-01-22 13:53:30 +0100658 * To prevent this issue, the TX FIFO is only filled to the
659 * unused RX FIFO fill length, regardless of what the TX
660 * FIFO status flag indicates.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100661 */
662 dev_dbg(&pl022->adev->dev,
663 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
664 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
665
666 /* Read as much as you can */
667 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
668 && (pl022->rx < pl022->rx_end)) {
669 switch (pl022->read) {
670 case READING_NULL:
671 readw(SSP_DR(pl022->virtbase));
672 break;
673 case READING_U8:
674 *(u8 *) (pl022->rx) =
675 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
676 break;
677 case READING_U16:
678 *(u16 *) (pl022->rx) =
679 (u16) readw(SSP_DR(pl022->virtbase));
680 break;
681 case READING_U32:
682 *(u32 *) (pl022->rx) =
683 readl(SSP_DR(pl022->virtbase));
684 break;
685 }
686 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100687 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100688 }
689 /*
Linus Walleijfc054752010-01-22 13:53:30 +0100690 * Write as much as possible up to the RX FIFO size
Linus Walleijb43d65f2009-06-09 08:11:42 +0100691 */
Linus Walleijfc054752010-01-22 13:53:30 +0100692 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
Linus Walleijb43d65f2009-06-09 08:11:42 +0100693 && (pl022->tx < pl022->tx_end)) {
694 switch (pl022->write) {
695 case WRITING_NULL:
696 writew(0x0, SSP_DR(pl022->virtbase));
697 break;
698 case WRITING_U8:
699 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
700 break;
701 case WRITING_U16:
702 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
703 break;
704 case WRITING_U32:
705 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
706 break;
707 }
708 pl022->tx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100709 pl022->exp_fifo_level++;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100710 /*
711 * This inner reader takes care of things appearing in the RX
712 * FIFO as we're transmitting. This will happen a lot since the
713 * clock starts running when you put things into the TX FIFO,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300714 * and then things are continuously clocked into the RX FIFO.
Linus Walleijb43d65f2009-06-09 08:11:42 +0100715 */
716 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
717 && (pl022->rx < pl022->rx_end)) {
718 switch (pl022->read) {
719 case READING_NULL:
720 readw(SSP_DR(pl022->virtbase));
721 break;
722 case READING_U8:
723 *(u8 *) (pl022->rx) =
724 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
725 break;
726 case READING_U16:
727 *(u16 *) (pl022->rx) =
728 (u16) readw(SSP_DR(pl022->virtbase));
729 break;
730 case READING_U32:
731 *(u32 *) (pl022->rx) =
732 readl(SSP_DR(pl022->virtbase));
733 break;
734 }
735 pl022->rx += (pl022->cur_chip->n_bytes);
Linus Walleijfc054752010-01-22 13:53:30 +0100736 pl022->exp_fifo_level--;
Linus Walleijb43d65f2009-06-09 08:11:42 +0100737 }
738 }
739 /*
740 * When we exit here the TX FIFO should be full and the RX FIFO
741 * should be empty
742 */
743}
744
Linus Walleijb43d65f2009-06-09 08:11:42 +0100745/**
746 * next_transfer - Move to the Next transfer in the current spi message
747 * @pl022: SSP driver private data structure
748 *
749 * This function moves though the linked list of spi transfers in the
750 * current spi message and returns with the state of current spi
751 * message i.e whether its last transfer is done(STATE_DONE) or
752 * Next transfer is ready(STATE_RUNNING)
753 */
754static void *next_transfer(struct pl022 *pl022)
755{
756 struct spi_message *msg = pl022->cur_msg;
757 struct spi_transfer *trans = pl022->cur_transfer;
758
759 /* Move to next transfer */
760 if (trans->transfer_list.next != &msg->transfers) {
761 pl022->cur_transfer =
762 list_entry(trans->transfer_list.next,
763 struct spi_transfer, transfer_list);
764 return STATE_RUNNING;
765 }
766 return STATE_DONE;
767}
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900768
769/*
770 * This DMA functionality is only compiled in if we have
771 * access to the generic DMA devices/DMA engine.
772 */
773#ifdef CONFIG_DMA_ENGINE
774static void unmap_free_dma_scatter(struct pl022 *pl022)
775{
776 /* Unmap and free the SG tables */
Linus Walleijb7298892010-12-22 23:13:07 +0100777 dma_unmap_sg(pl022->dma_tx_channel->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900778 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleijb7298892010-12-22 23:13:07 +0100779 dma_unmap_sg(pl022->dma_rx_channel->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900780 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
781 sg_free_table(&pl022->sgt_rx);
782 sg_free_table(&pl022->sgt_tx);
783}
784
785static void dma_callback(void *data)
786{
787 struct pl022 *pl022 = data;
788 struct spi_message *msg = pl022->cur_msg;
789
790 BUG_ON(!pl022->sgt_rx.sgl);
791
792#ifdef VERBOSE_DEBUG
793 /*
794 * Optionally dump out buffers to inspect contents, this is
795 * good if you want to convince yourself that the loopback
796 * read/write contents are the same, when adopting to a new
797 * DMA engine.
798 */
799 {
800 struct scatterlist *sg;
801 unsigned int i;
802
803 dma_sync_sg_for_cpu(&pl022->adev->dev,
804 pl022->sgt_rx.sgl,
805 pl022->sgt_rx.nents,
806 DMA_FROM_DEVICE);
807
808 for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
809 dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
810 print_hex_dump(KERN_ERR, "SPI RX: ",
811 DUMP_PREFIX_OFFSET,
812 16,
813 1,
814 sg_virt(sg),
815 sg_dma_len(sg),
816 1);
817 }
818 for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
819 dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
820 print_hex_dump(KERN_ERR, "SPI TX: ",
821 DUMP_PREFIX_OFFSET,
822 16,
823 1,
824 sg_virt(sg),
825 sg_dma_len(sg),
826 1);
827 }
828 }
829#endif
830
831 unmap_free_dma_scatter(pl022);
832
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300833 /* Update total bytes transferred */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900834 msg->actual_length += pl022->cur_transfer->len;
835 if (pl022->cur_transfer->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +0200836 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900837
838 /* Move to next transfer */
839 msg->state = next_transfer(pl022);
840 tasklet_schedule(&pl022->pump_transfers);
841}
842
843static void setup_dma_scatter(struct pl022 *pl022,
844 void *buffer,
845 unsigned int length,
846 struct sg_table *sgtab)
847{
848 struct scatterlist *sg;
849 int bytesleft = length;
850 void *bufp = buffer;
851 int mapbytes;
852 int i;
853
854 if (buffer) {
855 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
856 /*
857 * If there are less bytes left than what fits
858 * in the current page (plus page alignment offset)
859 * we just feed in this, else we stuff in as much
860 * as we can.
861 */
862 if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
863 mapbytes = bytesleft;
864 else
865 mapbytes = PAGE_SIZE - offset_in_page(bufp);
866 sg_set_page(sg, virt_to_page(bufp),
867 mapbytes, offset_in_page(bufp));
868 bufp += mapbytes;
869 bytesleft -= mapbytes;
870 dev_dbg(&pl022->adev->dev,
871 "set RX/TX target page @ %p, %d bytes, %d left\n",
872 bufp, mapbytes, bytesleft);
873 }
874 } else {
875 /* Map the dummy buffer on every page */
876 for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
877 if (bytesleft < PAGE_SIZE)
878 mapbytes = bytesleft;
879 else
880 mapbytes = PAGE_SIZE;
881 sg_set_page(sg, virt_to_page(pl022->dummypage),
882 mapbytes, 0);
883 bytesleft -= mapbytes;
884 dev_dbg(&pl022->adev->dev,
885 "set RX/TX to dummy page %d bytes, %d left\n",
886 mapbytes, bytesleft);
887
888 }
889 }
890 BUG_ON(bytesleft);
891}
892
893/**
894 * configure_dma - configures the channels for the next transfer
895 * @pl022: SSP driver's private data structure
896 */
897static int configure_dma(struct pl022 *pl022)
898{
899 struct dma_slave_config rx_conf = {
900 .src_addr = SSP_DR(pl022->phybase),
Vinod Koula485df42011-10-14 10:47:38 +0530901 .direction = DMA_DEV_TO_MEM,
Viresh Kumar258aea72012-02-01 16:12:19 +0530902 .device_fc = false,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900903 };
904 struct dma_slave_config tx_conf = {
905 .dst_addr = SSP_DR(pl022->phybase),
Vinod Koula485df42011-10-14 10:47:38 +0530906 .direction = DMA_MEM_TO_DEV,
Viresh Kumar258aea72012-02-01 16:12:19 +0530907 .device_fc = false,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900908 };
909 unsigned int pages;
910 int ret;
Linus Walleij082086f2010-12-22 23:13:37 +0100911 int rx_sglen, tx_sglen;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900912 struct dma_chan *rxchan = pl022->dma_rx_channel;
913 struct dma_chan *txchan = pl022->dma_tx_channel;
914 struct dma_async_tx_descriptor *rxdesc;
915 struct dma_async_tx_descriptor *txdesc;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900916
917 /* Check that the channels are available */
918 if (!rxchan || !txchan)
919 return -ENODEV;
920
Linus Walleij083be3f2011-06-16 10:14:28 +0200921 /*
922 * If supplied, the DMA burstsize should equal the FIFO trigger level.
923 * Notice that the DMA engine uses one-to-one mapping. Since we can
924 * not trigger on 2 elements this needs explicit mapping rather than
925 * calculation.
926 */
927 switch (pl022->rx_lev_trig) {
928 case SSP_RX_1_OR_MORE_ELEM:
929 rx_conf.src_maxburst = 1;
930 break;
931 case SSP_RX_4_OR_MORE_ELEM:
932 rx_conf.src_maxburst = 4;
933 break;
934 case SSP_RX_8_OR_MORE_ELEM:
935 rx_conf.src_maxburst = 8;
936 break;
937 case SSP_RX_16_OR_MORE_ELEM:
938 rx_conf.src_maxburst = 16;
939 break;
940 case SSP_RX_32_OR_MORE_ELEM:
941 rx_conf.src_maxburst = 32;
942 break;
943 default:
944 rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1;
945 break;
946 }
947
948 switch (pl022->tx_lev_trig) {
949 case SSP_TX_1_OR_MORE_EMPTY_LOC:
950 tx_conf.dst_maxburst = 1;
951 break;
952 case SSP_TX_4_OR_MORE_EMPTY_LOC:
953 tx_conf.dst_maxburst = 4;
954 break;
955 case SSP_TX_8_OR_MORE_EMPTY_LOC:
956 tx_conf.dst_maxburst = 8;
957 break;
958 case SSP_TX_16_OR_MORE_EMPTY_LOC:
959 tx_conf.dst_maxburst = 16;
960 break;
961 case SSP_TX_32_OR_MORE_EMPTY_LOC:
962 tx_conf.dst_maxburst = 32;
963 break;
964 default:
965 tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1;
966 break;
967 }
968
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900969 switch (pl022->read) {
970 case READING_NULL:
971 /* Use the same as for writing */
972 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
973 break;
974 case READING_U8:
975 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
976 break;
977 case READING_U16:
978 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
979 break;
980 case READING_U32:
981 rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
982 break;
983 }
984
985 switch (pl022->write) {
986 case WRITING_NULL:
987 /* Use the same as for reading */
988 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_UNDEFINED;
989 break;
990 case WRITING_U8:
991 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
992 break;
993 case WRITING_U16:
994 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
995 break;
996 case WRITING_U32:
Joe Perchesbc3f67a2010-11-14 19:04:47 -0800997 tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +0900998 break;
999 }
1000
1001 /* SPI pecularity: we need to read and write the same width */
1002 if (rx_conf.src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1003 rx_conf.src_addr_width = tx_conf.dst_addr_width;
1004 if (tx_conf.dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
1005 tx_conf.dst_addr_width = rx_conf.src_addr_width;
1006 BUG_ON(rx_conf.src_addr_width != tx_conf.dst_addr_width);
1007
Linus Walleijecd442f2011-02-08 13:03:12 +01001008 dmaengine_slave_config(rxchan, &rx_conf);
1009 dmaengine_slave_config(txchan, &tx_conf);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001010
1011 /* Create sglists for the transfers */
Viresh Kumarb1815652011-08-10 17:12:11 +05301012 pages = DIV_ROUND_UP(pl022->cur_transfer->len, PAGE_SIZE);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001013 dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
1014
Viresh Kumar538a18d2011-08-10 14:20:55 +05301015 ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_ATOMIC);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001016 if (ret)
1017 goto err_alloc_rx_sg;
1018
Viresh Kumar538a18d2011-08-10 14:20:55 +05301019 ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_ATOMIC);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001020 if (ret)
1021 goto err_alloc_tx_sg;
1022
1023 /* Fill in the scatterlists for the RX+TX buffers */
1024 setup_dma_scatter(pl022, pl022->rx,
1025 pl022->cur_transfer->len, &pl022->sgt_rx);
1026 setup_dma_scatter(pl022, pl022->tx,
1027 pl022->cur_transfer->len, &pl022->sgt_tx);
1028
1029 /* Map DMA buffers */
Linus Walleij082086f2010-12-22 23:13:37 +01001030 rx_sglen = dma_map_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001031 pl022->sgt_rx.nents, DMA_FROM_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +01001032 if (!rx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001033 goto err_rx_sgmap;
1034
Linus Walleij082086f2010-12-22 23:13:37 +01001035 tx_sglen = dma_map_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001036 pl022->sgt_tx.nents, DMA_TO_DEVICE);
Linus Walleij082086f2010-12-22 23:13:37 +01001037 if (!tx_sglen)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001038 goto err_tx_sgmap;
1039
1040 /* Send both scatterlists */
Alexandre Bounine16052822012-03-08 16:11:18 -05001041 rxdesc = dmaengine_prep_slave_sg(rxchan,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001042 pl022->sgt_rx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001043 rx_sglen,
Vinod Koula485df42011-10-14 10:47:38 +05301044 DMA_DEV_TO_MEM,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001045 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1046 if (!rxdesc)
1047 goto err_rxdesc;
1048
Alexandre Bounine16052822012-03-08 16:11:18 -05001049 txdesc = dmaengine_prep_slave_sg(txchan,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001050 pl022->sgt_tx.sgl,
Linus Walleij082086f2010-12-22 23:13:37 +01001051 tx_sglen,
Vinod Koula485df42011-10-14 10:47:38 +05301052 DMA_MEM_TO_DEV,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001053 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1054 if (!txdesc)
1055 goto err_txdesc;
1056
1057 /* Put the callback on the RX transfer only, that should finish last */
1058 rxdesc->callback = dma_callback;
1059 rxdesc->callback_param = pl022;
1060
1061 /* Submit and fire RX and TX with TX last so we're ready to read! */
Linus Walleijecd442f2011-02-08 13:03:12 +01001062 dmaengine_submit(rxdesc);
1063 dmaengine_submit(txdesc);
1064 dma_async_issue_pending(rxchan);
1065 dma_async_issue_pending(txchan);
Linus Walleijffbbdd212012-02-22 10:05:38 +01001066 pl022->dma_running = true;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001067
1068 return 0;
1069
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001070err_txdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001071 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001072err_rxdesc:
Linus Walleijecd442f2011-02-08 13:03:12 +01001073 dmaengine_terminate_all(rxchan);
Linus Walleijb7298892010-12-22 23:13:07 +01001074 dma_unmap_sg(txchan->device->dev, pl022->sgt_tx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001075 pl022->sgt_tx.nents, DMA_TO_DEVICE);
1076err_tx_sgmap:
Linus Walleijb7298892010-12-22 23:13:07 +01001077 dma_unmap_sg(rxchan->device->dev, pl022->sgt_rx.sgl,
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001078 pl022->sgt_tx.nents, DMA_FROM_DEVICE);
1079err_rx_sgmap:
1080 sg_free_table(&pl022->sgt_tx);
1081err_alloc_tx_sg:
1082 sg_free_table(&pl022->sgt_rx);
1083err_alloc_rx_sg:
1084 return -ENOMEM;
1085}
1086
Grant Likelyfd4a3192012-12-07 16:57:14 +00001087static int pl022_dma_probe(struct pl022 *pl022)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001088{
1089 dma_cap_mask_t mask;
1090
1091 /* Try to acquire a generic DMA engine slave channel */
1092 dma_cap_zero(mask);
1093 dma_cap_set(DMA_SLAVE, mask);
1094 /*
1095 * We need both RX and TX channels to do DMA, else do none
1096 * of them.
1097 */
1098 pl022->dma_rx_channel = dma_request_channel(mask,
1099 pl022->master_info->dma_filter,
1100 pl022->master_info->dma_rx_param);
1101 if (!pl022->dma_rx_channel) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301102 dev_dbg(&pl022->adev->dev, "no RX DMA channel!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001103 goto err_no_rxchan;
1104 }
1105
1106 pl022->dma_tx_channel = dma_request_channel(mask,
1107 pl022->master_info->dma_filter,
1108 pl022->master_info->dma_tx_param);
1109 if (!pl022->dma_tx_channel) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301110 dev_dbg(&pl022->adev->dev, "no TX DMA channel!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001111 goto err_no_txchan;
1112 }
1113
1114 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1115 if (!pl022->dummypage) {
Viresh Kumar43c64012011-05-16 09:40:10 +05301116 dev_dbg(&pl022->adev->dev, "no DMA dummypage!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001117 goto err_no_dummypage;
1118 }
1119
1120 dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
1121 dma_chan_name(pl022->dma_rx_channel),
1122 dma_chan_name(pl022->dma_tx_channel));
1123
1124 return 0;
1125
1126err_no_dummypage:
1127 dma_release_channel(pl022->dma_tx_channel);
1128err_no_txchan:
1129 dma_release_channel(pl022->dma_rx_channel);
1130 pl022->dma_rx_channel = NULL;
1131err_no_rxchan:
Viresh Kumar43c64012011-05-16 09:40:10 +05301132 dev_err(&pl022->adev->dev,
1133 "Failed to work in dma mode, work without dma!\n");
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001134 return -ENODEV;
1135}
1136
Arnd Bergmanndc715452013-01-28 16:24:37 +00001137static int pl022_dma_autoprobe(struct pl022 *pl022)
1138{
1139 struct device *dev = &pl022->adev->dev;
1140
1141 /* automatically configure DMA channels from platform, normally using DT */
1142 pl022->dma_rx_channel = dma_request_slave_channel(dev, "rx");
1143 if (!pl022->dma_rx_channel)
1144 goto err_no_rxchan;
1145
1146 pl022->dma_tx_channel = dma_request_slave_channel(dev, "tx");
1147 if (!pl022->dma_tx_channel)
1148 goto err_no_txchan;
1149
1150 pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
1151 if (!pl022->dummypage)
1152 goto err_no_dummypage;
1153
1154 return 0;
1155
1156err_no_dummypage:
1157 dma_release_channel(pl022->dma_tx_channel);
1158 pl022->dma_tx_channel = NULL;
1159err_no_txchan:
1160 dma_release_channel(pl022->dma_rx_channel);
1161 pl022->dma_rx_channel = NULL;
1162err_no_rxchan:
1163 return -ENODEV;
1164}
1165
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001166static void terminate_dma(struct pl022 *pl022)
1167{
1168 struct dma_chan *rxchan = pl022->dma_rx_channel;
1169 struct dma_chan *txchan = pl022->dma_tx_channel;
1170
Linus Walleijecd442f2011-02-08 13:03:12 +01001171 dmaengine_terminate_all(rxchan);
1172 dmaengine_terminate_all(txchan);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001173 unmap_free_dma_scatter(pl022);
Linus Walleijffbbdd212012-02-22 10:05:38 +01001174 pl022->dma_running = false;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001175}
1176
1177static void pl022_dma_remove(struct pl022 *pl022)
1178{
Linus Walleijffbbdd212012-02-22 10:05:38 +01001179 if (pl022->dma_running)
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001180 terminate_dma(pl022);
1181 if (pl022->dma_tx_channel)
1182 dma_release_channel(pl022->dma_tx_channel);
1183 if (pl022->dma_rx_channel)
1184 dma_release_channel(pl022->dma_rx_channel);
1185 kfree(pl022->dummypage);
1186}
1187
1188#else
1189static inline int configure_dma(struct pl022 *pl022)
1190{
1191 return -ENODEV;
1192}
1193
Arnd Bergmanndc715452013-01-28 16:24:37 +00001194static inline int pl022_dma_autoprobe(struct pl022 *pl022)
1195{
1196 return 0;
1197}
1198
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001199static inline int pl022_dma_probe(struct pl022 *pl022)
1200{
1201 return 0;
1202}
1203
1204static inline void pl022_dma_remove(struct pl022 *pl022)
1205{
1206}
1207#endif
1208
Linus Walleijb43d65f2009-06-09 08:11:42 +01001209/**
1210 * pl022_interrupt_handler - Interrupt handler for SSP controller
1211 *
1212 * This function handles interrupts generated for an interrupt based transfer.
1213 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1214 * current message's state as STATE_ERROR and schedule the tasklet
1215 * pump_transfers which will do the postprocessing of the current message by
1216 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1217 * more data, and writes data in TX FIFO till it is not full. If we complete
1218 * the transfer we move to the next transfer and schedule the tasklet.
1219 */
1220static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
1221{
1222 struct pl022 *pl022 = dev_id;
1223 struct spi_message *msg = pl022->cur_msg;
1224 u16 irq_status = 0;
1225 u16 flag = 0;
1226
1227 if (unlikely(!msg)) {
1228 dev_err(&pl022->adev->dev,
1229 "bad message state in interrupt handler");
1230 /* Never fail */
1231 return IRQ_HANDLED;
1232 }
1233
1234 /* Read the Interrupt Status Register */
1235 irq_status = readw(SSP_MIS(pl022->virtbase));
1236
1237 if (unlikely(!irq_status))
1238 return IRQ_NONE;
1239
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001240 /*
1241 * This handles the FIFO interrupts, the timeout
1242 * interrupts are flatly ignored, they cannot be
1243 * trusted.
1244 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001245 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
1246 /*
1247 * Overrun interrupt - bail out since our Data has been
1248 * corrupted
1249 */
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001250 dev_err(&pl022->adev->dev, "FIFO overrun\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001251 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
1252 dev_err(&pl022->adev->dev,
1253 "RXFIFO is full\n");
1254 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
1255 dev_err(&pl022->adev->dev,
1256 "TXFIFO is full\n");
1257
1258 /*
1259 * Disable and clear interrupts, disable SSP,
1260 * mark message with bad status so it can be
1261 * retried.
1262 */
1263 writew(DISABLE_ALL_INTERRUPTS,
1264 SSP_IMSC(pl022->virtbase));
1265 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1266 writew((readw(SSP_CR1(pl022->virtbase)) &
1267 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
1268 msg->state = STATE_ERROR;
1269
1270 /* Schedule message queue handler */
1271 tasklet_schedule(&pl022->pump_transfers);
1272 return IRQ_HANDLED;
1273 }
1274
1275 readwriter(pl022);
1276
1277 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
1278 flag = 1;
Chris Blair172289d2011-06-04 07:57:47 +01001279 /* Disable Transmit interrupt, enable receive interrupt */
1280 writew((readw(SSP_IMSC(pl022->virtbase)) &
1281 ~SSP_IMSC_MASK_TXIM) | SSP_IMSC_MASK_RXIM,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001282 SSP_IMSC(pl022->virtbase));
1283 }
1284
1285 /*
1286 * Since all transactions must write as much as shall be read,
1287 * we can conclude the entire transaction once RX is complete.
1288 * At this point, all TX will always be finished.
1289 */
1290 if (pl022->rx >= pl022->rx_end) {
1291 writew(DISABLE_ALL_INTERRUPTS,
1292 SSP_IMSC(pl022->virtbase));
1293 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
1294 if (unlikely(pl022->rx > pl022->rx_end)) {
1295 dev_warn(&pl022->adev->dev, "read %u surplus "
1296 "bytes (did you request an odd "
1297 "number of bytes on a 16bit bus?)\n",
1298 (u32) (pl022->rx - pl022->rx_end));
1299 }
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001300 /* Update total bytes transferred */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001301 msg->actual_length += pl022->cur_transfer->len;
1302 if (pl022->cur_transfer->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001303 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001304 /* Move to next transfer */
1305 msg->state = next_transfer(pl022);
1306 tasklet_schedule(&pl022->pump_transfers);
1307 return IRQ_HANDLED;
1308 }
1309
1310 return IRQ_HANDLED;
1311}
1312
1313/**
1314 * This sets up the pointers to memory for the next message to
1315 * send out on the SPI bus.
1316 */
1317static int set_up_next_transfer(struct pl022 *pl022,
1318 struct spi_transfer *transfer)
1319{
1320 int residue;
1321
1322 /* Sanity check the message for this bus width */
1323 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
1324 if (unlikely(residue != 0)) {
1325 dev_err(&pl022->adev->dev,
1326 "message of %u bytes to transmit but the current "
1327 "chip bus has a data width of %u bytes!\n",
1328 pl022->cur_transfer->len,
1329 pl022->cur_chip->n_bytes);
1330 dev_err(&pl022->adev->dev, "skipping this message\n");
1331 return -EIO;
1332 }
1333 pl022->tx = (void *)transfer->tx_buf;
1334 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
1335 pl022->rx = (void *)transfer->rx_buf;
1336 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
1337 pl022->write =
1338 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
1339 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
1340 return 0;
1341}
1342
1343/**
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001344 * pump_transfers - Tasklet function which schedules next transfer
1345 * when running in interrupt or DMA transfer mode.
Linus Walleijb43d65f2009-06-09 08:11:42 +01001346 * @data: SSP driver private data structure
1347 *
1348 */
1349static void pump_transfers(unsigned long data)
1350{
1351 struct pl022 *pl022 = (struct pl022 *) data;
1352 struct spi_message *message = NULL;
1353 struct spi_transfer *transfer = NULL;
1354 struct spi_transfer *previous = NULL;
1355
1356 /* Get current state information */
1357 message = pl022->cur_msg;
1358 transfer = pl022->cur_transfer;
1359
1360 /* Handle for abort */
1361 if (message->state == STATE_ERROR) {
1362 message->status = -EIO;
1363 giveback(pl022);
1364 return;
1365 }
1366
1367 /* Handle end of message */
1368 if (message->state == STATE_DONE) {
1369 message->status = 0;
1370 giveback(pl022);
1371 return;
1372 }
1373
1374 /* Delay if requested at end of transfer before CS change */
1375 if (message->state == STATE_RUNNING) {
1376 previous = list_entry(transfer->transfer_list.prev,
1377 struct spi_transfer,
1378 transfer_list);
1379 if (previous->delay_usecs)
1380 /*
1381 * FIXME: This runs in interrupt context.
1382 * Is this really smart?
1383 */
1384 udelay(previous->delay_usecs);
1385
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301386 /* Reselect chip select only if cs_change was requested */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001387 if (previous->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001388 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001389 } else {
1390 /* STATE_START */
1391 message->state = STATE_RUNNING;
1392 }
1393
1394 if (set_up_next_transfer(pl022, transfer)) {
1395 message->state = STATE_ERROR;
1396 message->status = -EIO;
1397 giveback(pl022);
1398 return;
1399 }
1400 /* Flush the FIFOs and let's go! */
1401 flush(pl022);
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001402
1403 if (pl022->cur_chip->enable_dma) {
1404 if (configure_dma(pl022)) {
1405 dev_dbg(&pl022->adev->dev,
1406 "configuration of DMA failed, fall back to interrupt mode\n");
1407 goto err_config_dma;
1408 }
1409 return;
1410 }
1411
1412err_config_dma:
Chris Blair172289d2011-06-04 07:57:47 +01001413 /* enable all interrupts except RX */
1414 writew(ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM, SSP_IMSC(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001415}
1416
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001417static void do_interrupt_dma_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001418{
Chris Blair172289d2011-06-04 07:57:47 +01001419 /*
1420 * Default is to enable all interrupts except RX -
1421 * this will be enabled once TX is complete
1422 */
1423 u32 irqflags = ENABLE_ALL_INTERRUPTS & ~SSP_IMSC_MASK_RXIM;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001424
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301425 /* Enable target chip, if not already active */
1426 if (!pl022->next_msg_cs_active)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001427 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301428
Linus Walleijb43d65f2009-06-09 08:11:42 +01001429 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
1430 /* Error path */
1431 pl022->cur_msg->state = STATE_ERROR;
1432 pl022->cur_msg->status = -EIO;
1433 giveback(pl022);
1434 return;
1435 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001436 /* If we're using DMA, set up DMA here */
1437 if (pl022->cur_chip->enable_dma) {
1438 /* Configure DMA transfer */
1439 if (configure_dma(pl022)) {
1440 dev_dbg(&pl022->adev->dev,
1441 "configuration of DMA failed, fall back to interrupt mode\n");
1442 goto err_config_dma;
1443 }
1444 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1445 irqflags = DISABLE_ALL_INTERRUPTS;
1446 }
1447err_config_dma:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001448 /* Enable SSP, turn on interrupts */
1449 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1450 SSP_CR1(pl022->virtbase));
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001451 writew(irqflags, SSP_IMSC(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001452}
1453
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001454static void do_polling_transfer(struct pl022 *pl022)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001455{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001456 struct spi_message *message = NULL;
1457 struct spi_transfer *transfer = NULL;
1458 struct spi_transfer *previous = NULL;
1459 struct chip_data *chip;
Magnus Templinga18c2662011-05-19 18:05:34 +02001460 unsigned long time, timeout;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001461
1462 chip = pl022->cur_chip;
1463 message = pl022->cur_msg;
1464
1465 while (message->state != STATE_DONE) {
1466 /* Handle for abort */
1467 if (message->state == STATE_ERROR)
1468 break;
1469 transfer = pl022->cur_transfer;
1470
1471 /* Delay if requested at end of transfer */
1472 if (message->state == STATE_RUNNING) {
1473 previous =
1474 list_entry(transfer->transfer_list.prev,
1475 struct spi_transfer, transfer_list);
1476 if (previous->delay_usecs)
1477 udelay(previous->delay_usecs);
1478 if (previous->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001479 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001480 } else {
1481 /* STATE_START */
1482 message->state = STATE_RUNNING;
Virupax Sadashivpetimath8b8d7192011-11-10 12:43:24 +05301483 if (!pl022->next_msg_cs_active)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001484 pl022_cs_control(pl022, SSP_CHIP_SELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001485 }
1486
1487 /* Configuration Changing Per Transfer */
1488 if (set_up_next_transfer(pl022, transfer)) {
1489 /* Error path */
1490 message->state = STATE_ERROR;
1491 break;
1492 }
1493 /* Flush FIFOs and enable SSP */
1494 flush(pl022);
1495 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1496 SSP_CR1(pl022->virtbase));
1497
Linus Walleij556f4ae2010-05-05 09:28:15 +00001498 dev_dbg(&pl022->adev->dev, "polling transfer ongoing ...\n");
Magnus Templinga18c2662011-05-19 18:05:34 +02001499
1500 timeout = jiffies + msecs_to_jiffies(SPI_POLLING_TIMEOUT);
1501 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end) {
1502 time = jiffies;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001503 readwriter(pl022);
Magnus Templinga18c2662011-05-19 18:05:34 +02001504 if (time_after(time, timeout)) {
1505 dev_warn(&pl022->adev->dev,
1506 "%s: timeout!\n", __func__);
1507 message->state = STATE_ERROR;
1508 goto out;
1509 }
Linus Walleij521999b2011-05-19 20:01:25 +02001510 cpu_relax();
Magnus Templinga18c2662011-05-19 18:05:34 +02001511 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001512
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001513 /* Update total byte transferred */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001514 message->actual_length += pl022->cur_transfer->len;
1515 if (pl022->cur_transfer->cs_change)
Roland Stiggef6f46de2012-08-22 15:49:17 +02001516 pl022_cs_control(pl022, SSP_CHIP_DESELECT);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001517 /* Move to next transfer */
1518 message->state = next_transfer(pl022);
1519 }
Magnus Templinga18c2662011-05-19 18:05:34 +02001520out:
Linus Walleijb43d65f2009-06-09 08:11:42 +01001521 /* Handle end of message */
1522 if (message->state == STATE_DONE)
1523 message->status = 0;
1524 else
1525 message->status = -EIO;
1526
1527 giveback(pl022);
1528 return;
1529}
1530
Linus Walleijffbbdd212012-02-22 10:05:38 +01001531static int pl022_transfer_one_message(struct spi_master *master,
1532 struct spi_message *msg)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001533{
Linus Walleijffbbdd212012-02-22 10:05:38 +01001534 struct pl022 *pl022 = spi_master_get_devdata(master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001535
1536 /* Initial message state */
Linus Walleijffbbdd212012-02-22 10:05:38 +01001537 pl022->cur_msg = msg;
1538 msg->state = STATE_START;
1539
1540 pl022->cur_transfer = list_entry(msg->transfers.next,
1541 struct spi_transfer, transfer_list);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001542
1543 /* Setup the SPI using the per chip configuration */
Linus Walleijffbbdd212012-02-22 10:05:38 +01001544 pl022->cur_chip = spi_get_ctldata(msg->spi);
Roland Stiggef6f46de2012-08-22 15:49:17 +02001545 pl022->cur_cs = pl022->chipselects[msg->spi->chip_select];
Chris Blaird4b6af22011-11-04 07:43:41 +00001546
Linus Walleijb43d65f2009-06-09 08:11:42 +01001547 restore_state(pl022);
1548 flush(pl022);
1549
1550 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1551 do_polling_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001552 else
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001553 do_interrupt_dma_transfer(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001554
1555 return 0;
1556}
1557
Linus Walleijffbbdd212012-02-22 10:05:38 +01001558static int pl022_unprepare_transfer_hardware(struct spi_master *master)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001559{
Linus Walleijffbbdd212012-02-22 10:05:38 +01001560 struct pl022 *pl022 = spi_master_get_devdata(master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001561
Linus Walleijffbbdd212012-02-22 10:05:38 +01001562 /* nothing more to do - disable spi/ssp and power off */
1563 writew((readw(SSP_CR1(pl022->virtbase)) &
1564 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
Linus Walleijb43d65f2009-06-09 08:11:42 +01001565
Linus Walleijb43d65f2009-06-09 08:11:42 +01001566 return 0;
1567}
1568
1569static int verify_controller_parameters(struct pl022 *pl022,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001570 struct pl022_config_chip const *chip_info)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001571{
Linus Walleijb43d65f2009-06-09 08:11:42 +01001572 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1573 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001574 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001575 "interface is configured incorrectly\n");
1576 return -EINVAL;
1577 }
1578 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1579 (!pl022->vendor->unidir)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001580 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001581 "unidirectional mode not supported in this "
1582 "hardware version\n");
1583 return -EINVAL;
1584 }
1585 if ((chip_info->hierarchy != SSP_MASTER)
1586 && (chip_info->hierarchy != SSP_SLAVE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001587 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001588 "hierarchy is configured incorrectly\n");
1589 return -EINVAL;
1590 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001591 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1592 && (chip_info->com_mode != DMA_TRANSFER)
1593 && (chip_info->com_mode != POLLING_TRANSFER)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001594 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001595 "Communication mode is configured incorrectly\n");
1596 return -EINVAL;
1597 }
Linus Walleij78b2b912011-06-16 10:14:46 +02001598 switch (chip_info->rx_lev_trig) {
1599 case SSP_RX_1_OR_MORE_ELEM:
1600 case SSP_RX_4_OR_MORE_ELEM:
1601 case SSP_RX_8_OR_MORE_ELEM:
1602 /* These are always OK, all variants can handle this */
1603 break;
1604 case SSP_RX_16_OR_MORE_ELEM:
1605 if (pl022->vendor->fifodepth < 16) {
1606 dev_err(&pl022->adev->dev,
1607 "RX FIFO Trigger Level is configured incorrectly\n");
1608 return -EINVAL;
1609 }
1610 break;
1611 case SSP_RX_32_OR_MORE_ELEM:
1612 if (pl022->vendor->fifodepth < 32) {
1613 dev_err(&pl022->adev->dev,
1614 "RX FIFO Trigger Level is configured incorrectly\n");
1615 return -EINVAL;
1616 }
1617 break;
1618 default:
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001619 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001620 "RX FIFO Trigger Level is configured incorrectly\n");
1621 return -EINVAL;
Linus Walleij78b2b912011-06-16 10:14:46 +02001622 break;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001623 }
Linus Walleij78b2b912011-06-16 10:14:46 +02001624 switch (chip_info->tx_lev_trig) {
1625 case SSP_TX_1_OR_MORE_EMPTY_LOC:
1626 case SSP_TX_4_OR_MORE_EMPTY_LOC:
1627 case SSP_TX_8_OR_MORE_EMPTY_LOC:
1628 /* These are always OK, all variants can handle this */
1629 break;
1630 case SSP_TX_16_OR_MORE_EMPTY_LOC:
1631 if (pl022->vendor->fifodepth < 16) {
1632 dev_err(&pl022->adev->dev,
1633 "TX FIFO Trigger Level is configured incorrectly\n");
1634 return -EINVAL;
1635 }
1636 break;
1637 case SSP_TX_32_OR_MORE_EMPTY_LOC:
1638 if (pl022->vendor->fifodepth < 32) {
1639 dev_err(&pl022->adev->dev,
1640 "TX FIFO Trigger Level is configured incorrectly\n");
1641 return -EINVAL;
1642 }
1643 break;
1644 default:
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001645 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001646 "TX FIFO Trigger Level is configured incorrectly\n");
1647 return -EINVAL;
Linus Walleij78b2b912011-06-16 10:14:46 +02001648 break;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001649 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001650 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1651 if ((chip_info->ctrl_len < SSP_BITS_4)
1652 || (chip_info->ctrl_len > SSP_BITS_32)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001653 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001654 "CTRL LEN is configured incorrectly\n");
1655 return -EINVAL;
1656 }
1657 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1658 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001659 dev_err(&pl022->adev->dev,
Linus Walleijb43d65f2009-06-09 08:11:42 +01001660 "Wait State is configured incorrectly\n");
1661 return -EINVAL;
1662 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001663 /* Half duplex is only available in the ST Micro version */
1664 if (pl022->vendor->extended_cr) {
1665 if ((chip_info->duplex !=
1666 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1667 && (chip_info->duplex !=
Julia Lawall4a4fd472010-09-29 17:31:30 +09001668 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001669 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001670 "Microwire duplex mode is configured incorrectly\n");
1671 return -EINVAL;
Julia Lawall4a4fd472010-09-29 17:31:30 +09001672 }
Linus Walleij556f4ae2010-05-05 09:28:15 +00001673 } else {
1674 if (chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
Linus Walleij5a1c98b2010-10-01 11:47:32 +02001675 dev_err(&pl022->adev->dev,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001676 "Microwire half duplex mode requested,"
1677 " but this is only available in the"
1678 " ST version of PL022\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001679 return -EINVAL;
1680 }
1681 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01001682 return 0;
1683}
1684
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301685static inline u32 spi_rate(u32 rate, u16 cpsdvsr, u16 scr)
1686{
1687 return rate / (cpsdvsr * (1 + scr));
1688}
1689
1690static int calculate_effective_freq(struct pl022 *pl022, int freq, struct
1691 ssp_clock_params * clk_freq)
Linus Walleijb43d65f2009-06-09 08:11:42 +01001692{
1693 /* Lets calculate the frequency parameters */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301694 u16 cpsdvsr = CPSDVR_MIN, scr = SCR_MIN;
1695 u32 rate, max_tclk, min_tclk, best_freq = 0, best_cpsdvsr = 0,
1696 best_scr = 0, tmp, found = 0;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001697
1698 rate = clk_get_rate(pl022->clk);
1699 /* cpsdvscr = 2 & scr 0 */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301700 max_tclk = spi_rate(rate, CPSDVR_MIN, SCR_MIN);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001701 /* cpsdvsr = 254 & scr = 255 */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301702 min_tclk = spi_rate(rate, CPSDVR_MAX, SCR_MAX);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001703
Viresh Kumarea505bc2012-04-19 11:48:15 +05301704 if (freq > max_tclk)
1705 dev_warn(&pl022->adev->dev,
1706 "Max speed that can be programmed is %d Hz, you requested %d\n",
1707 max_tclk, freq);
1708
1709 if (freq < min_tclk) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001710 dev_err(&pl022->adev->dev,
Viresh Kumarea505bc2012-04-19 11:48:15 +05301711 "Requested frequency: %d Hz is less than minimum possible %d Hz\n",
1712 freq, min_tclk);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001713 return -EINVAL;
1714 }
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301715
1716 /*
1717 * best_freq will give closest possible available rate (<= requested
1718 * freq) for all values of scr & cpsdvsr.
1719 */
1720 while ((cpsdvsr <= CPSDVR_MAX) && !found) {
1721 while (scr <= SCR_MAX) {
1722 tmp = spi_rate(rate, cpsdvsr, scr);
1723
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301724 if (tmp > freq) {
1725 /* we need lower freq */
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301726 scr++;
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301727 continue;
1728 }
1729
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301730 /*
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301731 * If found exact value, mark found and break.
1732 * If found more closer value, update and break.
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301733 */
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301734 if (tmp > best_freq) {
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301735 best_freq = tmp;
1736 best_cpsdvsr = cpsdvsr;
1737 best_scr = scr;
1738
1739 if (tmp == freq)
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301740 found = 1;
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301741 }
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301742 /*
1743 * increased scr will give lower rates, which are not
1744 * required
1745 */
1746 break;
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301747 }
1748 cpsdvsr += 2;
1749 scr = SCR_MIN;
1750 }
1751
Viresh Kumar5eb806a2012-04-19 14:44:21 +05301752 WARN(!best_freq, "pl022: Matching cpsdvsr and scr not found for %d Hz rate \n",
1753 freq);
1754
Viresh Kumar0379b2a2011-08-10 14:20:57 +05301755 clk_freq->cpsdvsr = (u8) (best_cpsdvsr & 0xFF);
1756 clk_freq->scr = (u8) (best_scr & 0xFF);
1757 dev_dbg(&pl022->adev->dev,
1758 "SSP Target Frequency is: %u, Effective Frequency is %u\n",
1759 freq, best_freq);
1760 dev_dbg(&pl022->adev->dev, "SSP cpsdvsr = %d, scr = %d\n",
1761 clk_freq->cpsdvsr, clk_freq->scr);
1762
Linus Walleijb43d65f2009-06-09 08:11:42 +01001763 return 0;
1764}
1765
Linus Walleijf9d629c2010-10-01 13:33:13 +02001766/*
1767 * A piece of default chip info unless the platform
1768 * supplies it.
1769 */
1770static const struct pl022_config_chip pl022_default_chip_info = {
1771 .com_mode = POLLING_TRANSFER,
1772 .iface = SSP_INTERFACE_MOTOROLA_SPI,
1773 .hierarchy = SSP_SLAVE,
1774 .slave_tx_disable = DO_NOT_DRIVE_TX,
1775 .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
1776 .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
1777 .ctrl_len = SSP_BITS_8,
1778 .wait_state = SSP_MWIRE_WAIT_ZERO,
1779 .duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
1780 .cs_control = null_cs_control,
1781};
1782
Linus Walleijb43d65f2009-06-09 08:11:42 +01001783/**
Linus Walleijb43d65f2009-06-09 08:11:42 +01001784 * pl022_setup - setup function registered to SPI master framework
1785 * @spi: spi device which is requesting setup
1786 *
1787 * This function is registered to the SPI framework for this SPI master
1788 * controller. If it is the first time when setup is called by this device,
1789 * this function will initialize the runtime state for this chip and save
1790 * the same in the device structure. Else it will update the runtime info
1791 * with the updated chip info. Nothing is really being written to the
1792 * controller hardware here, that is not done until the actual transfer
1793 * commence.
1794 */
Linus Walleijb43d65f2009-06-09 08:11:42 +01001795static int pl022_setup(struct spi_device *spi)
1796{
Linus Walleijf9d629c2010-10-01 13:33:13 +02001797 struct pl022_config_chip const *chip_info;
Roland Stigge6d3952a2012-08-22 15:49:18 +02001798 struct pl022_config_chip chip_info_dt;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001799 struct chip_data *chip;
Jonas Aabergc4a47842011-02-28 16:42:41 +01001800 struct ssp_clock_params clk_freq = { .cpsdvsr = 0, .scr = 0};
Linus Walleijb43d65f2009-06-09 08:11:42 +01001801 int status = 0;
1802 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001803 unsigned int bits = spi->bits_per_word;
1804 u32 tmp;
Roland Stigge6d3952a2012-08-22 15:49:18 +02001805 struct device_node *np = spi->dev.of_node;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001806
1807 if (!spi->max_speed_hz)
1808 return -EINVAL;
1809
1810 /* Get controller_state if one is supplied */
1811 chip = spi_get_ctldata(spi);
1812
1813 if (chip == NULL) {
1814 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1815 if (!chip) {
1816 dev_err(&spi->dev,
1817 "cannot allocate controller state\n");
1818 return -ENOMEM;
1819 }
1820 dev_dbg(&spi->dev,
1821 "allocated memory for controller's runtime state\n");
1822 }
1823
1824 /* Get controller data if one is supplied */
1825 chip_info = spi->controller_data;
1826
1827 if (chip_info == NULL) {
Roland Stigge6d3952a2012-08-22 15:49:18 +02001828 if (np) {
1829 chip_info_dt = pl022_default_chip_info;
1830
1831 chip_info_dt.hierarchy = SSP_MASTER;
1832 of_property_read_u32(np, "pl022,interface",
1833 &chip_info_dt.iface);
1834 of_property_read_u32(np, "pl022,com-mode",
1835 &chip_info_dt.com_mode);
1836 of_property_read_u32(np, "pl022,rx-level-trig",
1837 &chip_info_dt.rx_lev_trig);
1838 of_property_read_u32(np, "pl022,tx-level-trig",
1839 &chip_info_dt.tx_lev_trig);
1840 of_property_read_u32(np, "pl022,ctrl-len",
1841 &chip_info_dt.ctrl_len);
1842 of_property_read_u32(np, "pl022,wait-state",
1843 &chip_info_dt.wait_state);
1844 of_property_read_u32(np, "pl022,duplex",
1845 &chip_info_dt.duplex);
1846
1847 chip_info = &chip_info_dt;
1848 } else {
1849 chip_info = &pl022_default_chip_info;
1850 /* spi_board_info.controller_data not is supplied */
1851 dev_dbg(&spi->dev,
1852 "using default controller_data settings\n");
1853 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001854 } else
Linus Walleijb43d65f2009-06-09 08:11:42 +01001855 dev_dbg(&spi->dev,
1856 "using user supplied controller_data settings\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001857
1858 /*
1859 * We can override with custom divisors, else we use the board
1860 * frequency setting
1861 */
1862 if ((0 == chip_info->clk_freq.cpsdvsr)
1863 && (0 == chip_info->clk_freq.scr)) {
1864 status = calculate_effective_freq(pl022,
1865 spi->max_speed_hz,
Linus Walleijf9d629c2010-10-01 13:33:13 +02001866 &clk_freq);
Linus Walleijb43d65f2009-06-09 08:11:42 +01001867 if (status < 0)
1868 goto err_config_params;
1869 } else {
Linus Walleijf9d629c2010-10-01 13:33:13 +02001870 memcpy(&clk_freq, &chip_info->clk_freq, sizeof(clk_freq));
1871 if ((clk_freq.cpsdvsr % 2) != 0)
1872 clk_freq.cpsdvsr =
1873 clk_freq.cpsdvsr - 1;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001874 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001875 if ((clk_freq.cpsdvsr < CPSDVR_MIN)
1876 || (clk_freq.cpsdvsr > CPSDVR_MAX)) {
Virupax Sadashivpetimathe3f88ae2011-06-13 16:23:46 +05301877 status = -EINVAL;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001878 dev_err(&spi->dev,
1879 "cpsdvsr is configured incorrectly\n");
1880 goto err_config_params;
1881 }
1882
Linus Walleijb43d65f2009-06-09 08:11:42 +01001883 status = verify_controller_parameters(pl022, chip_info);
1884 if (status) {
1885 dev_err(&spi->dev, "controller data is incorrect");
1886 goto err_config_params;
1887 }
Linus Walleijf9d629c2010-10-01 13:33:13 +02001888
Linus Walleij083be3f2011-06-16 10:14:28 +02001889 pl022->rx_lev_trig = chip_info->rx_lev_trig;
1890 pl022->tx_lev_trig = chip_info->tx_lev_trig;
1891
Linus Walleijb43d65f2009-06-09 08:11:42 +01001892 /* Now set controller state based on controller data */
1893 chip->xfer_type = chip_info->com_mode;
Linus Walleijf9d629c2010-10-01 13:33:13 +02001894 if (!chip_info->cs_control) {
1895 chip->cs_control = null_cs_control;
Roland Stiggef6f46de2012-08-22 15:49:17 +02001896 if (!gpio_is_valid(pl022->chipselects[spi->chip_select]))
1897 dev_warn(&spi->dev,
1898 "invalid chip select\n");
Linus Walleijf9d629c2010-10-01 13:33:13 +02001899 } else
1900 chip->cs_control = chip_info->cs_control;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001901
Vinit Shenoyeb798c62012-04-17 12:40:13 +05301902 /* Check bits per word with vendor specific range */
1903 if ((bits <= 3) || (bits > pl022->vendor->max_bpw)) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001904 status = -ENOTSUPP;
Vinit Shenoyeb798c62012-04-17 12:40:13 +05301905 dev_err(&spi->dev, "illegal data size for this controller!\n");
1906 dev_err(&spi->dev, "This controller can only handle 4 <= n <= %d bit words\n",
1907 pl022->vendor->max_bpw);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001908 goto err_config_params;
1909 } else if (bits <= 8) {
1910 dev_dbg(&spi->dev, "4 <= n <=8 bits per word\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001911 chip->n_bytes = 1;
1912 chip->read = READING_U8;
1913 chip->write = WRITING_U8;
Kevin Wellsbde435a2010-09-16 06:18:50 -07001914 } else if (bits <= 16) {
Linus Walleijb43d65f2009-06-09 08:11:42 +01001915 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1916 chip->n_bytes = 2;
1917 chip->read = READING_U16;
1918 chip->write = WRITING_U16;
1919 } else {
Vinit Shenoyeb798c62012-04-17 12:40:13 +05301920 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1921 chip->n_bytes = 4;
1922 chip->read = READING_U32;
1923 chip->write = WRITING_U32;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001924 }
1925
1926 /* Now Initialize all register settings required for this chip */
1927 chip->cr0 = 0;
1928 chip->cr1 = 0;
1929 chip->dmacr = 0;
1930 chip->cpsr = 0;
1931 if ((chip_info->com_mode == DMA_TRANSFER)
1932 && ((pl022->master_info)->enable_dma)) {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001933 chip->enable_dma = true;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001934 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01001935 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1936 SSP_DMACR_MASK_RXDMAE, 0);
1937 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1938 SSP_DMACR_MASK_TXDMAE, 1);
1939 } else {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09001940 chip->enable_dma = false;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001941 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1942 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1943 SSP_DMACR_MASK_RXDMAE, 0);
1944 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1945 SSP_DMACR_MASK_TXDMAE, 1);
1946 }
1947
Linus Walleijf9d629c2010-10-01 13:33:13 +02001948 chip->cpsr = clk_freq.cpsdvsr;
Linus Walleijb43d65f2009-06-09 08:11:42 +01001949
Linus Walleij556f4ae2010-05-05 09:28:15 +00001950 /* Special setup for the ST micro extended control registers */
1951 if (pl022->vendor->extended_cr) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001952 u32 etx;
1953
Linus Walleij781c7b12010-05-07 08:40:53 +00001954 if (pl022->vendor->pl023) {
1955 /* These bits are only in the PL023 */
1956 SSP_WRITE_BITS(chip->cr1, chip_info->clkdelay,
1957 SSP_CR1_MASK_FBCLKDEL_ST, 13);
1958 } else {
1959 /* These bits are in the PL022 but not PL023 */
1960 SSP_WRITE_BITS(chip->cr0, chip_info->duplex,
1961 SSP_CR0_MASK_HALFDUP_ST, 5);
1962 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len,
1963 SSP_CR0_MASK_CSS_ST, 16);
1964 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1965 SSP_CR0_MASK_FRF_ST, 21);
1966 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state,
1967 SSP_CR1_MASK_MWAIT_ST, 6);
1968 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001969 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001970 SSP_CR0_MASK_DSS_ST, 0);
Kevin Wellsbde435a2010-09-16 06:18:50 -07001971
1972 if (spi->mode & SPI_LSB_FIRST) {
1973 tmp = SSP_RX_LSB;
1974 etx = SSP_TX_LSB;
1975 } else {
1976 tmp = SSP_RX_MSB;
1977 etx = SSP_TX_MSB;
1978 }
1979 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_RENDN_ST, 4);
1980 SSP_WRITE_BITS(chip->cr1, etx, SSP_CR1_MASK_TENDN_ST, 5);
Linus Walleij556f4ae2010-05-05 09:28:15 +00001981 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig,
1982 SSP_CR1_MASK_RXIFLSEL_ST, 7);
1983 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig,
1984 SSP_CR1_MASK_TXIFLSEL_ST, 10);
1985 } else {
Kevin Wellsbde435a2010-09-16 06:18:50 -07001986 SSP_WRITE_BITS(chip->cr0, bits - 1,
Linus Walleij556f4ae2010-05-05 09:28:15 +00001987 SSP_CR0_MASK_DSS, 0);
1988 SSP_WRITE_BITS(chip->cr0, chip_info->iface,
1989 SSP_CR0_MASK_FRF, 4);
1990 }
Kevin Wellsbde435a2010-09-16 06:18:50 -07001991
Linus Walleij556f4ae2010-05-05 09:28:15 +00001992 /* Stuff that is common for all versions */
Kevin Wellsbde435a2010-09-16 06:18:50 -07001993 if (spi->mode & SPI_CPOL)
1994 tmp = SSP_CLK_POL_IDLE_HIGH;
1995 else
1996 tmp = SSP_CLK_POL_IDLE_LOW;
1997 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPO, 6);
1998
1999 if (spi->mode & SPI_CPHA)
2000 tmp = SSP_CLK_SECOND_EDGE;
2001 else
2002 tmp = SSP_CLK_FIRST_EDGE;
2003 SSP_WRITE_BITS(chip->cr0, tmp, SSP_CR0_MASK_SPH, 7);
2004
Linus Walleijf9d629c2010-10-01 13:33:13 +02002005 SSP_WRITE_BITS(chip->cr0, clk_freq.scr, SSP_CR0_MASK_SCR, 8);
Linus Walleij781c7b12010-05-07 08:40:53 +00002006 /* Loopback is available on all versions except PL023 */
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002007 if (pl022->vendor->loopback) {
Kevin Wellsbde435a2010-09-16 06:18:50 -07002008 if (spi->mode & SPI_LOOP)
2009 tmp = LOOPBACK_ENABLED;
2010 else
2011 tmp = LOOPBACK_DISABLED;
2012 SSP_WRITE_BITS(chip->cr1, tmp, SSP_CR1_MASK_LBM, 0);
2013 }
Linus Walleijb43d65f2009-06-09 08:11:42 +01002014 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
2015 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
Viresh Kumarf1e45f82011-08-10 14:20:54 +05302016 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD,
2017 3);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002018
2019 /* Save controller_state */
2020 spi_set_ctldata(spi, chip);
2021 return status;
2022 err_config_params:
Kevin Wellsbde435a2010-09-16 06:18:50 -07002023 spi_set_ctldata(spi, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002024 kfree(chip);
2025 return status;
2026}
2027
2028/**
2029 * pl022_cleanup - cleanup function registered to SPI master framework
2030 * @spi: spi device which is requesting cleanup
2031 *
2032 * This function is registered to the SPI framework for this SPI master
2033 * controller. It will free the runtime state of chip.
2034 */
2035static void pl022_cleanup(struct spi_device *spi)
2036{
2037 struct chip_data *chip = spi_get_ctldata(spi);
2038
2039 spi_set_ctldata(spi, NULL);
2040 kfree(chip);
2041}
2042
Roland Stigge39a6ac12012-09-18 15:53:53 +02002043static struct pl022_ssp_controller *
2044pl022_platform_data_dt_get(struct device *dev)
2045{
2046 struct device_node *np = dev->of_node;
2047 struct pl022_ssp_controller *pd;
2048 u32 tmp;
2049
2050 if (!np) {
2051 dev_err(dev, "no dt node defined\n");
2052 return NULL;
2053 }
2054
2055 pd = devm_kzalloc(dev, sizeof(struct pl022_ssp_controller), GFP_KERNEL);
2056 if (!pd) {
2057 dev_err(dev, "cannot allocate platform data memory\n");
2058 return NULL;
2059 }
2060
2061 pd->bus_id = -1;
Linus Walleijdbd897b2013-05-23 19:46:40 +02002062 pd->enable_dma = 1;
Roland Stigge39a6ac12012-09-18 15:53:53 +02002063 of_property_read_u32(np, "num-cs", &tmp);
2064 pd->num_chipselect = tmp;
2065 of_property_read_u32(np, "pl022,autosuspend-delay",
2066 &pd->autosuspend_delay);
2067 pd->rt = of_property_read_bool(np, "pl022,rt");
2068
2069 return pd;
2070}
2071
Grant Likelyfd4a3192012-12-07 16:57:14 +00002072static int pl022_probe(struct amba_device *adev, const struct amba_id *id)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002073{
2074 struct device *dev = &adev->dev;
Jingoo Han8074cf02013-07-30 16:58:59 +09002075 struct pl022_ssp_controller *platform_info =
2076 dev_get_platdata(&adev->dev);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002077 struct spi_master *master;
2078 struct pl022 *pl022 = NULL; /*Data for this driver */
Roland Stigge6d3952a2012-08-22 15:49:18 +02002079 struct device_node *np = adev->dev.of_node;
2080 int status = 0, i, num_cs;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002081
2082 dev_info(&adev->dev,
2083 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
Roland Stigge39a6ac12012-09-18 15:53:53 +02002084 if (!platform_info && IS_ENABLED(CONFIG_OF))
2085 platform_info = pl022_platform_data_dt_get(dev);
2086
2087 if (!platform_info) {
2088 dev_err(dev, "probe: no platform data defined\n");
Linus Walleijaeef9912012-09-26 16:48:36 +02002089 return -ENODEV;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002090 }
2091
Roland Stigge6d3952a2012-08-22 15:49:18 +02002092 if (platform_info->num_chipselect) {
2093 num_cs = platform_info->num_chipselect;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002094 } else {
Roland Stigge39a6ac12012-09-18 15:53:53 +02002095 dev_err(dev, "probe: no chip select defined\n");
Linus Walleijaeef9912012-09-26 16:48:36 +02002096 return -ENODEV;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002097 }
2098
Linus Walleijb43d65f2009-06-09 08:11:42 +01002099 /* Allocate master with space for data */
Roland Stiggeb4b84822012-09-03 10:14:29 +02002100 master = spi_alloc_master(dev, sizeof(struct pl022));
Linus Walleijb43d65f2009-06-09 08:11:42 +01002101 if (master == NULL) {
2102 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
Linus Walleijaeef9912012-09-26 16:48:36 +02002103 return -ENOMEM;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002104 }
2105
2106 pl022 = spi_master_get_devdata(master);
2107 pl022->master = master;
2108 pl022->master_info = platform_info;
2109 pl022->adev = adev;
2110 pl022->vendor = id->data;
Roland Stiggeb4b84822012-09-03 10:14:29 +02002111 pl022->chipselects = devm_kzalloc(dev, num_cs * sizeof(int),
2112 GFP_KERNEL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002113
Linus Walleijf1c9cf02013-06-10 16:57:09 +02002114 pinctrl_pm_select_default_state(dev);
Patrice Chotard4f5e1b32012-09-19 14:23:46 +02002115
Linus Walleijb43d65f2009-06-09 08:11:42 +01002116 /*
2117 * Bus Number Which has been Assigned to this SSP controller
2118 * on this board
2119 */
2120 master->bus_num = platform_info->bus_id;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002121 master->num_chipselect = num_cs;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002122 master->cleanup = pl022_cleanup;
2123 master->setup = pl022_setup;
Mark Brown29b6e902013-07-28 15:35:08 +01002124 master->auto_runtime_pm = true;
Linus Walleijffbbdd212012-02-22 10:05:38 +01002125 master->transfer_one_message = pl022_transfer_one_message;
2126 master->unprepare_transfer_hardware = pl022_unprepare_transfer_hardware;
2127 master->rt = platform_info->rt;
Roland Stigge6d3952a2012-08-22 15:49:18 +02002128 master->dev.of_node = dev->of_node;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002129
Roland Stigge6d3952a2012-08-22 15:49:18 +02002130 if (platform_info->num_chipselect && platform_info->chipselects) {
2131 for (i = 0; i < num_cs; i++)
Roland Stiggef6f46de2012-08-22 15:49:17 +02002132 pl022->chipselects[i] = platform_info->chipselects[i];
Roland Stigge6d3952a2012-08-22 15:49:18 +02002133 } else if (IS_ENABLED(CONFIG_OF)) {
2134 for (i = 0; i < num_cs; i++) {
2135 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
2136
2137 if (cs_gpio == -EPROBE_DEFER) {
2138 status = -EPROBE_DEFER;
2139 goto err_no_gpio;
2140 }
2141
2142 pl022->chipselects[i] = cs_gpio;
2143
2144 if (gpio_is_valid(cs_gpio)) {
Linus Walleijaeef9912012-09-26 16:48:36 +02002145 if (devm_gpio_request(dev, cs_gpio, "ssp-pl022"))
Roland Stigge6d3952a2012-08-22 15:49:18 +02002146 dev_err(&adev->dev,
2147 "could not request %d gpio\n",
2148 cs_gpio);
2149 else if (gpio_direction_output(cs_gpio, 1))
2150 dev_err(&adev->dev,
2151 "could set gpio %d as output\n",
2152 cs_gpio);
2153 }
2154 }
2155 }
Roland Stiggef6f46de2012-08-22 15:49:17 +02002156
Kevin Wellsbde435a2010-09-16 06:18:50 -07002157 /*
2158 * Supports mode 0-3, loopback, and active low CS. Transfers are
2159 * always MS bit first on the original pl022.
2160 */
2161 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
2162 if (pl022->vendor->extended_cr)
2163 master->mode_bits |= SPI_LSB_FIRST;
2164
Linus Walleijb43d65f2009-06-09 08:11:42 +01002165 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
2166
2167 status = amba_request_regions(adev, NULL);
2168 if (status)
2169 goto err_no_ioregion;
2170
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002171 pl022->phybase = adev->res.start;
Linus Walleijaeef9912012-09-26 16:48:36 +02002172 pl022->virtbase = devm_ioremap(dev, adev->res.start,
2173 resource_size(&adev->res));
Linus Walleijb43d65f2009-06-09 08:11:42 +01002174 if (pl022->virtbase == NULL) {
2175 status = -ENOMEM;
2176 goto err_no_ioremap;
2177 }
Fabio Estevam7085f402013-08-21 21:35:37 -03002178 printk(KERN_INFO "pl022: mapped registers from %pa to %p\n",
2179 &adev->res.start, pl022->virtbase);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002180
Linus Walleijaeef9912012-09-26 16:48:36 +02002181 pl022->clk = devm_clk_get(&adev->dev, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002182 if (IS_ERR(pl022->clk)) {
2183 status = PTR_ERR(pl022->clk);
2184 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
2185 goto err_no_clk;
2186 }
Russell King7ff6bcf2011-09-22 14:27:11 +01002187
2188 status = clk_prepare(pl022->clk);
2189 if (status) {
2190 dev_err(&adev->dev, "could not prepare SSP/SPI bus clock\n");
2191 goto err_clk_prep;
2192 }
2193
Ulf Hansson71e63e72011-11-04 08:10:09 +01002194 status = clk_enable(pl022->clk);
2195 if (status) {
2196 dev_err(&adev->dev, "could not enable SSP/SPI bus clock\n");
2197 goto err_no_clk_en;
2198 }
2199
Linus Walleijffbbdd212012-02-22 10:05:38 +01002200 /* Initialize transfer pump */
2201 tasklet_init(&pl022->pump_transfers, pump_transfers,
2202 (unsigned long)pl022);
2203
Linus Walleijb43d65f2009-06-09 08:11:42 +01002204 /* Disable SSP */
Linus Walleijb43d65f2009-06-09 08:11:42 +01002205 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
2206 SSP_CR1(pl022->virtbase));
2207 load_ssp_default_config(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002208
Linus Walleijaeef9912012-09-26 16:48:36 +02002209 status = devm_request_irq(dev, adev->irq[0], pl022_interrupt_handler,
2210 0, "pl022", pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002211 if (status < 0) {
2212 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
2213 goto err_no_irq;
2214 }
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002215
Arnd Bergmanndc715452013-01-28 16:24:37 +00002216 /* Get DMA channels, try autoconfiguration first */
2217 status = pl022_dma_autoprobe(pl022);
2218
2219 /* If that failed, use channels from platform_info */
2220 if (status == 0)
2221 platform_info->enable_dma = 1;
2222 else if (platform_info->enable_dma) {
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002223 status = pl022_dma_probe(pl022);
2224 if (status != 0)
Viresh Kumar43c64012011-05-16 09:40:10 +05302225 platform_info->enable_dma = 0;
Linus Walleijb1b6b9a2010-09-29 17:31:35 +09002226 }
2227
Linus Walleijb43d65f2009-06-09 08:11:42 +01002228 /* Register with the SPI framework */
2229 amba_set_drvdata(adev, pl022);
2230 status = spi_register_master(master);
2231 if (status != 0) {
2232 dev_err(&adev->dev,
2233 "probe - problem registering spi master\n");
2234 goto err_spi_register;
2235 }
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002236 dev_dbg(dev, "probe succeeded\n");
Russell King92b97f02011-08-14 09:13:48 +01002237
2238 /* let runtime pm put suspend */
Chris Blair53e4ace2011-11-08 08:54:46 +00002239 if (platform_info->autosuspend_delay > 0) {
2240 dev_info(&adev->dev,
2241 "will use autosuspend for runtime pm, delay %dms\n",
2242 platform_info->autosuspend_delay);
2243 pm_runtime_set_autosuspend_delay(dev,
2244 platform_info->autosuspend_delay);
2245 pm_runtime_use_autosuspend(dev);
Chris Blair53e4ace2011-11-08 08:54:46 +00002246 }
Ulf Hansson0df34992012-10-17 14:27:08 +02002247 pm_runtime_put(dev);
2248
Linus Walleijb43d65f2009-06-09 08:11:42 +01002249 return 0;
2250
2251 err_spi_register:
Viresh Kumar3e3ea712011-08-10 14:20:58 +05302252 if (platform_info->enable_dma)
2253 pl022_dma_remove(pl022);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002254 err_no_irq:
Ulf Hansson71e63e72011-11-04 08:10:09 +01002255 clk_disable(pl022->clk);
2256 err_no_clk_en:
Russell King7ff6bcf2011-09-22 14:27:11 +01002257 clk_unprepare(pl022->clk);
2258 err_clk_prep:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002259 err_no_clk:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002260 err_no_ioremap:
2261 amba_release_regions(adev);
2262 err_no_ioregion:
Roland Stigge6d3952a2012-08-22 15:49:18 +02002263 err_no_gpio:
Linus Walleijb43d65f2009-06-09 08:11:42 +01002264 spi_master_put(master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002265 return status;
2266}
2267
Grant Likelyfd4a3192012-12-07 16:57:14 +00002268static int
Linus Walleijb43d65f2009-06-09 08:11:42 +01002269pl022_remove(struct amba_device *adev)
2270{
2271 struct pl022 *pl022 = amba_get_drvdata(adev);
Linus Walleij50658b62011-08-02 11:29:24 +02002272
Linus Walleijb43d65f2009-06-09 08:11:42 +01002273 if (!pl022)
2274 return 0;
2275
Russell King92b97f02011-08-14 09:13:48 +01002276 /*
2277 * undo pm_runtime_put() in probe. I assume that we're not
2278 * accessing the primecell here.
2279 */
2280 pm_runtime_get_noresume(&adev->dev);
2281
Linus Walleijb43d65f2009-06-09 08:11:42 +01002282 load_ssp_default_config(pl022);
Viresh Kumar3e3ea712011-08-10 14:20:58 +05302283 if (pl022->master_info->enable_dma)
2284 pl022_dma_remove(pl022);
2285
Linus Walleijb43d65f2009-06-09 08:11:42 +01002286 clk_disable(pl022->clk);
Russell King7ff6bcf2011-09-22 14:27:11 +01002287 clk_unprepare(pl022->clk);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002288 amba_release_regions(adev);
2289 tasklet_disable(&pl022->pump_transfers);
2290 spi_unregister_master(pl022->master);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002291 amba_set_drvdata(adev, NULL);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002292 return 0;
2293}
2294
Linus Walleijada7aec2012-09-26 18:06:22 +02002295#if defined(CONFIG_SUSPEND) || defined(CONFIG_PM_RUNTIME)
2296/*
2297 * These two functions are used from both suspend/resume and
2298 * the runtime counterparts to handle external resources like
2299 * clocks, pins and regulators when going to sleep.
2300 */
Patrice Chotardd8f18422012-10-17 14:27:24 +02002301static void pl022_suspend_resources(struct pl022 *pl022, bool runtime)
Linus Walleijada7aec2012-09-26 18:06:22 +02002302{
Linus Walleijada7aec2012-09-26 18:06:22 +02002303 clk_disable(pl022->clk);
2304
Linus Walleijf1c9cf02013-06-10 16:57:09 +02002305 if (runtime)
2306 pinctrl_pm_select_idle_state(&pl022->adev->dev);
2307 else
2308 pinctrl_pm_select_sleep_state(&pl022->adev->dev);
Linus Walleijada7aec2012-09-26 18:06:22 +02002309}
2310
Patrice Chotardd8f18422012-10-17 14:27:24 +02002311static void pl022_resume_resources(struct pl022 *pl022, bool runtime)
Linus Walleijada7aec2012-09-26 18:06:22 +02002312{
Patrice Chotardd8f18422012-10-17 14:27:24 +02002313 /* First go to the default state */
Linus Walleijf1c9cf02013-06-10 16:57:09 +02002314 pinctrl_pm_select_default_state(&pl022->adev->dev);
2315 if (!runtime)
Patrice Chotardd8f18422012-10-17 14:27:24 +02002316 /* Then let's idle the pins until the next transfer happens */
Linus Walleijf1c9cf02013-06-10 16:57:09 +02002317 pinctrl_pm_select_idle_state(&pl022->adev->dev);
Patrice Chotardd8f18422012-10-17 14:27:24 +02002318
Linus Walleijada7aec2012-09-26 18:06:22 +02002319 clk_enable(pl022->clk);
2320}
2321#endif
2322
Russell King92b97f02011-08-14 09:13:48 +01002323#ifdef CONFIG_SUSPEND
Peter Hüwe6cfa6272011-09-05 21:07:23 +01002324static int pl022_suspend(struct device *dev)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002325{
Russell King92b97f02011-08-14 09:13:48 +01002326 struct pl022 *pl022 = dev_get_drvdata(dev);
Linus Walleijffbbdd212012-02-22 10:05:38 +01002327 int ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002328
Linus Walleijffbbdd212012-02-22 10:05:38 +01002329 ret = spi_master_suspend(pl022->master);
2330 if (ret) {
2331 dev_warn(dev, "cannot suspend master\n");
2332 return ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002333 }
Ulf Hansson4964a262012-10-17 14:27:16 +02002334
2335 pm_runtime_get_sync(dev);
Patrice Chotardd8f18422012-10-17 14:27:24 +02002336 pl022_suspend_resources(pl022, false);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002337
Peter Hüwe6cfa6272011-09-05 21:07:23 +01002338 dev_dbg(dev, "suspended\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01002339 return 0;
2340}
2341
Russell King92b97f02011-08-14 09:13:48 +01002342static int pl022_resume(struct device *dev)
Linus Walleijb43d65f2009-06-09 08:11:42 +01002343{
Russell King92b97f02011-08-14 09:13:48 +01002344 struct pl022 *pl022 = dev_get_drvdata(dev);
Linus Walleijffbbdd212012-02-22 10:05:38 +01002345 int ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002346
Patrice Chotardd8f18422012-10-17 14:27:24 +02002347 pl022_resume_resources(pl022, false);
Ulf Hansson4964a262012-10-17 14:27:16 +02002348 pm_runtime_put(dev);
Linus Walleijada7aec2012-09-26 18:06:22 +02002349
Linus Walleijb43d65f2009-06-09 08:11:42 +01002350 /* Start the queue running */
Linus Walleijffbbdd212012-02-22 10:05:38 +01002351 ret = spi_master_resume(pl022->master);
2352 if (ret)
2353 dev_err(dev, "problem starting queue (%d)\n", ret);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002354 else
Russell King92b97f02011-08-14 09:13:48 +01002355 dev_dbg(dev, "resumed\n");
Linus Walleijb43d65f2009-06-09 08:11:42 +01002356
Linus Walleijffbbdd212012-02-22 10:05:38 +01002357 return ret;
Linus Walleijb43d65f2009-06-09 08:11:42 +01002358}
Linus Walleijb43d65f2009-06-09 08:11:42 +01002359#endif /* CONFIG_PM */
2360
Russell King92b97f02011-08-14 09:13:48 +01002361#ifdef CONFIG_PM_RUNTIME
2362static int pl022_runtime_suspend(struct device *dev)
2363{
2364 struct pl022 *pl022 = dev_get_drvdata(dev);
2365
Patrice Chotardd8f18422012-10-17 14:27:24 +02002366 pl022_suspend_resources(pl022, true);
Russell King92b97f02011-08-14 09:13:48 +01002367 return 0;
2368}
2369
2370static int pl022_runtime_resume(struct device *dev)
2371{
2372 struct pl022 *pl022 = dev_get_drvdata(dev);
Patrice Chotard4f5e1b32012-09-19 14:23:46 +02002373
Patrice Chotardd8f18422012-10-17 14:27:24 +02002374 pl022_resume_resources(pl022, true);
Russell King92b97f02011-08-14 09:13:48 +01002375 return 0;
2376}
2377#endif
2378
2379static const struct dev_pm_ops pl022_dev_pm_ops = {
2380 SET_SYSTEM_SLEEP_PM_OPS(pl022_suspend, pl022_resume)
2381 SET_RUNTIME_PM_OPS(pl022_runtime_suspend, pl022_runtime_resume, NULL)
2382};
2383
Linus Walleijb43d65f2009-06-09 08:11:42 +01002384static struct vendor_data vendor_arm = {
2385 .fifodepth = 8,
2386 .max_bpw = 16,
2387 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002388 .extended_cr = false,
Linus Walleij781c7b12010-05-07 08:40:53 +00002389 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002390 .loopback = true,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002391};
2392
Linus Walleijb43d65f2009-06-09 08:11:42 +01002393static struct vendor_data vendor_st = {
2394 .fifodepth = 32,
2395 .max_bpw = 32,
2396 .unidir = false,
Linus Walleij556f4ae2010-05-05 09:28:15 +00002397 .extended_cr = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002398 .pl023 = false,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002399 .loopback = true,
Linus Walleij781c7b12010-05-07 08:40:53 +00002400};
2401
2402static struct vendor_data vendor_st_pl023 = {
2403 .fifodepth = 32,
2404 .max_bpw = 32,
2405 .unidir = false,
2406 .extended_cr = true,
2407 .pl023 = true,
Philippe Langlais06fb01f2011-03-23 11:05:16 +01002408 .loopback = false,
2409};
2410
Linus Walleijb43d65f2009-06-09 08:11:42 +01002411static struct amba_id pl022_ids[] = {
2412 {
2413 /*
2414 * ARM PL022 variant, this has a 16bit wide
2415 * and 8 locations deep TX/RX FIFO
2416 */
2417 .id = 0x00041022,
2418 .mask = 0x000fffff,
2419 .data = &vendor_arm,
2420 },
2421 {
2422 /*
2423 * ST Micro derivative, this has 32bit wide
2424 * and 32 locations deep TX/RX FIFO
2425 */
Srinidhi Kasagare89e04f2009-10-05 06:13:53 +01002426 .id = 0x01080022,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002427 .mask = 0xffffffff,
2428 .data = &vendor_st,
2429 },
Linus Walleij781c7b12010-05-07 08:40:53 +00002430 {
2431 /*
2432 * ST-Ericsson derivative "PL023" (this is not
2433 * an official ARM number), this is a PL022 SSP block
2434 * stripped to SPI mode only, it has 32bit wide
2435 * and 32 locations deep TX/RX FIFO but no extended
2436 * CR0/CR1 register
2437 */
Viresh Kumarf1e45f82011-08-10 14:20:54 +05302438 .id = 0x00080023,
2439 .mask = 0xffffffff,
2440 .data = &vendor_st_pl023,
Linus Walleij781c7b12010-05-07 08:40:53 +00002441 },
Linus Walleijb43d65f2009-06-09 08:11:42 +01002442 { 0, 0 },
2443};
2444
Dave Martin7eeac712011-10-05 15:15:22 +01002445MODULE_DEVICE_TABLE(amba, pl022_ids);
2446
Linus Walleijb43d65f2009-06-09 08:11:42 +01002447static struct amba_driver pl022_driver = {
2448 .drv = {
2449 .name = "ssp-pl022",
Russell King92b97f02011-08-14 09:13:48 +01002450 .pm = &pl022_dev_pm_ops,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002451 },
2452 .id_table = pl022_ids,
2453 .probe = pl022_probe,
Grant Likelyfd4a3192012-12-07 16:57:14 +00002454 .remove = pl022_remove,
Linus Walleijb43d65f2009-06-09 08:11:42 +01002455};
2456
Linus Walleijb43d65f2009-06-09 08:11:42 +01002457static int __init pl022_init(void)
2458{
2459 return amba_driver_register(&pl022_driver);
2460}
Linus Walleij25c8e032010-09-06 11:02:12 +02002461subsys_initcall(pl022_init);
Linus Walleijb43d65f2009-06-09 08:11:42 +01002462
2463static void __exit pl022_exit(void)
2464{
2465 amba_driver_unregister(&pl022_driver);
2466}
Linus Walleijb43d65f2009-06-09 08:11:42 +01002467module_exit(pl022_exit);
2468
2469MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2470MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2471MODULE_LICENSE("GPL");