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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
Uwe Zeisbergerf30c2262006-10-03 23:01:26 +02002 * linux/arch/arm/mach-omap2/irq.c
Tony Lindgren1dbae812005-11-10 14:26:51 +00003 *
4 * Interrupt handler for OMAP2 boards.
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010014#include <linux/module.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000015#include <linux/init.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000016#include <linux/interrupt.h>
Paul Walmsley2e7509e2008-10-09 17:51:28 +030017#include <linux/io.h>
Tony Lindgrenee0839c2012-02-24 10:34:35 -080018
Marc Zyngier2db14992011-09-06 09:56:17 +010019#include <asm/exception.h>
Benoit Cousson52fa2122011-11-30 19:21:07 +010020#include <linux/irqdomain.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
R Sricharanc4082d42012-06-05 16:31:06 +053023#include <linux/of_irq.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000024
Felipe Balbi85980662014-09-15 16:15:02 -050025#include "irqchip.h"
26
27/* Define these here for now until we drop all board-files */
28#define OMAP24XX_IC_BASE 0x480fe000
29#define OMAP34XX_IC_BASE 0x48200000
Paul Walmsley2e7509e2008-10-09 17:51:28 +030030
31/* selected INTC register offsets */
32
33#define INTC_REVISION 0x0000
34#define INTC_SYSCONFIG 0x0010
35#define INTC_SYSSTATUS 0x0014
Tony Lindgren6ccc4c02008-12-10 17:36:52 -080036#define INTC_SIR 0x0040
Paul Walmsley2e7509e2008-10-09 17:51:28 +030037#define INTC_CONTROL 0x0048
Rajendra Nayak0addd612008-09-26 17:48:20 +053038#define INTC_PROTECTION 0x004C
39#define INTC_IDLE 0x0050
40#define INTC_THRESHOLD 0x0068
41#define INTC_MIR0 0x0084
Paul Walmsley2e7509e2008-10-09 17:51:28 +030042#define INTC_MIR_CLEAR0 0x0088
43#define INTC_MIR_SET0 0x008c
44#define INTC_PENDING_IRQ0 0x0098
Felipe Balbi11983652014-09-08 17:54:37 -070045#define INTC_PENDING_IRQ1 0x00b8
46#define INTC_PENDING_IRQ2 0x00d8
47#define INTC_PENDING_IRQ3 0x00f8
Felipe Balbi33c7c7b2014-09-08 17:54:32 -070048#define INTC_ILR0 0x0100
Tony Lindgren1dbae812005-11-10 14:26:51 +000049
Marc Zyngier2db14992011-09-06 09:56:17 +010050#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
Felipe Balbia88ab432014-09-08 17:54:35 -070051#define INTCPS_NR_ILR_REGS 128
Tony Lindgren3003ce32012-09-04 17:43:29 -070052#define INTCPS_NR_MIR_REGS 3
Marc Zyngier2db14992011-09-06 09:56:17 +010053
Tony Lindgren1dbae812005-11-10 14:26:51 +000054/*
55 * OMAP2 has a number of different interrupt controllers, each interrupt
56 * controller is identified as its own "bank". Register definitions are
57 * fairly consistent for each bank, but not all registers are implemented
58 * for each bank.. when in doubt, consult the TRM.
59 */
Tony Lindgren1dbae812005-11-10 14:26:51 +000060
Rajendra Nayak0addd612008-09-26 17:48:20 +053061/* Structure to save interrupt controller context */
Felipe Balbi272a8b02014-09-08 17:54:38 -070062struct omap_intc_regs {
Rajendra Nayak0addd612008-09-26 17:48:20 +053063 u32 sysconfig;
64 u32 protection;
65 u32 idle;
66 u32 threshold;
Felipe Balbia88ab432014-09-08 17:54:35 -070067 u32 ilr[INTCPS_NR_ILR_REGS];
Rajendra Nayak0addd612008-09-26 17:48:20 +053068 u32 mir[INTCPS_NR_MIR_REGS];
69};
Felipe Balbi131b48c2014-09-08 17:54:42 -070070static struct omap_intc_regs intc_context;
71
72static struct irq_domain *domain;
73static void __iomem *omap_irq_base;
Felipe Balbi52b1e122014-09-08 17:54:57 -070074static int omap_nr_pending = 3;
Felipe Balbi131b48c2014-09-08 17:54:42 -070075static int omap_nr_irqs = 96;
Rajendra Nayak0addd612008-09-26 17:48:20 +053076
Paul Walmsley2e7509e2008-10-09 17:51:28 +030077/* INTC bank register get/set */
Felipe Balbi71be00c2014-09-08 17:54:32 -070078static void intc_writel(u32 reg, u32 val)
Paul Walmsley2e7509e2008-10-09 17:51:28 +030079{
Felipe Balbi71be00c2014-09-08 17:54:32 -070080 writel_relaxed(val, omap_irq_base + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030081}
82
Felipe Balbi71be00c2014-09-08 17:54:32 -070083static u32 intc_readl(u32 reg)
Paul Walmsley2e7509e2008-10-09 17:51:28 +030084{
Felipe Balbi71be00c2014-09-08 17:54:32 -070085 return readl_relaxed(omap_irq_base + reg);
Paul Walmsley2e7509e2008-10-09 17:51:28 +030086}
87
Felipe Balbi131b48c2014-09-08 17:54:42 -070088void omap_intc_save_context(void)
89{
90 int i;
91
92 intc_context.sysconfig =
93 intc_readl(INTC_SYSCONFIG);
94 intc_context.protection =
95 intc_readl(INTC_PROTECTION);
96 intc_context.idle =
97 intc_readl(INTC_IDLE);
98 intc_context.threshold =
99 intc_readl(INTC_THRESHOLD);
100
101 for (i = 0; i < omap_nr_irqs; i++)
102 intc_context.ilr[i] =
103 intc_readl((INTC_ILR0 + 0x4 * i));
104 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
105 intc_context.mir[i] =
106 intc_readl(INTC_MIR0 + (0x20 * i));
107}
108
109void omap_intc_restore_context(void)
110{
111 int i;
112
113 intc_writel(INTC_SYSCONFIG, intc_context.sysconfig);
114 intc_writel(INTC_PROTECTION, intc_context.protection);
115 intc_writel(INTC_IDLE, intc_context.idle);
116 intc_writel(INTC_THRESHOLD, intc_context.threshold);
117
118 for (i = 0; i < omap_nr_irqs; i++)
119 intc_writel(INTC_ILR0 + 0x4 * i,
120 intc_context.ilr[i]);
121
122 for (i = 0; i < INTCPS_NR_MIR_REGS; i++)
123 intc_writel(INTC_MIR0 + 0x20 * i,
124 intc_context.mir[i]);
125 /* MIRs are saved and restore with other PRCM registers */
126}
127
128void omap3_intc_prepare_idle(void)
129{
130 /*
131 * Disable autoidle as it can stall interrupt controller,
132 * cf. errata ID i540 for 3430 (all revisions up to 3.1.x)
133 */
134 intc_writel(INTC_SYSCONFIG, 0);
135}
136
137void omap3_intc_resume_idle(void)
138{
139 /* Re-enable autoidle */
140 intc_writel(INTC_SYSCONFIG, 1);
141}
142
Tony Lindgren1dbae812005-11-10 14:26:51 +0000143/* XXX: FIQ and additional INTC support (only MPU at the moment) */
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100144static void omap_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000145{
Felipe Balbi71be00c2014-09-08 17:54:32 -0700146 intc_writel(INTC_CONTROL, 0x1);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000147}
148
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100149static void omap_mask_ack_irq(struct irq_data *d)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000150{
Tony Lindgren667a11f2011-05-16 02:07:38 -0700151 irq_gc_mask_disable_reg(d);
Lennert Buytenhekdf303472010-11-29 10:39:59 +0100152 omap_ack_irq(d);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000153}
154
Felipe Balbia88ab432014-09-08 17:54:35 -0700155static void __init omap_irq_soft_reset(void)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000156{
157 unsigned long tmp;
158
Felipe Balbi71be00c2014-09-08 17:54:32 -0700159 tmp = intc_readl(INTC_REVISION) & 0xff;
Felipe Balbia88ab432014-09-08 17:54:35 -0700160
Paul Walmsley7852ec02012-07-26 00:54:26 -0600161 pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
Felipe Balbia88ab432014-09-08 17:54:35 -0700162 omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000163
Felipe Balbi71be00c2014-09-08 17:54:32 -0700164 tmp = intc_readl(INTC_SYSCONFIG);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000165 tmp |= 1 << 1; /* soft reset */
Felipe Balbi71be00c2014-09-08 17:54:32 -0700166 intc_writel(INTC_SYSCONFIG, tmp);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000167
Felipe Balbi71be00c2014-09-08 17:54:32 -0700168 while (!(intc_readl(INTC_SYSSTATUS) & 0x1))
Tony Lindgren1dbae812005-11-10 14:26:51 +0000169 /* Wait for reset to complete */;
Juha Yrjola375e12a2006-12-06 17:13:50 -0800170
171 /* Enable autoidle */
Felipe Balbi71be00c2014-09-08 17:54:32 -0700172 intc_writel(INTC_SYSCONFIG, 1 << 0);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000173}
174
Jouni Hogander94434532009-02-03 15:49:04 -0800175int omap_irq_pending(void)
176{
Felipe Balbi6bd0f162014-09-15 16:15:03 -0500177 int i;
Jouni Hogander94434532009-02-03 15:49:04 -0800178
Felipe Balbi6bd0f162014-09-15 16:15:03 -0500179 for (i = 0; i < omap_nr_pending; i++)
180 if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)))
Felipe Balbia88ab432014-09-08 17:54:35 -0700181 return 1;
Jouni Hogander94434532009-02-03 15:49:04 -0800182 return 0;
183}
184
Felipe Balbi131b48c2014-09-08 17:54:42 -0700185void omap3_intc_suspend(void)
186{
187 /* A pending interrupt would prevent OMAP from entering suspend */
188 omap_ack_irq(NULL);
189}
190
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700191static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base)
192{
193 int ret;
194 int i;
195
196 ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC",
197 handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE,
198 IRQ_LEVEL, 0);
199 if (ret) {
200 pr_warn("Failed to allocate irq chips\n");
201 return ret;
202 }
203
204 for (i = 0; i < omap_nr_pending; i++) {
205 struct irq_chip_generic *gc;
206 struct irq_chip_type *ct;
207
208 gc = irq_get_domain_generic_chip(d, 32 * i);
209 gc->reg_base = base;
210 ct = gc->chip_types;
211
212 ct->type = IRQ_TYPE_LEVEL_MASK;
213 ct->handler = handle_level_irq;
214
215 ct->chip.irq_ack = omap_mask_ack_irq;
216 ct->chip.irq_mask = irq_gc_mask_disable_reg;
217 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
218
219 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
220
221 ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i;
222 ct->regs.disable = INTC_MIR_SET0 + 32 * i;
223 }
224
225 return 0;
226}
227
228static void __init omap_alloc_gc_legacy(void __iomem *base,
229 unsigned int irq_start, unsigned int num)
Tony Lindgren667a11f2011-05-16 02:07:38 -0700230{
231 struct irq_chip_generic *gc;
232 struct irq_chip_type *ct;
233
234 gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700235 handle_level_irq);
Tony Lindgren667a11f2011-05-16 02:07:38 -0700236 ct = gc->chip_types;
237 ct->chip.irq_ack = omap_mask_ack_irq;
238 ct->chip.irq_mask = irq_gc_mask_disable_reg;
239 ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
NeilBrowne3c83c22012-04-25 13:05:24 +1000240 ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE;
Tony Lindgren667a11f2011-05-16 02:07:38 -0700241
Tony Lindgren667a11f2011-05-16 02:07:38 -0700242 ct->regs.enable = INTC_MIR_CLEAR0;
243 ct->regs.disable = INTC_MIR_SET0;
244 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700245 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
Tony Lindgren667a11f2011-05-16 02:07:38 -0700246}
247
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700248static int __init omap_init_irq_of(struct device_node *node)
249{
250 int ret;
251
252 omap_irq_base = of_iomap(node, 0);
253 if (WARN_ON(!omap_irq_base))
254 return -ENOMEM;
255
256 domain = irq_domain_add_linear(node, omap_nr_irqs,
257 &irq_generic_chip_ops, NULL);
258
259 omap_irq_soft_reset();
260
261 ret = omap_alloc_gc_of(domain, omap_irq_base);
262 if (ret < 0)
263 irq_domain_remove(domain);
264
265 return ret;
266}
267
268static int __init omap_init_irq_legacy(u32 base)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000269{
Felipe Balbia88ab432014-09-08 17:54:35 -0700270 int j, irq_base;
Tony Lindgren1dbae812005-11-10 14:26:51 +0000271
Tony Lindgren741e3a82011-05-17 03:51:26 -0700272 omap_irq_base = ioremap(base, SZ_4K);
273 if (WARN_ON(!omap_irq_base))
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700274 return -ENOMEM;
Tony Lindgren741e3a82011-05-17 03:51:26 -0700275
Felipe Balbia74f0a12014-09-08 17:54:55 -0700276 irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100277 if (irq_base < 0) {
278 pr_warn("Couldn't allocate IRQ numbers\n");
279 irq_base = 0;
280 }
281
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700282 domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0,
Felipe Balbia88ab432014-09-08 17:54:35 -0700283 &irq_domain_simple_ops, NULL);
Benoit Cousson52fa2122011-11-30 19:21:07 +0100284
Felipe Balbia88ab432014-09-08 17:54:35 -0700285 omap_irq_soft_reset();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000286
Felipe Balbia88ab432014-09-08 17:54:35 -0700287 for (j = 0; j < omap_nr_irqs; j += 32)
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700288 omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32);
289
290 return 0;
291}
292
293static int __init omap_init_irq(u32 base, struct device_node *node)
294{
295 if (node)
296 return omap_init_irq_of(node);
297 else
298 return omap_init_irq_legacy(base);
Tony Lindgren1dbae812005-11-10 14:26:51 +0000299}
300
Felipe Balbi2aced892014-09-08 17:54:52 -0700301static asmlinkage void __exception_irq_entry
302omap_intc_handle_irq(struct pt_regs *regs)
Marc Zyngier2db14992011-09-06 09:56:17 +0100303{
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700304 u32 irqnr = 0;
Stefan Sørensen698b4852014-03-06 16:27:15 +0100305 int handled_irq = 0;
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700306 int i;
Marc Zyngier2db14992011-09-06 09:56:17 +0100307
308 do {
Felipe Balbid6a7c5c2014-09-08 17:54:57 -0700309 for (i = 0; i < omap_nr_pending; i++) {
310 irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i));
311 if (irqnr)
312 goto out;
313 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100314
315out:
316 if (!irqnr)
317 break;
318
Felipe Balbi11983652014-09-08 17:54:37 -0700319 irqnr = intc_readl(INTC_SIR);
Marc Zyngier2db14992011-09-06 09:56:17 +0100320 irqnr &= ACTIVEIRQ_MASK;
321
Benoit Cousson52fa2122011-11-30 19:21:07 +0100322 if (irqnr) {
323 irqnr = irq_find_mapping(domain, irqnr);
Marc Zyngier2db14992011-09-06 09:56:17 +0100324 handle_IRQ(irqnr, regs);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100325 handled_irq = 1;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100326 }
Marc Zyngier2db14992011-09-06 09:56:17 +0100327 } while (irqnr);
Stefan Sørensen698b4852014-03-06 16:27:15 +0100328
329 /* If an irq is masked or deasserted while active, we will
330 * keep ending up here with no irq handled. So remove it from
331 * the INTC with an ack.*/
332 if (!handled_irq)
333 omap_ack_irq(NULL);
Marc Zyngier2db14992011-09-06 09:56:17 +0100334}
335
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700336void __init omap2_init_irq(void)
337{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700338 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700339 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700340 omap_init_irq(OMAP24XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700341 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700342}
343
344void __init omap3_init_irq(void)
345{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700346 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700347 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700348 omap_init_irq(OMAP34XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700349 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700350}
351
352void __init ti81xx_init_irq(void)
353{
Felipe Balbia74f0a12014-09-08 17:54:55 -0700354 omap_nr_irqs = 96;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700355 omap_nr_pending = 4;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700356 omap_init_irq(OMAP34XX_IC_BASE, NULL);
Felipe Balbi2aced892014-09-08 17:54:52 -0700357 set_handle_irq(omap_intc_handle_irq);
Felipe Balbia4d3c5d2014-09-08 17:54:51 -0700358}
359
Felipe Balbi00b6b032014-09-08 17:54:43 -0700360static int __init intc_of_init(struct device_node *node,
Benoit Cousson52fa2122011-11-30 19:21:07 +0100361 struct device_node *parent)
362{
363 struct resource res;
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700364 int ret;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700365
Felipe Balbi52b1e122014-09-08 17:54:57 -0700366 omap_nr_pending = 3;
Felipe Balbia74f0a12014-09-08 17:54:55 -0700367 omap_nr_irqs = 96;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100368
369 if (WARN_ON(!node))
370 return -ENODEV;
371
372 if (of_address_to_resource(node, 0, &res)) {
373 WARN(1, "unable to get intc registers\n");
374 return -EINVAL;
375 }
376
Felipe Balbi52b1e122014-09-08 17:54:57 -0700377 if (of_device_is_compatible(node, "ti,am33xx-intc")) {
Felipe Balbia74f0a12014-09-08 17:54:55 -0700378 omap_nr_irqs = 128;
Felipe Balbi52b1e122014-09-08 17:54:57 -0700379 omap_nr_pending = 4;
380 }
Felipe Balbi470f30d2014-09-08 17:54:47 -0700381
Felipe Balbi55601c9f2014-09-08 17:54:58 -0700382 ret = omap_init_irq(-1, of_node_get(node));
383 if (ret < 0)
384 return ret;
Benoit Cousson52fa2122011-11-30 19:21:07 +0100385
Felipe Balbi2aced892014-09-08 17:54:52 -0700386 set_handle_irq(omap_intc_handle_irq);
Felipe Balbib15c76b2014-09-08 17:54:43 -0700387
Benoit Cousson52fa2122011-11-30 19:21:07 +0100388 return 0;
389}
390
Felipe Balbia35db9a2014-09-08 17:54:46 -0700391IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init);
392IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init);
393IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init);