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Vladimir Barinov44d0a872007-11-14 17:07:17 +01001/*
2 * ALSA SoC TLV320AIC3X codec driver
3 *
Vladimir Barinovd6b52032008-09-29 23:14:11 +04004 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
Vladimir Barinov44d0a872007-11-14 17:07:17 +01005 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _AIC3X_H
13#define _AIC3X_H
14
15/* AIC3X register space */
Jiri Prchal784a8972012-07-04 08:12:50 +020016#define AIC3X_CACHEREGNUM 110
Vladimir Barinov44d0a872007-11-14 17:07:17 +010017
18/* Page select register */
19#define AIC3X_PAGE_SELECT 0
20/* Software reset register */
21#define AIC3X_RESET 1
22/* Codec Sample rate select register */
23#define AIC3X_SAMPLE_RATE_SEL_REG 2
24/* PLL progrramming register A */
25#define AIC3X_PLL_PROGA_REG 3
26/* PLL progrramming register B */
27#define AIC3X_PLL_PROGB_REG 4
28/* PLL progrramming register C */
29#define AIC3X_PLL_PROGC_REG 5
30/* PLL progrramming register D */
31#define AIC3X_PLL_PROGD_REG 6
32/* Codec datapath setup register */
33#define AIC3X_CODEC_DATAPATH_REG 7
34/* Audio serial data interface control register A */
35#define AIC3X_ASD_INTF_CTRLA 8
36/* Audio serial data interface control register B */
37#define AIC3X_ASD_INTF_CTRLB 9
Troy Kiskya24f4f62008-12-19 13:05:22 -070038/* Audio serial data interface control register C */
39#define AIC3X_ASD_INTF_CTRLC 10
Vladimir Barinov44d0a872007-11-14 17:07:17 +010040/* Audio overflow status and PLL R value programming register */
41#define AIC3X_OVRF_STATUS_AND_PLLR_REG 11
Jarkko Nikula4d20f702008-06-27 14:07:57 +030042/* Audio codec digital filter control register */
43#define AIC3X_CODEC_DFILT_CTRL 12
Daniel Mack6f2a9742008-12-03 11:44:17 +010044/* Headset/button press detection register */
45#define AIC3X_HEADSET_DETECT_CTRL_A 13
46#define AIC3X_HEADSET_DETECT_CTRL_B 14
Vladimir Barinov44d0a872007-11-14 17:07:17 +010047/* ADC PGA Gain control registers */
48#define LADC_VOL 15
49#define RADC_VOL 16
50/* MIC3 control registers */
51#define MIC3LR_2_LADC_CTRL 17
52#define MIC3LR_2_RADC_CTRL 18
53/* Line1 Input control registers */
54#define LINE1L_2_LADC_CTRL 19
Daniel Mack54f01912008-11-26 17:47:36 +010055#define LINE1R_2_LADC_CTRL 21
Vladimir Barinov44d0a872007-11-14 17:07:17 +010056#define LINE1R_2_RADC_CTRL 22
Daniel Mack54f01912008-11-26 17:47:36 +010057#define LINE1L_2_RADC_CTRL 24
Vladimir Barinov44d0a872007-11-14 17:07:17 +010058/* Line2 Input control registers */
59#define LINE2L_2_LADC_CTRL 20
60#define LINE2R_2_RADC_CTRL 23
61/* MICBIAS Control Register */
62#define MICBIAS_CTRL 25
63
64/* AGC Control Registers A, B, C */
65#define LAGC_CTRL_A 26
66#define LAGC_CTRL_B 27
67#define LAGC_CTRL_C 28
68#define RAGC_CTRL_A 29
69#define RAGC_CTRL_B 30
70#define RAGC_CTRL_C 31
71
72/* DAC Power and Left High Power Output control registers */
73#define DAC_PWR 37
74#define HPLCOM_CFG 37
75/* Right High Power Output control registers */
76#define HPRCOM_CFG 38
Jiri Prchal784a8972012-07-04 08:12:50 +020077/* High Power Output Stage Control Register */
78#define HPOUT_SC 40
Vladimir Barinov44d0a872007-11-14 17:07:17 +010079/* DAC Output Switching control registers */
80#define DAC_LINE_MUX 41
81/* High Power Output Driver Pop Reduction registers */
82#define HPOUT_POP_REDUCTION 42
83/* DAC Digital control registers */
84#define LDAC_VOL 43
85#define RDAC_VOL 44
Jarkko Nikulab2eaac22010-08-27 16:56:48 +030086/* Left High Power Output control registers */
Vladimir Barinov44d0a872007-11-14 17:07:17 +010087#define LINE2L_2_HPLOUT_VOL 45
Vladimir Barinov44d0a872007-11-14 17:07:17 +010088#define PGAL_2_HPLOUT_VOL 46
Vladimir Barinov44d0a872007-11-14 17:07:17 +010089#define DACL1_2_HPLOUT_VOL 47
Jarkko Nikulac3b79e02010-08-27 16:56:49 +030090#define LINE2R_2_HPLOUT_VOL 48
Jarkko Nikulab2eaac22010-08-27 16:56:48 +030091#define PGAR_2_HPLOUT_VOL 49
Jarkko Nikulac3b79e02010-08-27 16:56:49 +030092#define DACR1_2_HPLOUT_VOL 50
Vladimir Barinov44d0a872007-11-14 17:07:17 +010093#define HPLOUT_CTRL 51
Jarkko Nikulab2eaac22010-08-27 16:56:48 +030094/* Left High Power COM control registers */
Vladimir Barinov44d0a872007-11-14 17:07:17 +010095#define LINE2L_2_HPLCOM_VOL 52
Vladimir Barinov44d0a872007-11-14 17:07:17 +010096#define PGAL_2_HPLCOM_VOL 53
Vladimir Barinov44d0a872007-11-14 17:07:17 +010097#define DACL1_2_HPLCOM_VOL 54
Jarkko Nikulac3b79e02010-08-27 16:56:49 +030098#define LINE2R_2_HPLCOM_VOL 55
Jarkko Nikulab2eaac22010-08-27 16:56:48 +030099#define PGAR_2_HPLCOM_VOL 56
Jarkko Nikulac3b79e02010-08-27 16:56:49 +0300100#define DACR1_2_HPLCOM_VOL 57
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100101#define HPLCOM_CTRL 58
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300102/* Right High Power Output control registers */
Jarkko Nikulac3b79e02010-08-27 16:56:49 +0300103#define LINE2L_2_HPROUT_VOL 59
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300104#define PGAL_2_HPROUT_VOL 60
Jarkko Nikulac3b79e02010-08-27 16:56:49 +0300105#define DACL1_2_HPROUT_VOL 61
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300106#define LINE2R_2_HPROUT_VOL 62
107#define PGAR_2_HPROUT_VOL 63
108#define DACR1_2_HPROUT_VOL 64
109#define HPROUT_CTRL 65
110/* Right High Power COM control registers */
Jarkko Nikulac3b79e02010-08-27 16:56:49 +0300111#define LINE2L_2_HPRCOM_VOL 66
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300112#define PGAL_2_HPRCOM_VOL 67
Jarkko Nikulac3b79e02010-08-27 16:56:49 +0300113#define DACL1_2_HPRCOM_VOL 68
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300114#define LINE2R_2_HPRCOM_VOL 69
115#define PGAR_2_HPRCOM_VOL 70
116#define DACR1_2_HPRCOM_VOL 71
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100117#define HPRCOM_CTRL 72
118/* Mono Line Output Plus/Minus control registers */
119#define LINE2L_2_MONOLOPM_VOL 73
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100120#define PGAL_2_MONOLOPM_VOL 74
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100121#define DACL1_2_MONOLOPM_VOL 75
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300122#define LINE2R_2_MONOLOPM_VOL 76
123#define PGAR_2_MONOLOPM_VOL 77
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100124#define DACR1_2_MONOLOPM_VOL 78
125#define MONOLOPM_CTRL 79
Randolph Chung6184f102010-08-20 12:47:53 +0800126/* Class-D speaker driver on tlv320aic3007 */
127#define CLASSD_CTRL 73
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300128/* Left Line Output Plus/Minus control registers */
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100129#define LINE2L_2_LLOPM_VOL 80
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100130#define PGAL_2_LLOPM_VOL 81
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100131#define DACL1_2_LLOPM_VOL 82
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300132#define LINE2R_2_LLOPM_VOL 83
133#define PGAR_2_LLOPM_VOL 84
Daniel Mack54f01912008-11-26 17:47:36 +0100134#define DACR1_2_LLOPM_VOL 85
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100135#define LLOPM_CTRL 86
Jarkko Nikulab2eaac22010-08-27 16:56:48 +0300136/* Right Line Output Plus/Minus control registers */
137#define LINE2L_2_RLOPM_VOL 87
138#define PGAL_2_RLOPM_VOL 88
139#define DACL1_2_RLOPM_VOL 89
140#define LINE2R_2_RLOPM_VOL 90
141#define PGAR_2_RLOPM_VOL 91
142#define DACR1_2_RLOPM_VOL 92
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100143#define RLOPM_CTRL 93
Daniel Mack54e7e612008-04-30 16:20:52 +0200144/* GPIO/IRQ registers */
145#define AIC3X_STICKY_IRQ_FLAGS_REG 96
146#define AIC3X_RT_IRQ_FLAGS_REG 97
147#define AIC3X_GPIO1_REG 98
148#define AIC3X_GPIO2_REG 99
149#define AIC3X_GPIOA_REG 100
Daniel Mack4f9c16c2008-04-30 16:20:19 +0200150#define AIC3X_GPIOB_REG 101
Daniel Mack54e7e612008-04-30 16:20:52 +0200151/* Clock generation control register */
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100152#define AIC3X_CLKGEN_CTRL_REG 102
Jiri Prchal784a8972012-07-04 08:12:50 +0200153/* New AGC registers */
154#define LAGCN_ATTACK 103
155#define LAGCN_DECAY 104
156#define RAGCN_ATTACK 105
157#define RAGCN_DECAY 106
158/* New Programmable ADC Digital Path and I2C Bus Condition Register */
159#define NEW_ADC_DIGITALPATH 107
160/* Passive Analog Signal Bypass Selection During Powerdown Register */
161#define PASSIVE_BYPASS 108
162/* DAC Quiescent Current Adjustment Register */
163#define DAC_ICC_ADJ 109
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100164
165/* Page select register bits */
166#define PAGE0_SELECT 0
167#define PAGE1_SELECT 1
168
169/* Audio serial data interface control register A bits */
170#define BIT_CLK_MASTER 0x80
171#define WORD_CLK_MASTER 0x40
172
173/* Codec Datapath setup register 7 */
174#define FSREF_44100 (1 << 7)
175#define FSREF_48000 (0 << 7)
176#define DUAL_RATE_MODE ((1 << 5) | (1 << 6))
177#define LDAC2LCH (0x1 << 3)
178#define RDAC2RCH (0x1 << 1)
Jiri Prchal784a8972012-07-04 08:12:50 +0200179#define LDAC2RCH (0x2 << 3)
180#define RDAC2LCH (0x2 << 1)
181#define LDAC2MONOMIX (0x3 << 3)
182#define RDAC2MONOMIX (0x3 << 1)
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100183
184/* PLL registers bitfields */
185#define PLLP_SHIFT 0
Hebbar, Gururajac9fe5732012-06-26 19:25:11 +0530186#define PLLP_MASK 7
Daniel Mack4f9c16c2008-04-30 16:20:19 +0200187#define PLLQ_SHIFT 3
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100188#define PLLR_SHIFT 0
189#define PLLJ_SHIFT 2
190#define PLLD_MSB_SHIFT 0
191#define PLLD_LSB_SHIFT 2
192
193/* Clock generation register bits */
Daniel Mack4f9c16c2008-04-30 16:20:19 +0200194#define CODEC_CLKIN_PLLDIV 0
195#define CODEC_CLKIN_CLKDIV 1
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100196#define PLL_CLKIN_SHIFT 4
197#define MCLK_SOURCE 0x0
198#define PLL_CLKDIV_SHIFT 0
Jiri Prchala1f34af2012-07-10 14:36:58 +0200199#define PLLCLK_IN_MASK 0x30
200#define PLLCLK_IN_SHIFT 4
201#define CLKDIV_IN_MASK 0xc0
202#define CLKDIV_IN_SHIFT 6
203/* clock in source */
204#define CLKIN_MCLK 0
205#define CLKIN_GPIO2 1
206#define CLKIN_BCLK 2
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100207
208/* Software reset register bits */
209#define SOFT_RESET 0x80
210
211/* PLL progrramming register A bits */
212#define PLL_ENABLE 0x80
213
214/* Route bits */
215#define ROUTE_ON 0x80
216
217/* Mute bits */
218#define UNMUTE 0x08
219#define MUTE_ON 0x80
220
221/* Power bits */
222#define LADC_PWR_ON 0x04
223#define RADC_PWR_ON 0x04
224#define LDAC_PWR_ON 0x80
225#define RDAC_PWR_ON 0x40
226#define HPLOUT_PWR_ON 0x01
227#define HPROUT_PWR_ON 0x01
228#define HPLCOM_PWR_ON 0x01
229#define HPRCOM_PWR_ON 0x01
230#define MONOLOPM_PWR_ON 0x01
231#define LLOPM_PWR_ON 0x01
232#define RLOPM_PWR_ON 0x01
233
234#define INVERT_VOL(val) (0x7f - val)
235
236/* Default output volume (inverted) */
237#define DEFAULT_VOL INVERT_VOL(0x50)
238/* Default input volume */
239#define DEFAULT_GAIN 0x20
240
Hebbar Gururajae2e8bfd2013-01-31 18:23:04 +0530241/* MICBIAS Control Register */
242#define MICBIAS_LEVEL_SHIFT (6)
243#define MICBIAS_LEVEL_MASK (3 << 6)
244
Daniel Mack6f2a9742008-12-03 11:44:17 +0100245/* headset detection / button API */
246
247/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
248 * and cellular headsets (GND + speaker output + microphone input).
249 * It is recommended to enable MIC bias for this function to work properly.
250 * For more information, please refer to the datasheet. */
251enum {
252 AIC3X_HEADSET_DETECT_OFF = 0,
253 AIC3X_HEADSET_DETECT_STEREO = 1,
254 AIC3X_HEADSET_DETECT_CELLULAR = 2,
255 AIC3X_HEADSET_DETECT_BOTH = 3
256};
257
258enum {
259 AIC3X_HEADSET_DEBOUNCE_16MS = 0,
260 AIC3X_HEADSET_DEBOUNCE_32MS = 1,
261 AIC3X_HEADSET_DEBOUNCE_64MS = 2,
262 AIC3X_HEADSET_DEBOUNCE_128MS = 3,
263 AIC3X_HEADSET_DEBOUNCE_256MS = 4,
264 AIC3X_HEADSET_DEBOUNCE_512MS = 5
265};
266
267enum {
268 AIC3X_BUTTON_DEBOUNCE_0MS = 0,
269 AIC3X_BUTTON_DEBOUNCE_8MS = 1,
270 AIC3X_BUTTON_DEBOUNCE_16MS = 2,
271 AIC3X_BUTTON_DEBOUNCE_32MS = 3
272};
273
274#define AIC3X_HEADSET_DETECT_ENABLED 0x80
275#define AIC3X_HEADSET_DETECT_SHIFT 5
276#define AIC3X_HEADSET_DETECT_MASK 3
277#define AIC3X_HEADSET_DEBOUNCE_SHIFT 2
278#define AIC3X_HEADSET_DEBOUNCE_MASK 7
279#define AIC3X_BUTTON_DEBOUNCE_SHIFT 0
280#define AIC3X_BUTTON_DEBOUNCE_MASK 3
281
Vladimir Barinov44d0a872007-11-14 17:07:17 +0100282#endif /* _AIC3X_H */