blob: b8c5187b9ee0da912b3a872b828705891a0146a4 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Tzachi Perelsteina0832792007-11-12 19:38:51 +02002 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12#include <linux/kernel.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090013#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
Tzachi Perelsteina0832792007-11-12 19:38:51 +020018#include <linux/mv643xx_i2c.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010019#include <linux/platform_device.h>
H Hartley Sweeten21782182010-05-21 18:41:01 +020020#include <linux/io.h>
Andrew Lunnb61d1572012-07-22 12:51:35 +020021#include <linux/of.h>
Maxime Ripard004e8ed2013-06-12 18:53:31 +020022#include <linux/of_device.h>
Andrew Lunnb61d1572012-07-22 12:51:35 +020023#include <linux/of_irq.h>
Andrew Lunnb61d1572012-07-22 12:51:35 +020024#include <linux/clk.h>
25#include <linux/err.h>
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +020026#include <linux/delay.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070027
Maxime Ripard683e69b2013-06-12 18:53:30 +020028#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
29#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
30#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
31
Linus Torvalds1da177e2005-04-16 15:20:36 -070032#define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
33#define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
34#define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
35#define MV64XXX_I2C_REG_CONTROL_START 0x00000020
36#define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
37#define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
38
39/* Ctlr status values */
40#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
41#define MV64XXX_I2C_STATUS_MAST_START 0x08
42#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
43#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
44#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
45#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
46#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
47#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
48#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
49#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
50#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
51#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
52#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
53#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
54#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
55#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
56#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
57
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +020058/* Register defines (I2C bridge) */
59#define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
60#define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
61#define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
62#define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
63#define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
64#define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
65#define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
66#define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
67#define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
68
69/* Bridge Control values */
70#define MV64XXX_I2C_BRIDGE_CONTROL_WR 0x00000001
71#define MV64XXX_I2C_BRIDGE_CONTROL_RD 0x00000002
72#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
73#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT 0x00001000
74#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
75#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
76#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE 0x00080000
77
78/* Bridge Status values */
79#define MV64XXX_I2C_BRIDGE_STATUS_ERROR 0x00000001
80#define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001
81#define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000
82
83
Linus Torvalds1da177e2005-04-16 15:20:36 -070084/* Driver states */
85enum {
86 MV64XXX_I2C_STATE_INVALID,
87 MV64XXX_I2C_STATE_IDLE,
88 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +010089 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
Linus Torvalds1da177e2005-04-16 15:20:36 -070090 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
Linus Torvalds1da177e2005-04-16 15:20:36 -070094};
95
96/* Driver actions */
97enum {
98 MV64XXX_I2C_ACTION_INVALID,
99 MV64XXX_I2C_ACTION_CONTINUE,
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200100 MV64XXX_I2C_ACTION_OFFLOAD_SEND_START,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101 MV64XXX_I2C_ACTION_SEND_START,
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100102 MV64XXX_I2C_ACTION_SEND_RESTART,
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200103 MV64XXX_I2C_ACTION_OFFLOAD_RESTART,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700104 MV64XXX_I2C_ACTION_SEND_ADDR_1,
105 MV64XXX_I2C_ACTION_SEND_ADDR_2,
106 MV64XXX_I2C_ACTION_SEND_DATA,
107 MV64XXX_I2C_ACTION_RCV_DATA,
108 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
109 MV64XXX_I2C_ACTION_SEND_STOP,
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200110 MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700111};
112
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200113struct mv64xxx_i2c_regs {
114 u8 addr;
115 u8 ext_addr;
116 u8 data;
117 u8 control;
118 u8 status;
119 u8 clock;
120 u8 soft_reset;
121};
122
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123struct mv64xxx_i2c_data {
Russell King4243fa02013-05-16 21:39:12 +0100124 struct i2c_msg *msgs;
125 int num_msgs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126 int irq;
127 u32 state;
128 u32 action;
Mark A. Greere91c0212005-12-18 17:22:01 +0100129 u32 aborting;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700130 u32 cntl_bits;
131 void __iomem *reg_base;
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200132 struct mv64xxx_i2c_regs reg_offsets;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700133 u32 addr1;
134 u32 addr2;
135 u32 bytes_left;
136 u32 byte_posn;
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100137 u32 send_stop;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700138 u32 block;
139 int rc;
140 u32 freq_m;
141 u32 freq_n;
Andrew Lunnb61d1572012-07-22 12:51:35 +0200142#if defined(CONFIG_HAVE_CLK)
143 struct clk *clk;
144#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700145 wait_queue_head_t waitq;
146 spinlock_t lock;
147 struct i2c_msg *msg;
148 struct i2c_adapter adapter;
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200149 bool offload_enabled;
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +0200150/* 5us delay in order to avoid repeated start timing violation */
151 bool errata_delay;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152};
153
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200154static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
155 .addr = 0x00,
156 .ext_addr = 0x10,
157 .data = 0x04,
158 .control = 0x08,
159 .status = 0x0c,
160 .clock = 0x0c,
161 .soft_reset = 0x1c,
162};
163
Maxime Ripard3d66ac72013-06-12 18:53:32 +0200164static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
165 .addr = 0x00,
166 .ext_addr = 0x04,
167 .data = 0x08,
168 .control = 0x0c,
169 .status = 0x10,
170 .clock = 0x14,
171 .soft_reset = 0x18,
172};
173
Russell King3420afb2013-05-16 21:38:11 +0100174static void
175mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
176 struct i2c_msg *msg)
177{
178 u32 dir = 0;
179
180 drv_data->msg = msg;
181 drv_data->byte_posn = 0;
182 drv_data->bytes_left = msg->len;
183 drv_data->aborting = 0;
184 drv_data->rc = 0;
185 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
186 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
187
188 if (msg->flags & I2C_M_RD)
189 dir = 1;
190
191 if (msg->flags & I2C_M_TEN) {
192 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
193 drv_data->addr2 = (u32)msg->addr & 0xff;
194 } else {
Maxime Ripard683e69b2013-06-12 18:53:30 +0200195 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
Russell King3420afb2013-05-16 21:38:11 +0100196 drv_data->addr2 = 0;
197 }
198}
199
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200200static int mv64xxx_i2c_offload_msg(struct mv64xxx_i2c_data *drv_data)
201{
202 unsigned long data_reg_hi = 0;
203 unsigned long data_reg_lo = 0;
204 unsigned long ctrl_reg;
205 struct i2c_msg *msg = drv_data->msgs;
206
207 drv_data->msg = msg;
208 drv_data->byte_posn = 0;
209 drv_data->bytes_left = msg->len;
210 drv_data->aborting = 0;
211 drv_data->rc = 0;
212 /* Only regular transactions can be offloaded */
213 if ((msg->flags & ~(I2C_M_TEN | I2C_M_RD)) != 0)
214 return -EINVAL;
215
216 /* Only 1-8 byte transfers can be offloaded */
217 if (msg->len < 1 || msg->len > 8)
218 return -EINVAL;
219
220 /* Build transaction */
221 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
222 (msg->addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
223
224 if ((msg->flags & I2C_M_TEN) != 0)
225 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
226
227 if ((msg->flags & I2C_M_RD) == 0) {
228 u8 local_buf[8] = { 0 };
229
230 memcpy(local_buf, msg->buf, msg->len);
231 data_reg_lo = cpu_to_le32(*((u32 *)local_buf));
232 data_reg_hi = cpu_to_le32(*((u32 *)(local_buf+4)));
233
234 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
235 (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT;
236
Thierry Reding85b3a932013-09-18 14:51:40 +0200237 writel(data_reg_lo,
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200238 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
Thierry Reding85b3a932013-09-18 14:51:40 +0200239 writel(data_reg_hi,
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200240 drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
241
242 } else {
243 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
244 (msg->len - 1) << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT;
245 }
246
247 /* Execute transaction */
248 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
249
250 return 0;
251}
252
253static void
254mv64xxx_i2c_update_offload_data(struct mv64xxx_i2c_data *drv_data)
255{
256 struct i2c_msg *msg = drv_data->msg;
257
258 if (msg->flags & I2C_M_RD) {
259 u32 data_reg_lo = readl(drv_data->reg_base +
260 MV64XXX_I2C_REG_RX_DATA_LO);
261 u32 data_reg_hi = readl(drv_data->reg_base +
262 MV64XXX_I2C_REG_RX_DATA_HI);
263 u8 local_buf[8] = { 0 };
264
265 *((u32 *)local_buf) = le32_to_cpu(data_reg_lo);
266 *((u32 *)(local_buf+4)) = le32_to_cpu(data_reg_hi);
267 memcpy(msg->buf, local_buf, msg->len);
268 }
269
270}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700271/*
272 *****************************************************************************
273 *
274 * Finite State Machine & Interrupt Routines
275 *
276 *****************************************************************************
277 */
Dale Farnswortha07ad1c2007-08-14 18:37:14 +0200278
279/* Reset hardware and initialize FSM */
280static void
281mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
282{
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200283 if (drv_data->offload_enabled) {
284 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
285 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
286 writel(0, drv_data->reg_base +
287 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
288 writel(0, drv_data->reg_base +
289 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
290 }
291
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200292 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
Maxime Ripard683e69b2013-06-12 18:53:30 +0200293 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200294 drv_data->reg_base + drv_data->reg_offsets.clock);
295 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
296 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
Dale Farnswortha07ad1c2007-08-14 18:37:14 +0200297 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200298 drv_data->reg_base + drv_data->reg_offsets.control);
Dale Farnswortha07ad1c2007-08-14 18:37:14 +0200299 drv_data->state = MV64XXX_I2C_STATE_IDLE;
300}
301
Linus Torvalds1da177e2005-04-16 15:20:36 -0700302static void
303mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
304{
305 /*
306 * If state is idle, then this is likely the remnants of an old
307 * operation that driver has given up on or the user has killed.
308 * If so, issue the stop condition and go to idle.
309 */
310 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
311 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
312 return;
313 }
314
Linus Torvalds1da177e2005-04-16 15:20:36 -0700315 /* The status from the ctlr [mostly] tells us what to do next */
316 switch (status) {
317 /* Start condition interrupt */
318 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
319 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
320 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
321 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
322 break;
323
324 /* Performing a write */
325 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
326 if (drv_data->msg->flags & I2C_M_TEN) {
327 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
328 drv_data->state =
329 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
330 break;
331 }
332 /* FALLTHRU */
333 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
334 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
Mark A. Greere91c0212005-12-18 17:22:01 +0100335 if ((drv_data->bytes_left == 0)
336 || (drv_data->aborting
337 && (drv_data->byte_posn != 0))) {
Russell King4243fa02013-05-16 21:39:12 +0100338 if (drv_data->send_stop || drv_data->aborting) {
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100339 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
340 drv_data->state = MV64XXX_I2C_STATE_IDLE;
341 } else {
342 drv_data->action =
343 MV64XXX_I2C_ACTION_SEND_RESTART;
344 drv_data->state =
345 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
346 }
Mark A. Greere91c0212005-12-18 17:22:01 +0100347 } else {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700348 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
349 drv_data->state =
350 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
351 drv_data->bytes_left--;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700352 }
353 break;
354
355 /* Performing a read */
356 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
357 if (drv_data->msg->flags & I2C_M_TEN) {
358 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
359 drv_data->state =
360 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
361 break;
362 }
363 /* FALLTHRU */
364 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
365 if (drv_data->bytes_left == 0) {
366 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
367 drv_data->state = MV64XXX_I2C_STATE_IDLE;
368 break;
369 }
370 /* FALLTHRU */
371 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
372 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
373 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
374 else {
375 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
376 drv_data->bytes_left--;
377 }
378 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
379
Mark A. Greere91c0212005-12-18 17:22:01 +0100380 if ((drv_data->bytes_left == 1) || drv_data->aborting)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700381 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
382 break;
383
384 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
385 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
386 drv_data->state = MV64XXX_I2C_STATE_IDLE;
387 break;
388
389 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
390 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
391 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
392 /* Doesn't seem to be a device at other end */
393 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
394 drv_data->state = MV64XXX_I2C_STATE_IDLE;
Guenter Roeck6faa3532013-06-19 14:53:52 -0700395 drv_data->rc = -ENXIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700396 break;
397
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200398 case MV64XXX_I2C_STATUS_OFFLOAD_OK:
399 if (drv_data->send_stop || drv_data->aborting) {
400 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP;
401 drv_data->state = MV64XXX_I2C_STATE_IDLE;
402 } else {
403 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_RESTART;
404 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
405 }
406 break;
407
Linus Torvalds1da177e2005-04-16 15:20:36 -0700408 default:
409 dev_err(&drv_data->adapter.dev,
410 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
411 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
412 drv_data->state, status, drv_data->msg->addr,
413 drv_data->msg->flags);
414 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
Dale Farnswortha07ad1c2007-08-14 18:37:14 +0200415 mv64xxx_i2c_hw_init(drv_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700416 drv_data->rc = -EIO;
417 }
418}
419
420static void
421mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
422{
423 switch(drv_data->action) {
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200424 case MV64XXX_I2C_ACTION_OFFLOAD_RESTART:
425 mv64xxx_i2c_update_offload_data(drv_data);
426 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
427 writel(0, drv_data->reg_base +
428 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
429 /* FALLTHRU */
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100430 case MV64XXX_I2C_ACTION_SEND_RESTART:
Russell King4243fa02013-05-16 21:39:12 +0100431 /* We should only get here if we have further messages */
432 BUG_ON(drv_data->num_msgs == 0);
433
Russell King4243fa02013-05-16 21:39:12 +0100434 drv_data->msgs++;
435 drv_data->num_msgs--;
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200436 if (!(drv_data->offload_enabled &&
437 mv64xxx_i2c_offload_msg(drv_data))) {
438 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
439 writel(drv_data->cntl_bits,
440 drv_data->reg_base + drv_data->reg_offsets.control);
Russell King4243fa02013-05-16 21:39:12 +0100441
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200442 /* Setup for the next message */
443 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
444 }
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +0200445 if (drv_data->errata_delay)
446 udelay(5);
447
Russell King4243fa02013-05-16 21:39:12 +0100448 /*
449 * We're never at the start of the message here, and by this
450 * time it's already too late to do any protocol mangling.
451 * Thankfully, do not advertise support for that feature.
452 */
453 drv_data->send_stop = drv_data->num_msgs == 1;
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100454 break;
455
Linus Torvalds1da177e2005-04-16 15:20:36 -0700456 case MV64XXX_I2C_ACTION_CONTINUE:
457 writel(drv_data->cntl_bits,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200458 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700459 break;
460
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200461 case MV64XXX_I2C_ACTION_OFFLOAD_SEND_START:
462 if (!mv64xxx_i2c_offload_msg(drv_data))
463 break;
464 else
465 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
466 /* FALLTHRU */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700467 case MV64XXX_I2C_ACTION_SEND_START:
468 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200469 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470 break;
471
472 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
473 writel(drv_data->addr1,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200474 drv_data->reg_base + drv_data->reg_offsets.data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700475 writel(drv_data->cntl_bits,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200476 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 break;
478
479 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
480 writel(drv_data->addr2,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200481 drv_data->reg_base + drv_data->reg_offsets.data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700482 writel(drv_data->cntl_bits,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200483 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 break;
485
486 case MV64XXX_I2C_ACTION_SEND_DATA:
487 writel(drv_data->msg->buf[drv_data->byte_posn++],
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200488 drv_data->reg_base + drv_data->reg_offsets.data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700489 writel(drv_data->cntl_bits,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200490 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700491 break;
492
493 case MV64XXX_I2C_ACTION_RCV_DATA:
494 drv_data->msg->buf[drv_data->byte_posn++] =
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200495 readl(drv_data->reg_base + drv_data->reg_offsets.data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496 writel(drv_data->cntl_bits,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200497 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498 break;
499
500 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
501 drv_data->msg->buf[drv_data->byte_posn++] =
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200502 readl(drv_data->reg_base + drv_data->reg_offsets.data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
504 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200505 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 drv_data->block = 0;
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +0200507 if (drv_data->errata_delay)
508 udelay(5);
509
Russell Kingd295a862013-05-16 10:30:59 +0000510 wake_up(&drv_data->waitq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700511 break;
512
513 case MV64XXX_I2C_ACTION_INVALID:
514 default:
515 dev_err(&drv_data->adapter.dev,
516 "mv64xxx_i2c_do_action: Invalid action: %d\n",
517 drv_data->action);
518 drv_data->rc = -EIO;
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200519
Linus Torvalds1da177e2005-04-16 15:20:36 -0700520 /* FALLTHRU */
521 case MV64XXX_I2C_ACTION_SEND_STOP:
522 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
523 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200524 drv_data->reg_base + drv_data->reg_offsets.control);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700525 drv_data->block = 0;
Russell Kingd295a862013-05-16 10:30:59 +0000526 wake_up(&drv_data->waitq);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700527 break;
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200528
529 case MV64XXX_I2C_ACTION_OFFLOAD_SEND_STOP:
530 mv64xxx_i2c_update_offload_data(drv_data);
531 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
532 writel(0, drv_data->reg_base +
533 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
534 drv_data->block = 0;
535 wake_up(&drv_data->waitq);
536 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700537 }
538}
539
Mikael Petterssonb0999cc2009-09-07 12:00:13 +0200540static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +0100541mv64xxx_i2c_intr(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700542{
543 struct mv64xxx_i2c_data *drv_data = dev_id;
544 unsigned long flags;
545 u32 status;
Mikael Petterssonb0999cc2009-09-07 12:00:13 +0200546 irqreturn_t rc = IRQ_NONE;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700547
548 spin_lock_irqsave(&drv_data->lock, flags);
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200549
550 if (drv_data->offload_enabled) {
551 while (readl(drv_data->reg_base +
552 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE)) {
553 int reg_status = readl(drv_data->reg_base +
554 MV64XXX_I2C_REG_BRIDGE_STATUS);
555 if (reg_status & MV64XXX_I2C_BRIDGE_STATUS_ERROR)
556 status = MV64XXX_I2C_STATUS_OFFLOAD_ERROR;
557 else
558 status = MV64XXX_I2C_STATUS_OFFLOAD_OK;
559 mv64xxx_i2c_fsm(drv_data, status);
560 mv64xxx_i2c_do_action(drv_data);
561 rc = IRQ_HANDLED;
562 }
563 }
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200564 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
Linus Torvalds1da177e2005-04-16 15:20:36 -0700565 MV64XXX_I2C_REG_CONTROL_IFLG) {
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200566 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567 mv64xxx_i2c_fsm(drv_data, status);
568 mv64xxx_i2c_do_action(drv_data);
569 rc = IRQ_HANDLED;
570 }
571 spin_unlock_irqrestore(&drv_data->lock, flags);
572
573 return rc;
574}
575
576/*
577 *****************************************************************************
578 *
579 * I2C Msg Execution Routines
580 *
581 *****************************************************************************
582 */
583static void
Linus Torvalds1da177e2005-04-16 15:20:36 -0700584mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
585{
586 long time_left;
587 unsigned long flags;
588 char abort = 0;
589
Russell Kingd295a862013-05-16 10:30:59 +0000590 time_left = wait_event_timeout(drv_data->waitq,
Jean Delvare8a52c6b2009-03-28 21:34:43 +0100591 !drv_data->block, drv_data->adapter.timeout);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700592
593 spin_lock_irqsave(&drv_data->lock, flags);
594 if (!time_left) { /* Timed out */
595 drv_data->rc = -ETIMEDOUT;
596 abort = 1;
597 } else if (time_left < 0) { /* Interrupted/Error */
598 drv_data->rc = time_left; /* errno value */
599 abort = 1;
600 }
601
602 if (abort && drv_data->block) {
Mark A. Greere91c0212005-12-18 17:22:01 +0100603 drv_data->aborting = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604 spin_unlock_irqrestore(&drv_data->lock, flags);
605
606 time_left = wait_event_timeout(drv_data->waitq,
Jean Delvare8a52c6b2009-03-28 21:34:43 +0100607 !drv_data->block, drv_data->adapter.timeout);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700608
Mark A. Greere91c0212005-12-18 17:22:01 +0100609 if ((time_left <= 0) && drv_data->block) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700610 drv_data->state = MV64XXX_I2C_STATE_IDLE;
611 dev_err(&drv_data->adapter.dev,
Mark A. Greere91c0212005-12-18 17:22:01 +0100612 "mv64xxx: I2C bus locked, block: %d, "
613 "time_left: %d\n", drv_data->block,
614 (int)time_left);
Dale Farnswortha07ad1c2007-08-14 18:37:14 +0200615 mv64xxx_i2c_hw_init(drv_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700616 }
617 } else
618 spin_unlock_irqrestore(&drv_data->lock, flags);
619}
620
621static int
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100622mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
Russell King4243fa02013-05-16 21:39:12 +0100623 int is_last)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700624{
625 unsigned long flags;
626
627 spin_lock_irqsave(&drv_data->lock, flags);
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200628 if (drv_data->offload_enabled) {
629 drv_data->action = MV64XXX_I2C_ACTION_OFFLOAD_SEND_START;
630 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
631 } else {
632 mv64xxx_i2c_prepare_for_io(drv_data, msg);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700633
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200634 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
635 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
636 }
Rodolfo Giomettieda6bee2010-11-26 17:06:56 +0100637 drv_data->send_stop = is_last;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700638 drv_data->block = 1;
639 mv64xxx_i2c_do_action(drv_data);
640 spin_unlock_irqrestore(&drv_data->lock, flags);
641
642 mv64xxx_i2c_wait_for_completion(drv_data);
643 return drv_data->rc;
644}
645
646/*
647 *****************************************************************************
648 *
649 * I2C Core Support Routines (Interface to higher level I2C code)
650 *
651 *****************************************************************************
652 */
653static u32
654mv64xxx_i2c_functionality(struct i2c_adapter *adap)
655{
656 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
657}
658
659static int
660mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
661{
662 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
Russell King4243fa02013-05-16 21:39:12 +0100663 int rc, ret = num;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664
Russell King4243fa02013-05-16 21:39:12 +0100665 BUG_ON(drv_data->msgs != NULL);
666 drv_data->msgs = msgs;
667 drv_data->num_msgs = num;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668
Russell King4243fa02013-05-16 21:39:12 +0100669 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
670 if (rc < 0)
671 ret = rc;
672
673 drv_data->num_msgs = 0;
674 drv_data->msgs = NULL;
675
676 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677}
678
Jean Delvare8f9082c2006-09-03 22:39:46 +0200679static const struct i2c_algorithm mv64xxx_i2c_algo = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680 .master_xfer = mv64xxx_i2c_xfer,
681 .functionality = mv64xxx_i2c_functionality,
682};
683
684/*
685 *****************************************************************************
686 *
687 * Driver Interface & Early Init Routines
688 *
689 *****************************************************************************
690 */
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200691static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
Maxime Ripard3d66ac72013-06-12 18:53:32 +0200692 { .compatible = "allwinner,sun4i-i2c", .data = &mv64xxx_i2c_regs_sun4i},
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200693 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200694 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
Gregory CLEMENT6cf70ae2013-12-31 16:59:33 +0100695 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200696 {}
697};
698MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
699
Andrew Lunnb61d1572012-07-22 12:51:35 +0200700#ifdef CONFIG_OF
Thierry Redingc1a99462013-09-18 14:50:52 +0200701#ifdef CONFIG_HAVE_CLK
Bill Pemberton0b255e92012-11-27 15:59:38 -0500702static int
Andrew Lunnb61d1572012-07-22 12:51:35 +0200703mv64xxx_calc_freq(const int tclk, const int n, const int m)
704{
705 return tclk / (10 * (m + 1) * (2 << n));
706}
707
Bill Pemberton0b255e92012-11-27 15:59:38 -0500708static bool
Andrew Lunnb61d1572012-07-22 12:51:35 +0200709mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
710 u32 *best_m)
711{
712 int freq, delta, best_delta = INT_MAX;
713 int m, n;
714
715 for (n = 0; n <= 7; n++)
716 for (m = 0; m <= 15; m++) {
717 freq = mv64xxx_calc_freq(tclk, n, m);
718 delta = req_freq - freq;
719 if (delta >= 0 && delta < best_delta) {
720 *best_m = m;
721 *best_n = n;
722 best_delta = delta;
723 }
724 if (best_delta == 0)
725 return true;
726 }
727 if (best_delta == INT_MAX)
728 return false;
729 return true;
730}
Thierry Redingc1a99462013-09-18 14:50:52 +0200731#endif /* CONFIG_HAVE_CLK */
Andrew Lunnb61d1572012-07-22 12:51:35 +0200732
Bill Pemberton0b255e92012-11-27 15:59:38 -0500733static int
Andrew Lunnb61d1572012-07-22 12:51:35 +0200734mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200735 struct device *dev)
Andrew Lunnb61d1572012-07-22 12:51:35 +0200736{
Andrew Lunnb61d1572012-07-22 12:51:35 +0200737 /* CLK is mandatory when using DT to describe the i2c bus. We
738 * need to know tclk in order to calculate bus clock
739 * factors.
740 */
741#if !defined(CONFIG_HAVE_CLK)
742 /* Have OF but no CLK */
743 return -ENODEV;
744#else
Thierry Redingc1a99462013-09-18 14:50:52 +0200745 const struct of_device_id *device;
746 struct device_node *np = dev->of_node;
747 u32 bus_freq, tclk;
748 int rc = 0;
749
Andrew Lunnb61d1572012-07-22 12:51:35 +0200750 if (IS_ERR(drv_data->clk)) {
751 rc = -ENODEV;
752 goto out;
753 }
754 tclk = clk_get_rate(drv_data->clk);
Gregory CLEMENT4c730a02013-06-21 15:32:06 +0200755
756 rc = of_property_read_u32(np, "clock-frequency", &bus_freq);
757 if (rc)
758 bus_freq = 100000; /* 100kHz by default */
759
Andrew Lunnb61d1572012-07-22 12:51:35 +0200760 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
761 &drv_data->freq_n, &drv_data->freq_m)) {
762 rc = -EINVAL;
763 goto out;
764 }
765 drv_data->irq = irq_of_parse_and_map(np, 0);
766
767 /* Its not yet defined how timeouts will be specified in device tree.
768 * So hard code the value to 1 second.
769 */
770 drv_data->adapter.timeout = HZ;
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200771
772 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
773 if (!device)
774 return -ENODEV;
775
776 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
777
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200778 /*
779 * For controllers embedded in new SoCs activate the
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +0200780 * Transaction Generator support and the errata fix.
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200781 */
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +0200782 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200783 drv_data->offload_enabled = true;
Gregory CLEMENTc1d15b62013-08-22 16:19:06 +0200784 drv_data->errata_delay = true;
785 }
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200786
Gregory CLEMENT6cf70ae2013-12-31 16:59:33 +0100787 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
788 drv_data->offload_enabled = false;
789 drv_data->errata_delay = true;
790 }
Andrew Lunnb61d1572012-07-22 12:51:35 +0200791out:
792 return rc;
793#endif
794}
795#else /* CONFIG_OF */
Bill Pemberton0b255e92012-11-27 15:59:38 -0500796static int
Andrew Lunnb61d1572012-07-22 12:51:35 +0200797mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200798 struct device *dev)
Andrew Lunnb61d1572012-07-22 12:51:35 +0200799{
800 return -ENODEV;
801}
802#endif /* CONFIG_OF */
803
Bill Pemberton0b255e92012-11-27 15:59:38 -0500804static int
Russell King3ae5eae2005-11-09 22:32:44 +0000805mv64xxx_i2c_probe(struct platform_device *pd)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 struct mv64xxx_i2c_data *drv_data;
Jingoo Han6d4028c2013-07-30 16:59:33 +0900808 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
Russell King16874b02013-05-16 21:33:09 +0100809 struct resource *r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700810 int rc;
811
Andrew Lunnb61d1572012-07-22 12:51:35 +0200812 if ((!pdata && !pd->dev.of_node))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700813 return -ENODEV;
814
Russell King2c911102013-05-16 21:35:10 +0100815 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
816 GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700817 if (!drv_data)
818 return -ENOMEM;
819
Russell King16874b02013-05-16 21:33:09 +0100820 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
821 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
Russell King2c911102013-05-16 21:35:10 +0100822 if (IS_ERR(drv_data->reg_base))
823 return PTR_ERR(drv_data->reg_base);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824
Mark A. Greere91c0212005-12-18 17:22:01 +0100825 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
David Brownell2096b952007-05-01 23:26:28 +0200826 sizeof(drv_data->adapter.name));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700827
828 init_waitqueue_head(&drv_data->waitq);
829 spin_lock_init(&drv_data->lock);
830
Andrew Lunnb61d1572012-07-22 12:51:35 +0200831#if defined(CONFIG_HAVE_CLK)
832 /* Not all platforms have a clk */
Russell King4c5c95f2013-05-16 21:34:10 +0100833 drv_data->clk = devm_clk_get(&pd->dev, NULL);
Andrew Lunnb61d1572012-07-22 12:51:35 +0200834 if (!IS_ERR(drv_data->clk)) {
835 clk_prepare(drv_data->clk);
836 clk_enable(drv_data->clk);
837 }
838#endif
839 if (pdata) {
840 drv_data->freq_m = pdata->freq_m;
841 drv_data->freq_n = pdata->freq_n;
842 drv_data->irq = platform_get_irq(pd, 0);
843 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
Gregory CLEMENT930ab3d2013-08-22 16:19:05 +0200844 drv_data->offload_enabled = false;
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200845 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
Andrew Lunnb61d1572012-07-22 12:51:35 +0200846 } else if (pd->dev.of_node) {
Maxime Ripard004e8ed2013-06-12 18:53:31 +0200847 rc = mv64xxx_of_config(drv_data, &pd->dev);
Andrew Lunnb61d1572012-07-22 12:51:35 +0200848 if (rc)
Russell King2c911102013-05-16 21:35:10 +0100849 goto exit_clk;
Andrew Lunnb61d1572012-07-22 12:51:35 +0200850 }
David Vrabel48944732006-01-19 17:56:29 +0000851 if (drv_data->irq < 0) {
852 rc = -ENXIO;
Russell King2c911102013-05-16 21:35:10 +0100853 goto exit_clk;
David Vrabel48944732006-01-19 17:56:29 +0000854 }
Andrew Lunnb61d1572012-07-22 12:51:35 +0200855
Jean Delvare12a917f2007-02-13 22:09:03 +0100856 drv_data->adapter.dev.parent = &pd->dev;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700857 drv_data->adapter.algo = &mv64xxx_i2c_algo;
858 drv_data->adapter.owner = THIS_MODULE;
Jean Delvare3401b2f2008-07-14 22:38:29 +0200859 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
Dale Farnsworth65b22ad2007-07-12 14:12:29 +0200860 drv_data->adapter.nr = pd->id;
Andrew Lunnb61d1572012-07-22 12:51:35 +0200861 drv_data->adapter.dev.of_node = pd->dev.of_node;
Russell King3ae5eae2005-11-09 22:32:44 +0000862 platform_set_drvdata(pd, drv_data);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 i2c_set_adapdata(&drv_data->adapter, drv_data);
864
Maxime Bizon3269bb62007-01-05 17:54:05 +0100865 mv64xxx_i2c_hw_init(drv_data);
866
Russell King0c195af2013-05-16 21:36:11 +0100867 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
868 MV64XXX_I2C_CTLR_NAME, drv_data);
869 if (rc) {
Mark A. Greerdfded4a2005-12-16 11:08:43 -0800870 dev_err(&drv_data->adapter.dev,
Russell King0c195af2013-05-16 21:36:11 +0100871 "mv64xxx: Can't register intr handler irq%d: %d\n",
872 drv_data->irq, rc);
Russell King2c911102013-05-16 21:35:10 +0100873 goto exit_clk;
Dale Farnsworth65b22ad2007-07-12 14:12:29 +0200874 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
Mark A. Greerdfded4a2005-12-16 11:08:43 -0800875 dev_err(&drv_data->adapter.dev,
876 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700877 goto exit_free_irq;
878 }
879
Linus Torvalds1da177e2005-04-16 15:20:36 -0700880 return 0;
881
Russell King2c911102013-05-16 21:35:10 +0100882exit_free_irq:
883 free_irq(drv_data->irq, drv_data);
884exit_clk:
Andrew Lunnb61d1572012-07-22 12:51:35 +0200885#if defined(CONFIG_HAVE_CLK)
886 /* Not all platforms have a clk */
887 if (!IS_ERR(drv_data->clk)) {
888 clk_disable(drv_data->clk);
889 clk_unprepare(drv_data->clk);
890 }
891#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700892 return rc;
893}
894
Bill Pemberton0b255e92012-11-27 15:59:38 -0500895static int
Russell King3ae5eae2005-11-09 22:32:44 +0000896mv64xxx_i2c_remove(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700897{
Russell King3ae5eae2005-11-09 22:32:44 +0000898 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700899
Lars-Peter Clausenbf51a8c2013-03-09 08:16:46 +0000900 i2c_del_adapter(&drv_data->adapter);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700901 free_irq(drv_data->irq, drv_data);
Andrew Lunnb61d1572012-07-22 12:51:35 +0200902#if defined(CONFIG_HAVE_CLK)
903 /* Not all platforms have a clk */
904 if (!IS_ERR(drv_data->clk)) {
905 clk_disable(drv_data->clk);
906 clk_unprepare(drv_data->clk);
907 }
908#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700909
Lars-Peter Clausenbf51a8c2013-03-09 08:16:46 +0000910 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700911}
912
Russell King3ae5eae2005-11-09 22:32:44 +0000913static struct platform_driver mv64xxx_i2c_driver = {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700914 .probe = mv64xxx_i2c_probe,
Bill Pemberton0b255e92012-11-27 15:59:38 -0500915 .remove = mv64xxx_i2c_remove,
Russell King3ae5eae2005-11-09 22:32:44 +0000916 .driver = {
917 .owner = THIS_MODULE,
918 .name = MV64XXX_I2C_CTLR_NAME,
Sachin Kamat4e905322013-09-30 09:04:25 +0530919 .of_match_table = mv64xxx_i2c_of_match_table,
Russell King3ae5eae2005-11-09 22:32:44 +0000920 },
Linus Torvalds1da177e2005-04-16 15:20:36 -0700921};
922
Axel Lina3664b52012-01-12 20:32:04 +0100923module_platform_driver(mv64xxx_i2c_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700924
925MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
926MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
927MODULE_LICENSE("GPL");