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Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -07001/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
Rayagond Kokatanurbd4242d2012-08-22 21:28:18 +000025#ifndef __COMMON_H__
26#define __COMMON_H__
27
Giuseppe CAVALLARObfab27a2011-12-21 03:58:19 +000028#include <linux/etherdevice.h>
Giuseppe CAVALLARO5e33c792010-01-06 23:07:21 +000029#include <linux/netdevice.h>
Giuseppe CAVALLARObfab27a2011-12-21 03:58:19 +000030#include <linux/phy.h>
31#include <linux/module.h>
Giuseppe CAVALLARO8f617542010-04-13 20:21:16 +000032#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
33#define STMMAC_VLAN_TAG_USED
34#include <linux/if_vlan.h>
35#endif
36
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +000037#include "descs.h"
Giuseppe CAVALLARO1c901a42011-09-01 21:51:38 +000038#include "mmc.h"
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +000039
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +000040/* Synopsys Core versions */
41#define DWMAC_CORE_3_40 0x34
42#define DWMAC_CORE_3_50 0x35
43
Giuseppe CAVALLARO56b106a2010-04-13 20:21:12 +000044#undef FRAME_FILTER_DEBUG
45/* #define FRAME_FILTER_DEBUG */
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070046
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070047struct stmmac_extra_stats {
48 /* Transmit errors */
49 unsigned long tx_underflow ____cacheline_aligned;
50 unsigned long tx_carrier;
51 unsigned long tx_losscarrier;
Giuseppe CAVALLARO3c20f722011-10-26 19:43:09 +000052 unsigned long vlan_tag;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070053 unsigned long tx_deferred;
54 unsigned long tx_vlan;
55 unsigned long tx_jabber;
56 unsigned long tx_frame_flushed;
57 unsigned long tx_payload_error;
58 unsigned long tx_ip_header_error;
59 /* Receive errors */
60 unsigned long rx_desc;
Giuseppe CAVALLARO3c20f722011-10-26 19:43:09 +000061 unsigned long sa_filter_fail;
62 unsigned long overflow_error;
63 unsigned long ipc_csum_error;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070064 unsigned long rx_collision;
65 unsigned long rx_crc;
Giuseppe CAVALLARO1cc5a732012-02-15 00:10:37 +000066 unsigned long dribbling_bit;
Giuseppe Cavallaro1b924032010-02-04 09:33:21 -080067 unsigned long rx_length;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070068 unsigned long rx_mii;
69 unsigned long rx_multicast;
70 unsigned long rx_gmac_overflow;
71 unsigned long rx_watchdog;
72 unsigned long da_rx_filter_fail;
73 unsigned long sa_rx_filter_fail;
74 unsigned long rx_missed_cntr;
75 unsigned long rx_overflow_cntr;
76 unsigned long rx_vlan;
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +000077 /* Tx/Rx IRQ error info */
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070078 unsigned long tx_undeflow_irq;
79 unsigned long tx_process_stopped_irq;
80 unsigned long tx_jabber_irq;
81 unsigned long rx_overflow_irq;
82 unsigned long rx_buf_unav_irq;
83 unsigned long rx_process_stopped_irq;
84 unsigned long rx_watchdog_irq;
85 unsigned long tx_early_irq;
86 unsigned long fatal_bus_error_irq;
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +000087 /* Tx/Rx IRQ Events */
88 unsigned long rx_early_irq;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070089 unsigned long threshold;
90 unsigned long tx_pkt_n;
91 unsigned long rx_pkt_n;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -070092 unsigned long normal_irq_n;
Giuseppe CAVALLARO9125cdd2012-11-25 23:10:42 +000093 unsigned long rx_normal_irq_n;
94 unsigned long napi_poll;
95 unsigned long tx_normal_irq_n;
96 unsigned long tx_clean;
97 unsigned long tx_reset_ic_bit;
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +000098 unsigned long irq_receive_pmt_irq_n;
99 /* MMC info */
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000100 unsigned long mmc_tx_irq_n;
101 unsigned long mmc_rx_irq_n;
102 unsigned long mmc_rx_csum_offload_irq_n;
103 /* EEE */
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000104 unsigned long irq_tx_path_in_lpi_mode_n;
105 unsigned long irq_tx_path_exit_lpi_mode_n;
106 unsigned long irq_rx_path_in_lpi_mode_n;
107 unsigned long irq_rx_path_exit_lpi_mode_n;
108 unsigned long phy_eee_wakeup_error_n;
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000109 /* Extended RDES status */
110 unsigned long ip_hdr_err;
111 unsigned long ip_payload_err;
112 unsigned long ip_csum_bypassed;
113 unsigned long ipv4_pkt_rcvd;
114 unsigned long ipv6_pkt_rcvd;
115 unsigned long rx_msg_type_ext_no_ptp;
116 unsigned long rx_msg_type_sync;
117 unsigned long rx_msg_type_follow_up;
118 unsigned long rx_msg_type_delay_req;
119 unsigned long rx_msg_type_delay_resp;
120 unsigned long rx_msg_type_pdelay_req;
121 unsigned long rx_msg_type_pdelay_resp;
122 unsigned long rx_msg_type_pdelay_follow_up;
123 unsigned long ptp_frame_type;
124 unsigned long ptp_ver;
125 unsigned long timestamp_dropped;
126 unsigned long av_pkt_rcvd;
127 unsigned long av_tagged_pkt_rcvd;
128 unsigned long vlan_tag_priority_val;
129 unsigned long l3_filter_match;
130 unsigned long l4_filter_match;
131 unsigned long l3_l4_filter_no_match;
Giuseppe CAVALLARO0982a0f2013-03-26 04:43:07 +0000132 /* PCS */
133 unsigned long irq_pcs_ane_n;
134 unsigned long irq_pcs_link_n;
135 unsigned long irq_rgmii_n;
Giuseppe CAVALLAROe58bb432013-03-26 04:43:08 +0000136 unsigned long pcs_link;
137 unsigned long pcs_duplex;
138 unsigned long pcs_speed;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700139};
140
Giuseppe CAVALLAROcd7201f2012-04-04 04:33:27 +0000141/* CSR Frequency Access Defines*/
142#define CSR_F_35M 35000000
143#define CSR_F_60M 60000000
144#define CSR_F_100M 100000000
145#define CSR_F_150M 150000000
146#define CSR_F_250M 250000000
147#define CSR_F_300M 300000000
148
149#define MAC_CSR_H_FRQ_MASK 0x20
150
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000151#define HASH_TABLE_SIZE 64
152#define PAUSE_TIME 0x200
153
154/* Flow Control defines */
155#define FLOW_OFF 0
156#define FLOW_RX 1
157#define FLOW_TX 2
158#define FLOW_AUTO (FLOW_TX | FLOW_RX)
159
Giuseppe CAVALLAROe58bb432013-03-26 04:43:08 +0000160/* PCS defines */
161#define STMMAC_PCS_RGMII (1 << 0)
162#define STMMAC_PCS_SGMII (1 << 1)
163#define STMMAC_PCS_TBI (1 << 2)
164#define STMMAC_PCS_RTBI (1 << 3)
165
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000166#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000167
Rayagond Kokatanur1db123f2011-10-18 00:01:22 +0000168/* DAM HW feature register fields */
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000169#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
170#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
171#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
172#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
173#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
174#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
175#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
176#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
177#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
178#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
179#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
180#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
181#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
182#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
183#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
184#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
185#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
186#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
187#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
188#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
189#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
190#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
191#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
192/* Timestamping with Internal System Time */
193#define DMA_HW_FEAT_INTTSEN 0x02000000
194#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
195#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
196#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
Giuseppe CAVALLARO0f1f88a2012-04-18 19:48:21 +0000197#define DEFAULT_DMA_PBL 8
Rayagond Kokatanur1db123f2011-10-18 00:01:22 +0000198
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +0000199/* Max/Min RI Watchdog Timer count value */
200#define MAX_DMA_RIWT 0xff
201#define MIN_DMA_RIWT 0x20
Giuseppe CAVALLARO9125cdd2012-11-25 23:10:42 +0000202/* Tx coalesce parameters */
203#define STMMAC_COAL_TX_TIMER 40000
204#define STMMAC_MAX_COAL_TX_TICK 100000
205#define STMMAC_TX_MAX_FRAMES 256
206#define STMMAC_TX_FRAMES 64
207
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000208/* Rx IPC status */
209enum rx_frame_status {
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700210 good_frame = 0,
211 discard_frame = 1,
212 csum_none = 2,
Giuseppe CAVALLARO3eeb2992010-07-27 00:09:47 +0000213 llc_snap = 4,
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700214};
215
Giuseppe CAVALLARO9125cdd2012-11-25 23:10:42 +0000216enum dma_irq_status {
217 tx_hard_error = 0x1,
218 tx_hard_error_bump_tc = 0x2,
219 handle_rx = 0x4,
220 handle_tx = 0x8,
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000221};
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700222
Giuseppe CAVALLARO0982a0f2013-03-26 04:43:07 +0000223#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 1)
224#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 2)
225#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 3)
226#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 4)
227
228#define CORE_PCS_ANE_COMPLETE (1 << 5)
229#define CORE_PCS_LINK_STATUS (1 << 6)
230#define CORE_RGMII_IRQ (1 << 7)
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000231
Giuseppe CAVALLAROe58bb432013-03-26 04:43:08 +0000232struct rgmii_adv {
233 unsigned int pause;
234 unsigned int duplex;
235 unsigned int lp_pause;
236 unsigned int lp_duplex;
237};
238
239#define STMMAC_PCS_PAUSE 1
240#define STMMAC_PCS_ASYM_PAUSE 2
241
Giuseppe CAVALLAROe7434822011-09-01 21:51:41 +0000242/* DMA HW capabilities */
243struct dma_features {
244 unsigned int mbps_10_100;
245 unsigned int mbps_1000;
246 unsigned int half_duplex;
247 unsigned int hash_filter;
248 unsigned int multi_addr;
249 unsigned int pcs;
250 unsigned int sma_mdio;
251 unsigned int pmt_remote_wake_up;
252 unsigned int pmt_magic_frame;
253 unsigned int rmon;
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000254 /* IEEE 1588-2002 */
Giuseppe CAVALLAROe7434822011-09-01 21:51:41 +0000255 unsigned int time_stamp;
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000256 /* IEEE 1588-2008 */
Giuseppe CAVALLAROe7434822011-09-01 21:51:41 +0000257 unsigned int atime_stamp;
258 /* 802.3az - Energy-Efficient Ethernet (EEE) */
259 unsigned int eee;
260 unsigned int av;
261 /* TX and RX csum */
262 unsigned int tx_coe;
263 unsigned int rx_coe_type1;
264 unsigned int rx_coe_type2;
265 unsigned int rxfifo_over_2048;
266 /* TX and RX number of channels */
267 unsigned int number_rx_channel;
268 unsigned int number_tx_channel;
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000269 /* Alternate (enhanced) DESC mode */
Giuseppe CAVALLAROe7434822011-09-01 21:51:41 +0000270 unsigned int enh_desc;
271};
272
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000273/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
274#define BUF_SIZE_16KiB 16384
275#define BUF_SIZE_8KiB 8192
276#define BUF_SIZE_4KiB 4096
277#define BUF_SIZE_2KiB 2048
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700278
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000279/* Power Down and WOL */
280#define PMT_NOT_SUPPORTED 0
281#define PMT_SUPPORTED 1
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700282
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000283/* Common MAC defines */
284#define MAC_CTRL_REG 0x00000000 /* MAC Control */
285#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
286#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700287
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000288/* Default LPI timers */
Giuseppe CAVALLAROf5351ef2013-06-18 07:03:23 +0200289#define STMMAC_DEFAULT_LIT_LS 0x3E8
290#define STMMAC_DEFAULT_TWT_LS 0x0
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000291
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000292#define STMMAC_CHAIN_MODE 0x1
293#define STMMAC_RING_MODE 0x2
294
Vince Bridgers2618abb2014-01-20 05:39:01 -0600295#define JUMBO_LEN 9000
296
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000297struct stmmac_desc_ops {
298 /* DMA RX descriptor ring initialization */
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000299 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
300 int end);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000301 /* DMA TX descriptor ring initialization */
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000302 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700303
304 /* Invoked by the xmit function to prepare the tx descriptor */
305 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000306 int csum_flag, int mode);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700307 /* Set/get the owner of the descriptor */
308 void (*set_tx_owner) (struct dma_desc *p);
309 int (*get_tx_owner) (struct dma_desc *p);
310 /* Invoked by the xmit function to close the tx descriptor */
311 void (*close_tx_desc) (struct dma_desc *p);
312 /* Clean the tx descriptor as soon as the tx irq is received */
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000313 void (*release_tx_desc) (struct dma_desc *p, int mode);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700314 /* Clear interrupt on tx frame completion. When this bit is
315 * set an interrupt happens as soon as the frame is transmitted */
316 void (*clear_tx_ic) (struct dma_desc *p);
317 /* Last tx segment reports the transmit status */
318 int (*get_tx_ls) (struct dma_desc *p);
319 /* Return the transmit status looking at the TDES1 */
320 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000321 struct dma_desc *p, void __iomem *ioaddr);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700322 /* Get the buffer size from the descriptor */
323 int (*get_tx_len) (struct dma_desc *p);
324 /* Handle extra events on specific interrupts hw dependent */
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700325 int (*get_rx_owner) (struct dma_desc *p);
326 void (*set_rx_owner) (struct dma_desc *p);
327 /* Get the receive frame size */
Deepak SIKRI38912bd2012-04-04 04:33:21 +0000328 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700329 /* Return the reception status looking at the RDES1 */
330 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
331 struct dma_desc *p);
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000332 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
333 struct dma_extended_desc *p);
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000334 /* Set tx timestamp enable bit */
335 void (*enable_tx_timestamp) (struct dma_desc *p);
336 /* get tx timestamp status */
337 int (*get_tx_timestamp_status) (struct dma_desc *p);
338 /* get timestamp value */
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000339 u64(*get_timestamp) (void *desc, u32 ats);
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000340 /* get rx timestamp status */
341 int (*get_rx_timestamp_status) (void *desc, u32 ats);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000342};
343
344struct stmmac_dma_ops {
345 /* DMA core initialization */
Giuseppe CAVALLAROb9cde0a2012-05-13 22:18:42 +0000346 int (*init) (void __iomem *ioaddr, int pbl, int fb, int mb,
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000347 int burst_len, u32 dma_tx, u32 dma_rx, int atds);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000348 /* Dump DMA registers */
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000349 void (*dump_regs) (void __iomem *ioaddr);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000350 /* Set tx/rx threshold in the csr6 register
351 * An invalid value enables the store-and-forward mode */
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000352 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000353 /* To track extra statistic (if supported) */
354 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000355 void __iomem *ioaddr);
356 void (*enable_dma_transmission) (void __iomem *ioaddr);
357 void (*enable_dma_irq) (void __iomem *ioaddr);
358 void (*disable_dma_irq) (void __iomem *ioaddr);
359 void (*start_tx) (void __iomem *ioaddr);
360 void (*stop_tx) (void __iomem *ioaddr);
361 void (*start_rx) (void __iomem *ioaddr);
362 void (*stop_rx) (void __iomem *ioaddr);
363 int (*dma_interrupt) (void __iomem *ioaddr,
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000364 struct stmmac_extra_stats *x);
Giuseppe CAVALLAROe7434822011-09-01 21:51:41 +0000365 /* If supported then get the optional core features */
366 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +0000367 /* Program the HW RX Watchdog */
368 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000369};
370
371struct stmmac_ops {
372 /* MAC core initialization */
Vince Bridgers2618abb2014-01-20 05:39:01 -0600373 void (*core_init) (void __iomem *ioaddr, int mtu);
Deepak SIKRI38912bd2012-04-04 04:33:21 +0000374 /* Enable and verify that the IPC module is supported */
375 int (*rx_ipc) (void __iomem *ioaddr);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000376 /* Dump MAC registers */
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000377 void (*dump_regs) (void __iomem *ioaddr);
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000378 /* Handle extra events on specific interrupts hw dependent */
Giuseppe CAVALLARO0982a0f2013-03-26 04:43:07 +0000379 int (*host_irq_status) (void __iomem *ioaddr,
380 struct stmmac_extra_stats *x);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700381 /* Multicast filter setting */
Giuseppe CAVALLAROcffb13f2012-05-13 22:18:41 +0000382 void (*set_filter) (struct net_device *dev, int id);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700383 /* Flow control setting */
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000384 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700385 unsigned int fc, unsigned int pause_time);
386 /* Set power management mode (e.g. magic frame) */
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000387 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700388 /* Set/Get Unicast MAC addresses */
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000389 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000390 unsigned int reg_n);
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000391 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000392 unsigned int reg_n);
Giuseppe CAVALLAROd7659552012-06-27 21:14:37 +0000393 void (*set_eee_mode) (void __iomem *ioaddr);
394 void (*reset_eee_mode) (void __iomem *ioaddr);
395 void (*set_eee_timer) (void __iomem *ioaddr, int ls, int tw);
396 void (*set_eee_pls) (void __iomem *ioaddr, int link);
Giuseppe CAVALLAROe58bb432013-03-26 04:43:08 +0000397 void (*ctrl_ane) (void __iomem *ioaddr, bool restart);
398 void (*get_adv) (void __iomem *ioaddr, struct rgmii_adv *adv);
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700399};
400
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000401struct stmmac_hwtimestamp {
402 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
403 void (*config_sub_second_increment) (void __iomem *ioaddr);
404 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000405 int (*config_addend) (void __iomem *ioaddr, u32 addend);
406 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
407 int add_sub);
408 u64(*get_systime) (void __iomem *ioaddr);
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000409};
410
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700411struct mac_link {
412 int port;
413 int duplex;
414 int speed;
415};
416
417struct mii_regs {
418 unsigned int addr; /* MII Address */
419 unsigned int data; /* MII Data */
420};
421
Giuseppe CAVALLARO286a8372011-10-18 00:01:24 +0000422struct stmmac_ring_mode_ops {
423 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
424 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000425 void (*refill_desc3) (void *priv, struct dma_desc *p);
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000426 void (*init_desc3) (struct dma_desc *p);
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000427 void (*clean_desc3) (void *priv, struct dma_desc *p);
Giuseppe CAVALLARO286a8372011-10-18 00:01:24 +0000428 int (*set_16kib_bfsize) (int mtu);
429};
430
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000431struct stmmac_chain_mode_ops {
Giuseppe CAVALLAROc24602e2013-03-26 04:43:06 +0000432 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
433 unsigned int extend_desc);
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000434 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
435 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000436 void (*refill_desc3) (void *priv, struct dma_desc *p);
437 void (*clean_desc3) (void *priv, struct dma_desc *p);
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000438};
439
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700440struct mac_device_info {
Giuseppe CAVALLAROceb694992013-04-08 02:10:01 +0000441 const struct stmmac_ops *mac;
442 const struct stmmac_desc_ops *desc;
443 const struct stmmac_dma_ops *dma;
444 const struct stmmac_ring_mode_ops *ring;
445 const struct stmmac_chain_mode_ops *chain;
Rayagond Kokatanur891434b2013-03-26 04:43:10 +0000446 const struct stmmac_hwtimestamp *ptp;
Giuseppe CAVALLAROdb98a0b2010-01-06 23:07:17 +0000447 struct mii_regs mii; /* MII register Addresses */
448 struct mac_link link;
Giuseppe CAVALLAROf0b9d782011-09-01 21:51:40 +0000449 unsigned int synopsys_uid;
Giuseppe Cavallaro47dd7a52009-10-14 15:13:45 -0700450};
451
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000452struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
453struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
Giuseppe CAVALLAROaec7ff22010-01-06 23:07:18 +0000454
Joe Perchesd6cc64e2013-09-23 11:37:59 -0700455void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
456 unsigned int high, unsigned int low);
457void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
458 unsigned int high, unsigned int low);
Giuseppe CAVALLARObfab27a2011-12-21 03:58:19 +0000459
Joe Perchesd6cc64e2013-09-23 11:37:59 -0700460void stmmac_set_mac(void __iomem *ioaddr, bool enable);
Giuseppe CAVALLARObfab27a2011-12-21 03:58:19 +0000461
Joe Perchesd6cc64e2013-09-23 11:37:59 -0700462void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
Giuseppe CAVALLARO286a8372011-10-18 00:01:24 +0000463extern const struct stmmac_ring_mode_ops ring_mode_ops;
Giuseppe CAVALLARO4a7d6662013-03-26 04:43:05 +0000464extern const struct stmmac_chain_mode_ops chain_mode_ops;
Rayagond Kokatanurbd4242d2012-08-22 21:28:18 +0000465
466#endif /* __COMMON_H__ */