Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 ARM Ltd. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | #ifndef __ASM_FUTEX_H |
| 17 | #define __ASM_FUTEX_H |
| 18 | |
| 19 | #ifdef __KERNEL__ |
| 20 | |
| 21 | #include <linux/futex.h> |
| 22 | #include <linux/uaccess.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 23 | |
| 24 | #include <asm/alternative.h> |
| 25 | #include <asm/cpufeature.h> |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 26 | #include <asm/errno.h> |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 27 | #include <asm/sysreg.h> |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 28 | |
| 29 | #define __futex_atomic_op(insn, ret, oldval, uaddr, tmp, oparg) \ |
| 30 | asm volatile( \ |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 31 | ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, \ |
| 32 | CONFIG_ARM64_PAN) \ |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 33 | " prfm pstl1strm, %2\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 34 | "1: ldxr %w1, %2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 35 | insn "\n" \ |
| 36 | "2: stlxr %w3, %w0, %2\n" \ |
| 37 | " cbnz %w3, 1b\n" \ |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 38 | " dmb ish\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 39 | "3:\n" \ |
| 40 | " .pushsection .fixup,\"ax\"\n" \ |
Will Deacon | 4da7a56 | 2013-11-06 19:31:24 +0000 | [diff] [blame] | 41 | " .align 2\n" \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 42 | "4: mov %w0, %w5\n" \ |
| 43 | " b 3b\n" \ |
| 44 | " .popsection\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame^] | 45 | _ASM_EXTABLE(1b, 4b) \ |
| 46 | _ASM_EXTABLE(2b, 4b) \ |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 47 | ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, \ |
| 48 | CONFIG_ARM64_PAN) \ |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 49 | : "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \ |
| 50 | : "r" (oparg), "Ir" (-EFAULT) \ |
Will Deacon | 95c4189 | 2014-02-04 12:29:13 +0000 | [diff] [blame] | 51 | : "memory") |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 52 | |
| 53 | static inline int |
| 54 | futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr) |
| 55 | { |
| 56 | int op = (encoded_op >> 28) & 7; |
| 57 | int cmp = (encoded_op >> 24) & 15; |
| 58 | int oparg = (encoded_op << 8) >> 20; |
| 59 | int cmparg = (encoded_op << 20) >> 20; |
| 60 | int oldval = 0, ret, tmp; |
| 61 | |
| 62 | if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) |
| 63 | oparg = 1 << oparg; |
| 64 | |
| 65 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
| 66 | return -EFAULT; |
| 67 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 68 | pagefault_disable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 69 | |
| 70 | switch (op) { |
| 71 | case FUTEX_OP_SET: |
| 72 | __futex_atomic_op("mov %w0, %w4", |
| 73 | ret, oldval, uaddr, tmp, oparg); |
| 74 | break; |
| 75 | case FUTEX_OP_ADD: |
| 76 | __futex_atomic_op("add %w0, %w1, %w4", |
| 77 | ret, oldval, uaddr, tmp, oparg); |
| 78 | break; |
| 79 | case FUTEX_OP_OR: |
| 80 | __futex_atomic_op("orr %w0, %w1, %w4", |
| 81 | ret, oldval, uaddr, tmp, oparg); |
| 82 | break; |
| 83 | case FUTEX_OP_ANDN: |
| 84 | __futex_atomic_op("and %w0, %w1, %w4", |
| 85 | ret, oldval, uaddr, tmp, ~oparg); |
| 86 | break; |
| 87 | case FUTEX_OP_XOR: |
| 88 | __futex_atomic_op("eor %w0, %w1, %w4", |
| 89 | ret, oldval, uaddr, tmp, oparg); |
| 90 | break; |
| 91 | default: |
| 92 | ret = -ENOSYS; |
| 93 | } |
| 94 | |
David Hildenbrand | 2f09b22 | 2015-05-11 17:52:17 +0200 | [diff] [blame] | 95 | pagefault_enable(); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 96 | |
| 97 | if (!ret) { |
| 98 | switch (cmp) { |
| 99 | case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break; |
| 100 | case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break; |
| 101 | case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break; |
| 102 | case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break; |
| 103 | case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break; |
| 104 | case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break; |
| 105 | default: ret = -ENOSYS; |
| 106 | } |
| 107 | } |
| 108 | return ret; |
| 109 | } |
| 110 | |
| 111 | static inline int |
| 112 | futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
| 113 | u32 oldval, u32 newval) |
| 114 | { |
| 115 | int ret = 0; |
| 116 | u32 val, tmp; |
| 117 | |
| 118 | if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
| 119 | return -EFAULT; |
| 120 | |
| 121 | asm volatile("// futex_atomic_cmpxchg_inatomic\n" |
James Morse | 811d61e | 2016-02-02 15:53:59 +0000 | [diff] [blame] | 122 | ALTERNATIVE("nop", SET_PSTATE_PAN(0), ARM64_HAS_PAN, CONFIG_ARM64_PAN) |
Will Deacon | 0ea366f | 2015-05-29 13:31:10 +0100 | [diff] [blame] | 123 | " prfm pstl1strm, %2\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 124 | "1: ldxr %w1, %2\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 125 | " sub %w3, %w1, %w4\n" |
| 126 | " cbnz %w3, 3f\n" |
| 127 | "2: stlxr %w3, %w5, %2\n" |
| 128 | " cbnz %w3, 1b\n" |
Will Deacon | 8e86f0b | 2014-02-04 12:29:12 +0000 | [diff] [blame] | 129 | " dmb ish\n" |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 130 | "3:\n" |
| 131 | " .pushsection .fixup,\"ax\"\n" |
| 132 | "4: mov %w0, %w6\n" |
| 133 | " b 3b\n" |
| 134 | " .popsection\n" |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame^] | 135 | _ASM_EXTABLE(1b, 4b) |
| 136 | _ASM_EXTABLE(2b, 4b) |
James Morse | 811d61e | 2016-02-02 15:53:59 +0000 | [diff] [blame] | 137 | ALTERNATIVE("nop", SET_PSTATE_PAN(1), ARM64_HAS_PAN, CONFIG_ARM64_PAN) |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 138 | : "+r" (ret), "=&r" (val), "+Q" (*uaddr), "=&r" (tmp) |
| 139 | : "r" (oldval), "r" (newval), "Ir" (-EFAULT) |
Will Deacon | 95c4189 | 2014-02-04 12:29:13 +0000 | [diff] [blame] | 140 | : "memory"); |
Catalin Marinas | 6170a97 | 2012-03-05 11:49:29 +0000 | [diff] [blame] | 141 | |
| 142 | *uval = val; |
| 143 | return ret; |
| 144 | } |
| 145 | |
| 146 | #endif /* __KERNEL__ */ |
| 147 | #endif /* __ASM_FUTEX_H */ |