Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2 | * MPC85XX common board code |
| 3 | * |
Kumar Gala | 4c8d3d9 | 2005-11-13 16:06:30 -0800 | [diff] [blame] | 4 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 5 | * |
| 6 | * Copyright 2004 Freescale Semiconductor Inc. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | */ |
| 13 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/types.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/pci.h> |
| 18 | #include <linux/serial.h> |
| 19 | #include <linux/tty.h> /* for linux/serial_core.h */ |
| 20 | #include <linux/serial_core.h> |
| 21 | #include <linux/serial_8250.h> |
| 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include <asm/time.h> |
| 24 | #include <asm/mpc85xx.h> |
| 25 | #include <asm/immap_85xx.h> |
| 26 | #include <asm/mmu.h> |
| 27 | #include <asm/ppc_sys.h> |
| 28 | #include <asm/kgdb.h> |
Paul Mackerras | fd582ec | 2005-10-11 22:08:12 +1000 | [diff] [blame] | 29 | #include <asm/machdep.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | |
| 31 | #include <syslib/ppc85xx_setup.h> |
| 32 | |
Kumar Gala | ba8c6d5 | 2005-06-21 17:15:28 -0700 | [diff] [blame] | 33 | extern void abort(void); |
| 34 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 35 | /* Return the amount of memory */ |
| 36 | unsigned long __init |
| 37 | mpc85xx_find_end_of_memory(void) |
| 38 | { |
| 39 | bd_t *binfo; |
| 40 | |
| 41 | binfo = (bd_t *) __res; |
| 42 | |
| 43 | return binfo->bi_memsize; |
| 44 | } |
| 45 | |
| 46 | /* The decrementer counts at the system (internal) clock freq divided by 8 */ |
| 47 | void __init |
| 48 | mpc85xx_calibrate_decr(void) |
| 49 | { |
| 50 | bd_t *binfo = (bd_t *) __res; |
| 51 | unsigned int freq, divisor; |
| 52 | |
| 53 | /* get the core frequency */ |
| 54 | freq = binfo->bi_busfreq; |
| 55 | |
| 56 | /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */ |
| 57 | divisor = 8; |
| 58 | tb_ticks_per_jiffy = freq / divisor / HZ; |
| 59 | tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000); |
| 60 | |
| 61 | /* Set the time base to zero */ |
| 62 | mtspr(SPRN_TBWL, 0); |
| 63 | mtspr(SPRN_TBWU, 0); |
| 64 | |
| 65 | /* Clear any pending timer interrupts */ |
| 66 | mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS); |
| 67 | |
| 68 | /* Enable decrementer interrupt */ |
| 69 | mtspr(SPRN_TCR, TCR_DIE); |
| 70 | } |
| 71 | |
| 72 | #ifdef CONFIG_SERIAL_8250 |
| 73 | void __init |
| 74 | mpc85xx_early_serial_map(void) |
| 75 | { |
| 76 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 77 | struct uart_port serial_req; |
| 78 | #endif |
| 79 | struct plat_serial8250_port *pdata; |
| 80 | bd_t *binfo = (bd_t *) __res; |
| 81 | pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART); |
| 82 | |
| 83 | /* Setup serial port access */ |
| 84 | pdata[0].uartclk = binfo->bi_busfreq; |
| 85 | pdata[0].mapbase += binfo->bi_immr_base; |
| 86 | pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE); |
| 87 | |
| 88 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 89 | memset(&serial_req, 0, sizeof (serial_req)); |
Russell King | 9b4a161 | 2006-02-05 10:48:10 +0000 | [diff] [blame] | 90 | serial_req.iotype = UPIO_MEM; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | serial_req.mapbase = pdata[0].mapbase; |
| 92 | serial_req.membase = pdata[0].membase; |
| 93 | serial_req.regshift = 0; |
| 94 | |
| 95 | gen550_init(0, &serial_req); |
| 96 | #endif |
| 97 | |
| 98 | pdata[1].uartclk = binfo->bi_busfreq; |
| 99 | pdata[1].mapbase += binfo->bi_immr_base; |
| 100 | pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE); |
| 101 | |
| 102 | #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB) |
| 103 | /* Assume gen550_init() doesn't modify serial_req */ |
| 104 | serial_req.mapbase = pdata[1].mapbase; |
| 105 | serial_req.membase = pdata[1].membase; |
| 106 | |
| 107 | gen550_init(1, &serial_req); |
| 108 | #endif |
| 109 | } |
| 110 | #endif |
| 111 | |
| 112 | void |
| 113 | mpc85xx_restart(char *cmd) |
| 114 | { |
| 115 | local_irq_disable(); |
| 116 | abort(); |
| 117 | } |
| 118 | |
| 119 | void |
| 120 | mpc85xx_power_off(void) |
| 121 | { |
| 122 | local_irq_disable(); |
| 123 | for(;;); |
| 124 | } |
| 125 | |
| 126 | void |
| 127 | mpc85xx_halt(void) |
| 128 | { |
| 129 | local_irq_disable(); |
| 130 | for(;;); |
| 131 | } |
| 132 | |
| 133 | #ifdef CONFIG_PCI |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 134 | |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 135 | #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 136 | extern void mpc85xx_cds_enable_via(struct pci_controller *hose); |
| 137 | extern void mpc85xx_cds_fixup_via(struct pci_controller *hose); |
| 138 | #endif |
| 139 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | static void __init |
| 141 | mpc85xx_setup_pci1(struct pci_controller *hose) |
| 142 | { |
| 143 | volatile struct ccsr_pci *pci; |
| 144 | volatile struct ccsr_guts *guts; |
| 145 | unsigned short temps; |
| 146 | bd_t *binfo = (bd_t *) __res; |
| 147 | |
| 148 | pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET, |
| 149 | MPC85xx_PCI1_SIZE); |
| 150 | |
| 151 | guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET, |
| 152 | MPC85xx_GUTS_SIZE); |
| 153 | |
| 154 | early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps); |
| 155 | temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 156 | early_write_config_word(hose, 0, 0, PCI_COMMAND, temps); |
| 157 | |
| 158 | #define PORDEVSR_PCI (0x00800000) /* PCI Mode */ |
| 159 | if (guts->pordevsr & PORDEVSR_PCI) { |
| 160 | early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); |
| 161 | } else { |
| 162 | /* PCI-X init */ |
| 163 | temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
| 164 | | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; |
| 165 | early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps); |
| 166 | } |
| 167 | |
| 168 | /* Disable all windows (except powar0 since its ignored) */ |
| 169 | pci->powar1 = 0; |
| 170 | pci->powar2 = 0; |
| 171 | pci->powar3 = 0; |
| 172 | pci->powar4 = 0; |
| 173 | pci->piwar1 = 0; |
| 174 | pci->piwar2 = 0; |
| 175 | pci->piwar3 = 0; |
| 176 | |
| 177 | /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */ |
| 178 | pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff; |
| 179 | pci->potear1 = 0x00000000; |
| 180 | pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff; |
| 181 | /* Enable, Mem R/W */ |
| 182 | pci->powar1 = 0x80044000 | |
| 183 | (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1); |
| 184 | |
Kumar Gala | 3fd07d3 | 2005-09-21 23:54:58 -0500 | [diff] [blame] | 185 | /* Setup outbound IO windows @ MPC85XX_PCI1_IO_BASE */ |
| 186 | pci->potar2 = (MPC85XX_PCI1_LOWER_IO >> 12) & 0x000fffff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 187 | pci->potear2 = 0x00000000; |
| 188 | pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff; |
| 189 | /* Enable, IO R/W */ |
| 190 | pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1); |
| 191 | |
| 192 | /* Setup 2G inbound Memory Window @ 0 */ |
| 193 | pci->pitar1 = 0x00000000; |
| 194 | pci->piwbar1 = 0x00000000; |
| 195 | pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local |
| 196 | Mem, Snoop R/W, 2G */ |
| 197 | } |
| 198 | |
| 199 | |
| 200 | extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin); |
| 201 | extern int mpc85xx_exclude_device(u_char bus, u_char devfn); |
| 202 | |
| 203 | #ifdef CONFIG_85xx_PCI2 |
| 204 | static void __init |
| 205 | mpc85xx_setup_pci2(struct pci_controller *hose) |
| 206 | { |
| 207 | volatile struct ccsr_pci *pci; |
| 208 | unsigned short temps; |
| 209 | bd_t *binfo = (bd_t *) __res; |
| 210 | |
| 211 | pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET, |
| 212 | MPC85xx_PCI2_SIZE); |
| 213 | |
| 214 | early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps); |
| 215 | temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; |
| 216 | early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps); |
| 217 | early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80); |
| 218 | |
| 219 | /* Disable all windows (except powar0 since its ignored) */ |
| 220 | pci->powar1 = 0; |
| 221 | pci->powar2 = 0; |
| 222 | pci->powar3 = 0; |
| 223 | pci->powar4 = 0; |
| 224 | pci->piwar1 = 0; |
| 225 | pci->piwar2 = 0; |
| 226 | pci->piwar3 = 0; |
| 227 | |
| 228 | /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */ |
| 229 | pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff; |
| 230 | pci->potear1 = 0x00000000; |
| 231 | pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff; |
| 232 | /* Enable, Mem R/W */ |
| 233 | pci->powar1 = 0x80044000 | |
Kumar Gala | 1273845 | 2005-07-27 11:44:10 -0700 | [diff] [blame] | 234 | (__ilog2(MPC85XX_PCI2_UPPER_MEM - MPC85XX_PCI2_LOWER_MEM + 1) - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | |
Kumar Gala | 3fd07d3 | 2005-09-21 23:54:58 -0500 | [diff] [blame] | 236 | /* Setup outbound IO windows @ MPC85XX_PCI2_IO_BASE */ |
Alexey Dobriyan | 53b3531 | 2006-03-24 03:16:13 -0800 | [diff] [blame] | 237 | pci->potar2 = (MPC85XX_PCI2_LOWER_IO >> 12) & 0x000fffff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | pci->potear2 = 0x00000000; |
| 239 | pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff; |
| 240 | /* Enable, IO R/W */ |
Kumar Gala | 1273845 | 2005-07-27 11:44:10 -0700 | [diff] [blame] | 241 | pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI2_IO_SIZE) - 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | |
| 243 | /* Setup 2G inbound Memory Window @ 0 */ |
| 244 | pci->pitar1 = 0x00000000; |
| 245 | pci->piwbar1 = 0x00000000; |
| 246 | pci->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local |
| 247 | Mem, Snoop R/W, 2G */ |
| 248 | } |
| 249 | #endif /* CONFIG_85xx_PCI2 */ |
| 250 | |
| 251 | int mpc85xx_pci1_last_busno = 0; |
| 252 | |
| 253 | void __init |
| 254 | mpc85xx_setup_hose(void) |
| 255 | { |
| 256 | struct pci_controller *hose_a; |
| 257 | #ifdef CONFIG_85xx_PCI2 |
| 258 | struct pci_controller *hose_b; |
| 259 | #endif |
| 260 | bd_t *binfo = (bd_t *) __res; |
| 261 | |
| 262 | hose_a = pcibios_alloc_controller(); |
| 263 | |
| 264 | if (!hose_a) |
| 265 | return; |
| 266 | |
| 267 | ppc_md.pci_swizzle = common_swizzle; |
| 268 | ppc_md.pci_map_irq = mpc85xx_map_irq; |
| 269 | |
| 270 | hose_a->first_busno = 0; |
| 271 | hose_a->bus_offset = 0; |
| 272 | hose_a->last_busno = 0xff; |
| 273 | |
| 274 | setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET, |
| 275 | binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET); |
| 276 | hose_a->set_cfg_type = 1; |
| 277 | |
| 278 | mpc85xx_setup_pci1(hose_a); |
| 279 | |
| 280 | hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET; |
| 281 | hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM; |
| 282 | hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM; |
| 283 | |
| 284 | hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO; |
| 285 | hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO; |
| 286 | hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE; |
| 287 | #ifdef CONFIG_85xx_PCI2 |
Al Viro | 92a11f9 | 2005-04-25 07:55:57 -0700 | [diff] [blame] | 288 | hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 289 | MPC85XX_PCI1_IO_SIZE + |
| 290 | MPC85XX_PCI2_IO_SIZE); |
| 291 | #else |
Al Viro | 92a11f9 | 2005-04-25 07:55:57 -0700 | [diff] [blame] | 292 | hose_a->io_base_virt = ioremap(MPC85XX_PCI1_IO_BASE, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | MPC85XX_PCI1_IO_SIZE); |
| 294 | #endif |
Al Viro | 92a11f9 | 2005-04-25 07:55:57 -0700 | [diff] [blame] | 295 | isa_io_base = (unsigned long)hose_a->io_base_virt; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
| 297 | /* setup resources */ |
| 298 | pci_init_resource(&hose_a->mem_resources[0], |
| 299 | MPC85XX_PCI1_LOWER_MEM, |
| 300 | MPC85XX_PCI1_UPPER_MEM, |
| 301 | IORESOURCE_MEM, "PCI1 host bridge"); |
| 302 | |
| 303 | pci_init_resource(&hose_a->io_resource, |
| 304 | MPC85XX_PCI1_LOWER_IO, |
| 305 | MPC85XX_PCI1_UPPER_IO, |
| 306 | IORESOURCE_IO, "PCI1 host bridge"); |
| 307 | |
| 308 | ppc_md.pci_exclude_device = mpc85xx_exclude_device; |
| 309 | |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 310 | #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 311 | /* Pre pciauto_bus_scan VIA init */ |
| 312 | mpc85xx_cds_enable_via(hose_a); |
| 313 | #endif |
| 314 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 315 | hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno); |
| 316 | |
Kumar Gala | c91999b | 2005-06-21 17:15:19 -0700 | [diff] [blame] | 317 | #if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS) |
Kumar Gala | ed36959 | 2005-05-28 15:52:07 -0700 | [diff] [blame] | 318 | /* Post pciauto_bus_scan VIA fixup */ |
| 319 | mpc85xx_cds_fixup_via(hose_a); |
| 320 | #endif |
| 321 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 322 | #ifdef CONFIG_85xx_PCI2 |
| 323 | hose_b = pcibios_alloc_controller(); |
| 324 | |
| 325 | if (!hose_b) |
| 326 | return; |
| 327 | |
| 328 | hose_b->bus_offset = hose_a->last_busno + 1; |
| 329 | hose_b->first_busno = hose_a->last_busno + 1; |
| 330 | hose_b->last_busno = 0xff; |
| 331 | |
| 332 | setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET, |
| 333 | binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET); |
| 334 | hose_b->set_cfg_type = 1; |
| 335 | |
| 336 | mpc85xx_setup_pci2(hose_b); |
| 337 | |
| 338 | hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET; |
| 339 | hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM; |
| 340 | hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM; |
| 341 | |
| 342 | hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO; |
| 343 | hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO; |
| 344 | hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE; |
Al Viro | 92a11f9 | 2005-04-25 07:55:57 -0700 | [diff] [blame] | 345 | hose_b->io_base_virt = hose_a->io_base_virt + MPC85XX_PCI1_IO_SIZE; |
| 346 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | /* setup resources */ |
| 348 | pci_init_resource(&hose_b->mem_resources[0], |
| 349 | MPC85XX_PCI2_LOWER_MEM, |
| 350 | MPC85XX_PCI2_UPPER_MEM, |
| 351 | IORESOURCE_MEM, "PCI2 host bridge"); |
| 352 | |
| 353 | pci_init_resource(&hose_b->io_resource, |
| 354 | MPC85XX_PCI2_LOWER_IO, |
| 355 | MPC85XX_PCI2_UPPER_IO, |
| 356 | IORESOURCE_IO, "PCI2 host bridge"); |
| 357 | |
| 358 | hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno); |
| 359 | |
| 360 | /* let board code know what the last bus number was on PCI1 */ |
| 361 | mpc85xx_pci1_last_busno = hose_a->last_busno; |
| 362 | #endif |
| 363 | return; |
| 364 | } |
| 365 | #endif /* CONFIG_PCI */ |
| 366 | |
| 367 | |