blob: 80a963d64e58c143db789743d664e998c9e1ee66 [file] [log] [blame]
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03001/* Intel i7 core/Nehalem Memory Controller kernel module
2 *
David Sterbae7bf0682010-12-27 16:51:15 +01003 * This driver supports the memory controllers found on the Intel
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -03004 * processor families i7core, i7core 7xx/8xx, i5core, Xeon 35xx,
5 * Xeon 55xx and Xeon 56xx also known as Nehalem, Nehalem-EP, Lynnfield
6 * and Westmere-EP.
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03007 *
8 * This file may be distributed under the terms of the
9 * GNU General Public License version 2 only.
10 *
Mauro Carvalho Chehab52707f92010-05-18 20:43:52 -030011 * Copyright (c) 2009-2010 by:
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030012 * Mauro Carvalho Chehab <mchehab@redhat.com>
13 *
14 * Red Hat Inc. http://www.redhat.com
15 *
16 * Forked and adapted from the i5400_edac driver
17 *
18 * Based on the following public Intel datasheets:
19 * Intel Core i7 Processor Extreme Edition and Intel Core i7 Processor
20 * Datasheet, Volume 2:
21 * http://download.intel.com/design/processor/datashts/320835.pdf
22 * Intel Xeon Processor 5500 Series Datasheet Volume 2
23 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
24 * also available at:
25 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
26 */
27
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030028#include <linux/module.h>
29#include <linux/init.h>
30#include <linux/pci.h>
31#include <linux/pci_ids.h>
32#include <linux/slab.h>
Randy Dunlap3b918c12009-11-08 01:36:40 -020033#include <linux/delay.h>
Nils Carlson535e9c72011-08-08 06:21:26 -030034#include <linux/dmi.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030035#include <linux/edac.h>
36#include <linux/mmzone.h>
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030037#include <linux/smp.h>
Borislav Petkov4140c542011-07-18 11:24:46 -030038#include <asm/mce.h>
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -030039#include <asm/processor.h>
Sedat Dilek4fad8092011-09-21 23:44:52 -030040#include <asm/div64.h>
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030041
42#include "edac_core.h"
43
Mauro Carvalho Chehab18c29002010-08-10 18:33:27 -030044/* Static vars */
45static LIST_HEAD(i7core_edac_list);
46static DEFINE_MUTEX(i7core_edac_lock);
47static int probed;
48
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -030049static int use_pci_fixup;
50module_param(use_pci_fixup, int, 0444);
51MODULE_PARM_DESC(use_pci_fixup, "Enable PCI fixup to seek for hidden devices");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030052/*
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -030053 * This is used for Nehalem-EP and Nehalem-EX devices, where the non-core
54 * registers start at bus 255, and are not reported by BIOS.
55 * We currently find devices with only 2 sockets. In order to support more QPI
56 * Quick Path Interconnect, just increment this number.
57 */
58#define MAX_SOCKET_BUSES 2
59
60
61/*
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030062 * Alter this version for the module when modifications are made
63 */
Michal Marek152ba392011-04-01 12:41:20 +020064#define I7CORE_REVISION " Ver: 1.0.0"
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030065#define EDAC_MOD_STR "i7core_edac"
66
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030067/*
68 * Debug macros
69 */
70#define i7core_printk(level, fmt, arg...) \
71 edac_printk(level, "i7core", fmt, ##arg)
72
73#define i7core_mc_printk(mci, level, fmt, arg...) \
74 edac_mc_chipset_printk(mci, level, "i7core", fmt, ##arg)
75
76/*
77 * i7core Memory Controller Registers
78 */
79
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030080 /* OFFSETS for Device 0 Function 0 */
81
82#define MC_CFG_CONTROL 0x90
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -030083 #define MC_CFG_UNLOCK 0x02
84 #define MC_CFG_LOCK 0x00
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -030085
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -030086 /* OFFSETS for Device 3 Function 0 */
87
88#define MC_CONTROL 0x48
89#define MC_STATUS 0x4c
90#define MC_MAX_DOD 0x64
91
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030092/*
David Mackey15ed1032012-04-17 11:30:52 -070093 * OFFSETS for Device 3 Function 4, as indicated on Xeon 5500 datasheet:
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -030094 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
95 */
96
97#define MC_TEST_ERR_RCV1 0x60
98 #define DIMM2_COR_ERR(r) ((r) & 0x7fff)
99
100#define MC_TEST_ERR_RCV0 0x64
101 #define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
102 #define DIMM0_COR_ERR(r) ((r) & 0x7fff)
103
David Mackey15ed1032012-04-17 11:30:52 -0700104/* OFFSETS for Device 3 Function 2, as indicated on Xeon 5500 datasheet */
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300105#define MC_SSRCONTROL 0x48
106 #define SSR_MODE_DISABLE 0x00
107 #define SSR_MODE_ENABLE 0x01
108 #define SSR_MODE_MASK 0x03
109
110#define MC_SCRUB_CONTROL 0x4c
111 #define STARTSCRUB (1 << 24)
Nils Carlson535e9c72011-08-08 06:21:26 -0300112 #define SCRUBINTERVAL_MASK 0xffffff
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -0300113
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300114#define MC_COR_ECC_CNT_0 0x80
115#define MC_COR_ECC_CNT_1 0x84
116#define MC_COR_ECC_CNT_2 0x88
117#define MC_COR_ECC_CNT_3 0x8c
118#define MC_COR_ECC_CNT_4 0x90
119#define MC_COR_ECC_CNT_5 0x94
120
121#define DIMM_TOP_COR_ERR(r) (((r) >> 16) & 0x7fff)
122#define DIMM_BOT_COR_ERR(r) ((r) & 0x7fff)
123
124
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300125 /* OFFSETS for Devices 4,5 and 6 Function 0 */
126
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300127#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
128 #define THREE_DIMMS_PRESENT (1 << 24)
129 #define SINGLE_QUAD_RANK_PRESENT (1 << 23)
130 #define QUAD_RANK_PRESENT (1 << 22)
131 #define REGISTERED_DIMM (1 << 15)
132
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300133#define MC_CHANNEL_MAPPER 0x60
134 #define RDLCH(r, ch) ((((r) >> (3 + (ch * 6))) & 0x07) - 1)
135 #define WRLCH(r, ch) ((((r) >> (ch * 6)) & 0x07) - 1)
136
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300137#define MC_CHANNEL_RANK_PRESENT 0x7c
138 #define RANK_PRESENT_MASK 0xffff
139
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300140#define MC_CHANNEL_ADDR_MATCH 0xf0
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300141#define MC_CHANNEL_ERROR_MASK 0xf8
142#define MC_CHANNEL_ERROR_INJECT 0xfc
143 #define INJECT_ADDR_PARITY 0x10
144 #define INJECT_ECC 0x08
145 #define MASK_CACHELINE 0x06
146 #define MASK_FULL_CACHELINE 0x06
147 #define MASK_MSB32_CACHELINE 0x04
148 #define MASK_LSB32_CACHELINE 0x02
149 #define NO_MASK_CACHELINE 0x00
150 #define REPEAT_EN 0x01
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300151
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300152 /* OFFSETS for Devices 4,5 and 6 Function 1 */
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300153
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300154#define MC_DOD_CH_DIMM0 0x48
155#define MC_DOD_CH_DIMM1 0x4c
156#define MC_DOD_CH_DIMM2 0x50
157 #define RANKOFFSET_MASK ((1 << 12) | (1 << 11) | (1 << 10))
158 #define RANKOFFSET(x) ((x & RANKOFFSET_MASK) >> 10)
159 #define DIMM_PRESENT_MASK (1 << 9)
160 #define DIMM_PRESENT(x) (((x) & DIMM_PRESENT_MASK) >> 9)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300161 #define MC_DOD_NUMBANK_MASK ((1 << 8) | (1 << 7))
162 #define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
163 #define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
164 #define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300165 #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300166 #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300167 #define MC_DOD_NUMCOL_MASK 3
168 #define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300169
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300170#define MC_RANK_PRESENT 0x7c
171
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300172#define MC_SAG_CH_0 0x80
173#define MC_SAG_CH_1 0x84
174#define MC_SAG_CH_2 0x88
175#define MC_SAG_CH_3 0x8c
176#define MC_SAG_CH_4 0x90
177#define MC_SAG_CH_5 0x94
178#define MC_SAG_CH_6 0x98
179#define MC_SAG_CH_7 0x9c
180
181#define MC_RIR_LIMIT_CH_0 0x40
182#define MC_RIR_LIMIT_CH_1 0x44
183#define MC_RIR_LIMIT_CH_2 0x48
184#define MC_RIR_LIMIT_CH_3 0x4C
185#define MC_RIR_LIMIT_CH_4 0x50
186#define MC_RIR_LIMIT_CH_5 0x54
187#define MC_RIR_LIMIT_CH_6 0x58
188#define MC_RIR_LIMIT_CH_7 0x5C
189#define MC_RIR_LIMIT_MASK ((1 << 10) - 1)
190
191#define MC_RIR_WAY_CH 0x80
192 #define MC_RIR_WAY_OFFSET_MASK (((1 << 14) - 1) & ~0x7)
193 #define MC_RIR_WAY_RANK_MASK 0x7
194
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300195/*
196 * i7core structs
197 */
198
199#define NUM_CHANS 3
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300200#define MAX_DIMMS 3 /* Max DIMMS per channel */
201#define MAX_MCR_FUNC 4
202#define MAX_CHAN_FUNC 3
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300203
204struct i7core_info {
205 u32 mc_control;
206 u32 mc_status;
207 u32 max_dod;
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300208 u32 ch_map;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300209};
210
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300211
212struct i7core_inject {
213 int enable;
214
215 u32 section;
216 u32 type;
217 u32 eccmask;
218
219 /* Error address mask */
220 int channel, dimm, rank, bank, page, col;
221};
222
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300223struct i7core_channel {
Mauro Carvalho Chehab0bf09e82012-04-26 11:47:29 -0300224 bool is_3dimms_present;
225 bool is_single_4rank;
226 bool has_4rank;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300227 u32 dimms;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300228};
229
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300230struct pci_id_descr {
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300231 int dev;
232 int func;
233 int dev_id;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300234 int optional;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300235};
236
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300237struct pci_id_table {
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300238 const struct pci_id_descr *descr;
239 int n_devs;
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300240};
241
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300242struct i7core_dev {
243 struct list_head list;
244 u8 socket;
245 struct pci_dev **pdev;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300246 int n_devs;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300247 struct mem_ctl_info *mci;
248};
249
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300250struct i7core_pvt {
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -0300251 struct device *addrmatch_dev, *chancounts_dev;
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300252
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300253 struct pci_dev *pci_noncore;
254 struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
255 struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
256
257 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300258
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300259 struct i7core_info info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300260 struct i7core_inject inject;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300261 struct i7core_channel channel[NUM_CHANS];
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -0300262
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300263 int ce_count_available;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300264
265 /* ECC corrected errors counts per udimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300266 unsigned long udimm_ce_count[MAX_DIMMS];
267 int udimm_last_ce_count[MAX_DIMMS];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300268 /* ECC corrected errors counts per rdimm */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300269 unsigned long rdimm_ce_count[NUM_CHANS][MAX_DIMMS];
270 int rdimm_last_ce_count[NUM_CHANS][MAX_DIMMS];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -0300271
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -0300272 bool is_registered, enable_scrub;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300273
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300274 /* Fifo double buffers */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -0300275 struct mce mce_entry[MCE_LOG_LEN];
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -0300276 struct mce mce_outentry[MCE_LOG_LEN];
277
278 /* Fifo in/out counters */
279 unsigned mce_in, mce_out;
280
281 /* Count indicator to show errors not got */
282 unsigned mce_overrun;
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300283
Nils Carlson535e9c72011-08-08 06:21:26 -0300284 /* DCLK Frequency used for computing scrub rate */
285 int dclk_freq;
286
Mauro Carvalho Chehab939747bd2010-08-10 11:22:01 -0300287 /* Struct to control EDAC polling */
288 struct edac_pci_ctl_info *i7core_pci;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300289};
290
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300291#define PCI_DESCR(device, function, device_id) \
292 .dev = (device), \
293 .func = (function), \
294 .dev_id = (device_id)
295
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300296static const struct pci_id_descr pci_dev_descr_i7core_nehalem[] = {
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300297 /* Memory controller */
298 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_I7_MCR) },
299 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_I7_MC_TAD) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300300 /* Exists only for RDIMM */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -0300301 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_I7_MC_RAS), .optional = 1 },
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300302 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_I7_MC_TEST) },
303
304 /* Channel 0 */
305 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH0_CTRL) },
306 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH0_ADDR) },
307 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH0_RANK) },
308 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH0_TC) },
309
310 /* Channel 1 */
311 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH1_CTRL) },
312 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH1_ADDR) },
313 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH1_RANK) },
314 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH1_TC) },
315
316 /* Channel 2 */
317 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_I7_MC_CH2_CTRL) },
318 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR) },
319 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK) },
320 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300321
322 /* Generic Non-core registers */
323 /*
324 * This is the PCI device on i7core and on Xeon 35xx (8086:2c41)
325 * On Xeon 55xx, however, it has a different id (8086:2c40). So,
326 * the probing code needs to test for the other address in case of
327 * failure of this one
328 */
329 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_I7_NONCORE) },
330
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300331};
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300332
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300333static const struct pci_id_descr pci_dev_descr_lynnfield[] = {
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300334 { PCI_DESCR( 3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR) },
335 { PCI_DESCR( 3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD) },
336 { PCI_DESCR( 3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST) },
337
338 { PCI_DESCR( 4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL) },
339 { PCI_DESCR( 4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR) },
340 { PCI_DESCR( 4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK) },
341 { PCI_DESCR( 4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC) },
342
Mauro Carvalho Chehab508fa172009-10-14 13:44:37 -0300343 { PCI_DESCR( 5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL) },
344 { PCI_DESCR( 5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR) },
345 { PCI_DESCR( 5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK) },
346 { PCI_DESCR( 5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300347
348 /*
349 * This is the PCI device has an alternate address on some
350 * processors like Core i7 860
351 */
352 { PCI_DESCR( 0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE) },
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300353};
354
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300355static const struct pci_id_descr pci_dev_descr_i7core_westmere[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300356 /* Memory controller */
357 { PCI_DESCR(3, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MCR_REV2) },
358 { PCI_DESCR(3, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TAD_REV2) },
359 /* Exists only for RDIMM */
360 { PCI_DESCR(3, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_RAS_REV2), .optional = 1 },
361 { PCI_DESCR(3, 4, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_TEST_REV2) },
362
363 /* Channel 0 */
364 { PCI_DESCR(4, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_CTRL_REV2) },
365 { PCI_DESCR(4, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_ADDR_REV2) },
366 { PCI_DESCR(4, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_RANK_REV2) },
367 { PCI_DESCR(4, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH0_TC_REV2) },
368
369 /* Channel 1 */
370 { PCI_DESCR(5, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_CTRL_REV2) },
371 { PCI_DESCR(5, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_ADDR_REV2) },
372 { PCI_DESCR(5, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_RANK_REV2) },
373 { PCI_DESCR(5, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH1_TC_REV2) },
374
375 /* Channel 2 */
376 { PCI_DESCR(6, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_CTRL_REV2) },
377 { PCI_DESCR(6, 1, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2) },
378 { PCI_DESCR(6, 2, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2) },
379 { PCI_DESCR(6, 3, PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2) },
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -0300380
381 /* Generic Non-core registers */
382 { PCI_DESCR(0, 0, PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2) },
383
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300384};
385
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300386#define PCI_ID_TABLE_ENTRY(A) { .descr=A, .n_devs = ARRAY_SIZE(A) }
387static const struct pci_id_table pci_dev_table[] = {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300388 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_nehalem),
389 PCI_ID_TABLE_ENTRY(pci_dev_descr_lynnfield),
390 PCI_ID_TABLE_ENTRY(pci_dev_descr_i7core_westmere),
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -0200391 {0,} /* 0 terminated list. */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -0300392};
393
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300394/*
395 * pci_device_id table for which devices we are looking for
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300396 */
Lionel Debroux36c46f32012-02-27 07:41:47 +0100397static DEFINE_PCI_DEVICE_TABLE(i7core_pci_tbl) = {
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -0300398 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58_HUB_MGMT)},
Mauro Carvalho Chehabf05da2f2009-10-14 13:31:06 -0300399 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNNFIELD_QPI_LINK0)},
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300400 {0,} /* 0 terminated list. */
401};
402
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300403/****************************************************************************
David Mackey15ed1032012-04-17 11:30:52 -0700404 Ancillary status routines
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300405 ****************************************************************************/
406
407 /* MC_CONTROL bits */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300408#define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
409#define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300410
411 /* MC_STATUS bits */
Keith Mannthey61053fd2009-09-02 23:46:59 -0300412#define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300413#define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300414
415 /* MC_MAX_DOD read functions */
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300416static inline int numdimms(u32 dimms)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300417{
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300418 return (dimms & 0x3) + 1;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300419}
420
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300421static inline int numrank(u32 rank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300422{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100423 static const int ranks[] = { 1, 2, 4, -EINVAL };
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300424
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300425 return ranks[rank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300426}
427
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300428static inline int numbank(u32 bank)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300429{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100430 static const int banks[] = { 4, 8, 16, -EINVAL };
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300431
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300432 return banks[bank & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300433}
434
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300435static inline int numrow(u32 row)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300436{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100437 static const int rows[] = {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300438 1 << 12, 1 << 13, 1 << 14, 1 << 15,
439 1 << 16, -EINVAL, -EINVAL, -EINVAL,
440 };
441
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300442 return rows[row & 0x7];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300443}
444
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300445static inline int numcol(u32 col)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300446{
Niklas Söderlundc31d34f2012-01-29 23:04:32 +0100447 static const int cols[] = {
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300448 1 << 10, 1 << 11, 1 << 12, -EINVAL,
449 };
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300450 return cols[col & 0x3];
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300451}
452
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300453static struct i7core_dev *get_i7core_dev(u8 socket)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -0300454{
455 struct i7core_dev *i7core_dev;
456
457 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
458 if (i7core_dev->socket == socket)
459 return i7core_dev;
460 }
461
462 return NULL;
463}
464
Hidetoshi Seto848b2f72010-08-20 04:24:44 -0300465static struct i7core_dev *alloc_i7core_dev(u8 socket,
466 const struct pci_id_table *table)
467{
468 struct i7core_dev *i7core_dev;
469
470 i7core_dev = kzalloc(sizeof(*i7core_dev), GFP_KERNEL);
471 if (!i7core_dev)
472 return NULL;
473
474 i7core_dev->pdev = kzalloc(sizeof(*i7core_dev->pdev) * table->n_devs,
475 GFP_KERNEL);
476 if (!i7core_dev->pdev) {
477 kfree(i7core_dev);
478 return NULL;
479 }
480
481 i7core_dev->socket = socket;
482 i7core_dev->n_devs = table->n_devs;
483 list_add_tail(&i7core_dev->list, &i7core_edac_list);
484
485 return i7core_dev;
486}
487
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -0300488static void free_i7core_dev(struct i7core_dev *i7core_dev)
489{
490 list_del(&i7core_dev->list);
491 kfree(i7core_dev->pdev);
492 kfree(i7core_dev);
493}
494
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300495/****************************************************************************
496 Memory check routines
497 ****************************************************************************/
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -0300498
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300499static int get_dimm_config(struct mem_ctl_info *mci)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300500{
501 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300502 struct pci_dev *pdev;
Mauro Carvalho Chehabba6c5c62009-07-15 09:02:32 -0300503 int i, j;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300504 enum edac_type mode;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300505 enum mem_type mtype;
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300506 struct dimm_info *dimm;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300507
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300508 /* Get data from the MC register, function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300509 pdev = pvt->pci_mcr[0];
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300510 if (!pdev)
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300511 return -ENODEV;
512
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300513 /* Device 3 function 0 reads */
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300514 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
515 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
516 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
517 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300518
Joe Perches956b9ba2012-04-29 17:08:39 -0300519 edac_dbg(0, "QPI %d control=0x%08x status=0x%08x dod=0x%08x map=0x%08x\n",
520 pvt->i7core_dev->socket, pvt->info.mc_control,
521 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300522
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300523 if (ECC_ENABLED(pvt)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300524 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300525 if (ECCx8(pvt))
526 mode = EDAC_S8ECD8ED;
527 else
528 mode = EDAC_S4ECD4ED;
529 } else {
Joe Perches956b9ba2012-04-29 17:08:39 -0300530 edac_dbg(0, "ECC disabled\n");
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300531 mode = EDAC_NONE;
532 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300533
534 /* FIXME: need to handle the error codes */
Joe Perches956b9ba2012-04-29 17:08:39 -0300535 edac_dbg(0, "DOD Max limits: DIMMS: %d, %d-ranked, %d-banked x%x x 0x%x\n",
536 numdimms(pvt->info.max_dod),
537 numrank(pvt->info.max_dod >> 2),
538 numbank(pvt->info.max_dod >> 4),
539 numrow(pvt->info.max_dod >> 6),
540 numcol(pvt->info.max_dod >> 9));
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300541
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300542 for (i = 0; i < NUM_CHANS; i++) {
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300543 u32 data, dimm_dod[3], value[8];
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300544
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -0300545 if (!pvt->pci_ch[i][0])
546 continue;
547
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300548 if (!CH_ACTIVE(pvt, i)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300549 edac_dbg(0, "Channel %i is not active\n", i);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300550 continue;
551 }
552 if (CH_DISABLED(pvt, i)) {
Joe Perches956b9ba2012-04-29 17:08:39 -0300553 edac_dbg(0, "Channel %i is disabled\n", i);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300554 continue;
555 }
556
Mauro Carvalho Chehabf122a892009-06-22 22:48:29 -0300557 /* Devices 4-6 function 0 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300558 pci_read_config_dword(pvt->pci_ch[i][0],
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300559 MC_CHANNEL_DIMM_INIT_PARAMS, &data);
560
Mauro Carvalho Chehab0bf09e82012-04-26 11:47:29 -0300561
562 if (data & THREE_DIMMS_PRESENT)
563 pvt->channel[i].is_3dimms_present = true;
564
565 if (data & SINGLE_QUAD_RANK_PRESENT)
566 pvt->channel[i].is_single_4rank = true;
567
568 if (data & QUAD_RANK_PRESENT)
569 pvt->channel[i].has_4rank = true;
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300570
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300571 if (data & REGISTERED_DIMM)
572 mtype = MEM_RDDR3;
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -0300573 else
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300574 mtype = MEM_DDR3;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300575
576 /* Devices 4-6 function 1 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300577 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300578 MC_DOD_CH_DIMM0, &dimm_dod[0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300579 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300580 MC_DOD_CH_DIMM1, &dimm_dod[1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300581 pci_read_config_dword(pvt->pci_ch[i][1],
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300582 MC_DOD_CH_DIMM2, &dimm_dod[2]);
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300583
Joe Perches956b9ba2012-04-29 17:08:39 -0300584 edac_dbg(0, "Ch%d phy rd%d, wr%d (0x%08x): %s%s%s%cDIMMs\n",
585 i,
586 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
587 data,
588 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
589 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
590 pvt->channel[i].has_4rank ? "HAS_4R " : "",
591 (data & REGISTERED_DIMM) ? 'R' : 'U');
Mauro Carvalho Chehab7dd69532009-06-22 22:48:30 -0300592
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300593 for (j = 0; j < 3; j++) {
594 u32 banks, ranks, rows, cols;
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300595 u32 size, npages;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300596
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300597 if (!DIMM_PRESENT(dimm_dod[j]))
598 continue;
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300599
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -0300600 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
601 i, j, 0);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300602 banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
603 ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
604 rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
605 cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
Mauro Carvalho Chehab1c6fed82009-06-22 22:48:30 -0300606
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300607 /* DDR3 has 8 I/O banks */
608 size = (rows * cols * banks * ranks) >> (20 - 3);
609
Joe Perches956b9ba2012-04-29 17:08:39 -0300610 edac_dbg(0, "\tdimm %d %d Mb offset: %x, bank: %d, rank: %d, row: %#x, col: %#x\n",
611 j, size,
612 RANKOFFSET(dimm_dod[j]),
613 banks, ranks, rows, cols);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300614
Mauro Carvalho Chehabe9144602010-08-10 20:26:35 -0300615 npages = MiB_TO_PAGES(size);
Mauro Carvalho Chehab5566cb72009-06-22 22:48:31 -0300616
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300617 dimm->nr_pages = npages;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -0300618
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300619 switch (banks) {
620 case 4:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300621 dimm->dtype = DEV_X4;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300622 break;
623 case 8:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300624 dimm->dtype = DEV_X8;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300625 break;
626 case 16:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300627 dimm->dtype = DEV_X16;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300628 break;
629 default:
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300630 dimm->dtype = DEV_UNKNOWN;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300631 }
632
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300633 snprintf(dimm->label, sizeof(dimm->label),
634 "CPU#%uChannel#%u_DIMM#%u",
635 pvt->i7core_dev->socket, i, j);
636 dimm->grain = 8;
637 dimm->edac_mode = mode;
638 dimm->mtype = mtype;
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300639 }
640
641 pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
642 pci_read_config_dword(pdev, MC_SAG_CH_1, &value[1]);
643 pci_read_config_dword(pdev, MC_SAG_CH_2, &value[2]);
644 pci_read_config_dword(pdev, MC_SAG_CH_3, &value[3]);
645 pci_read_config_dword(pdev, MC_SAG_CH_4, &value[4]);
646 pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
647 pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
648 pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
Joe Perches956b9ba2012-04-29 17:08:39 -0300649 edac_dbg(1, "\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
Mauro Carvalho Chehab854d3342009-06-22 22:48:30 -0300650 for (j = 0; j < 8; j++)
Joe Perches956b9ba2012-04-29 17:08:39 -0300651 edac_dbg(1, "\t\t%#x\t%#x\t%#x\n",
652 (value[j] >> 27) & 0x1,
653 (value[j] >> 24) & 0x7,
654 (value[j] & ((1 << 24) - 1)));
Mauro Carvalho Chehab0b2b7b72009-06-22 22:48:29 -0300655 }
656
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -0300657 return 0;
658}
659
660/****************************************************************************
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300661 Error insertion routines
662 ****************************************************************************/
663
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300664#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
665
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300666/* The i7core has independent error injection features per channel.
667 However, to have a simpler code, we don't allow enabling error injection
668 on more than one channel.
669 Also, since a change at an inject parameter will be applied only at enable,
670 we're disabling error injection on all write calls to the sysfs nodes that
671 controls the error code injection.
672 */
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300673static int disable_inject(const struct mem_ctl_info *mci)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300674{
675 struct i7core_pvt *pvt = mci->pvt_info;
676
677 pvt->inject.enable = 0;
678
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300679 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300680 return -ENODEV;
681
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300682 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300683 MC_CHANNEL_ERROR_INJECT, 0);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300684
685 return 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300686}
687
688/*
689 * i7core inject inject.section
690 *
691 * accept and store error injection inject.section value
692 * bit 0 - refers to the lower 32-byte half cacheline
693 * bit 1 - refers to the upper 32-byte half cacheline
694 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300695static ssize_t i7core_inject_section_store(struct device *dev,
696 struct device_attribute *mattr,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300697 const char *data, size_t count)
698{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300699 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300700 struct i7core_pvt *pvt = mci->pvt_info;
701 unsigned long value;
702 int rc;
703
704 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300705 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300706
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900707 rc = kstrtoul(data, 10, &value);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300708 if ((rc < 0) || (value > 3))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300709 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300710
711 pvt->inject.section = (u32) value;
712 return count;
713}
714
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300715static ssize_t i7core_inject_section_show(struct device *dev,
716 struct device_attribute *mattr,
717 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300718{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300719 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300720 struct i7core_pvt *pvt = mci->pvt_info;
721 return sprintf(data, "0x%08x\n", pvt->inject.section);
722}
723
724/*
725 * i7core inject.type
726 *
727 * accept and store error injection inject.section value
728 * bit 0 - repeat enable - Enable error repetition
729 * bit 1 - inject ECC error
730 * bit 2 - inject parity error
731 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300732static ssize_t i7core_inject_type_store(struct device *dev,
733 struct device_attribute *mattr,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300734 const char *data, size_t count)
735{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300736 struct mem_ctl_info *mci = to_mci(dev);
737struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300738 unsigned long value;
739 int rc;
740
741 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300742 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300743
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900744 rc = kstrtoul(data, 10, &value);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300745 if ((rc < 0) || (value > 7))
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300746 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300747
748 pvt->inject.type = (u32) value;
749 return count;
750}
751
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300752static ssize_t i7core_inject_type_show(struct device *dev,
753 struct device_attribute *mattr,
754 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300755{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300756 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300757 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300758
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300759 return sprintf(data, "0x%08x\n", pvt->inject.type);
760}
761
762/*
763 * i7core_inject_inject.eccmask_store
764 *
765 * The type of error (UE/CE) will depend on the inject.eccmask value:
766 * Any bits set to a 1 will flip the corresponding ECC bit
767 * Correctable errors can be injected by flipping 1 bit or the bits within
768 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
769 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
770 * uncorrectable error to be injected.
771 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300772static ssize_t i7core_inject_eccmask_store(struct device *dev,
773 struct device_attribute *mattr,
774 const char *data, size_t count)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300775{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300776 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300777 struct i7core_pvt *pvt = mci->pvt_info;
778 unsigned long value;
779 int rc;
780
781 if (pvt->inject.enable)
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -0300782 disable_inject(mci);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300783
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900784 rc = kstrtoul(data, 10, &value);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300785 if (rc < 0)
Mauro Carvalho Chehab2068def2009-08-05 19:28:27 -0300786 return -EIO;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300787
788 pvt->inject.eccmask = (u32) value;
789 return count;
790}
791
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300792static ssize_t i7core_inject_eccmask_show(struct device *dev,
793 struct device_attribute *mattr,
794 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300795{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300796 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300797 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300798
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300799 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
800}
801
802/*
803 * i7core_addrmatch
804 *
805 * The type of error (UE/CE) will depend on the inject.eccmask value:
806 * Any bits set to a 1 will flip the corresponding ECC bit
807 * Correctable errors can be injected by flipping 1 bit or the bits within
808 * a symbol pair (2 consecutive aligned 8-bit pairs - i.e. 7:0 and 15:8 or
809 * 23:16 and 31:24). Flipping bits in two symbol pairs will cause an
810 * uncorrectable error to be injected.
811 */
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300812
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300813#define DECLARE_ADDR_MATCH(param, limit) \
814static ssize_t i7core_inject_store_##param( \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300815 struct device *dev, \
816 struct device_attribute *mattr, \
817 const char *data, size_t count) \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300818{ \
Prarit Bhargava42709ef2012-10-16 09:02:27 -0400819 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300820 struct i7core_pvt *pvt; \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300821 long value; \
822 int rc; \
823 \
Joe Perches956b9ba2012-04-29 17:08:39 -0300824 edac_dbg(1, "\n"); \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300825 pvt = mci->pvt_info; \
826 \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300827 if (pvt->inject.enable) \
828 disable_inject(mci); \
829 \
Mauro Carvalho Chehab4f87fad2009-10-04 11:54:56 -0300830 if (!strcasecmp(data, "any") || !strcasecmp(data, "any\n"))\
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300831 value = -1; \
832 else { \
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900833 rc = kstrtoul(data, 10, &value); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300834 if ((rc < 0) || (value >= limit)) \
835 return -EIO; \
836 } \
837 \
838 pvt->inject.param = value; \
839 \
840 return count; \
841} \
842 \
843static ssize_t i7core_inject_show_##param( \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300844 struct device *dev, \
845 struct device_attribute *mattr, \
846 char *data) \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300847{ \
Prarit Bhargava42709ef2012-10-16 09:02:27 -0400848 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
Mauro Carvalho Chehabcc301b32009-09-24 16:23:42 -0300849 struct i7core_pvt *pvt; \
850 \
851 pvt = mci->pvt_info; \
Joe Perches956b9ba2012-04-29 17:08:39 -0300852 edac_dbg(1, "pvt=%p\n", pvt); \
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300853 if (pvt->inject.param < 0) \
854 return sprintf(data, "any\n"); \
855 else \
856 return sprintf(data, "%d\n", pvt->inject.param);\
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300857}
858
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300859#define ATTR_ADDR_MATCH(param) \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300860 static DEVICE_ATTR(param, S_IRUGO | S_IWUSR, \
861 i7core_inject_show_##param, \
862 i7core_inject_store_##param)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300863
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -0300864DECLARE_ADDR_MATCH(channel, 3);
865DECLARE_ADDR_MATCH(dimm, 3);
866DECLARE_ADDR_MATCH(rank, 4);
867DECLARE_ADDR_MATCH(bank, 32);
868DECLARE_ADDR_MATCH(page, 0x10000);
869DECLARE_ADDR_MATCH(col, 0x4000);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300870
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300871ATTR_ADDR_MATCH(channel);
872ATTR_ADDR_MATCH(dimm);
873ATTR_ADDR_MATCH(rank);
874ATTR_ADDR_MATCH(bank);
875ATTR_ADDR_MATCH(page);
876ATTR_ADDR_MATCH(col);
877
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -0300878static int write_and_test(struct pci_dev *dev, const int where, const u32 val)
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300879{
880 u32 read;
881 int count;
882
Joe Perches956b9ba2012-04-29 17:08:39 -0300883 edac_dbg(0, "setting pci %02x:%02x.%x reg=%02x value=%08x\n",
884 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
885 where, val);
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300886
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300887 for (count = 0; count < 10; count++) {
888 if (count)
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -0300889 msleep(100);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300890 pci_write_config_dword(dev, where, val);
891 pci_read_config_dword(dev, where, &read);
892
893 if (read == val)
894 return 0;
895 }
896
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -0300897 i7core_printk(KERN_ERR, "Error during set pci %02x:%02x.%x reg=%02x "
898 "write=%08x. Read=%08x\n",
899 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
900 where, val, read);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300901
902 return -EINVAL;
903}
904
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300905/*
906 * This routine prepares the Memory Controller for error injection.
907 * The error will be injected when some process tries to write to the
908 * memory that matches the given criteria.
909 * The criteria can be set in terms of a mask where dimm, rank, bank, page
910 * and col can be specified.
911 * A -1 value for any of the mask items will make the MCU to ignore
912 * that matching criteria for error injection.
913 *
914 * It should be noticed that the error will only happen after a write operation
915 * on a memory that matches the condition. if REPEAT_EN is not enabled at
916 * inject mask, then it will produce just one error. Otherwise, it will repeat
917 * until the injectmask would be cleaned.
918 *
919 * FIXME: This routine assumes that MAXNUMDIMMS value of MC_MAX_DOD
920 * is reliable enough to check if the MC is using the
921 * three channels. However, this is not clear at the datasheet.
922 */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300923static ssize_t i7core_inject_enable_store(struct device *dev,
924 struct device_attribute *mattr,
925 const char *data, size_t count)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300926{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -0300927 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300928 struct i7core_pvt *pvt = mci->pvt_info;
929 u32 injectmask;
930 u64 mask = 0;
931 int rc;
932 long enable;
933
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300934 if (!pvt->pci_ch[pvt->inject.channel][0])
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -0300935 return 0;
936
Jingoo Hanc7f62fc2013-06-01 16:08:22 +0900937 rc = kstrtoul(data, 10, &enable);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300938 if ((rc < 0))
939 return 0;
940
941 if (enable) {
942 pvt->inject.enable = 1;
943 } else {
944 disable_inject(mci);
945 return count;
946 }
947
948 /* Sets pvt->inject.dimm mask */
949 if (pvt->inject.dimm < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200950 mask |= 1LL << 41;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300951 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300952 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200953 mask |= (pvt->inject.dimm & 0x3LL) << 35;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300954 else
Alan Cox486dd092009-11-08 01:34:27 -0200955 mask |= (pvt->inject.dimm & 0x1LL) << 36;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300956 }
957
958 /* Sets pvt->inject.rank mask */
959 if (pvt->inject.rank < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200960 mask |= 1LL << 40;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300961 else {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300962 if (pvt->channel[pvt->inject.channel].dimms > 2)
Alan Cox486dd092009-11-08 01:34:27 -0200963 mask |= (pvt->inject.rank & 0x1LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300964 else
Alan Cox486dd092009-11-08 01:34:27 -0200965 mask |= (pvt->inject.rank & 0x3LL) << 34;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300966 }
967
968 /* Sets pvt->inject.bank mask */
969 if (pvt->inject.bank < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200970 mask |= 1LL << 39;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300971 else
Alan Cox486dd092009-11-08 01:34:27 -0200972 mask |= (pvt->inject.bank & 0x15LL) << 30;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300973
974 /* Sets pvt->inject.page mask */
975 if (pvt->inject.page < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200976 mask |= 1LL << 38;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300977 else
Alan Cox486dd092009-11-08 01:34:27 -0200978 mask |= (pvt->inject.page & 0xffff) << 14;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300979
980 /* Sets pvt->inject.column mask */
981 if (pvt->inject.col < 0)
Alan Cox486dd092009-11-08 01:34:27 -0200982 mask |= 1LL << 37;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300983 else
Alan Cox486dd092009-11-08 01:34:27 -0200984 mask |= (pvt->inject.col & 0x3fff);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300985
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300986 /*
987 * bit 0: REPEAT_EN
988 * bits 1-2: MASK_HALF_CACHELINE
989 * bit 3: INJECT_ECC
990 * bit 4: INJECT_ADDR_PARITY
991 */
992
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -0300993 injectmask = (pvt->inject.type & 1) |
994 (pvt->inject.section & 0x3) << 1 |
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -0300995 (pvt->inject.type & 0x6) << (3 - 1);
996
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300997 /* Unlock writes to registers - this register is write only */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -0300998 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -0300999 MC_CFG_CONTROL, 0x2);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001000
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001001 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001002 MC_CHANNEL_ADDR_MATCH, mask);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001003 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001004 MC_CHANNEL_ADDR_MATCH + 4, mask >> 32L);
1005
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001006 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001007 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
1008
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001009 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001010 MC_CHANNEL_ERROR_INJECT, injectmask);
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001011
1012 /*
1013 * This is something undocumented, based on my tests
1014 * Without writing 8 to this register, errors aren't injected. Not sure
1015 * why.
1016 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001017 pci_write_config_dword(pvt->pci_noncore,
Mauro Carvalho Chehab276b8242009-07-22 21:45:50 -03001018 MC_CFG_CONTROL, 8);
1019
Joe Perches956b9ba2012-04-29 17:08:39 -03001020 edac_dbg(0, "Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
1021 mask, pvt->inject.eccmask, injectmask);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001022
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001023
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001024 return count;
1025}
1026
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001027static ssize_t i7core_inject_enable_show(struct device *dev,
1028 struct device_attribute *mattr,
1029 char *data)
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001030{
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001031 struct mem_ctl_info *mci = to_mci(dev);
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001032 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001033 u32 injectmask;
1034
Mauro Carvalho Chehab52a2e4fc2009-10-14 11:21:58 -03001035 if (!pvt->pci_ch[pvt->inject.channel][0])
1036 return 0;
1037
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001038 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
Mauro Carvalho Chehab4157d9f2009-08-05 20:27:15 -03001039 MC_CHANNEL_ERROR_INJECT, &injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001040
Joe Perches956b9ba2012-04-29 17:08:39 -03001041 edac_dbg(0, "Inject error read: 0x%018x\n", injectmask);
Mauro Carvalho Chehab7b029d02009-06-22 22:48:29 -03001042
1043 if (injectmask & 0x0c)
1044 pvt->inject.enable = 1;
1045
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001046 return sprintf(data, "%d\n", pvt->inject.enable);
1047}
1048
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001049#define DECLARE_COUNTER(param) \
1050static ssize_t i7core_show_counter_##param( \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001051 struct device *dev, \
1052 struct device_attribute *mattr, \
1053 char *data) \
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001054{ \
Prarit Bhargava42709ef2012-10-16 09:02:27 -04001055 struct mem_ctl_info *mci = dev_get_drvdata(dev); \
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001056 struct i7core_pvt *pvt = mci->pvt_info; \
1057 \
Joe Perches956b9ba2012-04-29 17:08:39 -03001058 edac_dbg(1, "\n"); \
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001059 if (!pvt->ce_count_available || (pvt->is_registered)) \
1060 return sprintf(data, "data unavailable\n"); \
1061 return sprintf(data, "%lu\n", \
1062 pvt->udimm_ce_count[param]); \
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001063}
1064
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001065#define ATTR_COUNTER(param) \
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001066 static DEVICE_ATTR(udimm##param, S_IRUGO | S_IWUSR, \
1067 i7core_show_counter_##param, \
1068 NULL)
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001069
1070DECLARE_COUNTER(0);
1071DECLARE_COUNTER(1);
1072DECLARE_COUNTER(2);
1073
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001074ATTR_COUNTER(0);
1075ATTR_COUNTER(1);
1076ATTR_COUNTER(2);
1077
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001078/*
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001079 * inject_addrmatch device sysfs struct
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001080 */
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001081
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001082static struct attribute *i7core_addrmatch_attrs[] = {
1083 &dev_attr_channel.attr,
1084 &dev_attr_dimm.attr,
1085 &dev_attr_rank.attr,
1086 &dev_attr_bank.attr,
1087 &dev_attr_page.attr,
1088 &dev_attr_col.attr,
1089 NULL
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001090};
1091
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001092static struct attribute_group addrmatch_grp = {
1093 .attrs = i7core_addrmatch_attrs,
Mauro Carvalho Chehaba5538e52009-09-23 18:56:47 -03001094};
1095
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001096static const struct attribute_group *addrmatch_groups[] = {
1097 &addrmatch_grp,
1098 NULL
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001099};
1100
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001101static void addrmatch_release(struct device *device)
1102{
Joe Perches956b9ba2012-04-29 17:08:39 -03001103 edac_dbg(1, "Releasing device %s\n", dev_name(device));
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001104 kfree(device);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001105}
1106
1107static struct device_type addrmatch_type = {
1108 .groups = addrmatch_groups,
1109 .release = addrmatch_release,
Mauro Carvalho Chehabf338d732009-09-24 17:25:43 -03001110};
1111
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001112/*
1113 * all_channel_counts sysfs struct
1114 */
1115
1116static struct attribute *i7core_udimm_counters_attrs[] = {
1117 &dev_attr_udimm0.attr,
1118 &dev_attr_udimm1.attr,
1119 &dev_attr_udimm2.attr,
1120 NULL
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001121};
1122
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001123static struct attribute_group all_channel_counts_grp = {
1124 .attrs = i7core_udimm_counters_attrs,
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001125};
1126
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001127static const struct attribute_group *all_channel_counts_groups[] = {
1128 &all_channel_counts_grp,
1129 NULL
1130};
1131
1132static void all_channel_counts_release(struct device *device)
1133{
Joe Perches956b9ba2012-04-29 17:08:39 -03001134 edac_dbg(1, "Releasing device %s\n", dev_name(device));
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001135 kfree(device);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001136}
1137
1138static struct device_type all_channel_counts_type = {
1139 .groups = all_channel_counts_groups,
1140 .release = all_channel_counts_release,
1141};
1142
1143/*
1144 * inject sysfs attributes
1145 */
1146
1147static DEVICE_ATTR(inject_section, S_IRUGO | S_IWUSR,
1148 i7core_inject_section_show, i7core_inject_section_store);
1149
1150static DEVICE_ATTR(inject_type, S_IRUGO | S_IWUSR,
1151 i7core_inject_type_show, i7core_inject_type_store);
1152
1153
1154static DEVICE_ATTR(inject_eccmask, S_IRUGO | S_IWUSR,
1155 i7core_inject_eccmask_show, i7core_inject_eccmask_store);
1156
1157static DEVICE_ATTR(inject_enable, S_IRUGO | S_IWUSR,
1158 i7core_inject_enable_show, i7core_inject_enable_store);
1159
1160static int i7core_create_sysfs_devices(struct mem_ctl_info *mci)
1161{
1162 struct i7core_pvt *pvt = mci->pvt_info;
1163 int rc;
1164
1165 rc = device_create_file(&mci->dev, &dev_attr_inject_section);
1166 if (rc < 0)
1167 return rc;
1168 rc = device_create_file(&mci->dev, &dev_attr_inject_type);
1169 if (rc < 0)
1170 return rc;
1171 rc = device_create_file(&mci->dev, &dev_attr_inject_eccmask);
1172 if (rc < 0)
1173 return rc;
1174 rc = device_create_file(&mci->dev, &dev_attr_inject_enable);
1175 if (rc < 0)
1176 return rc;
1177
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001178 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL);
1179 if (!pvt->addrmatch_dev)
1180 return rc;
1181
1182 pvt->addrmatch_dev->type = &addrmatch_type;
1183 pvt->addrmatch_dev->bus = mci->dev.bus;
1184 device_initialize(pvt->addrmatch_dev);
1185 pvt->addrmatch_dev->parent = &mci->dev;
1186 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
1187 dev_set_drvdata(pvt->addrmatch_dev, mci);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001188
Joe Perches956b9ba2012-04-29 17:08:39 -03001189 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001190
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001191 rc = device_add(pvt->addrmatch_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001192 if (rc < 0)
1193 return rc;
1194
1195 if (!pvt->is_registered) {
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001196 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev),
1197 GFP_KERNEL);
1198 if (!pvt->chancounts_dev) {
1199 put_device(pvt->addrmatch_dev);
1200 device_del(pvt->addrmatch_dev);
1201 return rc;
1202 }
1203
1204 pvt->chancounts_dev->type = &all_channel_counts_type;
1205 pvt->chancounts_dev->bus = mci->dev.bus;
1206 device_initialize(pvt->chancounts_dev);
1207 pvt->chancounts_dev->parent = &mci->dev;
1208 dev_set_name(pvt->chancounts_dev, "all_channel_counts");
1209 dev_set_drvdata(pvt->chancounts_dev, mci);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001210
Joe Perches956b9ba2012-04-29 17:08:39 -03001211 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001212
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001213 rc = device_add(pvt->chancounts_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001214 if (rc < 0)
1215 return rc;
1216 }
1217 return 0;
1218}
1219
1220static void i7core_delete_sysfs_devices(struct mem_ctl_info *mci)
1221{
1222 struct i7core_pvt *pvt = mci->pvt_info;
1223
Joe Perches956b9ba2012-04-29 17:08:39 -03001224 edac_dbg(1, "\n");
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001225
1226 device_remove_file(&mci->dev, &dev_attr_inject_section);
1227 device_remove_file(&mci->dev, &dev_attr_inject_type);
1228 device_remove_file(&mci->dev, &dev_attr_inject_eccmask);
1229 device_remove_file(&mci->dev, &dev_attr_inject_enable);
1230
1231 if (!pvt->is_registered) {
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001232 put_device(pvt->chancounts_dev);
1233 device_del(pvt->chancounts_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001234 }
Mauro Carvalho Chehab356f0a32012-03-30 16:10:51 -03001235 put_device(pvt->addrmatch_dev);
1236 device_del(pvt->addrmatch_dev);
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03001237}
1238
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03001239/****************************************************************************
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001240 Device initialization routines: put/get, init/exit
1241 ****************************************************************************/
1242
1243/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001244 * i7core_put_all_devices 'put' all the devices that we have
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001245 * reserved via 'get'
1246 */
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001247static void i7core_put_devices(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001248{
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001249 int i;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001250
Joe Perches956b9ba2012-04-29 17:08:39 -03001251 edac_dbg(0, "\n");
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001252 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001253 struct pci_dev *pdev = i7core_dev->pdev[i];
1254 if (!pdev)
1255 continue;
Joe Perches956b9ba2012-04-29 17:08:39 -03001256 edac_dbg(0, "Removing dev %02x:%02x.%d\n",
1257 pdev->bus->number,
1258 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03001259 pci_dev_put(pdev);
1260 }
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001261}
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001262
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001263static void i7core_put_all_devices(void)
1264{
Mauro Carvalho Chehab42538682009-09-24 09:59:13 -03001265 struct i7core_dev *i7core_dev, *tmp;
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001266
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001267 list_for_each_entry_safe(i7core_dev, tmp, &i7core_edac_list, list) {
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03001268 i7core_put_devices(i7core_dev);
Hidetoshi Seto2aa9be42010-08-20 04:25:00 -03001269 free_i7core_dev(i7core_dev);
Mauro Carvalho Chehab39300e72010-08-11 23:40:15 -03001270 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001271}
1272
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001273static void __init i7core_xeon_pci_fixup(const struct pci_id_table *table)
Keith Manntheybc2d7242009-09-03 00:05:05 -03001274{
1275 struct pci_dev *pdev = NULL;
1276 int i;
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03001277
Keith Manntheybc2d7242009-09-03 00:05:05 -03001278 /*
David Sterbae7bf0682010-12-27 16:51:15 +01001279 * On Xeon 55xx, the Intel Quick Path Arch Generic Non-core pci buses
Keith Manntheybc2d7242009-09-03 00:05:05 -03001280 * aren't announced by acpi. So, we need to use a legacy scan probing
1281 * to detect them
1282 */
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001283 while (table && table->descr) {
1284 pdev = pci_get_device(PCI_VENDOR_ID_INTEL, table->descr[0].dev_id, NULL);
1285 if (unlikely(!pdev)) {
1286 for (i = 0; i < MAX_SOCKET_BUSES; i++)
1287 pcibios_scan_specific_bus(255-i);
1288 }
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001289 pci_dev_put(pdev);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001290 table++;
Keith Manntheybc2d7242009-09-03 00:05:05 -03001291 }
1292}
1293
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001294static unsigned i7core_pci_lastbus(void)
1295{
1296 int last_bus = 0, bus;
1297 struct pci_bus *b = NULL;
1298
1299 while ((b = pci_find_next_bus(b)) != NULL) {
1300 bus = b->number;
Joe Perches956b9ba2012-04-29 17:08:39 -03001301 edac_dbg(0, "Found bus %d\n", bus);
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001302 if (bus > last_bus)
1303 last_bus = bus;
1304 }
1305
Joe Perches956b9ba2012-04-29 17:08:39 -03001306 edac_dbg(0, "Last bus %d\n", last_bus);
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001307
1308 return last_bus;
1309}
1310
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001311/*
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001312 * i7core_get_all_devices Find and perform 'get' operation on the MCH's
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001313 * device/functions we want to reference for this driver
1314 *
1315 * Need to 'get' device 16 func 1 and func 2
1316 */
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001317static int i7core_get_onedevice(struct pci_dev **prev,
1318 const struct pci_id_table *table,
1319 const unsigned devno,
1320 const unsigned last_bus)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001321{
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001322 struct i7core_dev *i7core_dev;
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001323 const struct pci_id_descr *dev_descr = &table->descr[devno];
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001324
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001325 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03001326 u8 bus = 0;
1327 u8 socket = 0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001328
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001329 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001330 dev_descr->dev_id, *prev);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001331
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001332 /*
David Mackey15ed1032012-04-17 11:30:52 -07001333 * On Xeon 55xx, the Intel QuickPath Arch Generic Non-core regs
Mauro Carvalho Chehab224e8712011-03-17 17:02:59 -03001334 * is at addr 8086:2c40, instead of 8086:2c41. So, we need
1335 * to probe for the alternate address in case of failure
1336 */
1337 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_I7_NONCORE && !pdev)
1338 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1339 PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT, *prev);
1340
1341 if (dev_descr->dev_id == PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE && !pdev)
1342 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
1343 PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT,
1344 *prev);
1345
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001346 if (!pdev) {
1347 if (*prev) {
1348 *prev = pdev;
1349 return 0;
Mauro Carvalho Chehabd1fd4fb2009-07-10 18:39:53 -03001350 }
1351
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001352 if (dev_descr->optional)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001353 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001354
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001355 if (devno == 0)
1356 return -ENODEV;
1357
Daniel J Bluemanab089372010-07-23 23:16:52 +01001358 i7core_printk(KERN_INFO,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001359 "Device not found: dev %02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001360 dev_descr->dev, dev_descr->func,
1361 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001362
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001363 /* End of list, leave */
1364 return -ENODEV;
1365 }
1366 bus = pdev->bus->number;
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03001367
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001368 socket = last_bus - bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001369
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001370 i7core_dev = get_i7core_dev(socket);
1371 if (!i7core_dev) {
Hidetoshi Seto848b2f72010-08-20 04:24:44 -03001372 i7core_dev = alloc_i7core_dev(socket, table);
Hidetoshi Seto28966372010-08-20 04:28:51 -03001373 if (!i7core_dev) {
1374 pci_dev_put(pdev);
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001375 return -ENOMEM;
Hidetoshi Seto28966372010-08-20 04:28:51 -03001376 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001377 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001378
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001379 if (i7core_dev->pdev[devno]) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001380 i7core_printk(KERN_ERR,
1381 "Duplicated device for "
1382 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001383 bus, dev_descr->dev, dev_descr->func,
1384 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001385 pci_dev_put(pdev);
1386 return -ENODEV;
1387 }
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001388
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001389 i7core_dev->pdev[devno] = pdev;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001390
1391 /* Sanity check */
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001392 if (unlikely(PCI_SLOT(pdev->devfn) != dev_descr->dev ||
1393 PCI_FUNC(pdev->devfn) != dev_descr->func)) {
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001394 i7core_printk(KERN_ERR,
1395 "Device PCI ID %04x:%04x "
1396 "has dev %02x:%02x.%d instead of dev %02x:%02x.%d\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001397 PCI_VENDOR_ID_INTEL, dev_descr->dev_id,
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001398 bus, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001399 bus, dev_descr->dev, dev_descr->func);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001400 return -ENODEV;
1401 }
1402
1403 /* Be sure that the device is enabled */
1404 if (unlikely(pci_enable_device(pdev) < 0)) {
1405 i7core_printk(KERN_ERR,
1406 "Couldn't enable "
1407 "dev %02x:%02x.%d PCI ID %04x:%04x\n",
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001408 bus, dev_descr->dev, dev_descr->func,
1409 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001410 return -ENODEV;
1411 }
1412
Joe Perches956b9ba2012-04-29 17:08:39 -03001413 edac_dbg(0, "Detected socket %d dev %02x:%02x.%d PCI ID %04x:%04x\n",
1414 socket, bus, dev_descr->dev,
1415 dev_descr->func,
1416 PCI_VENDOR_ID_INTEL, dev_descr->dev_id);
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001417
Mauro Carvalho Chehaba3e15412010-08-21 08:52:41 -03001418 /*
1419 * As stated on drivers/pci/search.c, the reference count for
1420 * @from is always decremented if it is not %NULL. So, as we need
1421 * to get all devices up to null, we need to do a get for the device
1422 */
1423 pci_dev_get(pdev);
1424
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001425 *prev = pdev;
1426
1427 return 0;
1428}
1429
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03001430static int i7core_get_all_devices(void)
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001431{
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001432 int i, rc, last_bus;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001433 struct pci_dev *pdev = NULL;
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001434 const struct pci_id_table *table = pci_dev_table;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001435
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001436 last_bus = i7core_pci_lastbus();
1437
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001438 while (table && table->descr) {
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001439 for (i = 0; i < table->n_devs; i++) {
1440 pdev = NULL;
1441 do {
Hidetoshi Setob197cba2010-08-20 04:24:31 -03001442 rc = i7core_get_onedevice(&pdev, table, i,
Mauro Carvalho Chehabbda14282010-06-30 01:41:35 -03001443 last_bus);
Vernon Mauerybd9e19c2010-05-18 19:02:50 -03001444 if (rc < 0) {
1445 if (i == 0) {
1446 i = table->n_devs;
1447 break;
1448 }
1449 i7core_put_all_devices();
1450 return -ENODEV;
1451 }
1452 } while (pdev);
1453 }
Mauro Carvalho Chehab3c52cc52010-10-24 11:12:28 -02001454 table++;
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001455 }
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001456
Mauro Carvalho Chehabc77720b2009-07-18 10:43:08 -03001457 return 0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001458}
1459
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001460static int mci_bind_devs(struct mem_ctl_info *mci,
1461 struct i7core_dev *i7core_dev)
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001462{
1463 struct i7core_pvt *pvt = mci->pvt_info;
1464 struct pci_dev *pdev;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001465 int i, func, slot;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001466 char *family;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001467
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001468 pvt->is_registered = false;
1469 pvt->enable_scrub = false;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03001470 for (i = 0; i < i7core_dev->n_devs; i++) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001471 pdev = i7core_dev->pdev[i];
1472 if (!pdev)
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03001473 continue;
1474
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001475 func = PCI_FUNC(pdev->devfn);
1476 slot = PCI_SLOT(pdev->devfn);
1477 if (slot == 3) {
1478 if (unlikely(func > MAX_MCR_FUNC))
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001479 goto error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001480 pvt->pci_mcr[func] = pdev;
1481 } else if (likely(slot >= 4 && slot < 4 + NUM_CHANS)) {
1482 if (unlikely(func > MAX_CHAN_FUNC))
1483 goto error;
1484 pvt->pci_ch[slot - 4][func] = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001485 } else if (!slot && !func) {
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001486 pvt->pci_noncore = pdev;
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001487
1488 /* Detect the processor family */
1489 switch (pdev->device) {
1490 case PCI_DEVICE_ID_INTEL_I7_NONCORE:
1491 family = "Xeon 35xx/ i7core";
1492 pvt->enable_scrub = false;
1493 break;
1494 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT:
1495 family = "i7-800/i5-700";
1496 pvt->enable_scrub = false;
1497 break;
1498 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE:
1499 family = "Xeon 34xx";
1500 pvt->enable_scrub = false;
1501 break;
1502 case PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT:
1503 family = "Xeon 55xx";
1504 pvt->enable_scrub = true;
1505 break;
1506 case PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2:
1507 family = "Xeon 56xx / i7-900";
1508 pvt->enable_scrub = true;
1509 break;
1510 default:
1511 family = "unknown";
1512 pvt->enable_scrub = false;
1513 }
Joe Perches956b9ba2012-04-29 17:08:39 -03001514 edac_dbg(0, "Detected a processor type %s\n", family);
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001515 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001516 goto error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001517
Joe Perches956b9ba2012-04-29 17:08:39 -03001518 edac_dbg(0, "Associated fn %d.%d, dev = %p, socket %d\n",
1519 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1520 pdev, i7core_dev->socket);
Mauro Carvalho Chehab14d2c082009-09-02 23:52:36 -03001521
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001522 if (PCI_SLOT(pdev->devfn) == 3 &&
1523 PCI_FUNC(pdev->devfn) == 2)
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03001524 pvt->is_registered = true;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001525 }
Mauro Carvalho Chehabe9bd2e72009-07-09 22:14:35 -03001526
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03001527 return 0;
1528
1529error:
1530 i7core_printk(KERN_ERR, "Device %d, function %d "
1531 "is out of the expected range\n",
1532 slot, func);
1533 return -EINVAL;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001534}
1535
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001536/****************************************************************************
1537 Error check routines
1538 ****************************************************************************/
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001539
1540static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001541 const int chan,
1542 const int new0,
1543 const int new1,
1544 const int new2)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001545{
1546 struct i7core_pvt *pvt = mci->pvt_info;
1547 int add0 = 0, add1 = 0, add2 = 0;
1548 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001549 if (pvt->ce_count_available) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001550 /* Updates CE counters */
1551
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001552 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1553 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1554 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001555
1556 if (add2 < 0)
1557 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001558 pvt->rdimm_ce_count[chan][2] += add2;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001559
1560 if (add1 < 0)
1561 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001562 pvt->rdimm_ce_count[chan][1] += add1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001563
1564 if (add0 < 0)
1565 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001566 pvt->rdimm_ce_count[chan][0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001567 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001568 pvt->ce_count_available = 1;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001569
1570 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001571 pvt->rdimm_last_ce_count[chan][2] = new2;
1572 pvt->rdimm_last_ce_count[chan][1] = new1;
1573 pvt->rdimm_last_ce_count[chan][0] = new0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001574
1575 /*updated the edac core */
1576 if (add0 != 0)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001577 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add0,
1578 0, 0, 0,
1579 chan, 0, -1, "error", "");
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001580 if (add1 != 0)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001581 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add1,
1582 0, 0, 0,
1583 chan, 1, -1, "error", "");
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001584 if (add2 != 0)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001585 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add2,
1586 0, 0, 0,
1587 chan, 2, -1, "error", "");
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001588}
1589
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001590static void i7core_rdimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001591{
1592 struct i7core_pvt *pvt = mci->pvt_info;
1593 u32 rcv[3][2];
1594 int i, new0, new1, new2;
1595
1596 /*Read DEV 3: FUN 2: MC_COR_ECC_CNT regs directly*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001597 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001598 &rcv[0][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001599 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001600 &rcv[0][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001601 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001602 &rcv[1][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001603 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001604 &rcv[1][1]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001605 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001606 &rcv[2][0]);
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001607 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001608 &rcv[2][1]);
1609 for (i = 0 ; i < 3; i++) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001610 edac_dbg(3, "MC_COR_ECC_CNT%d = 0x%x; MC_COR_ECC_CNT%d = 0x%x\n",
1611 (i * 2), rcv[i][0], (i * 2) + 1, rcv[i][1]);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001612 /*if the channel has 3 dimms*/
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001613 if (pvt->channel[i].dimms > 2) {
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001614 new0 = DIMM_BOT_COR_ERR(rcv[i][0]);
1615 new1 = DIMM_TOP_COR_ERR(rcv[i][0]);
1616 new2 = DIMM_BOT_COR_ERR(rcv[i][1]);
1617 } else {
1618 new0 = DIMM_TOP_COR_ERR(rcv[i][0]) +
1619 DIMM_BOT_COR_ERR(rcv[i][0]);
1620 new1 = DIMM_TOP_COR_ERR(rcv[i][1]) +
1621 DIMM_BOT_COR_ERR(rcv[i][1]);
1622 new2 = 0;
1623 }
1624
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001625 i7core_rdimm_update_ce_count(mci, i, new0, new1, new2);
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001626 }
1627}
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001628
1629/* This function is based on the device 3 function 4 registers as described on:
1630 * Intel Xeon Processor 5500 Series Datasheet Volume 2
1631 * http://www.intel.com/Assets/PDF/datasheet/321322.pdf
1632 * also available at:
1633 * http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
1634 */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001635static void i7core_udimm_check_mc_ecc_err(struct mem_ctl_info *mci)
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001636{
1637 struct i7core_pvt *pvt = mci->pvt_info;
1638 u32 rcv1, rcv0;
1639 int new0, new1, new2;
1640
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001641 if (!pvt->pci_mcr[4]) {
Joe Perches956b9ba2012-04-29 17:08:39 -03001642 edac_dbg(0, "MCR registers not found\n");
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001643 return;
1644 }
1645
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001646 /* Corrected test errors */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001647 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1648 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001649
1650 /* Store the new values */
1651 new2 = DIMM2_COR_ERR(rcv1);
1652 new1 = DIMM1_COR_ERR(rcv0);
1653 new0 = DIMM0_COR_ERR(rcv0);
1654
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001655 /* Updates CE counters if it is not the first time here */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001656 if (pvt->ce_count_available) {
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001657 /* Updates CE counters */
1658 int add0, add1, add2;
1659
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001660 add2 = new2 - pvt->udimm_last_ce_count[2];
1661 add1 = new1 - pvt->udimm_last_ce_count[1];
1662 add0 = new0 - pvt->udimm_last_ce_count[0];
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001663
1664 if (add2 < 0)
1665 add2 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001666 pvt->udimm_ce_count[2] += add2;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001667
1668 if (add1 < 0)
1669 add1 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001670 pvt->udimm_ce_count[1] += add1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001671
1672 if (add0 < 0)
1673 add0 += 0x7fff;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001674 pvt->udimm_ce_count[0] += add0;
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001675
1676 if (add0 | add1 | add2)
1677 i7core_printk(KERN_ERR, "New Corrected error(s): "
1678 "dimm0: +%d, dimm1: +%d, dimm2 +%d\n",
1679 add0, add1, add2);
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001680 } else
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001681 pvt->ce_count_available = 1;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001682
1683 /* Store the new values */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001684 pvt->udimm_last_ce_count[2] = new2;
1685 pvt->udimm_last_ce_count[1] = new1;
1686 pvt->udimm_last_ce_count[0] = new0;
Mauro Carvalho Chehab442305b2009-06-22 22:48:29 -03001687}
1688
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001689/*
1690 * According with tables E-11 and E-12 of chapter E.3.3 of Intel 64 and IA-32
1691 * Architectures Software Developer’s Manual Volume 3B.
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001692 * Nehalem are defined as family 0x06, model 0x1a
1693 *
1694 * The MCA registers used here are the following ones:
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001695 * struct mce field MCA Register
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001696 * m->status MSR_IA32_MC8_STATUS
1697 * m->addr MSR_IA32_MC8_ADDR
1698 * m->misc MSR_IA32_MC8_MISC
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001699 * In the case of Nehalem, the error information is masked at .status and .misc
1700 * fields
1701 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001702static void i7core_mce_output_error(struct mem_ctl_info *mci,
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03001703 const struct mce *m)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001704{
Mauro Carvalho Chehabb4e8f0b2009-09-02 23:49:59 -03001705 struct i7core_pvt *pvt = mci->pvt_info;
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001706 char *type, *optype, *err;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001707 enum hw_event_mc_err_type tp_event;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001708 unsigned long error = m->status & 0x1ff0000l;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001709 bool uncorrected_error = m->mcgstatus & 1ll << 61;
1710 bool ripv = m->mcgstatus & 1;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001711 u32 optypenum = (m->status >> 4) & 0x07;
Mathias Krause8cf2d232011-08-18 09:17:00 +02001712 u32 core_err_cnt = (m->status >> 38) & 0x7fff;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001713 u32 dimm = (m->misc >> 16) & 0x3;
1714 u32 channel = (m->misc >> 18) & 0x3;
1715 u32 syndrome = m->misc >> 32;
1716 u32 errnum = find_first_bit(&error, 32);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001717
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001718 if (uncorrected_error) {
1719 if (ripv) {
1720 type = "FATAL";
1721 tp_event = HW_EVENT_ERR_FATAL;
1722 } else {
1723 type = "NON_FATAL";
1724 tp_event = HW_EVENT_ERR_UNCORRECTED;
1725 }
1726 } else {
1727 type = "CORRECTED";
1728 tp_event = HW_EVENT_ERR_CORRECTED;
1729 }
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001730
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001731 switch (optypenum) {
Mauro Carvalho Chehabb9905382009-08-05 21:36:35 -03001732 case 0:
1733 optype = "generic undef request";
1734 break;
1735 case 1:
1736 optype = "read error";
1737 break;
1738 case 2:
1739 optype = "write error";
1740 break;
1741 case 3:
1742 optype = "addr/cmd error";
1743 break;
1744 case 4:
1745 optype = "scrubbing error";
1746 break;
1747 default:
1748 optype = "reserved";
1749 break;
Mauro Carvalho Chehaba6395392009-07-17 10:54:23 -03001750 }
1751
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001752 switch (errnum) {
1753 case 16:
1754 err = "read ECC error";
1755 break;
1756 case 17:
1757 err = "RAS ECC error";
1758 break;
1759 case 18:
1760 err = "write parity error";
1761 break;
1762 case 19:
1763 err = "redundacy loss";
1764 break;
1765 case 20:
1766 err = "reserved";
1767 break;
1768 case 21:
1769 err = "memory range error";
1770 break;
1771 case 22:
1772 err = "RTID out of range";
1773 break;
1774 case 23:
1775 err = "address parity error";
1776 break;
1777 case 24:
1778 err = "byte enable parity error";
1779 break;
1780 default:
1781 err = "unknown";
1782 }
1783
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001784 /*
1785 * Call the helper to output message
1786 * FIXME: what to do if core_err_cnt > 1? Currently, it generates
1787 * only one event
1788 */
1789 if (uncorrected_error || !pvt->is_registered)
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001790 edac_mc_handle_error(tp_event, mci, core_err_cnt,
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03001791 m->addr >> PAGE_SHIFT,
1792 m->addr & ~PAGE_MASK,
1793 syndrome,
1794 channel, dimm, -1,
Mauro Carvalho Chehab00d18332012-06-04 13:38:52 -03001795 err, optype);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001796}
1797
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03001798/*
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001799 * i7core_check_error Retrieve and process errors reported by the
1800 * hardware. Called by the Core module.
1801 */
1802static void i7core_check_error(struct mem_ctl_info *mci)
1803{
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001804 struct i7core_pvt *pvt = mci->pvt_info;
1805 int i;
1806 unsigned count = 0;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001807 struct mce *m;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001808
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001809 /*
1810 * MCE first step: Copy all mce errors into a temporary buffer
1811 * We use a double buffering here, to reduce the risk of
Lucas De Marchi25985ed2011-03-30 22:57:33 -03001812 * losing an error.
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001813 */
1814 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001815 count = (pvt->mce_out + MCE_LOG_LEN - pvt->mce_in)
1816 % MCE_LOG_LEN;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001817 if (!count)
Vernon Mauery8a311e12010-04-16 19:40:19 -03001818 goto check_ce_error;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001819
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001820 m = pvt->mce_outentry;
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001821 if (pvt->mce_in + count > MCE_LOG_LEN) {
1822 unsigned l = MCE_LOG_LEN - pvt->mce_in;
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001823
1824 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * l);
1825 smp_wmb();
1826 pvt->mce_in = 0;
1827 count -= l;
1828 m += l;
1829 }
1830 memcpy(m, &pvt->mce_entry[pvt->mce_in], sizeof(*m) * count);
1831 smp_wmb();
1832 pvt->mce_in += count;
1833
1834 smp_rmb();
1835 if (pvt->mce_overrun) {
1836 i7core_printk(KERN_ERR, "Lost %d memory errors\n",
1837 pvt->mce_overrun);
1838 smp_wmb();
1839 pvt->mce_overrun = 0;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001840 }
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001841
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001842 /*
1843 * MCE second step: parse errors and display
1844 */
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001845 for (i = 0; i < count; i++)
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001846 i7core_mce_output_error(mci, &pvt->mce_outentry[i]);
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001847
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001848 /*
1849 * Now, let's increment CE error counts
1850 */
Vernon Mauery8a311e12010-04-16 19:40:19 -03001851check_ce_error:
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03001852 if (!pvt->is_registered)
1853 i7core_udimm_check_mc_ecc_err(mci);
1854 else
1855 i7core_rdimm_check_mc_ecc_err(mci);
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03001856}
1857
1858/*
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001859 * i7core_mce_check_error Replicates mcelog routine to get errors
1860 * This routine simply queues mcelog errors, and
1861 * return. The error itself should be handled later
1862 * by i7core_check_error.
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001863 * WARNING: As this routine should be called at NMI time, extra care should
1864 * be taken to avoid deadlocks, and to be as fast as possible.
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001865 */
Borislav Petkov4140c542011-07-18 11:24:46 -03001866static int i7core_mce_check_error(struct notifier_block *nb, unsigned long val,
1867 void *data)
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001868{
Borislav Petkov4140c542011-07-18 11:24:46 -03001869 struct mce *mce = (struct mce *)data;
1870 struct i7core_dev *i7_dev;
1871 struct mem_ctl_info *mci;
1872 struct i7core_pvt *pvt;
1873
1874 i7_dev = get_i7core_dev(mce->socketid);
1875 if (!i7_dev)
1876 return NOTIFY_BAD;
1877
1878 mci = i7_dev->mci;
1879 pvt = mci->pvt_info;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001880
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001881 /*
1882 * Just let mcelog handle it if the error is
1883 * outside the memory controller
1884 */
1885 if (((mce->status & 0xffff) >> 7) != 1)
Borislav Petkov4140c542011-07-18 11:24:46 -03001886 return NOTIFY_DONE;
Mauro Carvalho Chehab8a2f1182009-07-15 19:01:08 -03001887
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001888 /* Bank 8 registers are the only ones that we know how to handle */
1889 if (mce->bank != 8)
Borislav Petkov4140c542011-07-18 11:24:46 -03001890 return NOTIFY_DONE;
Mauro Carvalho Chehabf237fcf2009-07-15 19:53:24 -03001891
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001892 smp_rmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001893 if ((pvt->mce_out + 1) % MCE_LOG_LEN == pvt->mce_in) {
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001894 smp_wmb();
1895 pvt->mce_overrun++;
Borislav Petkov4140c542011-07-18 11:24:46 -03001896 return NOTIFY_DONE;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001897 }
Mauro Carvalho Chehab6e103be2009-10-05 09:40:09 -03001898
1899 /* Copy memory error at the ringbuffer */
1900 memcpy(&pvt->mce_entry[pvt->mce_out], mce, sizeof(*mce));
Mauro Carvalho Chehabca9c90b2009-10-04 10:15:40 -03001901 smp_wmb();
Mauro Carvalho Chehab321ece42009-10-08 13:11:08 -03001902 pvt->mce_out = (pvt->mce_out + 1) % MCE_LOG_LEN;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001903
Mauro Carvalho Chehabc5d34522009-07-17 10:28:15 -03001904 /* Handle fatal errors immediately */
1905 if (mce->mcgstatus & 1)
1906 i7core_check_error(mci);
1907
David Sterbae7bf0682010-12-27 16:51:15 +01001908 /* Advise mcelog that the errors were handled */
Borislav Petkov4140c542011-07-18 11:24:46 -03001909 return NOTIFY_STOP;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03001910}
1911
Borislav Petkov4140c542011-07-18 11:24:46 -03001912static struct notifier_block i7_mce_dec = {
1913 .notifier_call = i7core_mce_check_error,
1914};
1915
Nils Carlson535e9c72011-08-08 06:21:26 -03001916struct memdev_dmi_entry {
1917 u8 type;
1918 u8 length;
1919 u16 handle;
1920 u16 phys_mem_array_handle;
1921 u16 mem_err_info_handle;
1922 u16 total_width;
1923 u16 data_width;
1924 u16 size;
1925 u8 form;
1926 u8 device_set;
1927 u8 device_locator;
1928 u8 bank_locator;
1929 u8 memory_type;
1930 u16 type_detail;
1931 u16 speed;
1932 u8 manufacturer;
1933 u8 serial_number;
1934 u8 asset_tag;
1935 u8 part_number;
1936 u8 attributes;
1937 u32 extended_size;
1938 u16 conf_mem_clk_speed;
1939} __attribute__((__packed__));
1940
1941
1942/*
1943 * Decode the DRAM Clock Frequency, be paranoid, make sure that all
1944 * memory devices show the same speed, and if they don't then consider
1945 * all speeds to be invalid.
1946 */
1947static void decode_dclk(const struct dmi_header *dh, void *_dclk_freq)
1948{
1949 int *dclk_freq = _dclk_freq;
1950 u16 dmi_mem_clk_speed;
1951
1952 if (*dclk_freq == -1)
1953 return;
1954
1955 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
1956 struct memdev_dmi_entry *memdev_dmi_entry =
1957 (struct memdev_dmi_entry *)dh;
1958 unsigned long conf_mem_clk_speed_offset =
1959 (unsigned long)&memdev_dmi_entry->conf_mem_clk_speed -
1960 (unsigned long)&memdev_dmi_entry->type;
1961 unsigned long speed_offset =
1962 (unsigned long)&memdev_dmi_entry->speed -
1963 (unsigned long)&memdev_dmi_entry->type;
1964
1965 /* Check that a DIMM is present */
1966 if (memdev_dmi_entry->size == 0)
1967 return;
1968
1969 /*
1970 * Pick the configured speed if it's available, otherwise
1971 * pick the DIMM speed, or we don't have a speed.
1972 */
1973 if (memdev_dmi_entry->length > conf_mem_clk_speed_offset) {
1974 dmi_mem_clk_speed =
1975 memdev_dmi_entry->conf_mem_clk_speed;
1976 } else if (memdev_dmi_entry->length > speed_offset) {
1977 dmi_mem_clk_speed = memdev_dmi_entry->speed;
1978 } else {
1979 *dclk_freq = -1;
1980 return;
1981 }
1982
1983 if (*dclk_freq == 0) {
1984 /* First pass, speed was 0 */
1985 if (dmi_mem_clk_speed > 0) {
1986 /* Set speed if a valid speed is read */
1987 *dclk_freq = dmi_mem_clk_speed;
1988 } else {
1989 /* Otherwise we don't have a valid speed */
1990 *dclk_freq = -1;
1991 }
1992 } else if (*dclk_freq > 0 &&
1993 *dclk_freq != dmi_mem_clk_speed) {
1994 /*
1995 * If we have a speed, check that all DIMMS are the same
1996 * speed, otherwise set the speed as invalid.
1997 */
1998 *dclk_freq = -1;
1999 }
2000 }
2001}
2002
2003/*
2004 * The default DCLK frequency is used as a fallback if we
2005 * fail to find anything reliable in the DMI. The value
2006 * is taken straight from the datasheet.
2007 */
2008#define DEFAULT_DCLK_FREQ 800
2009
2010static int get_dclk_freq(void)
2011{
2012 int dclk_freq = 0;
2013
2014 dmi_walk(decode_dclk, (void *)&dclk_freq);
2015
2016 if (dclk_freq < 1)
2017 return DEFAULT_DCLK_FREQ;
2018
2019 return dclk_freq;
2020}
2021
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002022/*
2023 * set_sdram_scrub_rate This routine sets byte/sec bandwidth scrub rate
2024 * to hardware according to SCRUBINTERVAL formula
2025 * found in datasheet.
2026 */
2027static int set_sdram_scrub_rate(struct mem_ctl_info *mci, u32 new_bw)
2028{
2029 struct i7core_pvt *pvt = mci->pvt_info;
2030 struct pci_dev *pdev;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002031 u32 dw_scrub;
2032 u32 dw_ssr;
2033
2034 /* Get data from the MC register, function 2 */
2035 pdev = pvt->pci_mcr[2];
2036 if (!pdev)
2037 return -ENODEV;
2038
2039 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &dw_scrub);
2040
2041 if (new_bw == 0) {
2042 /* Prepare to disable petrol scrub */
2043 dw_scrub &= ~STARTSCRUB;
2044 /* Stop the patrol scrub engine */
Nils Carlson535e9c72011-08-08 06:21:26 -03002045 write_and_test(pdev, MC_SCRUB_CONTROL,
2046 dw_scrub & ~SCRUBINTERVAL_MASK);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002047
2048 /* Get current status of scrub rate and set bit to disable */
2049 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2050 dw_ssr &= ~SSR_MODE_MASK;
2051 dw_ssr |= SSR_MODE_DISABLE;
2052 } else {
Nils Carlson535e9c72011-08-08 06:21:26 -03002053 const int cache_line_size = 64;
2054 const u32 freq_dclk_mhz = pvt->dclk_freq;
2055 unsigned long long scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002056 /*
2057 * Translate the desired scrub rate to a register value and
Nils Carlson535e9c72011-08-08 06:21:26 -03002058 * program the corresponding register value.
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002059 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002060 scrub_interval = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002061 cache_line_size * 1000000;
2062 do_div(scrub_interval, new_bw);
Nils Carlson535e9c72011-08-08 06:21:26 -03002063
2064 if (!scrub_interval || scrub_interval > SCRUBINTERVAL_MASK)
2065 return -EINVAL;
2066
2067 dw_scrub = SCRUBINTERVAL_MASK & scrub_interval;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002068
2069 /* Start the patrol scrub engine */
2070 pci_write_config_dword(pdev, MC_SCRUB_CONTROL,
2071 STARTSCRUB | dw_scrub);
2072
2073 /* Get current status of scrub rate and set bit to enable */
2074 pci_read_config_dword(pdev, MC_SSRCONTROL, &dw_ssr);
2075 dw_ssr &= ~SSR_MODE_MASK;
2076 dw_ssr |= SSR_MODE_ENABLE;
2077 }
2078 /* Disable or enable scrubbing */
2079 pci_write_config_dword(pdev, MC_SSRCONTROL, dw_ssr);
2080
2081 return new_bw;
2082}
2083
2084/*
2085 * get_sdram_scrub_rate This routine convert current scrub rate value
David Mackey15ed1032012-04-17 11:30:52 -07002086 * into byte/sec bandwidth according to
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002087 * SCRUBINTERVAL formula found in datasheet.
2088 */
2089static int get_sdram_scrub_rate(struct mem_ctl_info *mci)
2090{
2091 struct i7core_pvt *pvt = mci->pvt_info;
2092 struct pci_dev *pdev;
2093 const u32 cache_line_size = 64;
Nils Carlson535e9c72011-08-08 06:21:26 -03002094 const u32 freq_dclk_mhz = pvt->dclk_freq;
2095 unsigned long long scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002096 u32 scrubval;
2097
2098 /* Get data from the MC register, function 2 */
2099 pdev = pvt->pci_mcr[2];
2100 if (!pdev)
2101 return -ENODEV;
2102
2103 /* Get current scrub control data */
2104 pci_read_config_dword(pdev, MC_SCRUB_CONTROL, &scrubval);
2105
2106 /* Mask highest 8-bits to 0 */
Nils Carlson535e9c72011-08-08 06:21:26 -03002107 scrubval &= SCRUBINTERVAL_MASK;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002108 if (!scrubval)
2109 return 0;
2110
2111 /* Calculate scrub rate value into byte/sec bandwidth */
Nils Carlson535e9c72011-08-08 06:21:26 -03002112 scrub_rate = (unsigned long long)freq_dclk_mhz *
Sedat Dilek4fad8092011-09-21 23:44:52 -03002113 1000000 * cache_line_size;
2114 do_div(scrub_rate, scrubval);
Nils Carlson535e9c72011-08-08 06:21:26 -03002115 return (int)scrub_rate;
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002116}
2117
2118static void enable_sdram_scrub_setting(struct mem_ctl_info *mci)
2119{
2120 struct i7core_pvt *pvt = mci->pvt_info;
2121 u32 pci_lock;
2122
2123 /* Unlock writes to pci registers */
2124 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2125 pci_lock &= ~0x3;
2126 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2127 pci_lock | MC_CFG_UNLOCK);
2128
2129 mci->set_sdram_scrub_rate = set_sdram_scrub_rate;
2130 mci->get_sdram_scrub_rate = get_sdram_scrub_rate;
2131}
2132
2133static void disable_sdram_scrub_setting(struct mem_ctl_info *mci)
2134{
2135 struct i7core_pvt *pvt = mci->pvt_info;
2136 u32 pci_lock;
2137
2138 /* Lock writes to pci registers */
2139 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2140 pci_lock &= ~0x3;
2141 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2142 pci_lock | MC_CFG_LOCK);
2143}
2144
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002145static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2146{
2147 pvt->i7core_pci = edac_pci_create_generic_ctl(
2148 &pvt->i7core_dev->pdev[0]->dev,
2149 EDAC_MOD_STR);
2150 if (unlikely(!pvt->i7core_pci))
Mauro Carvalho Chehabf9902f22010-08-21 09:42:05 -03002151 i7core_printk(KERN_WARNING,
2152 "Unable to setup PCI error report via EDAC\n");
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002153}
2154
2155static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2156{
2157 if (likely(pvt->i7core_pci))
2158 edac_pci_release_generic_ctl(pvt->i7core_pci);
2159 else
2160 i7core_printk(KERN_ERR,
2161 "Couldn't find mem_ctl_info for socket %d\n",
2162 pvt->i7core_dev->socket);
2163 pvt->i7core_pci = NULL;
2164}
2165
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002166static void i7core_unregister_mci(struct i7core_dev *i7core_dev)
2167{
2168 struct mem_ctl_info *mci = i7core_dev->mci;
2169 struct i7core_pvt *pvt;
2170
2171 if (unlikely(!mci || !mci->pvt_info)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002172 edac_dbg(0, "MC: dev = %p\n", &i7core_dev->pdev[0]->dev);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002173
2174 i7core_printk(KERN_ERR, "Couldn't find mci handler\n");
2175 return;
2176 }
2177
2178 pvt = mci->pvt_info;
2179
Joe Perches956b9ba2012-04-29 17:08:39 -03002180 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002181
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002182 /* Disable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002183 if (pvt->enable_scrub)
2184 disable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002185
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002186 /* Disable EDAC polling */
2187 i7core_pci_ctl_release(pvt);
2188
2189 /* Remove MC sysfs nodes */
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03002190 i7core_delete_sysfs_devices(mci);
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03002191 edac_mc_del_mc(mci->pdev);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002192
Joe Perches956b9ba2012-04-29 17:08:39 -03002193 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002194 kfree(mci->ctl_name);
2195 edac_mc_free(mci);
2196 i7core_dev->mci = NULL;
2197}
2198
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002199static int i7core_register_mci(struct i7core_dev *i7core_dev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002200{
2201 struct mem_ctl_info *mci;
2202 struct i7core_pvt *pvt;
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002203 int rc;
2204 struct edac_mc_layer layers[2];
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002205
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002206 /* allocate a new MC control structure */
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002207
2208 layers[0].type = EDAC_MC_LAYER_CHANNEL;
2209 layers[0].size = NUM_CHANS;
2210 layers[0].is_virt_csrow = false;
2211 layers[1].type = EDAC_MC_LAYER_SLOT;
2212 layers[1].size = MAX_DIMMS;
2213 layers[1].is_virt_csrow = true;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -03002214 mci = edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
Mauro Carvalho Chehab0975c162012-04-16 15:10:12 -03002215 sizeof(*pvt));
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002216 if (unlikely(!mci))
2217 return -ENOMEM;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002218
Joe Perches956b9ba2012-04-29 17:08:39 -03002219 edac_dbg(0, "MC: mci = %p, dev = %p\n", mci, &i7core_dev->pdev[0]->dev);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002220
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002221 pvt = mci->pvt_info;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002222 memset(pvt, 0, sizeof(*pvt));
Mauro Carvalho Chehab67166af2009-07-15 06:56:23 -03002223
Mauro Carvalho Chehab6d37d242010-08-20 12:48:26 -03002224 /* Associates i7core_dev and mci for future usage */
2225 pvt->i7core_dev = i7core_dev;
2226 i7core_dev->mci = mci;
2227
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002228 /*
2229 * FIXME: how to handle RDDR3 at MCI level? It is possible to have
2230 * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
2231 * memory channels
2232 */
2233 mci->mtype_cap = MEM_FLAG_DDR3;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002234 mci->edac_ctl_cap = EDAC_FLAG_NONE;
2235 mci->edac_cap = EDAC_FLAG_NONE;
2236 mci->mod_name = "i7core_edac.c";
2237 mci->mod_ver = I7CORE_REVISION;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002238 mci->ctl_name = kasprintf(GFP_KERNEL, "i7 core #%d",
2239 i7core_dev->socket);
2240 mci->dev_name = pci_name(i7core_dev->pdev[0]);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002241 mci->ctl_page_to_phys = NULL;
Mauro Carvalho Chehab1288c182010-08-10 18:57:01 -03002242
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002243 /* Store pci devices at mci for faster access */
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002244 rc = mci_bind_devs(mci, i7core_dev);
Mauro Carvalho Chehab41fcb7f2009-06-22 22:48:31 -03002245 if (unlikely(rc < 0))
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002246 goto fail0;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002247
Hidetoshi Seto59398132010-08-20 04:28:25 -03002248
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002249 /* Get dimm basic config */
Hidetoshi Seto2e5185f2010-08-20 04:32:56 -03002250 get_dimm_config(mci);
Hidetoshi Seto59398132010-08-20 04:28:25 -03002251 /* record ptr to the generic device */
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03002252 mci->pdev = &i7core_dev->pdev[0]->dev;
Hidetoshi Seto59398132010-08-20 04:28:25 -03002253 /* Set the function pointer to an actual operation function */
2254 mci->edac_check = i7core_check_error;
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002255
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002256 /* Enable scrubrate setting */
Mauro Carvalho Chehab27100db2011-08-04 21:35:27 -03002257 if (pvt->enable_scrub)
2258 enable_sdram_scrub_setting(mci);
Samuel Gabrielssone8b6a122011-03-30 10:21:23 -03002259
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002260 /* add this new MC control structure to EDAC's list of MCs */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002261 if (unlikely(edac_mc_add_mc(mci))) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002262 edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002263 /* FIXME: perhaps some code should go here that disables error
2264 * reporting if we just enabled it
2265 */
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002266
2267 rc = -EINVAL;
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002268 goto fail0;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002269 }
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03002270 if (i7core_create_sysfs_devices(mci)) {
Joe Perches956b9ba2012-04-29 17:08:39 -03002271 edac_dbg(0, "MC: failed to create sysfs nodes\n");
Mauro Carvalho Chehab5c4cdb52012-03-21 11:08:06 -03002272 edac_mc_del_mc(mci->pdev);
2273 rc = -EINVAL;
2274 goto fail0;
2275 }
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002276
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002277 /* Default error mask is any memory */
Mauro Carvalho Chehabef708b52009-06-22 22:48:30 -03002278 pvt->inject.channel = 0;
Mauro Carvalho Chehab194a40f2009-06-22 22:48:28 -03002279 pvt->inject.dimm = -1;
2280 pvt->inject.rank = -1;
2281 pvt->inject.bank = -1;
2282 pvt->inject.page = -1;
2283 pvt->inject.col = -1;
2284
Hidetoshi Setoa3aa0a42010-08-20 04:25:18 -03002285 /* allocating generic PCI control info */
2286 i7core_pci_ctl_create(pvt);
2287
Nils Carlson535e9c72011-08-08 06:21:26 -03002288 /* DCLK for scrub rate setting */
2289 pvt->dclk_freq = get_dclk_freq();
2290
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002291 return 0;
2292
Hidetoshi Seto628c5dd2010-08-20 04:28:40 -03002293fail0:
2294 kfree(mci->ctl_name);
2295 edac_mc_free(mci);
Hidetoshi Seto1c6edbb2010-08-20 04:32:33 -03002296 i7core_dev->mci = NULL;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002297 return rc;
2298}
2299
2300/*
2301 * i7core_probe Probe for ONE instance of device to see if it is
2302 * present.
2303 * return:
2304 * 0 for FOUND a device
2305 * < 0 for error code
2306 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002307
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002308static int i7core_probe(struct pci_dev *pdev, const struct pci_device_id *id)
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002309{
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002310 int rc, count = 0;
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002311 struct i7core_dev *i7core_dev;
2312
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002313 /* get the pci devices we want to reserve for our use */
2314 mutex_lock(&i7core_edac_lock);
2315
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002316 /*
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002317 * All memory controllers are allocated at the first pass.
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002318 */
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002319 if (unlikely(probed >= 1)) {
2320 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehab76a7bd82010-10-24 11:36:19 -02002321 return -ENODEV;
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002322 }
2323 probed++;
Mauro Carvalho Chehabde06eee2009-10-14 08:02:40 -03002324
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002325 rc = i7core_get_all_devices();
Mauro Carvalho Chehabf4742942009-09-05 02:35:08 -03002326 if (unlikely(rc < 0))
2327 goto fail0;
2328
2329 list_for_each_entry(i7core_dev, &i7core_edac_list, list) {
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002330 count++;
Hidetoshi Setoaace4282010-08-20 04:32:45 -03002331 rc = i7core_register_mci(i7core_dev);
Mauro Carvalho Chehabd4c27792009-09-05 04:12:02 -03002332 if (unlikely(rc < 0))
2333 goto fail1;
Mauro Carvalho Chehabd5381642009-07-09 22:06:41 -03002334 }
2335
Mauro Carvalho Chehab40557592010-11-30 08:14:30 -02002336 /*
2337 * Nehalem-EX uses a different memory controller. However, as the
2338 * memory controller is not visible on some Nehalem/Nehalem-EP, we
2339 * need to indirectly probe via a X58 PCI device. The same devices
2340 * are found on (some) Nehalem-EX. So, on those machines, the
2341 * probe routine needs to return -ENODEV, as the actual Memory
2342 * Controller registers won't be detected.
2343 */
2344 if (!count) {
2345 rc = -ENODEV;
2346 goto fail1;
2347 }
2348
2349 i7core_printk(KERN_INFO,
2350 "Driver loaded, %d memory controller(s) found.\n",
2351 count);
Mauro Carvalho Chehab8f331902009-06-22 22:48:29 -03002352
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002353 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002354 return 0;
2355
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002356fail1:
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002357 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2358 i7core_unregister_mci(i7core_dev);
2359
Mauro Carvalho Chehab13d6e9b2009-09-05 12:15:20 -03002360 i7core_put_all_devices();
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002361fail0:
2362 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehabb7c76152009-06-22 22:48:30 -03002363 return rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002364}
2365
2366/*
2367 * i7core_remove destructor for one instance of device
2368 *
2369 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002370static void i7core_remove(struct pci_dev *pdev)
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002371{
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002372 struct i7core_dev *i7core_dev;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002373
Joe Perches956b9ba2012-04-29 17:08:39 -03002374 edac_dbg(0, "\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002375
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002376 /*
2377 * we have a trouble here: pdev value for removal will be wrong, since
2378 * it will point to the X58 register used to detect that the machine
2379 * is a Nehalem or upper design. However, due to the way several PCI
2380 * devices are grouped together to provide MC functionality, we need
2381 * to use a different method for releasing the devices
2382 */
Mauro Carvalho Chehab87d1d272009-06-22 22:48:29 -03002383
Mauro Carvalho Chehab66607702009-09-05 00:52:11 -03002384 mutex_lock(&i7core_edac_lock);
Hidetoshi Seto71fe0172010-08-20 04:29:47 -03002385
2386 if (unlikely(!probed)) {
2387 mutex_unlock(&i7core_edac_lock);
2388 return;
2389 }
2390
Mauro Carvalho Chehab88ef5ea2010-08-20 15:39:38 -03002391 list_for_each_entry(i7core_dev, &i7core_edac_list, list)
2392 i7core_unregister_mci(i7core_dev);
Hidetoshi Seto64c10f62010-08-20 04:28:14 -03002393
2394 /* Release PCI resources */
2395 i7core_put_all_devices();
2396
Mauro Carvalho Chehab2d95d812010-06-30 01:42:21 -03002397 probed--;
2398
Mauro Carvalho Chehab22e6bcb2009-09-05 23:06:50 -03002399 mutex_unlock(&i7core_edac_lock);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002400}
2401
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002402MODULE_DEVICE_TABLE(pci, i7core_pci_tbl);
2403
2404/*
2405 * i7core_driver pci_driver structure for this module
2406 *
2407 */
2408static struct pci_driver i7core_driver = {
2409 .name = "i7core_edac",
2410 .probe = i7core_probe,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08002411 .remove = i7core_remove,
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002412 .id_table = i7core_pci_tbl,
2413};
2414
2415/*
2416 * i7core_init Module entry function
2417 * Try to initialize this module for its devices
2418 */
2419static int __init i7core_init(void)
2420{
2421 int pci_rc;
2422
Joe Perches956b9ba2012-04-29 17:08:39 -03002423 edac_dbg(2, "\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002424
2425 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
2426 opstate_init();
2427
Mauro Carvalho Chehab54a08ab2010-08-19 15:51:00 -03002428 if (use_pci_fixup)
2429 i7core_xeon_pci_fixup(pci_dev_table);
Keith Manntheybc2d7242009-09-03 00:05:05 -03002430
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002431 pci_rc = pci_register_driver(&i7core_driver);
2432
Chen Gonge35fca42012-05-08 20:40:12 -03002433 if (pci_rc >= 0) {
2434 mce_register_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002435 return 0;
Chen Gonge35fca42012-05-08 20:40:12 -03002436 }
Mauro Carvalho Chehab3ef288a2009-09-02 23:43:33 -03002437
2438 i7core_printk(KERN_ERR, "Failed to register device with error %d.\n",
2439 pci_rc);
2440
2441 return pci_rc;
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002442}
2443
2444/*
2445 * i7core_exit() Module exit function
2446 * Unregister the driver
2447 */
2448static void __exit i7core_exit(void)
2449{
Joe Perches956b9ba2012-04-29 17:08:39 -03002450 edac_dbg(2, "\n");
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002451 pci_unregister_driver(&i7core_driver);
Chen Gonge35fca42012-05-08 20:40:12 -03002452 mce_unregister_decode_chain(&i7_mce_dec);
Mauro Carvalho Chehaba0c36a12009-06-22 22:41:15 -03002453}
2454
2455module_init(i7core_init);
2456module_exit(i7core_exit);
2457
2458MODULE_LICENSE("GPL");
2459MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
2460MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
2461MODULE_DESCRIPTION("MC Driver for Intel i7 Core memory controllers - "
2462 I7CORE_REVISION);
2463
2464module_param(edac_op_state, int, 0444);
2465MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");