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Rafał Miłecki8369ae32011-05-09 18:56:46 +02001/*
2 * Broadcom specific AMBA
3 * ChipCommon core driver
4 *
5 * Copyright 2005, Broadcom Corporation
Michael Büscheb032b92011-07-04 20:50:05 +02006 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +01007 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
Rafał Miłecki8369ae32011-05-09 18:56:46 +02008 *
9 * Licensed under the GNU/GPL. See COPYING for details.
10 */
11
12#include "bcma_private.h"
Hauke Mehrtensa22a3112012-12-05 18:46:01 +010013#include <linux/bcm47xx_wdt.h>
Paul Gortmaker44a8e372011-07-27 21:21:04 -040014#include <linux/export.h>
Hauke Mehrtensa4855f392012-12-05 18:46:02 +010015#include <linux/platform_device.h>
Rafał Miłecki8369ae32011-05-09 18:56:46 +020016#include <linux/bcma/bcma.h>
17
18static inline u32 bcma_cc_write32_masked(struct bcma_drv_cc *cc, u16 offset,
19 u32 mask, u32 value)
20{
21 value &= mask;
22 value |= bcma_cc_read32(cc, offset) & ~mask;
23 bcma_cc_write32(cc, offset, value);
24
25 return value;
26}
27
Hauke Mehrtens69516182013-03-27 17:23:11 +010028u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +010029{
30 if (cc->capabilities & BCMA_CC_CAP_PMU)
Rafał Miłecki5b5ac412012-12-07 12:56:56 +010031 return bcma_pmu_get_alp_clock(cc);
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +010032
33 return 20000000;
34}
Hauke Mehrtens69516182013-03-27 17:23:11 +010035EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
Hauke Mehrtens56fd5f02012-12-05 18:45:59 +010036
Hauke Mehrtensf6354c82012-12-05 18:46:00 +010037static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
38{
39 struct bcma_bus *bus = cc->core->bus;
40 u32 nb;
41
42 if (cc->capabilities & BCMA_CC_CAP_PMU) {
43 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
44 nb = 32;
45 else if (cc->core->id.rev < 26)
46 nb = 16;
47 else
48 nb = (cc->core->id.rev >= 37) ? 32 : 24;
49 } else {
50 nb = 28;
51 }
52 if (nb == 32)
53 return 0xffffffff;
54 else
55 return (1 << nb) - 1;
56}
57
Hauke Mehrtensa22a3112012-12-05 18:46:01 +010058static u32 bcma_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
59 u32 ticks)
60{
61 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
62
63 return bcma_chipco_watchdog_timer_set(cc, ticks);
64}
65
66static u32 bcma_chipco_watchdog_timer_set_ms_wdt(struct bcm47xx_wdt *wdt,
67 u32 ms)
68{
69 struct bcma_drv_cc *cc = bcm47xx_wdt_get_drvdata(wdt);
70 u32 ticks;
71
72 ticks = bcma_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
73 return ticks / cc->ticks_per_ms;
74}
75
76static int bcma_chipco_watchdog_ticks_per_ms(struct bcma_drv_cc *cc)
77{
78 struct bcma_bus *bus = cc->core->bus;
79
80 if (cc->capabilities & BCMA_CC_CAP_PMU) {
81 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706)
Oscar Forner Martinezd0f66df2014-12-27 19:24:28 +000082 /* 4706 CC and PMU watchdogs are clocked at 1/4 of ALP
83 * clock
84 */
Rafał Miłecki5b5ac412012-12-07 12:56:56 +010085 return bcma_chipco_get_alp_clock(cc) / 4000;
Hauke Mehrtensa22a3112012-12-05 18:46:01 +010086 else
87 /* based on 32KHz ILP clock */
88 return 32;
89 } else {
Rafał Miłecki5b5ac412012-12-07 12:56:56 +010090 return bcma_chipco_get_alp_clock(cc) / 1000;
Hauke Mehrtensa22a3112012-12-05 18:46:01 +010091 }
92}
Hauke Mehrtensf6354c82012-12-05 18:46:00 +010093
Hauke Mehrtensa4855f392012-12-05 18:46:02 +010094int bcma_chipco_watchdog_register(struct bcma_drv_cc *cc)
95{
96 struct bcm47xx_wdt wdt = {};
97 struct platform_device *pdev;
98
99 wdt.driver_data = cc;
100 wdt.timer_set = bcma_chipco_watchdog_timer_set_wdt;
101 wdt.timer_set_ms = bcma_chipco_watchdog_timer_set_ms_wdt;
Oscar Forner Martinezd0f66df2014-12-27 19:24:28 +0000102 wdt.max_timer_ms =
103 bcma_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
Hauke Mehrtensa4855f392012-12-05 18:46:02 +0100104
105 pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
106 cc->core->bus->num, &wdt,
107 sizeof(wdt));
108 if (IS_ERR(pdev))
109 return PTR_ERR(pdev);
110
111 cc->watchdog = pdev;
112
113 return 0;
114}
115
Hauke Mehrtens49655bb2012-09-29 20:29:49 +0200116void bcma_core_chipcommon_early_init(struct bcma_drv_cc *cc)
117{
118 if (cc->early_setup_done)
119 return;
120
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000121 spin_lock_init(&cc->gpio_lock);
122
Hauke Mehrtens49655bb2012-09-29 20:29:49 +0200123 if (cc->core->id.rev >= 11)
124 cc->status = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
125 cc->capabilities = bcma_cc_read32(cc, BCMA_CC_CAP);
126 if (cc->core->id.rev >= 35)
127 cc->capabilities_ext = bcma_cc_read32(cc, BCMA_CC_CAP_EXT);
128
129 if (cc->capabilities & BCMA_CC_CAP_PMU)
130 bcma_pmu_early_init(cc);
131
132 cc->early_setup_done = true;
133}
134
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200135void bcma_core_chipcommon_init(struct bcma_drv_cc *cc)
136{
Rafał Miłecki18dfa492011-07-14 21:49:19 +0200137 u32 leddc_on = 10;
138 u32 leddc_off = 90;
139
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200140 if (cc->setup_done)
141 return;
142
Hauke Mehrtens49655bb2012-09-29 20:29:49 +0200143 bcma_core_chipcommon_early_init(cc);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200144
Rafał Miłecki1073e4e2011-05-11 02:08:09 +0200145 if (cc->core->id.rev >= 20) {
Rafał Miłecki88f9b652013-06-26 10:02:11 +0200146 u32 pullup = 0, pulldown = 0;
147
148 if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
149 pullup = 0x402e0;
150 pulldown = 0x20500;
151 }
152
153 bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
154 bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
Rafał Miłecki1073e4e2011-05-11 02:08:09 +0200155 }
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200156
157 if (cc->capabilities & BCMA_CC_CAP_PMU)
158 bcma_pmu_init(cc);
159 if (cc->capabilities & BCMA_CC_CAP_PCTL)
Rafał Miłecki3d9d8af2012-07-05 22:07:32 +0200160 bcma_err(cc->core->bus, "Power control not implemented!\n");
Rafał Miłecki18dfa492011-07-14 21:49:19 +0200161
162 if (cc->core->id.rev >= 16) {
163 if (cc->core->bus->sprom.leddc_on_time &&
164 cc->core->bus->sprom.leddc_off_time) {
165 leddc_on = cc->core->bus->sprom.leddc_on_time;
166 leddc_off = cc->core->bus->sprom.leddc_off_time;
167 }
168 bcma_cc_write32(cc, BCMA_CC_GPIOTIMER,
169 ((leddc_on << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
170 (leddc_off << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT)));
171 }
Hauke Mehrtensa22a3112012-12-05 18:46:01 +0100172 cc->ticks_per_ms = bcma_chipco_watchdog_ticks_per_ms(cc);
Hauke Mehrtens517f43e2011-07-23 01:20:07 +0200173
174 cc->setup_done = true;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200175}
176
177/* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
Hauke Mehrtensa22a3112012-12-05 18:46:01 +0100178u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks)
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200179{
Hauke Mehrtensf6354c82012-12-05 18:46:00 +0100180 u32 maxt;
Hauke Mehrtensf6354c82012-12-05 18:46:00 +0100181
182 maxt = bcma_chipco_watchdog_get_max_timer(cc);
183 if (cc->capabilities & BCMA_CC_CAP_PMU) {
184 if (ticks == 1)
185 ticks = 2;
186 else if (ticks > maxt)
187 ticks = maxt;
188 bcma_cc_write32(cc, BCMA_CC_PMU_WATCHDOG, ticks);
189 } else {
Rafał Miłecki68fcd242015-01-24 00:23:21 +0100190 struct bcma_bus *bus = cc->core->bus;
191
192 if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4707 &&
193 bus->chipinfo.id != BCMA_CHIP_ID_BCM53018)
194 bcma_core_set_clockmode(cc->core,
195 ticks ? BCMA_CLKMODE_FAST : BCMA_CLKMODE_DYNAMIC);
196
Hauke Mehrtensf6354c82012-12-05 18:46:00 +0100197 if (ticks > maxt)
198 ticks = maxt;
199 /* instant NMI */
200 bcma_cc_write32(cc, BCMA_CC_WATCHDOG, ticks);
201 }
Hauke Mehrtensa22a3112012-12-05 18:46:01 +0100202 return ticks;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200203}
204
205void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value)
206{
207 bcma_cc_write32_masked(cc, BCMA_CC_IRQMASK, mask, value);
208}
209
210u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask)
211{
212 return bcma_cc_read32(cc, BCMA_CC_IRQSTAT) & mask;
213}
214
215u32 bcma_chipco_gpio_in(struct bcma_drv_cc *cc, u32 mask)
216{
217 return bcma_cc_read32(cc, BCMA_CC_GPIOIN) & mask;
218}
219
220u32 bcma_chipco_gpio_out(struct bcma_drv_cc *cc, u32 mask, u32 value)
221{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000222 unsigned long flags;
223 u32 res;
224
225 spin_lock_irqsave(&cc->gpio_lock, flags);
226 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUT, mask, value);
227 spin_unlock_irqrestore(&cc->gpio_lock, flags);
228
229 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200230}
Hauke Mehrtensca84a6c2013-03-27 17:23:12 +0100231EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200232
233u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
234{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000235 unsigned long flags;
236 u32 res;
237
238 spin_lock_irqsave(&cc->gpio_lock, flags);
239 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOOUTEN, mask, value);
240 spin_unlock_irqrestore(&cc->gpio_lock, flags);
241
242 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200243}
Hauke Mehrtensca84a6c2013-03-27 17:23:12 +0100244EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200245
Hauke Mehrtens3e8bb502012-11-20 22:24:29 +0000246/*
247 * If the bit is set to 0, chipcommon controlls this GPIO,
248 * if the bit is set to 1, it is used by some part of the chip and not our code.
249 */
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200250u32 bcma_chipco_gpio_control(struct bcma_drv_cc *cc, u32 mask, u32 value)
251{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000252 unsigned long flags;
253 u32 res;
254
255 spin_lock_irqsave(&cc->gpio_lock, flags);
256 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOCTL, mask, value);
257 spin_unlock_irqrestore(&cc->gpio_lock, flags);
258
259 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200260}
261EXPORT_SYMBOL_GPL(bcma_chipco_gpio_control);
262
263u32 bcma_chipco_gpio_intmask(struct bcma_drv_cc *cc, u32 mask, u32 value)
264{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000265 unsigned long flags;
266 u32 res;
267
268 spin_lock_irqsave(&cc->gpio_lock, flags);
269 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOIRQ, mask, value);
270 spin_unlock_irqrestore(&cc->gpio_lock, flags);
271
272 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200273}
274
275u32 bcma_chipco_gpio_polarity(struct bcma_drv_cc *cc, u32 mask, u32 value)
276{
Hauke Mehrtensef85fb22012-11-20 22:24:27 +0000277 unsigned long flags;
278 u32 res;
279
280 spin_lock_irqsave(&cc->gpio_lock, flags);
281 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPOL, mask, value);
282 spin_unlock_irqrestore(&cc->gpio_lock, flags);
283
284 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200285}
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200286
Hauke Mehrtensea3488f2012-11-20 22:24:28 +0000287u32 bcma_chipco_gpio_pullup(struct bcma_drv_cc *cc, u32 mask, u32 value)
288{
289 unsigned long flags;
290 u32 res;
291
292 if (cc->core->id.rev < 20)
293 return 0;
294
295 spin_lock_irqsave(&cc->gpio_lock, flags);
296 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLUP, mask, value);
297 spin_unlock_irqrestore(&cc->gpio_lock, flags);
298
299 return res;
300}
301
302u32 bcma_chipco_gpio_pulldown(struct bcma_drv_cc *cc, u32 mask, u32 value)
303{
304 unsigned long flags;
305 u32 res;
306
307 if (cc->core->id.rev < 20)
308 return 0;
309
310 spin_lock_irqsave(&cc->gpio_lock, flags);
311 res = bcma_cc_write32_masked(cc, BCMA_CC_GPIOPULLDOWN, mask, value);
312 spin_unlock_irqrestore(&cc->gpio_lock, flags);
313
314 return res;
Rafał Miłecki8369ae32011-05-09 18:56:46 +0200315}
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200316
317#ifdef CONFIG_BCMA_DRIVER_MIPS
318void bcma_chipco_serial_init(struct bcma_drv_cc *cc)
319{
320 unsigned int irq;
321 u32 baud_base;
322 u32 i;
323 unsigned int ccrev = cc->core->id.rev;
324 struct bcma_serial_port *ports = cc->serial_ports;
325
326 if (ccrev >= 11 && ccrev != 15) {
Rafał Miłecki5b5ac412012-12-07 12:56:56 +0100327 baud_base = bcma_chipco_get_alp_clock(cc);
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200328 if (ccrev >= 21) {
329 /* Turn off UART clock before switching clocksource. */
330 bcma_cc_write32(cc, BCMA_CC_CORECTL,
331 bcma_cc_read32(cc, BCMA_CC_CORECTL)
332 & ~BCMA_CC_CORECTL_UARTCLKEN);
333 }
334 /* Set the override bit so we don't divide it */
335 bcma_cc_write32(cc, BCMA_CC_CORECTL,
336 bcma_cc_read32(cc, BCMA_CC_CORECTL)
337 | BCMA_CC_CORECTL_UARTCLK0);
338 if (ccrev >= 21) {
339 /* Re-enable the UART clock. */
340 bcma_cc_write32(cc, BCMA_CC_CORECTL,
341 bcma_cc_read32(cc, BCMA_CC_CORECTL)
342 | BCMA_CC_CORECTL_UARTCLKEN);
343 }
344 } else {
Oscar Forner Martinezd0f66df2014-12-27 19:24:28 +0000345 bcma_err(cc->core->bus, "serial not supported on this device ccrev: 0x%x\n",
346 ccrev);
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200347 return;
348 }
349
Hauke Mehrtens85eb92e2014-11-01 16:54:55 +0100350 irq = bcma_core_irq(cc->core, 0);
Hauke Mehrtense3afe0e2011-07-23 01:20:10 +0200351
352 /* Determine the registers of the UARTs */
353 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
354 for (i = 0; i < cc->nr_serial_ports; i++) {
355 ports[i].regs = cc->core->io_addr + BCMA_CC_UART0_DATA +
356 (i * 256);
357 ports[i].irq = irq;
358 ports[i].baud_base = baud_base;
359 ports[i].reg_shift = 0;
360 }
361}
362#endif /* CONFIG_BCMA_DRIVER_MIPS */