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Arthur Jones8f421c592008-07-25 01:49:04 -07001/*
2 * Intel 5100 Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * This module is based on the following document:
8 *
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
10 * http://download.intel.com/design/chipsets/datashts/318378.pdf
11 *
Nils Carlsonbbead212009-12-15 16:47:42 -080012 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
Lucas De Marchi25985ed2011-03-30 22:57:33 -030014 * rows for each respective channel are laid out one after another,
Nils Carlsonbbead212009-12-15 16:47:42 -080015 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -030017 *
18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
19 * several ranks. However, instead of showing memories as ranks, it outputs
20 * them as DIMM's. An internal table creates the association between ranks
21 * and DIMM's.
Arthur Jones8f421c592008-07-25 01:49:04 -070022 */
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/pci.h>
26#include <linux/pci_ids.h>
Arthur Jones8f421c592008-07-25 01:49:04 -070027#include <linux/edac.h>
28#include <linux/delay.h>
29#include <linux/mmzone.h>
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -030030#include <linux/debugfs.h>
Arthur Jones8f421c592008-07-25 01:49:04 -070031
32#include "edac_core.h"
33
Arthur Jonesb238e572008-07-25 01:49:08 -070034/* register addresses */
Arthur Jones8f421c592008-07-25 01:49:04 -070035
36/* device 16, func 1 */
Arthur Jones43920a52008-07-25 01:49:06 -070037#define I5100_MC 0x40 /* Memory Control Register */
Nils Carlson295439f2009-12-15 16:47:42 -080038#define I5100_MC_SCRBEN_MASK (1 << 7)
39#define I5100_MC_SCRBDONE_MASK (1 << 4)
Arthur Jones8f421c592008-07-25 01:49:04 -070040#define I5100_MS 0x44 /* Memory Status Register */
41#define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
Arthur Jones8f421c592008-07-25 01:49:04 -070042#define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
Arthur Jones8f421c592008-07-25 01:49:04 -070043#define I5100_TOLM 0x6c /* Top of Low Memory */
Arthur Jones8f421c592008-07-25 01:49:04 -070044#define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
45#define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
46#define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
47#define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
Arthur Jones8f421c592008-07-25 01:49:04 -070048#define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
Arthur Jones8f421c592008-07-25 01:49:04 -070049#define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
50#define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
51#define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
Arthur Jonesf7952ff2008-07-25 01:49:05 -070052#define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
53#define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
54#define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
55#define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
56#define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
57#define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
Niklas Söderlundb6378cb2012-02-17 07:36:54 -030058#define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
Arthur Jones8f421c592008-07-25 01:49:04 -070059#define I5100_FERR_NF_MEM_ANY_MASK \
60 (I5100_FERR_NF_MEM_M16ERR_MASK | \
61 I5100_FERR_NF_MEM_M15ERR_MASK | \
Arthur Jonesf7952ff2008-07-25 01:49:05 -070062 I5100_FERR_NF_MEM_M14ERR_MASK | \
63 I5100_FERR_NF_MEM_M12ERR_MASK | \
64 I5100_FERR_NF_MEM_M11ERR_MASK | \
65 I5100_FERR_NF_MEM_M10ERR_MASK | \
66 I5100_FERR_NF_MEM_M6ERR_MASK | \
67 I5100_FERR_NF_MEM_M5ERR_MASK | \
68 I5100_FERR_NF_MEM_M4ERR_MASK | \
69 I5100_FERR_NF_MEM_M1ERR_MASK)
Arthur Jones8f421c592008-07-25 01:49:04 -070070#define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
Arthur Jones178d5a72008-07-25 01:49:06 -070071#define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
Niklas Söderlund53ceafd2012-08-08 12:30:57 -030072#define I5100_MEM0EINJMSK0 0x200 /* Injection Mask0 Register Channel 0 */
73#define I5100_MEM1EINJMSK0 0x208 /* Injection Mask0 Register Channel 1 */
74#define I5100_MEMXEINJMSK0_EINJEN (1 << 27)
75#define I5100_MEM0EINJMSK1 0x204 /* Injection Mask1 Register Channel 0 */
76#define I5100_MEM1EINJMSK1 0x206 /* Injection Mask1 Register Channel 1 */
77
78/* Device 19, Function 0 */
79#define I5100_DINJ0 0x9a
Arthur Jones8f421c592008-07-25 01:49:04 -070080
81/* device 21 and 22, func 0 */
82#define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
83#define I5100_DMIR 0x15c /* DIMM Interleave Range */
Arthur Jones8f421c592008-07-25 01:49:04 -070084#define I5100_VALIDLOG 0x18c /* Valid Log Markers */
Arthur Jones8f421c592008-07-25 01:49:04 -070085#define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
Arthur Jones8f421c592008-07-25 01:49:04 -070086#define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
Arthur Jones8f421c592008-07-25 01:49:04 -070087#define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
Arthur Jones8f421c592008-07-25 01:49:04 -070088#define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
Arthur Jones8f421c592008-07-25 01:49:04 -070089#define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
Arthur Jones8f421c592008-07-25 01:49:04 -070090#define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
Arthur Jonesb238e572008-07-25 01:49:08 -070091#define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
92
93/* bit field accessors */
94
Nils Carlson295439f2009-12-15 16:47:42 -080095static inline u32 i5100_mc_scrben(u32 mc)
96{
97 return mc >> 7 & 1;
98}
99
Arthur Jonesb238e572008-07-25 01:49:08 -0700100static inline u32 i5100_mc_errdeten(u32 mc)
101{
102 return mc >> 5 & 1;
103}
104
Nils Carlson295439f2009-12-15 16:47:42 -0800105static inline u32 i5100_mc_scrbdone(u32 mc)
106{
107 return mc >> 4 & 1;
108}
109
Arthur Jonesb238e572008-07-25 01:49:08 -0700110static inline u16 i5100_spddata_rdo(u16 a)
111{
112 return a >> 15 & 1;
113}
114
115static inline u16 i5100_spddata_sbe(u16 a)
116{
117 return a >> 13 & 1;
118}
119
120static inline u16 i5100_spddata_busy(u16 a)
121{
122 return a >> 12 & 1;
123}
124
125static inline u16 i5100_spddata_data(u16 a)
126{
127 return a & ((1 << 8) - 1);
128}
129
130static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
131 u32 data, u32 cmd)
132{
133 return ((dti & ((1 << 4) - 1)) << 28) |
134 ((ckovrd & 1) << 27) |
135 ((sa & ((1 << 3) - 1)) << 24) |
136 ((ba & ((1 << 8) - 1)) << 16) |
137 ((data & ((1 << 8) - 1)) << 8) |
138 (cmd & 1);
139}
140
141static inline u16 i5100_tolm_tolm(u16 a)
142{
143 return a >> 12 & ((1 << 4) - 1);
144}
145
146static inline u16 i5100_mir_limit(u16 a)
147{
148 return a >> 4 & ((1 << 12) - 1);
149}
150
151static inline u16 i5100_mir_way1(u16 a)
152{
153 return a >> 1 & 1;
154}
155
156static inline u16 i5100_mir_way0(u16 a)
157{
158 return a & 1;
159}
160
161static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
162{
163 return a >> 28 & 1;
164}
165
166static inline u32 i5100_ferr_nf_mem_any(u32 a)
167{
168 return a & I5100_FERR_NF_MEM_ANY_MASK;
169}
170
171static inline u32 i5100_nerr_nf_mem_any(u32 a)
172{
173 return i5100_ferr_nf_mem_any(a);
174}
175
176static inline u32 i5100_dmir_limit(u32 a)
177{
178 return a >> 16 & ((1 << 11) - 1);
179}
180
181static inline u32 i5100_dmir_rank(u32 a, u32 i)
182{
183 return a >> (4 * i) & ((1 << 2) - 1);
184}
185
186static inline u16 i5100_mtr_present(u16 a)
187{
188 return a >> 10 & 1;
189}
190
191static inline u16 i5100_mtr_ethrottle(u16 a)
192{
193 return a >> 9 & 1;
194}
195
196static inline u16 i5100_mtr_width(u16 a)
197{
198 return a >> 8 & 1;
199}
200
201static inline u16 i5100_mtr_numbank(u16 a)
202{
203 return a >> 6 & 1;
204}
205
206static inline u16 i5100_mtr_numrow(u16 a)
207{
208 return a >> 2 & ((1 << 2) - 1);
209}
210
211static inline u16 i5100_mtr_numcol(u16 a)
212{
213 return a & ((1 << 2) - 1);
214}
215
216
217static inline u32 i5100_validlog_redmemvalid(u32 a)
218{
219 return a >> 2 & 1;
220}
221
222static inline u32 i5100_validlog_recmemvalid(u32 a)
223{
224 return a >> 1 & 1;
225}
226
227static inline u32 i5100_validlog_nrecmemvalid(u32 a)
228{
229 return a & 1;
230}
231
232static inline u32 i5100_nrecmema_merr(u32 a)
233{
234 return a >> 15 & ((1 << 5) - 1);
235}
236
237static inline u32 i5100_nrecmema_bank(u32 a)
238{
239 return a >> 12 & ((1 << 3) - 1);
240}
241
242static inline u32 i5100_nrecmema_rank(u32 a)
243{
244 return a >> 8 & ((1 << 3) - 1);
245}
246
247static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
248{
249 return a & ((1 << 8) - 1);
250}
251
252static inline u32 i5100_nrecmemb_cas(u32 a)
253{
254 return a >> 16 & ((1 << 13) - 1);
255}
256
257static inline u32 i5100_nrecmemb_ras(u32 a)
258{
259 return a & ((1 << 16) - 1);
260}
261
262static inline u32 i5100_redmemb_ecc_locator(u32 a)
263{
264 return a & ((1 << 18) - 1);
265}
266
267static inline u32 i5100_recmema_merr(u32 a)
268{
269 return i5100_nrecmema_merr(a);
270}
271
272static inline u32 i5100_recmema_bank(u32 a)
273{
274 return i5100_nrecmema_bank(a);
275}
276
277static inline u32 i5100_recmema_rank(u32 a)
278{
279 return i5100_nrecmema_rank(a);
280}
281
Arthur Jonesb238e572008-07-25 01:49:08 -0700282static inline u32 i5100_recmemb_cas(u32 a)
283{
284 return i5100_nrecmemb_cas(a);
285}
286
287static inline u32 i5100_recmemb_ras(u32 a)
288{
289 return i5100_nrecmemb_ras(a);
290}
Arthur Jones8f421c592008-07-25 01:49:04 -0700291
292/* some generic limits */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800293#define I5100_MAX_RANKS_PER_CHAN 6
294#define I5100_CHANNELS 2
Arthur Jones8f421c592008-07-25 01:49:04 -0700295#define I5100_MAX_RANKS_PER_DIMM 4
296#define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800297#define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
Arthur Jones8f421c592008-07-25 01:49:04 -0700298#define I5100_MAX_RANK_INTERLEAVE 4
299#define I5100_MAX_DMIRS 5
Nils Carlson295439f2009-12-15 16:47:42 -0800300#define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
Arthur Jones8f421c592008-07-25 01:49:04 -0700301
302struct i5100_priv {
303 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800304 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
Arthur Jones8f421c592008-07-25 01:49:04 -0700305
306 /*
307 * mainboard chip select map -- maps i5100 chip selects to
308 * DIMM slot chip selects. In the case of only 4 ranks per
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800309 * channel, the mapping is fairly obvious but not unique.
310 * we map -1 -> NC and assume both channels use the same
Arthur Jones8f421c592008-07-25 01:49:04 -0700311 * map...
312 *
313 */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800314 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
Arthur Jones8f421c592008-07-25 01:49:04 -0700315
316 /* memory interleave range */
317 struct {
318 u64 limit;
319 unsigned way[2];
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800320 } mir[I5100_CHANNELS];
Arthur Jones8f421c592008-07-25 01:49:04 -0700321
322 /* adjusted memory interleave range register */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800323 unsigned amir[I5100_CHANNELS];
Arthur Jones8f421c592008-07-25 01:49:04 -0700324
325 /* dimm interleave range */
326 struct {
327 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
328 u64 limit;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800329 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
Arthur Jones8f421c592008-07-25 01:49:04 -0700330
331 /* memory technology registers... */
332 struct {
333 unsigned present; /* 0 or 1 */
334 unsigned ethrottle; /* 0 or 1 */
335 unsigned width; /* 4 or 8 bits */
336 unsigned numbank; /* 2 or 3 lines */
337 unsigned numrow; /* 13 .. 16 lines */
338 unsigned numcol; /* 11 .. 12 lines */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800339 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
Arthur Jones8f421c592008-07-25 01:49:04 -0700340
341 u64 tolm; /* top of low memory in bytes */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800342 unsigned ranksperchan; /* number of ranks per channel */
Arthur Jones8f421c592008-07-25 01:49:04 -0700343
344 struct pci_dev *mc; /* device 16 func 1 */
Niklas Söderlund52608ba2012-08-08 12:30:56 -0300345 struct pci_dev *einj; /* device 19 func 0 */
Arthur Jones8f421c592008-07-25 01:49:04 -0700346 struct pci_dev *ch0mm; /* device 21 func 0 */
347 struct pci_dev *ch1mm; /* device 22 func 0 */
Nils Carlson295439f2009-12-15 16:47:42 -0800348
349 struct delayed_work i5100_scrubbing;
350 int scrub_enable;
Niklas Söderlund53ceafd2012-08-08 12:30:57 -0300351
352 /* Error injection */
353 u8 inject_channel;
354 u8 inject_hlinesel;
355 u8 inject_deviceptr1;
356 u8 inject_deviceptr2;
357 u16 inject_eccmask1;
358 u16 inject_eccmask2;
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300359
360 struct dentry *debugfs;
Arthur Jones8f421c592008-07-25 01:49:04 -0700361};
362
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300363static struct dentry *i5100_debugfs;
364
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800365/* map a rank/chan to a slot number on the mainboard */
Arthur Jones8f421c592008-07-25 01:49:04 -0700366static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800367 int chan, int rank)
Arthur Jones8f421c592008-07-25 01:49:04 -0700368{
369 const struct i5100_priv *priv = mci->pvt_info;
370 int i;
371
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800372 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700373 int j;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800374 const int numrank = priv->dimm_numrank[chan][i];
Arthur Jones8f421c592008-07-25 01:49:04 -0700375
376 for (j = 0; j < numrank; j++)
377 if (priv->dimm_csmap[i][j] == rank)
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800378 return i * 2 + chan;
Arthur Jones8f421c592008-07-25 01:49:04 -0700379 }
380
381 return -1;
382}
383
Arthur Jones8f421c592008-07-25 01:49:04 -0700384static const char *i5100_err_msg(unsigned err)
385{
Arthur Jonesb238e572008-07-25 01:49:08 -0700386 static const char *merrs[] = {
Arthur Jones8f421c592008-07-25 01:49:04 -0700387 "unknown", /* 0 */
388 "uncorrectable data ECC on replay", /* 1 */
389 "unknown", /* 2 */
390 "unknown", /* 3 */
391 "aliased uncorrectable demand data ECC", /* 4 */
392 "aliased uncorrectable spare-copy data ECC", /* 5 */
393 "aliased uncorrectable patrol data ECC", /* 6 */
394 "unknown", /* 7 */
395 "unknown", /* 8 */
396 "unknown", /* 9 */
397 "non-aliased uncorrectable demand data ECC", /* 10 */
398 "non-aliased uncorrectable spare-copy data ECC", /* 11 */
399 "non-aliased uncorrectable patrol data ECC", /* 12 */
400 "unknown", /* 13 */
401 "correctable demand data ECC", /* 14 */
402 "correctable spare-copy data ECC", /* 15 */
403 "correctable patrol data ECC", /* 16 */
404 "unknown", /* 17 */
405 "SPD protocol error", /* 18 */
406 "unknown", /* 19 */
407 "spare copy initiated", /* 20 */
408 "spare copy completed", /* 21 */
409 };
410 unsigned i;
411
412 for (i = 0; i < ARRAY_SIZE(merrs); i++)
413 if (1 << i & err)
414 return merrs[i];
415
416 return "none";
417}
418
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800419/* convert csrow index into a rank (per channel -- 0..5) */
Arthur Jones8f421c592008-07-25 01:49:04 -0700420static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
421{
422 const struct i5100_priv *priv = mci->pvt_info;
423
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800424 return csrow % priv->ranksperchan;
Arthur Jones8f421c592008-07-25 01:49:04 -0700425}
426
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800427/* convert csrow index into a channel (0..1) */
428static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
Arthur Jones8f421c592008-07-25 01:49:04 -0700429{
430 const struct i5100_priv *priv = mci->pvt_info;
431
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800432 return csrow / priv->ranksperchan;
Arthur Jones8f421c592008-07-25 01:49:04 -0700433}
434
Arthur Jones8f421c592008-07-25 01:49:04 -0700435static void i5100_handle_ce(struct mem_ctl_info *mci,
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800436 int chan,
Arthur Jones8f421c592008-07-25 01:49:04 -0700437 unsigned bank,
438 unsigned rank,
439 unsigned long syndrome,
440 unsigned cas,
441 unsigned ras,
442 const char *msg)
443{
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300444 char detail[80];
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300445
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300446 /* Form out message */
447 snprintf(detail, sizeof(detail),
448 "bank %u, cas %u, ras %u\n",
449 bank, cas, ras);
Arthur Jones8f421c592008-07-25 01:49:04 -0700450
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300451 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300452 0, 0, syndrome,
453 chan, rank, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300454 msg, detail);
Arthur Jones8f421c592008-07-25 01:49:04 -0700455}
456
457static void i5100_handle_ue(struct mem_ctl_info *mci,
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800458 int chan,
Arthur Jones8f421c592008-07-25 01:49:04 -0700459 unsigned bank,
460 unsigned rank,
461 unsigned long syndrome,
462 unsigned cas,
463 unsigned ras,
464 const char *msg)
465{
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300466 char detail[80];
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300467
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300468 /* Form out message */
469 snprintf(detail, sizeof(detail),
470 "bank %u, cas %u, ras %u\n",
471 bank, cas, ras);
Arthur Jones8f421c592008-07-25 01:49:04 -0700472
Mauro Carvalho Chehab9eb07a72012-06-04 13:27:43 -0300473 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300474 0, 0, syndrome,
475 chan, rank, -1,
Mauro Carvalho Chehab03f7eae2012-06-04 11:29:25 -0300476 msg, detail);
Arthur Jones8f421c592008-07-25 01:49:04 -0700477}
478
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800479static void i5100_read_log(struct mem_ctl_info *mci, int chan,
Arthur Jones8f421c592008-07-25 01:49:04 -0700480 u32 ferr, u32 nerr)
481{
482 struct i5100_priv *priv = mci->pvt_info;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800483 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
Arthur Jones8f421c592008-07-25 01:49:04 -0700484 u32 dw;
485 u32 dw2;
486 unsigned syndrome = 0;
487 unsigned ecc_loc = 0;
488 unsigned merr;
489 unsigned bank;
490 unsigned rank;
491 unsigned cas;
492 unsigned ras;
493
494 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
495
Arthur Jonesb238e572008-07-25 01:49:08 -0700496 if (i5100_validlog_redmemvalid(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700497 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700498 syndrome = dw2;
Arthur Jones8f421c592008-07-25 01:49:04 -0700499 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700500 ecc_loc = i5100_redmemb_ecc_locator(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700501 }
502
Arthur Jonesb238e572008-07-25 01:49:08 -0700503 if (i5100_validlog_recmemvalid(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700504 const char *msg;
505
506 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700507 merr = i5100_recmema_merr(dw2);
508 bank = i5100_recmema_bank(dw2);
509 rank = i5100_recmema_rank(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700510
511 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700512 cas = i5100_recmemb_cas(dw2);
513 ras = i5100_recmemb_ras(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700514
515 /* FIXME: not really sure if this is what merr is...
516 */
517 if (!merr)
518 msg = i5100_err_msg(ferr);
519 else
520 msg = i5100_err_msg(nerr);
521
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800522 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
Arthur Jones8f421c592008-07-25 01:49:04 -0700523 }
524
Arthur Jonesb238e572008-07-25 01:49:08 -0700525 if (i5100_validlog_nrecmemvalid(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700526 const char *msg;
527
528 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700529 merr = i5100_nrecmema_merr(dw2);
530 bank = i5100_nrecmema_bank(dw2);
531 rank = i5100_nrecmema_rank(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700532
533 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
Arthur Jonesb238e572008-07-25 01:49:08 -0700534 cas = i5100_nrecmemb_cas(dw2);
535 ras = i5100_nrecmemb_ras(dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700536
537 /* FIXME: not really sure if this is what merr is...
538 */
539 if (!merr)
540 msg = i5100_err_msg(ferr);
541 else
542 msg = i5100_err_msg(nerr);
543
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800544 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
Arthur Jones8f421c592008-07-25 01:49:04 -0700545 }
546
547 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
548}
549
550static void i5100_check_error(struct mem_ctl_info *mci)
551{
552 struct i5100_priv *priv = mci->pvt_info;
Niklas Söderlunddf95e422011-12-09 13:12:15 -0300553 u32 dw, dw2;
Arthur Jones8f421c592008-07-25 01:49:04 -0700554
555 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
Arthur Jonesb238e572008-07-25 01:49:08 -0700556 if (i5100_ferr_nf_mem_any(dw)) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700557
558 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700559
Arthur Jonesb238e572008-07-25 01:49:08 -0700560 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
561 i5100_ferr_nf_mem_any(dw),
562 i5100_nerr_nf_mem_any(dw2));
Niklas Söderlunddf95e422011-12-09 13:12:15 -0300563
564 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
Arthur Jones8f421c592008-07-25 01:49:04 -0700565 }
Niklas Söderlunddf95e422011-12-09 13:12:15 -0300566 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
Arthur Jones8f421c592008-07-25 01:49:04 -0700567}
568
Nils Carlson295439f2009-12-15 16:47:42 -0800569/* The i5100 chipset will scrub the entire memory once, then
570 * set a done bit. Continuous scrubbing is achieved by enqueing
571 * delayed work to a workqueue, checking every few minutes if
572 * the scrubbing has completed and if so reinitiating it.
573 */
574
575static void i5100_refresh_scrubbing(struct work_struct *work)
576{
577 struct delayed_work *i5100_scrubbing = container_of(work,
578 struct delayed_work,
579 work);
580 struct i5100_priv *priv = container_of(i5100_scrubbing,
581 struct i5100_priv,
582 i5100_scrubbing);
583 u32 dw;
584
585 pci_read_config_dword(priv->mc, I5100_MC, &dw);
586
587 if (priv->scrub_enable) {
588
589 pci_read_config_dword(priv->mc, I5100_MC, &dw);
590
591 if (i5100_mc_scrbdone(dw)) {
592 dw |= I5100_MC_SCRBEN_MASK;
593 pci_write_config_dword(priv->mc, I5100_MC, dw);
594 pci_read_config_dword(priv->mc, I5100_MC, &dw);
595 }
596
597 schedule_delayed_work(&(priv->i5100_scrubbing),
598 I5100_SCRUB_REFRESH_RATE);
599 }
600}
601/*
602 * The bandwidth is based on experimentation, feel free to refine it.
603 */
Borislav Petkoveba042a2010-05-25 18:21:07 +0200604static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
Nils Carlson295439f2009-12-15 16:47:42 -0800605{
606 struct i5100_priv *priv = mci->pvt_info;
607 u32 dw;
608
609 pci_read_config_dword(priv->mc, I5100_MC, &dw);
Borislav Petkoveba042a2010-05-25 18:21:07 +0200610 if (bandwidth) {
Nils Carlson295439f2009-12-15 16:47:42 -0800611 priv->scrub_enable = 1;
612 dw |= I5100_MC_SCRBEN_MASK;
613 schedule_delayed_work(&(priv->i5100_scrubbing),
614 I5100_SCRUB_REFRESH_RATE);
615 } else {
616 priv->scrub_enable = 0;
617 dw &= ~I5100_MC_SCRBEN_MASK;
618 cancel_delayed_work(&(priv->i5100_scrubbing));
619 }
620 pci_write_config_dword(priv->mc, I5100_MC, dw);
621
622 pci_read_config_dword(priv->mc, I5100_MC, &dw);
623
Borislav Petkoveba042a2010-05-25 18:21:07 +0200624 bandwidth = 5900000 * i5100_mc_scrben(dw);
Nils Carlson295439f2009-12-15 16:47:42 -0800625
Borislav Petkov39094442010-11-24 19:52:09 +0100626 return bandwidth;
Nils Carlson295439f2009-12-15 16:47:42 -0800627}
628
Borislav Petkov39094442010-11-24 19:52:09 +0100629static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
Nils Carlson295439f2009-12-15 16:47:42 -0800630{
631 struct i5100_priv *priv = mci->pvt_info;
632 u32 dw;
633
634 pci_read_config_dword(priv->mc, I5100_MC, &dw);
635
Borislav Petkov39094442010-11-24 19:52:09 +0100636 return 5900000 * i5100_mc_scrben(dw);
Nils Carlson295439f2009-12-15 16:47:42 -0800637}
638
Arthur Jones8f421c592008-07-25 01:49:04 -0700639static struct pci_dev *pci_get_device_func(unsigned vendor,
640 unsigned device,
641 unsigned func)
642{
643 struct pci_dev *ret = NULL;
644
645 while (1) {
646 ret = pci_get_device(vendor, device, ret);
647
648 if (!ret)
649 break;
650
651 if (PCI_FUNC(ret->devfn) == func)
652 break;
653 }
654
655 return ret;
656}
657
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800658static unsigned long i5100_npages(struct mem_ctl_info *mci, int csrow)
Arthur Jones8f421c592008-07-25 01:49:04 -0700659{
660 struct i5100_priv *priv = mci->pvt_info;
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800661 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
662 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
Arthur Jones8f421c592008-07-25 01:49:04 -0700663 unsigned addr_lines;
664
665 /* dimm present? */
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800666 if (!priv->mtr[chan][chan_rank].present)
Arthur Jones8f421c592008-07-25 01:49:04 -0700667 return 0ULL;
668
669 addr_lines =
670 I5100_DIMM_ADDR_LINES +
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800671 priv->mtr[chan][chan_rank].numcol +
672 priv->mtr[chan][chan_rank].numrow +
673 priv->mtr[chan][chan_rank].numbank;
Arthur Jones8f421c592008-07-25 01:49:04 -0700674
675 return (unsigned long)
676 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
677}
678
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800679static void i5100_init_mtr(struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700680{
681 struct i5100_priv *priv = mci->pvt_info;
682 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
683 int i;
684
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800685 for (i = 0; i < I5100_CHANNELS; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700686 int j;
687 struct pci_dev *pdev = mms[i];
688
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800689 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700690 const unsigned addr =
691 (j < 4) ? I5100_MTR_0 + j * 2 :
692 I5100_MTR_4 + (j - 4) * 2;
693 u16 w;
694
695 pci_read_config_word(pdev, addr, &w);
696
Arthur Jonesb238e572008-07-25 01:49:08 -0700697 priv->mtr[i][j].present = i5100_mtr_present(w);
698 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
699 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
700 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
701 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
702 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700703 }
704 }
705}
706
707/*
708 * FIXME: make this into a real i2c adapter (so that dimm-decode
709 * will work)?
710 */
711static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
712 u8 ch, u8 slot, u8 addr, u8 *byte)
713{
714 struct i5100_priv *priv = mci->pvt_info;
715 u16 w;
Arthur Jones8f421c592008-07-25 01:49:04 -0700716 unsigned long et;
717
718 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700719 if (i5100_spddata_busy(w))
Arthur Jones8f421c592008-07-25 01:49:04 -0700720 return -1;
721
Arthur Jonesb238e572008-07-25 01:49:08 -0700722 pci_write_config_dword(priv->mc, I5100_SPDCMD,
723 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
724 0, 0));
Arthur Jones8f421c592008-07-25 01:49:04 -0700725
726 /* wait up to 100ms */
727 et = jiffies + HZ / 10;
728 udelay(100);
729 while (1) {
730 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700731 if (!i5100_spddata_busy(w))
Arthur Jones8f421c592008-07-25 01:49:04 -0700732 break;
733 udelay(100);
734 }
735
Arthur Jonesb238e572008-07-25 01:49:08 -0700736 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
Arthur Jones8f421c592008-07-25 01:49:04 -0700737 return -1;
738
Arthur Jonesb238e572008-07-25 01:49:08 -0700739 *byte = i5100_spddata_data(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700740
741 return 0;
742}
743
744/*
745 * fill dimm chip select map
746 *
747 * FIXME:
Arthur Jones8f421c592008-07-25 01:49:04 -0700748 * o not the only way to may chip selects to dimm slots
749 * o investigate if there is some way to obtain this map from the bios
750 */
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800751static void i5100_init_dimm_csmap(struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700752{
753 struct i5100_priv *priv = mci->pvt_info;
754 int i;
755
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800756 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700757 int j;
758
759 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
760 priv->dimm_csmap[i][j] = -1; /* default NC */
761 }
762
763 /* only 2 chip selects per slot... */
Nils Carlsonbbead212009-12-15 16:47:42 -0800764 if (priv->ranksperchan == 4) {
765 priv->dimm_csmap[0][0] = 0;
766 priv->dimm_csmap[0][1] = 3;
767 priv->dimm_csmap[1][0] = 1;
768 priv->dimm_csmap[1][1] = 2;
769 priv->dimm_csmap[2][0] = 2;
770 priv->dimm_csmap[3][0] = 3;
771 } else {
772 priv->dimm_csmap[0][0] = 0;
773 priv->dimm_csmap[0][1] = 1;
774 priv->dimm_csmap[1][0] = 2;
775 priv->dimm_csmap[1][1] = 3;
776 priv->dimm_csmap[2][0] = 4;
777 priv->dimm_csmap[2][1] = 5;
778 }
Arthur Jones8f421c592008-07-25 01:49:04 -0700779}
780
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800781static void i5100_init_dimm_layout(struct pci_dev *pdev,
782 struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700783{
784 struct i5100_priv *priv = mci->pvt_info;
785 int i;
786
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800787 for (i = 0; i < I5100_CHANNELS; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700788 int j;
789
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800790 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700791 u8 rank;
792
793 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
794 priv->dimm_numrank[i][j] = 0;
795 else
796 priv->dimm_numrank[i][j] = (rank & 3) + 1;
797 }
798 }
799
800 i5100_init_dimm_csmap(mci);
801}
802
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800803static void i5100_init_interleaving(struct pci_dev *pdev,
804 struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700805{
806 u16 w;
807 u32 dw;
808 struct i5100_priv *priv = mci->pvt_info;
809 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
810 int i;
811
812 pci_read_config_word(pdev, I5100_TOLM, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700813 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
Arthur Jones8f421c592008-07-25 01:49:04 -0700814
815 pci_read_config_word(pdev, I5100_MIR0, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700816 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
817 priv->mir[0].way[1] = i5100_mir_way1(w);
818 priv->mir[0].way[0] = i5100_mir_way0(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700819
820 pci_read_config_word(pdev, I5100_MIR1, &w);
Arthur Jonesb238e572008-07-25 01:49:08 -0700821 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
822 priv->mir[1].way[1] = i5100_mir_way1(w);
823 priv->mir[1].way[0] = i5100_mir_way0(w);
Arthur Jones8f421c592008-07-25 01:49:04 -0700824
825 pci_read_config_word(pdev, I5100_AMIR_0, &w);
826 priv->amir[0] = w;
827 pci_read_config_word(pdev, I5100_AMIR_1, &w);
828 priv->amir[1] = w;
829
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800830 for (i = 0; i < I5100_CHANNELS; i++) {
Arthur Jones8f421c592008-07-25 01:49:04 -0700831 int j;
832
833 for (j = 0; j < 5; j++) {
834 int k;
835
836 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
837
838 priv->dmir[i][j].limit =
Arthur Jonesb238e572008-07-25 01:49:08 -0700839 (u64) i5100_dmir_limit(dw) << 28;
Arthur Jones8f421c592008-07-25 01:49:04 -0700840 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
841 priv->dmir[i][j].rank[k] =
Arthur Jonesb238e572008-07-25 01:49:08 -0700842 i5100_dmir_rank(dw, k);
Arthur Jones8f421c592008-07-25 01:49:04 -0700843 }
844 }
845
846 i5100_init_mtr(mci);
847}
848
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800849static void i5100_init_csrows(struct mem_ctl_info *mci)
Arthur Jones8f421c592008-07-25 01:49:04 -0700850{
851 int i;
Arthur Jones8f421c592008-07-25 01:49:04 -0700852 struct i5100_priv *priv = mci->pvt_info;
853
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300854 for (i = 0; i < mci->tot_dimms; i++) {
855 struct dimm_info *dimm;
Arthur Jones8f421c592008-07-25 01:49:04 -0700856 const unsigned long npages = i5100_npages(mci, i);
Nils Carlsonb18dfd02009-12-15 16:47:40 -0800857 const unsigned chan = i5100_csrow_to_chan(mci, i);
Arthur Jones8f421c592008-07-25 01:49:04 -0700858 const unsigned rank = i5100_csrow_to_rank(mci, i);
859
860 if (!npages)
861 continue;
862
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300863 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
864 chan, rank, 0);
Mauro Carvalho Chehab084a4fc2012-01-27 18:38:08 -0300865
Mauro Carvalho Chehaba895bf82012-01-28 09:09:38 -0300866 dimm->nr_pages = npages;
Dan Carpenter9d6c7cb2014-02-13 14:17:38 +0300867 dimm->grain = 32;
868 dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
869 DEV_X4 : DEV_X8;
870 dimm->mtype = MEM_RDDR2;
871 dimm->edac_mode = EDAC_SECDED;
872 snprintf(dimm->label, sizeof(dimm->label), "DIMM%u",
873 i5100_rank_to_slot(mci, chan, rank));
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300874
Joe Perches956b9ba2012-04-29 17:08:39 -0300875 edac_dbg(2, "dimm channel %d, rank %d, size %ld\n",
876 chan, rank, (long)PAGES_TO_MiB(npages));
Arthur Jones8f421c592008-07-25 01:49:04 -0700877 }
878}
879
Niklas Söderlund53ceafd2012-08-08 12:30:57 -0300880/****************************************************************************
881 * Error injection routines
882 ****************************************************************************/
883
884static void i5100_do_inject(struct mem_ctl_info *mci)
885{
886 struct i5100_priv *priv = mci->pvt_info;
887 u32 mask0;
888 u16 mask1;
889
890 /* MEM[1:0]EINJMSK0
891 * 31 - ADDRMATCHEN
892 * 29:28 - HLINESEL
893 * 00 Reserved
894 * 01 Lower half of cache line
895 * 10 Upper half of cache line
896 * 11 Both upper and lower parts of cache line
897 * 27 - EINJEN
898 * 25:19 - XORMASK1 for deviceptr1
899 * 9:5 - SEC2RAM for deviceptr2
900 * 4:0 - FIR2RAM for deviceptr1
901 */
902 mask0 = ((priv->inject_hlinesel & 0x3) << 28) |
903 I5100_MEMXEINJMSK0_EINJEN |
904 ((priv->inject_eccmask1 & 0xffff) << 10) |
905 ((priv->inject_deviceptr2 & 0x1f) << 5) |
906 (priv->inject_deviceptr1 & 0x1f);
907
908 /* MEM[1:0]EINJMSK1
909 * 15:0 - XORMASK2 for deviceptr2
910 */
911 mask1 = priv->inject_eccmask2;
912
913 if (priv->inject_channel == 0) {
914 pci_write_config_dword(priv->mc, I5100_MEM0EINJMSK0, mask0);
915 pci_write_config_word(priv->mc, I5100_MEM0EINJMSK1, mask1);
916 } else {
917 pci_write_config_dword(priv->mc, I5100_MEM1EINJMSK0, mask0);
918 pci_write_config_word(priv->mc, I5100_MEM1EINJMSK1, mask1);
919 }
920
921 /* Error Injection Response Function
922 * Intel 5100 Memory Controller Hub Chipset (318378) datasheet
923 * hints about this register but carry no data about them. All
924 * data regarding device 19 is based on experimentation and the
925 * Intel 7300 Chipset Memory Controller Hub (318082) datasheet
926 * which appears to be accurate for the i5100 in this area.
927 *
928 * The injection code don't work without setting this register.
929 * The register needs to be flipped off then on else the hardware
930 * will only preform the first injection.
931 *
932 * Stop condition bits 7:4
933 * 1010 - Stop after one injection
934 * 1011 - Never stop injecting faults
935 *
936 * Start condition bits 3:0
937 * 1010 - Never start
938 * 1011 - Start immediately
939 */
940 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xaa);
941 pci_write_config_byte(priv->einj, I5100_DINJ0, 0xab);
942}
943
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300944#define to_mci(k) container_of(k, struct mem_ctl_info, dev)
945static ssize_t inject_enable_write(struct file *file, const char __user *data,
946 size_t count, loff_t *ppos)
947{
948 struct device *dev = file->private_data;
949 struct mem_ctl_info *mci = to_mci(dev);
950
951 i5100_do_inject(mci);
952
953 return count;
954}
955
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300956static const struct file_operations i5100_inject_enable_fops = {
Wei Yongjunb0769892013-02-26 17:18:34 +0800957 .open = simple_open,
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300958 .write = inject_enable_write,
959 .llseek = generic_file_llseek,
960};
961
962static int i5100_setup_debugfs(struct mem_ctl_info *mci)
963{
964 struct i5100_priv *priv = mci->pvt_info;
965
966 if (!i5100_debugfs)
967 return -ENODEV;
968
Borislav Petkov88d84ac2013-07-19 12:28:25 +0200969 priv->debugfs = debugfs_create_dir(mci->bus->name, i5100_debugfs);
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -0300970
971 if (!priv->debugfs)
972 return -ENOMEM;
973
974 debugfs_create_x8("inject_channel", S_IRUGO | S_IWUSR, priv->debugfs,
975 &priv->inject_channel);
976 debugfs_create_x8("inject_hlinesel", S_IRUGO | S_IWUSR, priv->debugfs,
977 &priv->inject_hlinesel);
978 debugfs_create_x8("inject_deviceptr1", S_IRUGO | S_IWUSR, priv->debugfs,
979 &priv->inject_deviceptr1);
980 debugfs_create_x8("inject_deviceptr2", S_IRUGO | S_IWUSR, priv->debugfs,
981 &priv->inject_deviceptr2);
982 debugfs_create_x16("inject_eccmask1", S_IRUGO | S_IWUSR, priv->debugfs,
983 &priv->inject_eccmask1);
984 debugfs_create_x16("inject_eccmask2", S_IRUGO | S_IWUSR, priv->debugfs,
985 &priv->inject_eccmask2);
986 debugfs_create_file("inject_enable", S_IWUSR, priv->debugfs,
987 &mci->dev, &i5100_inject_enable_fops);
988
989 return 0;
990
991}
992
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -0800993static int i5100_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
Arthur Jones8f421c592008-07-25 01:49:04 -0700994{
995 int rc;
996 struct mem_ctl_info *mci;
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -0300997 struct edac_mc_layer layers[2];
Arthur Jones8f421c592008-07-25 01:49:04 -0700998 struct i5100_priv *priv;
Niklas Söderlund52608ba2012-08-08 12:30:56 -0300999 struct pci_dev *ch0mm, *ch1mm, *einj;
Arthur Jones8f421c592008-07-25 01:49:04 -07001000 int ret = 0;
1001 u32 dw;
1002 int ranksperch;
1003
1004 if (PCI_FUNC(pdev->devfn) != 1)
1005 return -ENODEV;
1006
1007 rc = pci_enable_device(pdev);
1008 if (rc < 0) {
1009 ret = rc;
1010 goto bail;
1011 }
1012
Arthur Jones43920a52008-07-25 01:49:06 -07001013 /* ECC enabled? */
1014 pci_read_config_dword(pdev, I5100_MC, &dw);
Arthur Jonesb238e572008-07-25 01:49:08 -07001015 if (!i5100_mc_errdeten(dw)) {
Arthur Jones43920a52008-07-25 01:49:06 -07001016 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
1017 ret = -ENODEV;
Arthur Jonesb238e572008-07-25 01:49:08 -07001018 goto bail_pdev;
Arthur Jones43920a52008-07-25 01:49:06 -07001019 }
1020
Arthur Jones8f421c592008-07-25 01:49:04 -07001021 /* figure out how many ranks, from strapped state of 48GB_Mode input */
1022 pci_read_config_dword(pdev, I5100_MS, &dw);
1023 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
1024
Arthur Jones178d5a72008-07-25 01:49:06 -07001025 /* enable error reporting... */
1026 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
1027 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
1028 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
1029
Arthur Jones8f421c592008-07-25 01:49:04 -07001030 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
1031 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1032 PCI_DEVICE_ID_INTEL_5100_21, 0);
Arthur Jonesb238e572008-07-25 01:49:08 -07001033 if (!ch0mm) {
1034 ret = -ENODEV;
1035 goto bail_pdev;
1036 }
Arthur Jones8f421c592008-07-25 01:49:04 -07001037
1038 rc = pci_enable_device(ch0mm);
1039 if (rc < 0) {
1040 ret = rc;
1041 goto bail_ch0;
1042 }
1043
1044 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
1045 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1046 PCI_DEVICE_ID_INTEL_5100_22, 0);
1047 if (!ch1mm) {
1048 ret = -ENODEV;
Arthur Jonesb238e572008-07-25 01:49:08 -07001049 goto bail_disable_ch0;
Arthur Jones8f421c592008-07-25 01:49:04 -07001050 }
1051
1052 rc = pci_enable_device(ch1mm);
1053 if (rc < 0) {
1054 ret = rc;
1055 goto bail_ch1;
1056 }
1057
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -03001058 layers[0].type = EDAC_MC_LAYER_CHANNEL;
1059 layers[0].size = 2;
1060 layers[0].is_virt_csrow = false;
1061 layers[1].type = EDAC_MC_LAYER_SLOT;
1062 layers[1].size = ranksperch;
1063 layers[1].is_virt_csrow = true;
Mauro Carvalho Chehabca0907b2012-05-02 14:37:00 -03001064 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
Mauro Carvalho Chehabd1afaa02012-04-16 15:09:52 -03001065 sizeof(*priv));
Arthur Jones8f421c592008-07-25 01:49:04 -07001066 if (!mci) {
1067 ret = -ENOMEM;
Arthur Jonesb238e572008-07-25 01:49:08 -07001068 goto bail_disable_ch1;
Arthur Jones8f421c592008-07-25 01:49:04 -07001069 }
1070
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001071
1072 /* device 19, func 0, Error injection */
1073 einj = pci_get_device_func(PCI_VENDOR_ID_INTEL,
1074 PCI_DEVICE_ID_INTEL_5100_19, 0);
1075 if (!einj) {
1076 ret = -ENODEV;
1077 goto bail_einj;
1078 }
1079
1080 rc = pci_enable_device(einj);
1081 if (rc < 0) {
1082 ret = rc;
1083 goto bail_disable_einj;
1084 }
1085
1086
Mauro Carvalho Chehabfd687502012-03-16 07:44:18 -03001087 mci->pdev = &pdev->dev;
Arthur Jones8f421c592008-07-25 01:49:04 -07001088
1089 priv = mci->pvt_info;
Nils Carlsonb18dfd02009-12-15 16:47:40 -08001090 priv->ranksperchan = ranksperch;
Arthur Jones8f421c592008-07-25 01:49:04 -07001091 priv->mc = pdev;
1092 priv->ch0mm = ch0mm;
1093 priv->ch1mm = ch1mm;
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001094 priv->einj = einj;
Arthur Jones8f421c592008-07-25 01:49:04 -07001095
Nils Carlson295439f2009-12-15 16:47:42 -08001096 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
1097
1098 /* If scrubbing was already enabled by the bios, start maintaining it */
1099 pci_read_config_dword(pdev, I5100_MC, &dw);
1100 if (i5100_mc_scrben(dw)) {
1101 priv->scrub_enable = 1;
1102 schedule_delayed_work(&(priv->i5100_scrubbing),
1103 I5100_SCRUB_REFRESH_RATE);
1104 }
1105
Arthur Jones8f421c592008-07-25 01:49:04 -07001106 i5100_init_dimm_layout(pdev, mci);
1107 i5100_init_interleaving(pdev, mci);
1108
1109 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1110 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
1111 mci->edac_cap = EDAC_FLAG_SECDED;
1112 mci->mod_name = "i5100_edac.c";
1113 mci->mod_ver = "not versioned";
1114 mci->ctl_name = "i5100";
1115 mci->dev_name = pci_name(pdev);
Arthur Jonesb238e572008-07-25 01:49:08 -07001116 mci->ctl_page_to_phys = NULL;
Arthur Jones8f421c592008-07-25 01:49:04 -07001117
1118 mci->edac_check = i5100_check_error;
Nils Carlson295439f2009-12-15 16:47:42 -08001119 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
1120 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
Arthur Jones8f421c592008-07-25 01:49:04 -07001121
Niklas Söderlund53ceafd2012-08-08 12:30:57 -03001122 priv->inject_channel = 0;
1123 priv->inject_hlinesel = 0;
1124 priv->inject_deviceptr1 = 0;
1125 priv->inject_deviceptr2 = 0;
1126 priv->inject_eccmask1 = 0;
1127 priv->inject_eccmask2 = 0;
1128
Arthur Jones8f421c592008-07-25 01:49:04 -07001129 i5100_init_csrows(mci);
1130
1131 /* this strange construction seems to be in every driver, dunno why */
1132 switch (edac_op_state) {
1133 case EDAC_OPSTATE_POLL:
1134 case EDAC_OPSTATE_NMI:
1135 break;
1136 default:
1137 edac_op_state = EDAC_OPSTATE_POLL;
1138 break;
1139 }
1140
1141 if (edac_mc_add_mc(mci)) {
1142 ret = -ENODEV;
Nils Carlson295439f2009-12-15 16:47:42 -08001143 goto bail_scrub;
Arthur Jones8f421c592008-07-25 01:49:04 -07001144 }
1145
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001146 i5100_setup_debugfs(mci);
1147
Arthur Jonesb238e572008-07-25 01:49:08 -07001148 return ret;
Arthur Jones8f421c592008-07-25 01:49:04 -07001149
Nils Carlson295439f2009-12-15 16:47:42 -08001150bail_scrub:
1151 priv->scrub_enable = 0;
1152 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
Arthur Jones8f421c592008-07-25 01:49:04 -07001153 edac_mc_free(mci);
1154
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001155bail_disable_einj:
1156 pci_disable_device(einj);
1157
1158bail_einj:
1159 pci_dev_put(einj);
1160
Arthur Jonesb238e572008-07-25 01:49:08 -07001161bail_disable_ch1:
1162 pci_disable_device(ch1mm);
1163
Arthur Jones8f421c592008-07-25 01:49:04 -07001164bail_ch1:
1165 pci_dev_put(ch1mm);
1166
Arthur Jonesb238e572008-07-25 01:49:08 -07001167bail_disable_ch0:
1168 pci_disable_device(ch0mm);
1169
Arthur Jones8f421c592008-07-25 01:49:04 -07001170bail_ch0:
1171 pci_dev_put(ch0mm);
1172
Arthur Jonesb238e572008-07-25 01:49:08 -07001173bail_pdev:
1174 pci_disable_device(pdev);
1175
Arthur Jones8f421c592008-07-25 01:49:04 -07001176bail:
1177 return ret;
1178}
1179
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001180static void i5100_remove_one(struct pci_dev *pdev)
Arthur Jones8f421c592008-07-25 01:49:04 -07001181{
1182 struct mem_ctl_info *mci;
1183 struct i5100_priv *priv;
1184
1185 mci = edac_mc_del_mc(&pdev->dev);
1186
1187 if (!mci)
1188 return;
1189
1190 priv = mci->pvt_info;
Nils Carlson295439f2009-12-15 16:47:42 -08001191
Mauro Carvalho Chehab59b97962013-02-21 11:01:23 -03001192 debugfs_remove_recursive(priv->debugfs);
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001193
Nils Carlson295439f2009-12-15 16:47:42 -08001194 priv->scrub_enable = 0;
1195 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1196
Arthur Jonesb238e572008-07-25 01:49:08 -07001197 pci_disable_device(pdev);
1198 pci_disable_device(priv->ch0mm);
1199 pci_disable_device(priv->ch1mm);
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001200 pci_disable_device(priv->einj);
Arthur Jones8f421c592008-07-25 01:49:04 -07001201 pci_dev_put(priv->ch0mm);
1202 pci_dev_put(priv->ch1mm);
Niklas Söderlund52608ba2012-08-08 12:30:56 -03001203 pci_dev_put(priv->einj);
Arthur Jones8f421c592008-07-25 01:49:04 -07001204
1205 edac_mc_free(mci);
1206}
1207
Jingoo Hanba935f42013-12-06 10:23:08 +01001208static const struct pci_device_id i5100_pci_tbl[] = {
Arthur Jones8f421c592008-07-25 01:49:04 -07001209 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1210 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1211 { 0, }
1212};
1213MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1214
1215static struct pci_driver i5100_driver = {
1216 .name = KBUILD_BASENAME,
1217 .probe = i5100_init_one,
Greg Kroah-Hartman9b3c6e82012-12-21 13:23:51 -08001218 .remove = i5100_remove_one,
Arthur Jones8f421c592008-07-25 01:49:04 -07001219 .id_table = i5100_pci_tbl,
1220};
1221
1222static int __init i5100_init(void)
1223{
1224 int pci_rc;
1225
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001226 i5100_debugfs = debugfs_create_dir("i5100_edac", NULL);
Arthur Jones8f421c592008-07-25 01:49:04 -07001227
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001228 pci_rc = pci_register_driver(&i5100_driver);
Arthur Jones8f421c592008-07-25 01:49:04 -07001229 return (pci_rc < 0) ? pci_rc : 0;
1230}
1231
1232static void __exit i5100_exit(void)
1233{
Mauro Carvalho Chehab59b97962013-02-21 11:01:23 -03001234 debugfs_remove(i5100_debugfs);
Niklas Söderlund9cbc6d32012-08-08 12:30:58 -03001235
Arthur Jones8f421c592008-07-25 01:49:04 -07001236 pci_unregister_driver(&i5100_driver);
1237}
1238
1239module_init(i5100_init);
1240module_exit(i5100_exit);
1241
1242MODULE_LICENSE("GPL");
1243MODULE_AUTHOR
1244 ("Arthur Jones <ajones@riverbed.com>");
1245MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");