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Paul Walmsley02bfc032009-09-03 20:14:05 +03001/*
Paul Walmsley73591542010-02-22 22:09:32 -07002 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
Paul Walmsley02bfc032009-09-03 20:14:05 +03003 *
Paul Walmsley78183f32011-07-09 19:14:05 -06004 * Copyright (C) 2009-2011 Nokia Corporation
Paul Walmsley0a78c5c2012-04-19 04:04:31 -06005 * Copyright (C) 2012 Texas Instruments, Inc.
Paul Walmsley02bfc032009-09-03 20:14:05 +03006 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * XXX handle crossbar/shared link difference for L3?
Paul Walmsley73591542010-02-22 22:09:32 -070013 * XXX these should be marked initdata for multi-OMAP kernels
Paul Walmsley02bfc032009-09-03 20:14:05 +030014 */
Tony Lindgren3a8761c2012-10-08 09:11:22 -070015
16#include <linux/i2c-omap.h>
Arnd Bergmann22037472012-08-24 15:21:06 +020017#include <linux/platform_data/asoc-ti-mcbsp.h>
18#include <linux/platform_data/spi-omap2-mcspi.h>
19
Lokesh Vutla2b6c4e72012-10-15 14:04:53 -070020#include <plat-omap/dma-omap.h>
Thara Gopinathb6b58222011-02-23 00:14:05 -070021#include <plat/dmtimer.h>
Tony Lindgren2a296c82012-10-02 17:41:35 -070022
23#include "omap_hwmod.h"
Tony Lindgren68f39e72012-10-15 12:09:43 -070024#include "mmc.h"
Tony Lindgren1e0f51a2012-09-20 11:42:02 -070025#include "l3_2xxx.h"
Paul Walmsley02bfc032009-09-03 20:14:05 +030026
Tony Lindgrendbc04162012-08-31 10:59:07 -070027#include "soc.h"
Paul Walmsley43b40992010-02-22 22:09:34 -070028#include "omap_hwmod_common_data.h"
Paul Walmsley02bfc032009-09-03 20:14:05 +030029#include "prm-regbits-24xx.h"
Varadarajan, Charulatha165e2162010-09-23 20:02:40 +053030#include "cm-regbits-24xx.h"
Tony Lindgren3a8761c2012-10-08 09:11:22 -070031#include "i2c.h"
Paul Walmsleyff2516f2010-12-21 15:39:15 -070032#include "wd_timer.h"
Paul Walmsley02bfc032009-09-03 20:14:05 +030033
Paul Walmsley73591542010-02-22 22:09:32 -070034/*
35 * OMAP2430 hardware module integration data
36 *
Paul Walmsley844a3b62012-04-19 04:04:33 -060037 * All of the data in this section should be autogeneratable from the
Paul Walmsley73591542010-02-22 22:09:32 -070038 * TI hardware database or other technical documentation. Data that
39 * is driver-specific or driver-kernel integration-specific belongs
40 * elsewhere.
41 */
42
Paul Walmsley844a3b62012-04-19 04:04:33 -060043/*
44 * IP blocks
45 */
Senthilvadivu Guruswamyde56dbb2011-02-22 09:51:15 +020046
Paul Walmsley844a3b62012-04-19 04:04:33 -060047/* IVA2 (IVA2) */
Paul Walmsley3af35fb2012-04-19 04:04:38 -060048static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
49 { .name = "logic", .rst_shift = 0 },
50 { .name = "mmu", .rst_shift = 1 },
51};
52
Paul Walmsley08072ac2010-07-26 16:34:33 -060053static struct omap_hwmod omap2430_iva_hwmod = {
54 .name = "iva",
55 .class = &iva_hwmod_class,
Paul Walmsley3af35fb2012-04-19 04:04:38 -060056 .clkdm_name = "dsp_clkdm",
57 .rst_lines = omap2430_iva_resets,
58 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
59 .main_clk = "dsp_fck",
Paul Walmsley08072ac2010-07-26 16:34:33 -060060};
61
Paul Walmsley20042902010-09-30 02:40:12 +053062/* I2C common */
63static struct omap_hwmod_class_sysconfig i2c_sysc = {
64 .rev_offs = 0x00,
65 .sysc_offs = 0x20,
66 .syss_offs = 0x10,
Avinash.H.Md73d65f2011-03-03 14:22:46 -070067 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
68 SYSS_HAS_RESET_STATUS),
Paul Walmsley20042902010-09-30 02:40:12 +053069 .sysc_fields = &omap_hwmod_sysc_type1,
70};
71
72static struct omap_hwmod_class i2c_class = {
73 .name = "i2c",
74 .sysc = &i2c_sysc,
Andy Greendb791a72011-07-10 05:27:15 -060075 .rev = OMAP_I2C_IP_VERSION_1,
Avinash.H.M6d3c55f2011-07-10 05:27:16 -060076 .reset = &omap_i2c_reset,
Paul Walmsley20042902010-09-30 02:40:12 +053077};
78
Benoit Cousson50ebb772010-12-21 21:08:34 -070079static struct omap_i2c_dev_attr i2c_dev_attr = {
Paul Walmsley20042902010-09-30 02:40:12 +053080 .fifo_depth = 8, /* bytes */
Andy Green4d4441a2011-07-10 05:27:16 -060081 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
82 OMAP_I2C_FLAG_BUS_SHIFT_2 |
83 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
Paul Walmsley20042902010-09-30 02:40:12 +053084};
85
Benoit Cousson50ebb772010-12-21 21:08:34 -070086/* I2C1 */
Paul Walmsley20042902010-09-30 02:40:12 +053087static struct omap_hwmod omap2430_i2c1_hwmod = {
88 .name = "i2c1",
Andy Green3e600522011-07-10 05:27:14 -060089 .flags = HWMOD_16BIT_REG,
Paul Walmsley0d619a82011-07-09 19:14:07 -060090 .mpu_irqs = omap2_i2c1_mpu_irqs,
Paul Walmsleyd826ebf2011-07-09 19:14:07 -060091 .sdma_reqs = omap2_i2c1_sdma_reqs,
Paul Walmsley20042902010-09-30 02:40:12 +053092 .main_clk = "i2chs1_fck",
93 .prcm = {
94 .omap2 = {
95 /*
96 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
97 * I2CHS IP's do not follow the usual pattern.
98 * prcm_reg_id alone cannot be used to program
99 * the iclk and fclk. Needs to be handled using
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300100 * additional flags when clk handling is moved
Paul Walmsley20042902010-09-30 02:40:12 +0530101 * to hwmod framework.
102 */
103 .module_offs = CORE_MOD,
104 .prcm_reg_id = 1,
105 .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
106 .idlest_reg_id = 1,
107 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
108 },
109 },
Paul Walmsley20042902010-09-30 02:40:12 +0530110 .class = &i2c_class,
Benoit Cousson50ebb772010-12-21 21:08:34 -0700111 .dev_attr = &i2c_dev_attr,
Paul Walmsley20042902010-09-30 02:40:12 +0530112};
113
114/* I2C2 */
Paul Walmsley20042902010-09-30 02:40:12 +0530115static struct omap_hwmod omap2430_i2c2_hwmod = {
116 .name = "i2c2",
Andy Green3e600522011-07-10 05:27:14 -0600117 .flags = HWMOD_16BIT_REG,
Paul Walmsley0d619a82011-07-09 19:14:07 -0600118 .mpu_irqs = omap2_i2c2_mpu_irqs,
Paul Walmsleyd826ebf2011-07-09 19:14:07 -0600119 .sdma_reqs = omap2_i2c2_sdma_reqs,
Paul Walmsley20042902010-09-30 02:40:12 +0530120 .main_clk = "i2chs2_fck",
121 .prcm = {
122 .omap2 = {
123 .module_offs = CORE_MOD,
124 .prcm_reg_id = 1,
125 .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
126 .idlest_reg_id = 1,
127 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
128 },
129 },
Paul Walmsley20042902010-09-30 02:40:12 +0530130 .class = &i2c_class,
Benoit Cousson50ebb772010-12-21 21:08:34 -0700131 .dev_attr = &i2c_dev_attr,
Paul Walmsley20042902010-09-30 02:40:12 +0530132};
133
Varadarajan, Charulathaaeac0e42010-12-07 16:26:56 -0800134/* gpio5 */
135static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700136 { .irq = 33 + OMAP_INTC_START, }, /* INT_24XX_GPIO_BANK5 */
137 { .irq = -1 },
Varadarajan, Charulathaaeac0e42010-12-07 16:26:56 -0800138};
139
Varadarajan, Charulathaaeac0e42010-12-07 16:26:56 -0800140static struct omap_hwmod omap2430_gpio5_hwmod = {
141 .name = "gpio5",
Avinash.H.Mf95440c2011-04-05 21:10:15 +0530142 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
Varadarajan, Charulathaaeac0e42010-12-07 16:26:56 -0800143 .mpu_irqs = omap243x_gpio5_irqs,
Varadarajan, Charulathaaeac0e42010-12-07 16:26:56 -0800144 .main_clk = "gpio5_fck",
145 .prcm = {
146 .omap2 = {
147 .prcm_reg_id = 2,
148 .module_bit = OMAP2430_EN_GPIO5_SHIFT,
149 .module_offs = CORE_MOD,
150 .idlest_reg_id = 2,
151 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
152 },
153 },
Paul Walmsley273b9462011-07-09 19:14:08 -0600154 .class = &omap2xxx_gpio_hwmod_class,
Paul Walmsleycb484272012-04-19 04:04:33 -0600155 .dev_attr = &omap2xxx_gpio_dev_attr,
Varadarajan, Charulathaaeac0e42010-12-07 16:26:56 -0800156};
157
G, Manjunath Kondaiah82cbd1a2010-12-20 18:27:18 -0800158/* dma attributes */
159static struct omap_dma_dev_attr dma_dev_attr = {
160 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
161 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
162 .lch_count = 32,
163};
164
G, Manjunath Kondaiah82cbd1a2010-12-20 18:27:18 -0800165static struct omap_hwmod omap2430_dma_system_hwmod = {
166 .name = "dma",
Paul Walmsley273b9462011-07-09 19:14:08 -0600167 .class = &omap2xxx_dma_hwmod_class,
Paul Walmsley0d619a82011-07-09 19:14:07 -0600168 .mpu_irqs = omap2_dma_system_irqs,
G, Manjunath Kondaiah82cbd1a2010-12-20 18:27:18 -0800169 .main_clk = "core_l3_ck",
G, Manjunath Kondaiah82cbd1a2010-12-20 18:27:18 -0800170 .dev_attr = &dma_dev_attr,
G, Manjunath Kondaiah82cbd1a2010-12-20 18:27:18 -0800171 .flags = HWMOD_NO_IDLEST,
172};
173
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800174/* mailbox */
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800175static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700176 { .irq = 26 + OMAP_INTC_START, },
177 { .irq = -1 },
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800178};
179
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800180static struct omap_hwmod omap2430_mailbox_hwmod = {
181 .name = "mailbox",
Paul Walmsley273b9462011-07-09 19:14:08 -0600182 .class = &omap2xxx_mailbox_hwmod_class,
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800183 .mpu_irqs = omap2430_mailbox_irqs,
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800184 .main_clk = "mailboxes_ick",
185 .prcm = {
186 .omap2 = {
187 .prcm_reg_id = 1,
188 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
189 .module_offs = CORE_MOD,
190 .idlest_reg_id = 1,
191 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
192 },
193 },
Omar Ramirez Lunafca1ab52011-02-24 12:51:32 -0800194};
195
Charulatha V7f904c72011-02-17 09:53:10 -0800196/* mcspi3 */
197static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700198 { .irq = 91 + OMAP_INTC_START, },
199 { .irq = -1 },
Charulatha V7f904c72011-02-17 09:53:10 -0800200};
201
202static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
203 { .name = "tx0", .dma_req = 15 }, /* DMA_SPI3_TX0 */
204 { .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
205 { .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
206 { .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
Paul Walmsleybc614952011-07-09 19:14:07 -0600207 { .dma_req = -1 }
Charulatha V7f904c72011-02-17 09:53:10 -0800208};
209
Charulatha V7f904c72011-02-17 09:53:10 -0800210static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
211 .num_chipselect = 2,
212};
213
214static struct omap_hwmod omap2430_mcspi3_hwmod = {
Paul Walmsleybec93812012-04-19 04:03:50 -0600215 .name = "mcspi3",
Charulatha V7f904c72011-02-17 09:53:10 -0800216 .mpu_irqs = omap2430_mcspi3_mpu_irqs,
Charulatha V7f904c72011-02-17 09:53:10 -0800217 .sdma_reqs = omap2430_mcspi3_sdma_reqs,
Charulatha V7f904c72011-02-17 09:53:10 -0800218 .main_clk = "mcspi3_fck",
219 .prcm = {
220 .omap2 = {
221 .module_offs = CORE_MOD,
222 .prcm_reg_id = 2,
223 .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
224 .idlest_reg_id = 2,
225 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
226 },
227 },
Paul Walmsley273b9462011-07-09 19:14:08 -0600228 .class = &omap2xxx_mcspi_class,
229 .dev_attr = &omap_mcspi3_dev_attr,
Charulatha V7f904c72011-02-17 09:53:10 -0800230};
231
Paul Walmsley844a3b62012-04-19 04:04:33 -0600232/* usbhsotg */
Hema HK44d02ac2011-02-17 12:07:17 +0530233static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
234 .rev_offs = 0x0400,
235 .sysc_offs = 0x0404,
236 .syss_offs = 0x0408,
237 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
238 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
239 SYSC_HAS_AUTOIDLE),
240 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
241 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
242 .sysc_fields = &omap_hwmod_sysc_type1,
243};
244
245static struct omap_hwmod_class usbotg_class = {
246 .name = "usbotg",
247 .sysc = &omap2430_usbhsotg_sysc,
248};
249
250/* usb_otg_hs */
251static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
252
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700253 { .name = "mc", .irq = 92 + OMAP_INTC_START, },
254 { .name = "dma", .irq = 93 + OMAP_INTC_START, },
255 { .irq = -1 },
Hema HK44d02ac2011-02-17 12:07:17 +0530256};
257
258static struct omap_hwmod omap2430_usbhsotg_hwmod = {
259 .name = "usb_otg_hs",
260 .mpu_irqs = omap2430_usbhsotg_mpu_irqs,
Hema HK44d02ac2011-02-17 12:07:17 +0530261 .main_clk = "usbhs_ick",
262 .prcm = {
263 .omap2 = {
264 .prcm_reg_id = 1,
265 .module_bit = OMAP2430_EN_USBHS_MASK,
266 .module_offs = CORE_MOD,
267 .idlest_reg_id = 1,
268 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
269 },
270 },
Hema HK44d02ac2011-02-17 12:07:17 +0530271 .class = &usbotg_class,
272 /*
273 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
274 * broken when autoidle is enabled
275 * workaround is to disable the autoidle bit at module level.
276 */
277 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
278 | HWMOD_SWSUP_MSTANDBY,
Hema HK44d02ac2011-02-17 12:07:17 +0530279};
280
Charulatha V37801b32011-02-24 12:51:46 -0800281/*
282 * 'mcbsp' class
283 * multi channel buffered serial port controller
284 */
Tony Lindgren04aa67d2011-02-22 10:54:12 -0800285
Charulatha V37801b32011-02-24 12:51:46 -0800286static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
287 .rev_offs = 0x007C,
288 .sysc_offs = 0x008C,
289 .sysc_flags = (SYSC_HAS_SOFTRESET),
290 .sysc_fields = &omap_hwmod_sysc_type1,
291};
292
293static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
294 .name = "mcbsp",
295 .sysc = &omap2430_mcbsp_sysc,
296 .rev = MCBSP_CONFIG_TYPE2,
297};
298
Peter Ujfalusidb382a82012-06-18 16:18:43 -0600299static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
300 { .role = "pad_fck", .clk = "mcbsp_clks" },
301 { .role = "prcm_fck", .clk = "func_96m_ck" },
302};
303
Charulatha V37801b32011-02-24 12:51:46 -0800304/* mcbsp1 */
305static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700306 { .name = "tx", .irq = 59 + OMAP_INTC_START, },
307 { .name = "rx", .irq = 60 + OMAP_INTC_START, },
308 { .name = "ovr", .irq = 61 + OMAP_INTC_START, },
309 { .name = "common", .irq = 64 + OMAP_INTC_START, },
310 { .irq = -1 },
Charulatha V37801b32011-02-24 12:51:46 -0800311};
312
Charulatha V37801b32011-02-24 12:51:46 -0800313static struct omap_hwmod omap2430_mcbsp1_hwmod = {
314 .name = "mcbsp1",
315 .class = &omap2430_mcbsp_hwmod_class,
316 .mpu_irqs = omap2430_mcbsp1_irqs,
Paul Walmsleyd826ebf2011-07-09 19:14:07 -0600317 .sdma_reqs = omap2_mcbsp1_sdma_reqs,
Charulatha V37801b32011-02-24 12:51:46 -0800318 .main_clk = "mcbsp1_fck",
319 .prcm = {
320 .omap2 = {
321 .prcm_reg_id = 1,
322 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
323 .module_offs = CORE_MOD,
324 .idlest_reg_id = 1,
325 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
326 },
327 },
Peter Ujfalusidb382a82012-06-18 16:18:43 -0600328 .opt_clks = mcbsp_opt_clks,
329 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
Charulatha V37801b32011-02-24 12:51:46 -0800330};
331
332/* mcbsp2 */
333static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700334 { .name = "tx", .irq = 62 + OMAP_INTC_START, },
335 { .name = "rx", .irq = 63 + OMAP_INTC_START, },
336 { .name = "common", .irq = 16 + OMAP_INTC_START, },
337 { .irq = -1 },
Charulatha V37801b32011-02-24 12:51:46 -0800338};
339
Charulatha V37801b32011-02-24 12:51:46 -0800340static struct omap_hwmod omap2430_mcbsp2_hwmod = {
341 .name = "mcbsp2",
342 .class = &omap2430_mcbsp_hwmod_class,
343 .mpu_irqs = omap2430_mcbsp2_irqs,
Paul Walmsleyd826ebf2011-07-09 19:14:07 -0600344 .sdma_reqs = omap2_mcbsp2_sdma_reqs,
Charulatha V37801b32011-02-24 12:51:46 -0800345 .main_clk = "mcbsp2_fck",
346 .prcm = {
347 .omap2 = {
348 .prcm_reg_id = 1,
349 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
350 .module_offs = CORE_MOD,
351 .idlest_reg_id = 1,
352 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
353 },
354 },
Peter Ujfalusidb382a82012-06-18 16:18:43 -0600355 .opt_clks = mcbsp_opt_clks,
356 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
Charulatha V37801b32011-02-24 12:51:46 -0800357};
358
359/* mcbsp3 */
360static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700361 { .name = "tx", .irq = 89 + OMAP_INTC_START, },
362 { .name = "rx", .irq = 90 + OMAP_INTC_START, },
363 { .name = "common", .irq = 17 + OMAP_INTC_START, },
364 { .irq = -1 },
Charulatha V37801b32011-02-24 12:51:46 -0800365};
366
Charulatha V37801b32011-02-24 12:51:46 -0800367static struct omap_hwmod omap2430_mcbsp3_hwmod = {
368 .name = "mcbsp3",
369 .class = &omap2430_mcbsp_hwmod_class,
370 .mpu_irqs = omap2430_mcbsp3_irqs,
Paul Walmsleyd826ebf2011-07-09 19:14:07 -0600371 .sdma_reqs = omap2_mcbsp3_sdma_reqs,
Charulatha V37801b32011-02-24 12:51:46 -0800372 .main_clk = "mcbsp3_fck",
373 .prcm = {
374 .omap2 = {
375 .prcm_reg_id = 1,
376 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
377 .module_offs = CORE_MOD,
378 .idlest_reg_id = 2,
379 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
380 },
381 },
Peter Ujfalusidb382a82012-06-18 16:18:43 -0600382 .opt_clks = mcbsp_opt_clks,
383 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
Charulatha V37801b32011-02-24 12:51:46 -0800384};
385
386/* mcbsp4 */
387static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700388 { .name = "tx", .irq = 54 + OMAP_INTC_START, },
389 { .name = "rx", .irq = 55 + OMAP_INTC_START, },
390 { .name = "common", .irq = 18 + OMAP_INTC_START, },
391 { .irq = -1 },
Charulatha V37801b32011-02-24 12:51:46 -0800392};
393
394static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
395 { .name = "rx", .dma_req = 20 },
396 { .name = "tx", .dma_req = 19 },
Paul Walmsleybc614952011-07-09 19:14:07 -0600397 { .dma_req = -1 }
Charulatha V37801b32011-02-24 12:51:46 -0800398};
399
Charulatha V37801b32011-02-24 12:51:46 -0800400static struct omap_hwmod omap2430_mcbsp4_hwmod = {
401 .name = "mcbsp4",
402 .class = &omap2430_mcbsp_hwmod_class,
403 .mpu_irqs = omap2430_mcbsp4_irqs,
Charulatha V37801b32011-02-24 12:51:46 -0800404 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
Charulatha V37801b32011-02-24 12:51:46 -0800405 .main_clk = "mcbsp4_fck",
406 .prcm = {
407 .omap2 = {
408 .prcm_reg_id = 1,
409 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
410 .module_offs = CORE_MOD,
411 .idlest_reg_id = 2,
412 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
413 },
414 },
Peter Ujfalusidb382a82012-06-18 16:18:43 -0600415 .opt_clks = mcbsp_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
Charulatha V37801b32011-02-24 12:51:46 -0800417};
418
419/* mcbsp5 */
420static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700421 { .name = "tx", .irq = 81 + OMAP_INTC_START, },
422 { .name = "rx", .irq = 82 + OMAP_INTC_START, },
423 { .name = "common", .irq = 19 + OMAP_INTC_START, },
424 { .irq = -1 },
Charulatha V37801b32011-02-24 12:51:46 -0800425};
426
427static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
428 { .name = "rx", .dma_req = 22 },
429 { .name = "tx", .dma_req = 21 },
Paul Walmsleybc614952011-07-09 19:14:07 -0600430 { .dma_req = -1 }
Charulatha V37801b32011-02-24 12:51:46 -0800431};
432
Charulatha V37801b32011-02-24 12:51:46 -0800433static struct omap_hwmod omap2430_mcbsp5_hwmod = {
434 .name = "mcbsp5",
435 .class = &omap2430_mcbsp_hwmod_class,
436 .mpu_irqs = omap2430_mcbsp5_irqs,
Charulatha V37801b32011-02-24 12:51:46 -0800437 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
Charulatha V37801b32011-02-24 12:51:46 -0800438 .main_clk = "mcbsp5_fck",
439 .prcm = {
440 .omap2 = {
441 .prcm_reg_id = 1,
442 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
443 .module_offs = CORE_MOD,
444 .idlest_reg_id = 2,
445 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
446 },
447 },
Peter Ujfalusidb382a82012-06-18 16:18:43 -0600448 .opt_clks = mcbsp_opt_clks,
449 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
Charulatha V37801b32011-02-24 12:51:46 -0800450};
Tony Lindgren04aa67d2011-02-22 10:54:12 -0800451
Paul Walmsleybce06f32011-03-01 13:12:55 -0800452/* MMC/SD/SDIO common */
Paul Walmsleybce06f32011-03-01 13:12:55 -0800453static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
454 .rev_offs = 0x1fc,
455 .sysc_offs = 0x10,
456 .syss_offs = 0x14,
457 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
458 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
459 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
460 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
461 .sysc_fields = &omap_hwmod_sysc_type1,
462};
463
464static struct omap_hwmod_class omap2430_mmc_class = {
465 .name = "mmc",
466 .sysc = &omap2430_mmc_sysc,
467};
468
469/* MMC/SD/SDIO1 */
Paul Walmsleybce06f32011-03-01 13:12:55 -0800470static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700471 { .irq = 83 + OMAP_INTC_START, },
472 { .irq = -1 },
Paul Walmsleybce06f32011-03-01 13:12:55 -0800473};
474
475static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
476 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
477 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
Paul Walmsleybc614952011-07-09 19:14:07 -0600478 { .dma_req = -1 }
Paul Walmsleybce06f32011-03-01 13:12:55 -0800479};
480
481static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
482 { .role = "dbck", .clk = "mmchsdb1_fck" },
483};
484
Kishore Kadiyala6ab89462011-03-01 13:12:56 -0800485static struct omap_mmc_dev_attr mmc1_dev_attr = {
486 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
487};
488
Paul Walmsleybce06f32011-03-01 13:12:55 -0800489static struct omap_hwmod omap2430_mmc1_hwmod = {
490 .name = "mmc1",
491 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
492 .mpu_irqs = omap2430_mmc1_mpu_irqs,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800493 .sdma_reqs = omap2430_mmc1_sdma_reqs,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800494 .opt_clks = omap2430_mmc1_opt_clks,
495 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
496 .main_clk = "mmchs1_fck",
497 .prcm = {
498 .omap2 = {
499 .module_offs = CORE_MOD,
500 .prcm_reg_id = 2,
501 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
502 .idlest_reg_id = 2,
503 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
504 },
505 },
Kishore Kadiyala6ab89462011-03-01 13:12:56 -0800506 .dev_attr = &mmc1_dev_attr,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800507 .class = &omap2430_mmc_class,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800508};
509
510/* MMC/SD/SDIO2 */
Paul Walmsleybce06f32011-03-01 13:12:55 -0800511static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
Tony Lindgren7d7e1eb2012-08-27 17:43:01 -0700512 { .irq = 86 + OMAP_INTC_START, },
513 { .irq = -1 },
Paul Walmsleybce06f32011-03-01 13:12:55 -0800514};
515
516static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
517 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
518 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
Paul Walmsleybc614952011-07-09 19:14:07 -0600519 { .dma_req = -1 }
Paul Walmsleybce06f32011-03-01 13:12:55 -0800520};
521
522static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
523 { .role = "dbck", .clk = "mmchsdb2_fck" },
524};
525
Paul Walmsleybce06f32011-03-01 13:12:55 -0800526static struct omap_hwmod omap2430_mmc2_hwmod = {
527 .name = "mmc2",
528 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
529 .mpu_irqs = omap2430_mmc2_mpu_irqs,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800530 .sdma_reqs = omap2430_mmc2_sdma_reqs,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800531 .opt_clks = omap2430_mmc2_opt_clks,
532 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
533 .main_clk = "mmchs2_fck",
534 .prcm = {
535 .omap2 = {
536 .module_offs = CORE_MOD,
537 .prcm_reg_id = 2,
538 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
539 .idlest_reg_id = 2,
540 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
541 },
542 },
Paul Walmsleybce06f32011-03-01 13:12:55 -0800543 .class = &omap2430_mmc_class,
Paul Walmsleybce06f32011-03-01 13:12:55 -0800544};
Kevin Hilman046465b2010-09-27 20:19:30 +0530545
Paul Walmsleyf32bd772012-05-08 11:34:28 -0600546/* HDQ1W/1-wire */
547static struct omap_hwmod omap2430_hdq1w_hwmod = {
548 .name = "hdq1w",
549 .mpu_irqs = omap2_hdq1w_mpu_irqs,
550 .main_clk = "hdq_fck",
551 .prcm = {
552 .omap2 = {
553 .module_offs = CORE_MOD,
554 .prcm_reg_id = 1,
555 .module_bit = OMAP24XX_EN_HDQ_SHIFT,
556 .idlest_reg_id = 1,
557 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
558 },
559 },
560 .class = &omap2_hdq1w_class,
561};
562
Paul Walmsley844a3b62012-04-19 04:04:33 -0600563/*
564 * interfaces
565 */
566
567/* L3 -> L4_CORE interface */
Paul Walmsley844a3b62012-04-19 04:04:33 -0600568/* l3_core -> usbhsotg interface */
569static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
570 .master = &omap2430_usbhsotg_hwmod,
Paul Walmsleycb484272012-04-19 04:04:33 -0600571 .slave = &omap2xxx_l3_main_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600572 .clk = "core_l3_ck",
573 .user = OCP_USER_MPU,
574};
575
576/* L4 CORE -> I2C1 interface */
577static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600578 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600579 .slave = &omap2430_i2c1_hwmod,
580 .clk = "i2c1_ick",
581 .addr = omap2_i2c1_addr_space,
582 .user = OCP_USER_MPU | OCP_USER_SDMA,
583};
584
585/* L4 CORE -> I2C2 interface */
586static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600587 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600588 .slave = &omap2430_i2c2_hwmod,
589 .clk = "i2c2_ick",
590 .addr = omap2_i2c2_addr_space,
591 .user = OCP_USER_MPU | OCP_USER_SDMA,
592};
593
Paul Walmsley844a3b62012-04-19 04:04:33 -0600594static struct omap_hwmod_addr_space omap2430_usbhsotg_addrs[] = {
595 {
596 .pa_start = OMAP243X_HS_BASE,
597 .pa_end = OMAP243X_HS_BASE + SZ_4K - 1,
598 .flags = ADDR_TYPE_RT
599 },
600 { }
601};
602
603/* l4_core ->usbhsotg interface */
604static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600605 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600606 .slave = &omap2430_usbhsotg_hwmod,
607 .clk = "usb_l4_ick",
608 .addr = omap2430_usbhsotg_addrs,
609 .user = OCP_USER_MPU,
610};
611
612/* L4 CORE -> MMC1 interface */
613static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600614 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600615 .slave = &omap2430_mmc1_hwmod,
616 .clk = "mmchs1_ick",
617 .addr = omap2430_mmc1_addr_space,
618 .user = OCP_USER_MPU | OCP_USER_SDMA,
619};
620
621/* L4 CORE -> MMC2 interface */
622static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600623 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600624 .slave = &omap2430_mmc2_hwmod,
625 .clk = "mmchs2_ick",
626 .addr = omap2430_mmc2_addr_space,
627 .user = OCP_USER_MPU | OCP_USER_SDMA,
628};
629
Paul Walmsley844a3b62012-04-19 04:04:33 -0600630/* l4 core -> mcspi3 interface */
631static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600632 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600633 .slave = &omap2430_mcspi3_hwmod,
634 .clk = "mcspi3_ick",
635 .addr = omap2430_mcspi3_addr_space,
636 .user = OCP_USER_MPU | OCP_USER_SDMA,
637};
638
639/* IVA2 <- L3 interface */
640static struct omap_hwmod_ocp_if omap2430_l3__iva = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600641 .master = &omap2xxx_l3_main_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600642 .slave = &omap2430_iva_hwmod,
Paul Walmsley3af35fb2012-04-19 04:04:38 -0600643 .clk = "core_l3_ck",
Paul Walmsley844a3b62012-04-19 04:04:33 -0600644 .user = OCP_USER_MPU | OCP_USER_SDMA,
645};
646
647static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
648 {
649 .pa_start = 0x49018000,
650 .pa_end = 0x49018000 + SZ_1K - 1,
651 .flags = ADDR_TYPE_RT
652 },
653 { }
654};
655
656/* l4_wkup -> timer1 */
657static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600658 .master = &omap2xxx_l4_wkup_hwmod,
659 .slave = &omap2xxx_timer1_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600660 .clk = "gpt1_ick",
661 .addr = omap2430_timer1_addrs,
662 .user = OCP_USER_MPU | OCP_USER_SDMA,
663};
664
Paul Walmsley844a3b62012-04-19 04:04:33 -0600665/* l4_wkup -> wd_timer2 */
666static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
667 {
668 .pa_start = 0x49016000,
669 .pa_end = 0x4901607f,
670 .flags = ADDR_TYPE_RT
671 },
672 { }
673};
674
675static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600676 .master = &omap2xxx_l4_wkup_hwmod,
677 .slave = &omap2xxx_wd_timer2_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600678 .clk = "mpu_wdt_ick",
679 .addr = omap2430_wd_timer2_addrs,
680 .user = OCP_USER_MPU | OCP_USER_SDMA,
681};
682
Paul Walmsley844a3b62012-04-19 04:04:33 -0600683/* l4_wkup -> gpio1 */
684static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
685 {
686 .pa_start = 0x4900C000,
687 .pa_end = 0x4900C1ff,
688 .flags = ADDR_TYPE_RT
689 },
690 { }
691};
692
693static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600694 .master = &omap2xxx_l4_wkup_hwmod,
695 .slave = &omap2xxx_gpio1_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600696 .clk = "gpios_ick",
697 .addr = omap2430_gpio1_addr_space,
698 .user = OCP_USER_MPU | OCP_USER_SDMA,
699};
700
701/* l4_wkup -> gpio2 */
702static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
703 {
704 .pa_start = 0x4900E000,
705 .pa_end = 0x4900E1ff,
706 .flags = ADDR_TYPE_RT
707 },
708 { }
709};
710
711static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600712 .master = &omap2xxx_l4_wkup_hwmod,
713 .slave = &omap2xxx_gpio2_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600714 .clk = "gpios_ick",
715 .addr = omap2430_gpio2_addr_space,
716 .user = OCP_USER_MPU | OCP_USER_SDMA,
717};
718
719/* l4_wkup -> gpio3 */
720static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
721 {
722 .pa_start = 0x49010000,
723 .pa_end = 0x490101ff,
724 .flags = ADDR_TYPE_RT
725 },
726 { }
727};
728
729static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600730 .master = &omap2xxx_l4_wkup_hwmod,
731 .slave = &omap2xxx_gpio3_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600732 .clk = "gpios_ick",
733 .addr = omap2430_gpio3_addr_space,
734 .user = OCP_USER_MPU | OCP_USER_SDMA,
735};
736
737/* l4_wkup -> gpio4 */
738static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
739 {
740 .pa_start = 0x49012000,
741 .pa_end = 0x490121ff,
742 .flags = ADDR_TYPE_RT
743 },
744 { }
745};
746
747static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600748 .master = &omap2xxx_l4_wkup_hwmod,
749 .slave = &omap2xxx_gpio4_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600750 .clk = "gpios_ick",
751 .addr = omap2430_gpio4_addr_space,
752 .user = OCP_USER_MPU | OCP_USER_SDMA,
753};
754
755/* l4_core -> gpio5 */
756static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
757 {
758 .pa_start = 0x480B6000,
759 .pa_end = 0x480B61ff,
760 .flags = ADDR_TYPE_RT
761 },
762 { }
763};
764
765static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600766 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600767 .slave = &omap2430_gpio5_hwmod,
768 .clk = "gpio5_ick",
769 .addr = omap2430_gpio5_addr_space,
770 .user = OCP_USER_MPU | OCP_USER_SDMA,
771};
772
773/* dma_system -> L3 */
774static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
775 .master = &omap2430_dma_system_hwmod,
Paul Walmsleycb484272012-04-19 04:04:33 -0600776 .slave = &omap2xxx_l3_main_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600777 .clk = "core_l3_ck",
778 .user = OCP_USER_MPU | OCP_USER_SDMA,
779};
780
781/* l4_core -> dma_system */
782static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600783 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600784 .slave = &omap2430_dma_system_hwmod,
785 .clk = "sdma_ick",
786 .addr = omap2_dma_system_addrs,
787 .user = OCP_USER_MPU | OCP_USER_SDMA,
788};
789
790/* l4_core -> mailbox */
791static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600792 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600793 .slave = &omap2430_mailbox_hwmod,
794 .addr = omap2_mailbox_addrs,
795 .user = OCP_USER_MPU | OCP_USER_SDMA,
796};
797
798/* l4_core -> mcbsp1 */
799static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600800 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600801 .slave = &omap2430_mcbsp1_hwmod,
802 .clk = "mcbsp1_ick",
803 .addr = omap2_mcbsp1_addrs,
804 .user = OCP_USER_MPU | OCP_USER_SDMA,
805};
806
807/* l4_core -> mcbsp2 */
808static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600809 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600810 .slave = &omap2430_mcbsp2_hwmod,
811 .clk = "mcbsp2_ick",
812 .addr = omap2xxx_mcbsp2_addrs,
813 .user = OCP_USER_MPU | OCP_USER_SDMA,
814};
815
816static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
817 {
818 .name = "mpu",
819 .pa_start = 0x4808C000,
820 .pa_end = 0x4808C0ff,
821 .flags = ADDR_TYPE_RT
822 },
823 { }
824};
825
826/* l4_core -> mcbsp3 */
827static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600828 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600829 .slave = &omap2430_mcbsp3_hwmod,
830 .clk = "mcbsp3_ick",
831 .addr = omap2430_mcbsp3_addrs,
832 .user = OCP_USER_MPU | OCP_USER_SDMA,
833};
834
835static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
836 {
837 .name = "mpu",
838 .pa_start = 0x4808E000,
839 .pa_end = 0x4808E0ff,
840 .flags = ADDR_TYPE_RT
841 },
842 { }
843};
844
845/* l4_core -> mcbsp4 */
846static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600847 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600848 .slave = &omap2430_mcbsp4_hwmod,
849 .clk = "mcbsp4_ick",
850 .addr = omap2430_mcbsp4_addrs,
851 .user = OCP_USER_MPU | OCP_USER_SDMA,
852};
853
854static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
855 {
856 .name = "mpu",
857 .pa_start = 0x48096000,
858 .pa_end = 0x480960ff,
859 .flags = ADDR_TYPE_RT
860 },
861 { }
862};
863
864/* l4_core -> mcbsp5 */
865static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
Paul Walmsleycb484272012-04-19 04:04:33 -0600866 .master = &omap2xxx_l4_core_hwmod,
Paul Walmsley844a3b62012-04-19 04:04:33 -0600867 .slave = &omap2430_mcbsp5_hwmod,
868 .clk = "mcbsp5_ick",
869 .addr = omap2430_mcbsp5_addrs,
870 .user = OCP_USER_MPU | OCP_USER_SDMA,
871};
872
Paul Walmsleyf32bd772012-05-08 11:34:28 -0600873/* l4_core -> hdq1w */
874static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
875 .master = &omap2xxx_l4_core_hwmod,
876 .slave = &omap2430_hdq1w_hwmod,
877 .clk = "hdq_ick",
878 .addr = omap2_hdq1w_addr_space,
879 .user = OCP_USER_MPU | OCP_USER_SDMA,
880 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
881};
882
Vaibhav Hiremathc8d82ff2012-05-08 11:34:30 -0600883/* l4_wkup -> 32ksync_counter */
884static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
885 {
886 .pa_start = 0x49020000,
887 .pa_end = 0x4902001f,
888 .flags = ADDR_TYPE_RT
889 },
890 { }
891};
892
Afzal Mohammed49484a62012-09-23 17:28:24 -0600893static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
894 {
895 .pa_start = 0x6e000000,
896 .pa_end = 0x6e000fff,
897 .flags = ADDR_TYPE_RT
898 },
899 { }
900};
901
Vaibhav Hiremathc8d82ff2012-05-08 11:34:30 -0600902static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
903 .master = &omap2xxx_l4_wkup_hwmod,
904 .slave = &omap2xxx_counter_32k_hwmod,
905 .clk = "sync_32k_ick",
906 .addr = omap2430_counter_32k_addrs,
907 .user = OCP_USER_MPU | OCP_USER_SDMA,
908};
909
Afzal Mohammed49484a62012-09-23 17:28:24 -0600910static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
911 .master = &omap2xxx_l3_main_hwmod,
912 .slave = &omap2xxx_gpmc_hwmod,
913 .clk = "core_l3_ck",
914 .addr = omap2430_gpmc_addrs,
915 .user = OCP_USER_MPU | OCP_USER_SDMA,
916};
917
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600918static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
Paul Walmsley6a297552012-04-19 04:04:34 -0600919 &omap2xxx_l3_main__l4_core,
920 &omap2xxx_mpu__l3_main,
921 &omap2xxx_dss__l3,
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600922 &omap2430_usbhsotg__l3,
923 &omap2430_l4_core__i2c1,
924 &omap2430_l4_core__i2c2,
Paul Walmsley6a297552012-04-19 04:04:34 -0600925 &omap2xxx_l4_core__l4_wkup,
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600926 &omap2_l4_core__uart1,
927 &omap2_l4_core__uart2,
928 &omap2_l4_core__uart3,
929 &omap2430_l4_core__usbhsotg,
930 &omap2430_l4_core__mmc1,
931 &omap2430_l4_core__mmc2,
Paul Walmsley6a297552012-04-19 04:04:34 -0600932 &omap2xxx_l4_core__mcspi1,
933 &omap2xxx_l4_core__mcspi2,
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600934 &omap2430_l4_core__mcspi3,
935 &omap2430_l3__iva,
936 &omap2430_l4_wkup__timer1,
Paul Walmsley6a297552012-04-19 04:04:34 -0600937 &omap2xxx_l4_core__timer2,
938 &omap2xxx_l4_core__timer3,
939 &omap2xxx_l4_core__timer4,
940 &omap2xxx_l4_core__timer5,
941 &omap2xxx_l4_core__timer6,
942 &omap2xxx_l4_core__timer7,
943 &omap2xxx_l4_core__timer8,
944 &omap2xxx_l4_core__timer9,
945 &omap2xxx_l4_core__timer10,
946 &omap2xxx_l4_core__timer11,
947 &omap2xxx_l4_core__timer12,
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600948 &omap2430_l4_wkup__wd_timer2,
Paul Walmsley6a297552012-04-19 04:04:34 -0600949 &omap2xxx_l4_core__dss,
950 &omap2xxx_l4_core__dss_dispc,
951 &omap2xxx_l4_core__dss_rfbi,
952 &omap2xxx_l4_core__dss_venc,
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600953 &omap2430_l4_wkup__gpio1,
954 &omap2430_l4_wkup__gpio2,
955 &omap2430_l4_wkup__gpio3,
956 &omap2430_l4_wkup__gpio4,
957 &omap2430_l4_core__gpio5,
958 &omap2430_dma_system__l3,
959 &omap2430_l4_core__dma_system,
960 &omap2430_l4_core__mailbox,
961 &omap2430_l4_core__mcbsp1,
962 &omap2430_l4_core__mcbsp2,
963 &omap2430_l4_core__mcbsp3,
964 &omap2430_l4_core__mcbsp4,
965 &omap2430_l4_core__mcbsp5,
Paul Walmsleyf32bd772012-05-08 11:34:28 -0600966 &omap2430_l4_core__hdq1w,
Paul Walmsleye9b0a2f2012-09-23 17:28:25 -0600967 &omap2xxx_l4_core__rng,
Vaibhav Hiremathc8d82ff2012-05-08 11:34:30 -0600968 &omap2430_l4_wkup__counter_32k,
Afzal Mohammed49484a62012-09-23 17:28:24 -0600969 &omap2430_l3__gpmc,
Paul Walmsley02bfc032009-09-03 20:14:05 +0300970 NULL,
971};
972
Paul Walmsley73591542010-02-22 22:09:32 -0700973int __init omap2430_hwmod_init(void)
974{
Kevin Hilman9ebfd282012-06-18 12:12:23 -0600975 omap_hwmod_init();
Paul Walmsley0a78c5c2012-04-19 04:04:31 -0600976 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
Paul Walmsley73591542010-02-22 22:09:32 -0700977}