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Vladimir Barinov310355c2008-02-18 11:40:22 +01001/*
2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
3 *
Vladimir Barinovd6b52032008-09-29 23:14:11 +04004 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
Vladimir Barinov310355c2008-02-18 11:40:22 +01005 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/device.h>
15#include <linux/delay.h>
16#include <linux/io.h>
17#include <linux/clk.h>
18
19#include <sound/core.h>
20#include <sound/pcm.h>
21#include <sound/pcm_params.h>
22#include <sound/initval.h>
23#include <sound/soc.h>
24
Mark Brownff7d04b2009-07-08 16:54:51 +010025#include <mach/asp.h>
26
Vladimir Barinov310355c2008-02-18 11:40:22 +010027#include "davinci-pcm.h"
28
David Brownella62114c2009-05-14 12:47:42 -070029
30/*
31 * NOTE: terminology here is confusing.
32 *
33 * - This driver supports the "Audio Serial Port" (ASP),
34 * found on dm6446, dm355, and other DaVinci chips.
35 *
36 * - But it labels it a "Multi-channel Buffered Serial Port"
37 * (McBSP) as on older chips like the dm642 ... which was
38 * backward-compatible, possibly explaining that confusion.
39 *
40 * - OMAP chips have a controller called McBSP, which is
41 * incompatible with the DaVinci flavor of McBSP.
42 *
43 * - Newer DaVinci chips have a controller called McASP,
44 * incompatible with ASP and with either McBSP.
45 *
46 * In short: this uses ASP to implement I2S, not McBSP.
47 * And it won't be the only DaVinci implemention of I2S.
48 */
Vladimir Barinov310355c2008-02-18 11:40:22 +010049#define DAVINCI_MCBSP_DRR_REG 0x00
50#define DAVINCI_MCBSP_DXR_REG 0x04
51#define DAVINCI_MCBSP_SPCR_REG 0x08
52#define DAVINCI_MCBSP_RCR_REG 0x0c
53#define DAVINCI_MCBSP_XCR_REG 0x10
54#define DAVINCI_MCBSP_SRGR_REG 0x14
55#define DAVINCI_MCBSP_PCR_REG 0x24
56
57#define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
58#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
59#define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
60#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
61#define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
62#define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
63#define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
64
65#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
66#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
67#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
Troy Kiskyf5cfa952009-07-04 19:29:57 -070068#define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
Vladimir Barinov310355c2008-02-18 11:40:22 +010069#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
70
71#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
72#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
73#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
74#define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
75#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
76
77#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
78#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
79#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
80
81#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
82#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
83#define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
84#define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
Hugo Villeneuveb402dff2008-11-08 13:26:09 -050085#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
Vladimir Barinov310355c2008-02-18 11:40:22 +010086#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
87#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
88#define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
89#define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
90
Vladimir Barinov310355c2008-02-18 11:40:22 +010091enum {
92 DAVINCI_MCBSP_WORD_8 = 0,
93 DAVINCI_MCBSP_WORD_12,
94 DAVINCI_MCBSP_WORD_16,
95 DAVINCI_MCBSP_WORD_20,
96 DAVINCI_MCBSP_WORD_24,
97 DAVINCI_MCBSP_WORD_32,
98};
99
100static struct davinci_pcm_dma_params davinci_i2s_pcm_out = {
101 .name = "I2S PCM Stereo out",
102};
103
104static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
105 .name = "I2S PCM Stereo in",
106};
107
108struct davinci_mcbsp_dev {
109 void __iomem *base;
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700110#define MOD_DSP_A 0
111#define MOD_DSP_B 1
112 int mode;
Troy Kiskyc392bec2009-07-04 19:29:52 -0700113 u32 pcr;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100114 struct clk *clk;
115 struct davinci_pcm_dma_params *dma_params[2];
116};
117
118static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
119 int reg, u32 val)
120{
121 __raw_writel(val, dev->base + reg);
122}
123
124static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
125{
126 return __raw_readl(dev->base + reg);
127}
128
Troy Kiskyc392bec2009-07-04 19:29:52 -0700129static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
130{
131 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
132 /* The clock needs to toggle to complete reset.
133 * So, fake it by toggling the clk polarity.
134 */
135 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
136 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
137}
138
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700139static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
140 struct snd_pcm_substream *substream)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100141{
142 struct snd_soc_pcm_runtime *rtd = substream->private_data;
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530143 struct snd_soc_device *socdev = rtd->socdev;
Mark Brown87689d52008-12-02 16:01:14 +0000144 struct snd_soc_platform *platform = socdev->card->platform;
Troy Kiskyc392bec2009-07-04 19:29:52 -0700145 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
Troy Kisky35cf6352009-07-04 19:29:51 -0700146 u32 spcr;
Troy Kiskyc392bec2009-07-04 19:29:52 -0700147 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
Troy Kisky35cf6352009-07-04 19:29:51 -0700148 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700149 if (spcr & mask) {
150 /* start off disabled */
151 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
152 spcr & ~mask);
153 toggle_clock(dev, playback);
154 }
Troy Kisky1bef4492009-07-04 19:29:55 -0700155 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
156 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
157 /* Start the sample generator */
158 spcr |= DAVINCI_MCBSP_SPCR_GRST;
159 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
160 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100161
Troy Kisky1bef4492009-07-04 19:29:55 -0700162 if (playback) {
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530163 /* Stop the DMA to avoid data loss */
164 /* while the transmitter is out of reset to handle XSYNCERR */
165 if (platform->pcm_ops->trigger) {
Troy Kiskyeba575c2009-07-04 19:29:54 -0700166 int ret = platform->pcm_ops->trigger(substream,
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530167 SNDRV_PCM_TRIGGER_STOP);
168 if (ret < 0)
169 printk(KERN_DEBUG "Playback DMA stop failed\n");
170 }
171
172 /* Enable the transmitter */
Troy Kisky35cf6352009-07-04 19:29:51 -0700173 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
174 spcr |= DAVINCI_MCBSP_SPCR_XRST;
175 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530176
177 /* wait for any unexpected frame sync error to occur */
178 udelay(100);
179
180 /* Disable the transmitter to clear any outstanding XSYNCERR */
Troy Kisky35cf6352009-07-04 19:29:51 -0700181 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
182 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
183 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700184 toggle_clock(dev, playback);
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530185
186 /* Restart the DMA */
187 if (platform->pcm_ops->trigger) {
Troy Kiskyeba575c2009-07-04 19:29:54 -0700188 int ret = platform->pcm_ops->trigger(substream,
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530189 SNDRV_PCM_TRIGGER_START);
190 if (ret < 0)
191 printk(KERN_DEBUG "Playback DMA start failed\n");
192 }
Naresh Medisettyfb0ef642008-11-12 10:26:31 +0530193 }
194
Troy Kisky1bef4492009-07-04 19:29:55 -0700195 /* Enable transmitter or receiver */
Troy Kisky35cf6352009-07-04 19:29:51 -0700196 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
Troy Kisky1bef4492009-07-04 19:29:55 -0700197 spcr |= mask;
198
199 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
200 /* Start frame sync */
201 spcr |= DAVINCI_MCBSP_SPCR_FRST;
202 }
Troy Kisky35cf6352009-07-04 19:29:51 -0700203 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100204}
205
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700206static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100207{
Troy Kisky35cf6352009-07-04 19:29:51 -0700208 u32 spcr;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100209
210 /* Reset transmitter/receiver and sample rate/frame sync generators */
Troy Kisky35cf6352009-07-04 19:29:51 -0700211 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
212 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700213 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
Troy Kisky35cf6352009-07-04 19:29:51 -0700214 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700215 toggle_clock(dev, playback);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100216}
217
Mark Browndee89c42008-11-18 22:11:38 +0000218static int davinci_i2s_startup(struct snd_pcm_substream *substream,
Troy Kisky9333b592009-07-04 19:29:56 -0700219 struct snd_soc_dai *cpu_dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100220{
Troy Kisky9333b592009-07-04 19:29:56 -0700221 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100222 cpu_dai->dma_data = dev->dma_params[substream->stream];
Vladimir Barinov310355c2008-02-18 11:40:22 +0100223 return 0;
224}
225
Troy Kisky21903c12008-12-18 12:36:43 -0700226#define DEFAULT_BITPERSAMPLE 16
227
Liam Girdwood9cb132d2008-07-07 16:07:42 +0100228static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
Vladimir Barinov310355c2008-02-18 11:40:22 +0100229 unsigned int fmt)
230{
231 struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
Troy Kisky21903c12008-12-18 12:36:43 -0700232 unsigned int pcr;
233 unsigned int srgr;
Troy Kisky21903c12008-12-18 12:36:43 -0700234 srgr = DAVINCI_MCBSP_SRGR_FSGM |
235 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
236 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100237
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700238 /* set master/slave audio interface */
Vladimir Barinov310355c2008-02-18 11:40:22 +0100239 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
240 case SND_SOC_DAIFMT_CBS_CFS:
Troy Kisky21903c12008-12-18 12:36:43 -0700241 /* cpu is master */
242 pcr = DAVINCI_MCBSP_PCR_FSXM |
243 DAVINCI_MCBSP_PCR_FSRM |
244 DAVINCI_MCBSP_PCR_CLKXM |
245 DAVINCI_MCBSP_PCR_CLKRM;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100246 break;
Hugo Villeneuveb402dff2008-11-08 13:26:09 -0500247 case SND_SOC_DAIFMT_CBM_CFS:
248 /* McBSP CLKR pin is the input for the Sample Rate Generator.
249 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
Troy Kisky21903c12008-12-18 12:36:43 -0700250 pcr = DAVINCI_MCBSP_PCR_SCLKME |
251 DAVINCI_MCBSP_PCR_FSXM |
252 DAVINCI_MCBSP_PCR_FSRM;
Hugo Villeneuveb402dff2008-11-08 13:26:09 -0500253 break;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100254 case SND_SOC_DAIFMT_CBM_CFM:
Troy Kisky21903c12008-12-18 12:36:43 -0700255 /* codec is master */
256 pcr = 0;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100257 break;
258 default:
Troy Kisky21903c12008-12-18 12:36:43 -0700259 printk(KERN_ERR "%s:bad master\n", __func__);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100260 return -EINVAL;
261 }
262
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700263 /* interface format */
Troy Kisky69ab8202008-12-18 12:36:44 -0700264 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
Troy Kisky69ab8202008-12-18 12:36:44 -0700265 case SND_SOC_DAIFMT_I2S:
Troy Kisky07d8d9d2008-12-19 13:05:24 -0700266 /* Davinci doesn't support TRUE I2S, but some codecs will have
267 * the left and right channels contiguous. This allows
268 * dsp_a mode to be used with an inverted normal frame clk.
269 * If your codec is master and does not have contiguous
270 * channels, then you will have sound on only one channel.
271 * Try using a different mode, or codec as slave.
272 *
273 * The TLV320AIC33 is an example of a codec where this works.
274 * It has a variable bit clock frequency allowing it to have
275 * valid data on every bit clock.
276 *
277 * The TLV320AIC23 is an example of a codec where this does not
278 * work. It has a fixed bit clock frequency with progressively
279 * more empty bit clock slots between channels as the sample
280 * rate is lowered.
281 */
282 fmt ^= SND_SOC_DAIFMT_NB_IF;
283 case SND_SOC_DAIFMT_DSP_A:
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700284 dev->mode = MOD_DSP_A;
285 break;
286 case SND_SOC_DAIFMT_DSP_B:
287 dev->mode = MOD_DSP_B;
Troy Kisky69ab8202008-12-18 12:36:44 -0700288 break;
289 default:
290 printk(KERN_ERR "%s:bad format\n", __func__);
291 return -EINVAL;
292 }
293
Vladimir Barinov310355c2008-02-18 11:40:22 +0100294 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
Troy Kisky9e031622008-12-19 13:05:23 -0700295 case SND_SOC_DAIFMT_NB_NF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700296 /* CLKRP Receive clock polarity,
297 * 1 - sampled on rising edge of CLKR
298 * valid on rising edge
299 * CLKXP Transmit clock polarity,
300 * 1 - clocked on falling edge of CLKX
301 * valid on rising edge
302 * FSRP Receive frame sync pol, 0 - active high
303 * FSXP Transmit frame sync pol, 0 - active high
304 */
Troy Kisky21903c12008-12-18 12:36:43 -0700305 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100306 break;
Troy Kisky9e031622008-12-19 13:05:23 -0700307 case SND_SOC_DAIFMT_IB_IF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700308 /* CLKRP Receive clock polarity,
309 * 0 - sampled on falling edge of CLKR
310 * valid on falling edge
311 * CLKXP Transmit clock polarity,
312 * 0 - clocked on rising edge of CLKX
313 * valid on falling edge
314 * FSRP Receive frame sync pol, 1 - active low
315 * FSXP Transmit frame sync pol, 1 - active low
316 */
Troy Kisky21903c12008-12-18 12:36:43 -0700317 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100318 break;
Troy Kisky9e031622008-12-19 13:05:23 -0700319 case SND_SOC_DAIFMT_NB_IF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700320 /* CLKRP Receive clock polarity,
321 * 1 - sampled on rising edge of CLKR
322 * valid on rising edge
323 * CLKXP Transmit clock polarity,
324 * 1 - clocked on falling edge of CLKX
325 * valid on rising edge
326 * FSRP Receive frame sync pol, 1 - active low
327 * FSXP Transmit frame sync pol, 1 - active low
328 */
Troy Kisky21903c12008-12-18 12:36:43 -0700329 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
330 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100331 break;
Troy Kisky9e031622008-12-19 13:05:23 -0700332 case SND_SOC_DAIFMT_IB_NF:
Troy Kisky664b4af2008-12-18 12:36:41 -0700333 /* CLKRP Receive clock polarity,
334 * 0 - sampled on falling edge of CLKR
335 * valid on falling edge
336 * CLKXP Transmit clock polarity,
337 * 0 - clocked on rising edge of CLKX
338 * valid on falling edge
339 * FSRP Receive frame sync pol, 0 - active high
340 * FSXP Transmit frame sync pol, 0 - active high
341 */
Vladimir Barinov310355c2008-02-18 11:40:22 +0100342 break;
343 default:
344 return -EINVAL;
345 }
Troy Kisky21903c12008-12-18 12:36:43 -0700346 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
Troy Kiskyc392bec2009-07-04 19:29:52 -0700347 dev->pcr = pcr;
Troy Kisky21903c12008-12-18 12:36:43 -0700348 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100349 return 0;
350}
351
352static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
Mark Browndee89c42008-11-18 22:11:38 +0000353 struct snd_pcm_hw_params *params,
354 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100355{
356 struct snd_soc_pcm_runtime *rtd = substream->private_data;
357 struct davinci_pcm_dma_params *dma_params = rtd->dai->cpu_dai->dma_data;
358 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
359 struct snd_interval *i = NULL;
360 int mcbsp_word_length;
Troy Kisky35cf6352009-07-04 19:29:51 -0700361 unsigned int rcr, xcr, srgr;
362 u32 spcr;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100363
364 /* general line settings */
Troy Kisky35cf6352009-07-04 19:29:51 -0700365 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530366 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
Troy Kisky35cf6352009-07-04 19:29:51 -0700367 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
368 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530369 } else {
Troy Kisky35cf6352009-07-04 19:29:51 -0700370 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
371 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
Naresh Medisettycb6e2062008-11-18 11:01:03 +0530372 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100373
374 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
Troy Kisky35cf6352009-07-04 19:29:51 -0700375 srgr = DAVINCI_MCBSP_SRGR_FSGM;
376 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100377
378 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
Troy Kisky35cf6352009-07-04 19:29:51 -0700379 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
380 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100381
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700382 rcr = DAVINCI_MCBSP_RCR_RFIG;
383 xcr = DAVINCI_MCBSP_XCR_XFIG;
384 if (dev->mode == MOD_DSP_B) {
385 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
386 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
387 } else {
388 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
389 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
390 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100391 /* Determine xfer data type */
392 switch (params_format(params)) {
393 case SNDRV_PCM_FORMAT_S8:
394 dma_params->data_type = 1;
395 mcbsp_word_length = DAVINCI_MCBSP_WORD_8;
396 break;
397 case SNDRV_PCM_FORMAT_S16_LE:
398 dma_params->data_type = 2;
399 mcbsp_word_length = DAVINCI_MCBSP_WORD_16;
400 break;
401 case SNDRV_PCM_FORMAT_S32_LE:
402 dma_params->data_type = 4;
403 mcbsp_word_length = DAVINCI_MCBSP_WORD_32;
404 break;
405 default:
Jean Delvare9b6e12e2008-08-26 15:47:55 +0200406 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
Vladimir Barinov310355c2008-02-18 11:40:22 +0100407 return -EINVAL;
408 }
409
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700410 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(1);
411 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(1);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100412
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700413 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
414 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
415 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
416 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
417
418 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
Troy Kisky35cf6352009-07-04 19:29:51 -0700419 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
Troy Kiskyf5cfa952009-07-04 19:29:57 -0700420 else
421 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100422 return 0;
423}
424
Troy Kiskyaf0adf32009-07-04 19:29:59 -0700425static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
426 struct snd_soc_dai *dai)
427{
428 struct snd_soc_pcm_runtime *rtd = substream->private_data;
429 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
430 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
431 davinci_mcbsp_stop(dev, playback);
432 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) {
433 /* codec is master */
434 davinci_mcbsp_start(dev, substream);
435 }
436 return 0;
437}
438
Mark Browndee89c42008-11-18 22:11:38 +0000439static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
440 struct snd_soc_dai *dai)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100441{
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700442 struct snd_soc_pcm_runtime *rtd = substream->private_data;
443 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100444 int ret = 0;
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700445 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
Troy Kiskyaf0adf32009-07-04 19:29:59 -0700446 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0)
447 return 0; /* return if codec is master */
Vladimir Barinov310355c2008-02-18 11:40:22 +0100448
449 switch (cmd) {
450 case SNDRV_PCM_TRIGGER_START:
451 case SNDRV_PCM_TRIGGER_RESUME:
452 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700453 davinci_mcbsp_start(dev, substream);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100454 break;
455 case SNDRV_PCM_TRIGGER_STOP:
456 case SNDRV_PCM_TRIGGER_SUSPEND:
457 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Troy Kiskyf9af37c2009-07-04 19:29:53 -0700458 davinci_mcbsp_stop(dev, playback);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100459 break;
460 default:
461 ret = -EINVAL;
462 }
Vladimir Barinov310355c2008-02-18 11:40:22 +0100463 return ret;
464}
465
Troy Kiskyaf0adf32009-07-04 19:29:59 -0700466static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
467 struct snd_soc_dai *dai)
468{
469 struct snd_soc_pcm_runtime *rtd = substream->private_data;
470 struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
471 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
472 davinci_mcbsp_stop(dev, playback);
473}
474
Chaithrika U S5204d492009-06-05 06:28:23 -0400475#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
476
477static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
478 .startup = davinci_i2s_startup,
Mark Brown3f405b42009-07-07 19:18:46 +0100479 .shutdown = davinci_i2s_shutdown,
480 .prepare = davinci_i2s_prepare,
Chaithrika U S5204d492009-06-05 06:28:23 -0400481 .trigger = davinci_i2s_trigger,
482 .hw_params = davinci_i2s_hw_params,
483 .set_fmt = davinci_i2s_set_dai_fmt,
484
485};
486
487struct snd_soc_dai davinci_i2s_dai = {
488 .name = "davinci-i2s",
489 .id = 0,
490 .playback = {
491 .channels_min = 2,
492 .channels_max = 2,
493 .rates = DAVINCI_I2S_RATES,
494 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
495 .capture = {
496 .channels_min = 2,
497 .channels_max = 2,
498 .rates = DAVINCI_I2S_RATES,
499 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
500 .ops = &davinci_i2s_dai_ops,
501
502};
503EXPORT_SYMBOL_GPL(davinci_i2s_dai);
504
505static int davinci_i2s_probe(struct platform_device *pdev)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100506{
Chaithrika U S5204d492009-06-05 06:28:23 -0400507 struct snd_platform_data *pdata = pdev->dev.platform_data;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100508 struct davinci_mcbsp_dev *dev;
Chaithrika U S5204d492009-06-05 06:28:23 -0400509 struct resource *mem, *ioarea, *res;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100510 int ret;
511
512 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
513 if (!mem) {
514 dev_err(&pdev->dev, "no mem resource?\n");
515 return -ENODEV;
516 }
517
518 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
519 pdev->name);
520 if (!ioarea) {
521 dev_err(&pdev->dev, "McBSP region already claimed\n");
522 return -EBUSY;
523 }
524
525 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL);
526 if (!dev) {
527 ret = -ENOMEM;
528 goto err_release_region;
529 }
530
Kevin Hilman3e46a442009-07-15 10:42:09 -0700531 dev->clk = clk_get(&pdev->dev, NULL);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100532 if (IS_ERR(dev->clk)) {
533 ret = -ENODEV;
534 goto err_free_mem;
535 }
536 clk_enable(dev->clk);
537
538 dev->base = (void __iomem *)IO_ADDRESS(mem->start);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100539
540 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK] = &davinci_i2s_pcm_out;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100541 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->dma_addr =
542 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG);
543
544 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE] = &davinci_i2s_pcm_in;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100545 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->dma_addr =
546 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG);
547
Chaithrika U S5204d492009-06-05 06:28:23 -0400548 /* first TX, then RX */
549 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
550 if (!res) {
551 dev_err(&pdev->dev, "no DMA resource\n");
Chaithrika U Sefd13be2009-06-08 06:49:41 -0400552 ret = -ENXIO;
Chaithrika U S5204d492009-06-05 06:28:23 -0400553 goto err_free_mem;
554 }
555 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK]->channel = res->start;
556
557 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
558 if (!res) {
559 dev_err(&pdev->dev, "no DMA resource\n");
Chaithrika U Sefd13be2009-06-08 06:49:41 -0400560 ret = -ENXIO;
Chaithrika U S5204d492009-06-05 06:28:23 -0400561 goto err_free_mem;
562 }
563 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE]->channel = res->start;
564
565 davinci_i2s_dai.private_data = dev;
566 ret = snd_soc_register_dai(&davinci_i2s_dai);
567 if (ret != 0)
568 goto err_free_mem;
569
Vladimir Barinov310355c2008-02-18 11:40:22 +0100570 return 0;
571
572err_free_mem:
573 kfree(dev);
574err_release_region:
575 release_mem_region(mem->start, (mem->end - mem->start) + 1);
576
577 return ret;
578}
579
Chaithrika U S5204d492009-06-05 06:28:23 -0400580static int davinci_i2s_remove(struct platform_device *pdev)
Vladimir Barinov310355c2008-02-18 11:40:22 +0100581{
Chaithrika U S5204d492009-06-05 06:28:23 -0400582 struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100583 struct resource *mem;
584
Chaithrika U S5204d492009-06-05 06:28:23 -0400585 snd_soc_unregister_dai(&davinci_i2s_dai);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100586 clk_disable(dev->clk);
587 clk_put(dev->clk);
588 dev->clk = NULL;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100589 kfree(dev);
Vladimir Barinov310355c2008-02-18 11:40:22 +0100590 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
591 release_mem_region(mem->start, (mem->end - mem->start) + 1);
Chaithrika U S5204d492009-06-05 06:28:23 -0400592
593 return 0;
Vladimir Barinov310355c2008-02-18 11:40:22 +0100594}
595
Chaithrika U S5204d492009-06-05 06:28:23 -0400596static struct platform_driver davinci_mcbsp_driver = {
597 .probe = davinci_i2s_probe,
598 .remove = davinci_i2s_remove,
599 .driver = {
600 .name = "davinci-asp",
601 .owner = THIS_MODULE,
602 },
Eric Miao6335d052009-03-03 09:41:00 +0800603};
604
Takashi Iwaic9b3a402008-12-10 07:47:22 +0100605static int __init davinci_i2s_init(void)
Mark Brown3f4b7832008-12-03 19:26:35 +0000606{
Chaithrika U S5204d492009-06-05 06:28:23 -0400607 return platform_driver_register(&davinci_mcbsp_driver);
Mark Brown3f4b7832008-12-03 19:26:35 +0000608}
609module_init(davinci_i2s_init);
610
611static void __exit davinci_i2s_exit(void)
612{
Chaithrika U S5204d492009-06-05 06:28:23 -0400613 platform_driver_unregister(&davinci_mcbsp_driver);
Mark Brown3f4b7832008-12-03 19:26:35 +0000614}
615module_exit(davinci_i2s_exit);
616
Vladimir Barinov310355c2008-02-18 11:40:22 +0100617MODULE_AUTHOR("Vladimir Barinov");
618MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
619MODULE_LICENSE("GPL");