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Komal Shah010d442c42006-08-13 23:44:09 +02001/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
Komal Shah010d442c42006-08-13 23:44:09 +02005 * Copyright (C) 2005 Nokia Corporation
Tony Lindgrenc1a473b2008-11-21 13:39:47 -08006 * Copyright (C) 2004 - 2007 Texas Instruments.
Komal Shah010d442c42006-08-13 23:44:09 +02007 *
Tony Lindgrenc1a473b2008-11-21 13:39:47 -08008 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
Komal Shah010d442c42006-08-13 23:44:09 +020015 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
Tony Lindgrenc1a473b2008-11-21 13:39:47 -080039#include <linux/io.h>
Benoit Cousson61451972011-12-22 15:56:36 +010040#include <linux/of.h>
41#include <linux/of_i2c.h>
42#include <linux/of_device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090043#include <linux/slab.h>
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -070044#include <linux/i2c-omap.h>
Rajendra Nayak27b1fec2010-09-28 21:02:58 +053045#include <linux/pm_runtime.h>
Komal Shah010d442c42006-08-13 23:44:09 +020046
Paul Walmsley9c76b872008-11-21 13:39:55 -080047/* I2C controller revisions */
Andy Green4e80f722011-05-30 07:43:07 -070048#define OMAP_I2C_OMAP1_REV_2 0x20
Paul Walmsley9c76b872008-11-21 13:39:55 -080049
50/* I2C controller revisions present on specific hardware */
51#define OMAP_I2C_REV_ON_2430 0x36
Jon Hunterf518b482012-06-28 20:41:31 +053052#define OMAP_I2C_REV_ON_3430_3530 0x3C
53#define OMAP_I2C_REV_ON_3630_4430 0x40
Paul Walmsley9c76b872008-11-21 13:39:55 -080054
Komal Shah010d442c42006-08-13 23:44:09 +020055/* timeout waiting for the controller to respond */
56#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
57
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -080058/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -070059enum {
60 OMAP_I2C_REV_REG = 0,
61 OMAP_I2C_IE_REG,
62 OMAP_I2C_STAT_REG,
63 OMAP_I2C_IV_REG,
64 OMAP_I2C_WE_REG,
65 OMAP_I2C_SYSS_REG,
66 OMAP_I2C_BUF_REG,
67 OMAP_I2C_CNT_REG,
68 OMAP_I2C_DATA_REG,
69 OMAP_I2C_SYSC_REG,
70 OMAP_I2C_CON_REG,
71 OMAP_I2C_OA_REG,
72 OMAP_I2C_SA_REG,
73 OMAP_I2C_PSC_REG,
74 OMAP_I2C_SCLL_REG,
75 OMAP_I2C_SCLH_REG,
76 OMAP_I2C_SYSTEST_REG,
77 OMAP_I2C_BUFSTAT_REG,
Andy Greenb8853082011-05-30 07:43:04 -070078 /* only on OMAP4430 */
79 OMAP_I2C_IP_V2_REVNB_LO,
80 OMAP_I2C_IP_V2_REVNB_HI,
81 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
82 OMAP_I2C_IP_V2_IRQENABLE_SET,
83 OMAP_I2C_IP_V2_IRQENABLE_CLR,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -070084};
Komal Shah010d442c42006-08-13 23:44:09 +020085
86/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -080087#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
88#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
Komal Shah010d442c42006-08-13 23:44:09 +020089#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
90#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
91#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
92#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
93#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
94
95/* I2C Status Register (OMAP_I2C_STAT): */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -080096#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
97#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
Komal Shah010d442c42006-08-13 23:44:09 +020098#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
99#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
100#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
101#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
102#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
103#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
104#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
105#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
106#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
107#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
108
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -0800109/* I2C WE wakeup enable register */
110#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
111#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
112#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
113#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
114#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
115#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
116#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
117#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
118#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
119#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
120
121#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
122 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
123 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
124 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
125 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
126
Komal Shah010d442c42006-08-13 23:44:09 +0200127/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
128#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800129#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
Komal Shah010d442c42006-08-13 23:44:09 +0200130#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800131#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
Komal Shah010d442c42006-08-13 23:44:09 +0200132
133/* I2C Configuration Register (OMAP_I2C_CON): */
134#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
135#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800136#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
Komal Shah010d442c42006-08-13 23:44:09 +0200137#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
138#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
139#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
140#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
141#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
142#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
143#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
144
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800145/* I2C SCL time value when Master */
146#define OMAP_I2C_SCLL_HSSCLL 8
147#define OMAP_I2C_SCLH_HSSCLH 8
148
Komal Shah010d442c42006-08-13 23:44:09 +0200149/* I2C System Test Register (OMAP_I2C_SYSTEST): */
150#ifdef DEBUG
151#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
152#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
153#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
154#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
155#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
156#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
157#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
158#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
159#endif
160
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800161/* OCP_SYSSTATUS bit definitions */
162#define SYSS_RESETDONE_MASK (1 << 0)
Komal Shah010d442c42006-08-13 23:44:09 +0200163
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800164/* OCP_SYSCONFIG bit definitions */
165#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
166#define SYSC_SIDLEMODE_MASK (0x3 << 3)
167#define SYSC_ENAWAKEUP_MASK (1 << 2)
168#define SYSC_SOFTRESET_MASK (1 << 1)
169#define SYSC_AUTOIDLE_MASK (1 << 0)
170
171#define SYSC_IDLEMODE_SMART 0x2
172#define SYSC_CLOCKACTIVITY_FCLK 0x2
173
manjugk manjugkf3083d92010-05-11 11:35:20 -0700174/* Errata definitions */
175#define I2C_OMAP_ERRATA_I207 (1 << 0)
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530176#define I2C_OMAP_ERRATA_I462 (1 << 1)
Komal Shah010d442c42006-08-13 23:44:09 +0200177
Komal Shah010d442c42006-08-13 23:44:09 +0200178struct omap_i2c_dev {
179 struct device *dev;
180 void __iomem *base; /* virtual */
181 int irq;
Cory Maccarroned84d3ea2009-12-12 17:54:02 -0800182 int reg_shift; /* bit shift for I2C register addresses */
Komal Shah010d442c42006-08-13 23:44:09 +0200183 struct completion cmd_complete;
184 struct resource *ioarea;
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -0700185 u32 latency; /* maximum mpu wkup latency */
186 void (*set_mpu_wkup_lat)(struct device *dev,
187 long latency);
Benoit Cousson61451972011-12-22 15:56:36 +0100188 u32 speed; /* Speed of bus in kHz */
189 u32 dtrev; /* extra revision from DT */
190 u32 flags;
Komal Shah010d442c42006-08-13 23:44:09 +0200191 u16 cmd_err;
192 u8 *buf;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700193 u8 *regs;
Komal Shah010d442c42006-08-13 23:44:09 +0200194 size_t buf_len;
195 struct i2c_adapter adapter;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800196 u8 fifo_size; /* use as flag and value
197 * fifo_size==0 implies no fifo
198 * if set, should be trsh+1
199 */
Paul Walmsley9c76b872008-11-21 13:39:55 -0800200 u8 rev;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800201 unsigned b_hw:1; /* bad h/w fixes */
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100202 u16 iestate; /* Saved interrupt register */
Rajendra Nayakef871432009-11-23 08:59:18 -0800203 u16 pscstate;
204 u16 scllstate;
205 u16 sclhstate;
206 u16 bufstate;
207 u16 syscstate;
208 u16 westate;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700209 u16 errata;
Komal Shah010d442c42006-08-13 23:44:09 +0200210};
211
Andy Greena1295572011-05-30 07:43:06 -0700212static const u8 reg_map_ip_v1[] = {
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700213 [OMAP_I2C_REV_REG] = 0x00,
214 [OMAP_I2C_IE_REG] = 0x01,
215 [OMAP_I2C_STAT_REG] = 0x02,
216 [OMAP_I2C_IV_REG] = 0x03,
217 [OMAP_I2C_WE_REG] = 0x03,
218 [OMAP_I2C_SYSS_REG] = 0x04,
219 [OMAP_I2C_BUF_REG] = 0x05,
220 [OMAP_I2C_CNT_REG] = 0x06,
221 [OMAP_I2C_DATA_REG] = 0x07,
222 [OMAP_I2C_SYSC_REG] = 0x08,
223 [OMAP_I2C_CON_REG] = 0x09,
224 [OMAP_I2C_OA_REG] = 0x0a,
225 [OMAP_I2C_SA_REG] = 0x0b,
226 [OMAP_I2C_PSC_REG] = 0x0c,
227 [OMAP_I2C_SCLL_REG] = 0x0d,
228 [OMAP_I2C_SCLH_REG] = 0x0e,
229 [OMAP_I2C_SYSTEST_REG] = 0x0f,
230 [OMAP_I2C_BUFSTAT_REG] = 0x10,
231};
232
Andy Greena1295572011-05-30 07:43:06 -0700233static const u8 reg_map_ip_v2[] = {
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700234 [OMAP_I2C_REV_REG] = 0x04,
235 [OMAP_I2C_IE_REG] = 0x2c,
236 [OMAP_I2C_STAT_REG] = 0x28,
237 [OMAP_I2C_IV_REG] = 0x34,
238 [OMAP_I2C_WE_REG] = 0x34,
239 [OMAP_I2C_SYSS_REG] = 0x90,
240 [OMAP_I2C_BUF_REG] = 0x94,
241 [OMAP_I2C_CNT_REG] = 0x98,
242 [OMAP_I2C_DATA_REG] = 0x9c,
Alexander Aring2727b172011-12-08 15:43:53 +0100243 [OMAP_I2C_SYSC_REG] = 0x10,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700244 [OMAP_I2C_CON_REG] = 0xa4,
245 [OMAP_I2C_OA_REG] = 0xa8,
246 [OMAP_I2C_SA_REG] = 0xac,
247 [OMAP_I2C_PSC_REG] = 0xb0,
248 [OMAP_I2C_SCLL_REG] = 0xb4,
249 [OMAP_I2C_SCLH_REG] = 0xb8,
250 [OMAP_I2C_SYSTEST_REG] = 0xbC,
251 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
Andy Greenb8853082011-05-30 07:43:04 -0700252 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
253 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
254 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
255 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
256 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700257};
258
Komal Shah010d442c42006-08-13 23:44:09 +0200259static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
260 int reg, u16 val)
261{
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700262 __raw_writew(val, i2c_dev->base +
263 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
Komal Shah010d442c42006-08-13 23:44:09 +0200264}
265
266static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
267{
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -0700268 return __raw_readw(i2c_dev->base +
269 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
Komal Shah010d442c42006-08-13 23:44:09 +0200270}
271
Komal Shah010d442c42006-08-13 23:44:09 +0200272static int omap_i2c_init(struct omap_i2c_dev *dev)
273{
Rajendra Nayakef871432009-11-23 08:59:18 -0800274 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800275 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
Komal Shah010d442c42006-08-13 23:44:09 +0200276 unsigned long fclk_rate = 12000000;
277 unsigned long timeout;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800278 unsigned long internal_clk = 0;
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530279 struct clk *fclk;
Komal Shah010d442c42006-08-13 23:44:09 +0200280
Andy Green4e80f722011-05-30 07:43:07 -0700281 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
Manjunatha GK57eb81b2009-12-11 11:09:08 +0530282 /* Disable I2C controller before soft reset */
283 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
284 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
285 ~(OMAP_I2C_CON_EN));
286
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800287 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
Komal Shah010d442c42006-08-13 23:44:09 +0200288 /* For some reason we need to set the EN bit before the
289 * reset done bit gets set. */
290 timeout = jiffies + OMAP_I2C_TIMEOUT;
291 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
292 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800293 SYSS_RESETDONE_MASK)) {
Komal Shah010d442c42006-08-13 23:44:09 +0200294 if (time_after(jiffies, timeout)) {
Joe Perchesfce3ff02007-12-12 13:45:24 +0100295 dev_warn(dev->dev, "timeout waiting "
Komal Shah010d442c42006-08-13 23:44:09 +0200296 "for controller reset\n");
297 return -ETIMEDOUT;
298 }
299 msleep(1);
300 }
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800301
302 /* SYSC register is cleared by the reset; rewrite it */
303 if (dev->rev == OMAP_I2C_REV_ON_2430) {
304
305 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
306 SYSC_AUTOIDLE_MASK);
307
Jon Hunterf518b482012-06-28 20:41:31 +0530308 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
Rajendra Nayakef871432009-11-23 08:59:18 -0800309 dev->syscstate = SYSC_AUTOIDLE_MASK;
310 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
311 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800312 __ffs(SYSC_SIDLEMODE_MASK));
Rajendra Nayakef871432009-11-23 08:59:18 -0800313 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800314 __ffs(SYSC_CLOCKACTIVITY_MASK));
315
Rajendra Nayakef871432009-11-23 08:59:18 -0800316 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
317 dev->syscstate);
Kalle Jokiniemi5043e9e72008-11-21 13:39:55 -0800318 /*
319 * Enabling all wakup sources to stop I2C freezing on
320 * WFI instruction.
321 * REVISIT: Some wkup sources might not be needed.
322 */
Rajendra Nayakef871432009-11-23 08:59:18 -0800323 dev->westate = OMAP_I2C_WE_ALL;
Shubhrajyoti Dcb28e582011-08-03 13:58:08 +0530324 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
325 dev->westate);
Paul Walmsleyfdd07fe2008-11-21 13:39:55 -0800326 }
Komal Shah010d442c42006-08-13 23:44:09 +0200327 }
328 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
329
Benoit Cousson61451972011-12-22 15:56:36 +0100330 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
Russell King0e9ae102009-01-22 19:31:46 +0000331 /*
332 * The I2C functional clock is the armxor_ck, so there's
333 * no need to get "armxor_ck" separately. Now, if OMAP2420
334 * always returns 12MHz for the functional clock, we can
335 * do this bit unconditionally.
336 */
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530337 fclk = clk_get(dev->dev, "fck");
338 fclk_rate = clk_get_rate(fclk);
339 clk_put(fclk);
Komal Shah010d442c42006-08-13 23:44:09 +0200340
Komal Shah010d442c42006-08-13 23:44:09 +0200341 /* TRM for 5912 says the I2C clock must be prescaled to be
342 * between 7 - 12 MHz. The XOR input clock is typically
343 * 12, 13 or 19.2 MHz. So we should have code that produces:
344 *
345 * XOR MHz Divider Prescaler
346 * 12 1 0
347 * 13 2 1
348 * 19.2 2 1
349 */
Jean Delvared7aef132006-12-10 21:21:34 +0100350 if (fclk_rate > 12000000)
351 psc = fclk_rate / 12000000;
Komal Shah010d442c42006-08-13 23:44:09 +0200352 }
353
Benoit Cousson61451972011-12-22 15:56:36 +0100354 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800355
Aaro Koskinen84bf2c82009-05-27 17:54:46 +0300356 /*
357 * HSI2C controller internal clk rate should be 19.2 Mhz for
358 * HS and for all modes on 2430. On 34xx we can use lower rate
359 * to get longer filter period for better noise suppression.
360 * The filter is iclk (fclk for HS) period.
361 */
Andy Green3be00532011-05-30 07:43:09 -0700362 if (dev->speed > 400 ||
Benoit Cousson61451972011-12-22 15:56:36 +0100363 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
Aaro Koskinen84bf2c82009-05-27 17:54:46 +0300364 internal_clk = 19200;
365 else if (dev->speed > 100)
366 internal_clk = 9600;
367 else
368 internal_clk = 4000;
Rajendra Nayak27b1fec2010-09-28 21:02:58 +0530369 fclk = clk_get(dev->dev, "fck");
370 fclk_rate = clk_get_rate(fclk) / 1000;
371 clk_put(fclk);
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800372
373 /* Compute prescaler divisor */
374 psc = fclk_rate / internal_clk;
375 psc = psc - 1;
376
377 /* If configured for High Speed */
378 if (dev->speed > 400) {
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300379 unsigned long scl;
380
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800381 /* For first phase of HS mode */
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300382 scl = internal_clk / 400;
383 fsscll = scl - (scl / 3) - 7;
384 fssclh = (scl / 3) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800385
386 /* For second phase of HS mode */
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300387 scl = fclk_rate / dev->speed;
388 hsscll = scl - (scl / 3) - 7;
389 hssclh = (scl / 3) - 5;
390 } else if (dev->speed > 100) {
391 unsigned long scl;
392
393 /* Fast mode */
394 scl = internal_clk / dev->speed;
395 fsscll = scl - (scl / 3) - 7;
396 fssclh = (scl / 3) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800397 } else {
Aaro Koskinenbaf46b42009-05-27 17:54:45 +0300398 /* Standard mode */
399 fsscll = internal_clk / (dev->speed * 2) - 7;
400 fssclh = internal_clk / (dev->speed * 2) - 5;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800401 }
402 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
403 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
404 } else {
405 /* Program desired operating rate */
406 fclk_rate /= (psc + 1) * 1000;
407 if (psc > 2)
408 psc = 2;
409 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
410 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
411 }
412
Komal Shah010d442c42006-08-13 23:44:09 +0200413 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
414 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
415
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800416 /* SCL low and high time values */
417 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
418 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
Komal Shah010d442c42006-08-13 23:44:09 +0200419
Rajendra Nayakef871432009-11-23 08:59:18 -0800420 if (dev->fifo_size) {
421 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
422 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
423 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
424 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
425 }
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800426
Komal Shah010d442c42006-08-13 23:44:09 +0200427 /* Take the I2C module out of reset: */
428 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
429
430 /* Enable interrupts */
Rajendra Nayakef871432009-11-23 08:59:18 -0800431 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800432 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
433 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
Rajendra Nayakef871432009-11-23 08:59:18 -0800434 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
435 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
Benoit Cousson61451972011-12-22 15:56:36 +0100436 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
Rajendra Nayakef871432009-11-23 08:59:18 -0800437 dev->pscstate = psc;
438 dev->scllstate = scll;
439 dev->sclhstate = sclh;
440 dev->bufstate = buf;
441 }
Komal Shah010d442c42006-08-13 23:44:09 +0200442 return 0;
443}
444
445/*
446 * Waiting on Bus Busy
447 */
448static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
449{
450 unsigned long timeout;
451
452 timeout = jiffies + OMAP_I2C_TIMEOUT;
453 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
454 if (time_after(jiffies, timeout)) {
455 dev_warn(dev->dev, "timeout waiting for bus ready\n");
456 return -ETIMEDOUT;
457 }
458 msleep(1);
459 }
460
461 return 0;
462}
463
464/*
465 * Low level master read/write transaction.
466 */
467static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
468 struct i2c_msg *msg, int stop)
469{
470 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530471 unsigned long timeout;
Komal Shah010d442c42006-08-13 23:44:09 +0200472 u16 w;
473
474 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
475 msg->addr, msg->len, msg->flags, stop);
476
477 if (msg->len == 0)
478 return -EINVAL;
479
480 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
481
482 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
483 dev->buf = msg->buf;
484 dev->buf_len = msg->len;
485
486 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
487
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800488 /* Clear the FIFO Buffers */
489 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
490 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
491 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
492
Shubhrajyoti D0e33bbb2012-06-28 20:41:29 +0530493 INIT_COMPLETION(dev->cmd_complete);
Komal Shah010d442c42006-08-13 23:44:09 +0200494 dev->cmd_err = 0;
495
496 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800497
498 /* High speed configuration */
499 if (dev->speed > 400)
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800500 w |= OMAP_I2C_CON_OPMODE_HS;
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -0800501
Laurent Pinchartfb604a32012-07-24 14:13:59 +0200502 if (msg->flags & I2C_M_STOP)
503 stop = 1;
Komal Shah010d442c42006-08-13 23:44:09 +0200504 if (msg->flags & I2C_M_TEN)
505 w |= OMAP_I2C_CON_XA;
506 if (!(msg->flags & I2C_M_RD))
507 w |= OMAP_I2C_CON_TRX;
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800508
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800509 if (!dev->b_hw && stop)
Komal Shah010d442c42006-08-13 23:44:09 +0200510 w |= OMAP_I2C_CON_STP;
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800511
Komal Shah010d442c42006-08-13 23:44:09 +0200512 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
513
Jarkko Nikulab7af3492008-11-21 13:39:45 -0800514 /*
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800515 * Don't write stt and stp together on some hardware.
516 */
517 if (dev->b_hw && stop) {
518 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
519 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
520 while (con & OMAP_I2C_CON_STT) {
521 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
522
523 /* Let the user know if i2c is in a bad state */
524 if (time_after(jiffies, delay)) {
525 dev_err(dev->dev, "controller timed out "
526 "waiting for start condition to finish\n");
527 return -ETIMEDOUT;
528 }
529 cpu_relax();
530 }
531
532 w |= OMAP_I2C_CON_STP;
533 w &= ~OMAP_I2C_CON_STT;
534 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
535 }
536
537 /*
Jarkko Nikulab7af3492008-11-21 13:39:45 -0800538 * REVISIT: We should abort the transfer on signals, but the bus goes
539 * into arbitration and we're currently unable to recover from it.
540 */
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530541 timeout = wait_for_completion_timeout(&dev->cmd_complete,
542 OMAP_I2C_TIMEOUT);
Komal Shah010d442c42006-08-13 23:44:09 +0200543 dev->buf_len = 0;
Shubhrajyoti D33d54982012-05-29 16:26:17 +0530544 if (timeout == 0) {
Komal Shah010d442c42006-08-13 23:44:09 +0200545 dev_err(dev->dev, "controller timed out\n");
546 omap_i2c_init(dev);
547 return -ETIMEDOUT;
548 }
549
550 if (likely(!dev->cmd_err))
551 return 0;
552
553 /* We have an error */
554 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
555 OMAP_I2C_STAT_XUDF)) {
556 omap_i2c_init(dev);
557 return -EIO;
558 }
559
560 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
561 if (msg->flags & I2C_M_IGNORE_NAK)
562 return 0;
563 if (stop) {
564 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
565 w |= OMAP_I2C_CON_STP;
566 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
567 }
568 return -EREMOTEIO;
569 }
570 return -EIO;
571}
572
573
574/*
575 * Prepare controller for a transaction and call omap_i2c_xfer_msg
576 * to do the work during IRQ processing.
577 */
578static int
579omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
580{
581 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
582 int i;
583 int r;
584
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +0530585 r = pm_runtime_get_sync(dev->dev);
586 if (IS_ERR_VALUE(r))
Kevin Hilman33ec5e82012-06-26 18:45:32 -0700587 goto out;
Komal Shah010d442c42006-08-13 23:44:09 +0200588
Tony Lindgrenc1a473b2008-11-21 13:39:47 -0800589 r = omap_i2c_wait_for_bb(dev);
590 if (r < 0)
Komal Shah010d442c42006-08-13 23:44:09 +0200591 goto out;
592
Samu Onkalo6a91b552010-11-18 12:04:20 +0200593 if (dev->set_mpu_wkup_lat != NULL)
594 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
595
Komal Shah010d442c42006-08-13 23:44:09 +0200596 for (i = 0; i < num; i++) {
597 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
598 if (r != 0)
599 break;
600 }
601
Samu Onkalo6a91b552010-11-18 12:04:20 +0200602 if (dev->set_mpu_wkup_lat != NULL)
603 dev->set_mpu_wkup_lat(dev->dev, -1);
604
Komal Shah010d442c42006-08-13 23:44:09 +0200605 if (r == 0)
606 r = num;
Mathias Nyman5c64eb22010-08-26 07:36:44 +0000607
608 omap_i2c_wait_for_bb(dev);
Komal Shah010d442c42006-08-13 23:44:09 +0200609out:
Kevin Hilmanfab67af2011-05-17 16:31:38 +0200610 pm_runtime_put(dev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +0200611 return r;
612}
613
614static u32
615omap_i2c_func(struct i2c_adapter *adap)
616{
Laurent Pinchartfb604a32012-07-24 14:13:59 +0200617 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
618 I2C_FUNC_PROTOCOL_MANGLING;
Komal Shah010d442c42006-08-13 23:44:09 +0200619}
620
621static inline void
622omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
623{
624 dev->cmd_err |= err;
625 complete(&dev->cmd_complete);
626}
627
628static inline void
629omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
630{
631 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
632}
633
manjugk manjugkf3083d92010-05-11 11:35:20 -0700634static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
635{
636 /*
637 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
638 * Not applicable for OMAP4.
639 * Under certain rare conditions, RDR could be set again
640 * when the bus is busy, then ignore the interrupt and
641 * clear the interrupt.
642 */
643 if (stat & OMAP_I2C_STAT_RDR) {
644 /* Step 1: If RDR is set, clear it */
645 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
646
647 /* Step 2: */
648 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
649 & OMAP_I2C_STAT_BB)) {
650
651 /* Step 3: */
652 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
653 & OMAP_I2C_STAT_RDR) {
654 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
655 dev_dbg(dev->dev, "RDR when bus is busy.\n");
656 }
657
658 }
659 }
660}
661
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800662/* rev1 devices are apparently only on some 15xx */
663#ifdef CONFIG_ARCH_OMAP15XX
664
Komal Shah010d442c42006-08-13 23:44:09 +0200665static irqreturn_t
Andy Green4e80f722011-05-30 07:43:07 -0700666omap_i2c_omap1_isr(int this_irq, void *dev_id)
Komal Shah010d442c42006-08-13 23:44:09 +0200667{
668 struct omap_i2c_dev *dev = dev_id;
669 u16 iv, w;
670
Kevin Hilmanfab67af2011-05-17 16:31:38 +0200671 if (pm_runtime_suspended(dev->dev))
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100672 return IRQ_NONE;
673
Komal Shah010d442c42006-08-13 23:44:09 +0200674 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
675 switch (iv) {
676 case 0x00: /* None */
677 break;
678 case 0x01: /* Arbitration lost */
679 dev_err(dev->dev, "Arbitration lost\n");
680 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
681 break;
682 case 0x02: /* No acknowledgement */
683 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
684 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
685 break;
686 case 0x03: /* Register access ready */
687 omap_i2c_complete_cmd(dev, 0);
688 break;
689 case 0x04: /* Receive data ready */
690 if (dev->buf_len) {
691 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
692 *dev->buf++ = w;
693 dev->buf_len--;
694 if (dev->buf_len) {
695 *dev->buf++ = w >> 8;
696 dev->buf_len--;
697 }
698 } else
699 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
700 break;
701 case 0x05: /* Transmit data ready */
702 if (dev->buf_len) {
703 w = *dev->buf++;
704 dev->buf_len--;
705 if (dev->buf_len) {
706 w |= *dev->buf++ << 8;
707 dev->buf_len--;
708 }
709 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
710 } else
711 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
712 break;
713 default:
714 return IRQ_NONE;
715 }
716
717 return IRQ_HANDLED;
718}
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800719#else
Andy Green4e80f722011-05-30 07:43:07 -0700720#define omap_i2c_omap1_isr NULL
Paul Walmsley43469d8e2008-11-21 13:39:47 -0800721#endif
Komal Shah010d442c42006-08-13 23:44:09 +0200722
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700723/*
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530724 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700725 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
726 * them from the memory to the I2C interface.
727 */
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530728static int errata_omap3_i462(struct omap_i2c_dev *dev, u16 *stat, int *err)
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700729{
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700730 unsigned long timeout = 10000;
731
732 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700733 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
Felipe Balbi540a4792012-09-12 16:27:59 +0530734 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700735 OMAP_I2C_STAT_XDR));
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700736 return -ETIMEDOUT;
737 }
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700738
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700739 cpu_relax();
740 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
741 }
742
Alexander Shishkine9f59b92010-05-11 11:35:17 -0700743 if (!timeout) {
744 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
745 return 0;
746 }
747
Shubhrajyoti De7e62df2012-05-29 16:26:21 +0530748 *err |= OMAP_I2C_STAT_XUDF;
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700749 return 0;
750}
751
Komal Shah010d442c42006-08-13 23:44:09 +0200752static irqreturn_t
David Howells7d12e782006-10-05 14:55:46 +0100753omap_i2c_isr(int this_irq, void *dev_id)
Komal Shah010d442c42006-08-13 23:44:09 +0200754{
755 struct omap_i2c_dev *dev = dev_id;
756 u16 bits;
757 u16 stat, w;
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800758 int err, count = 0;
Komal Shah010d442c42006-08-13 23:44:09 +0200759
Kevin Hilmanfab67af2011-05-17 16:31:38 +0200760 if (pm_runtime_suspended(dev->dev))
Tony Lindgrenf08ac4e2008-03-23 20:28:20 +0100761 return IRQ_NONE;
762
Komal Shah010d442c42006-08-13 23:44:09 +0200763 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
764 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
765 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
766 if (count++ == 100) {
767 dev_warn(dev->dev, "Too much work in one IRQ\n");
768 break;
769 }
770
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500771 err = 0;
772complete:
Nishanth Menondcc4ec22009-08-20 11:21:14 -0500773 /*
774 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
775 * acked after the data operation is complete.
776 * Ref: TRM SWPU114Q Figure 18-31
777 */
778 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
779 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
780 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
Komal Shah010d442c42006-08-13 23:44:09 +0200781
Jan Weitzel78e1cf42011-12-07 11:50:16 -0800782 if (stat & OMAP_I2C_STAT_NACK)
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800783 err |= OMAP_I2C_STAT_NACK;
Jan Weitzel78e1cf42011-12-07 11:50:16 -0800784
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800785 if (stat & OMAP_I2C_STAT_AL) {
786 dev_err(dev->dev, "Arbitration lost\n");
787 err |= OMAP_I2C_STAT_AL;
788 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530789
Ben Dooksa5a595c2011-02-23 00:43:55 +0000790 /*
Richard woodruffcb527ed2011-02-16 10:24:16 +0530791 * ProDB0017052: Clear ARDY bit twice
Ben Dooksa5a595c2011-02-23 00:43:55 +0000792 */
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800793 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
Sonasath, Moiz04c688d2009-07-21 10:14:40 -0500794 OMAP_I2C_STAT_AL)) {
Felipe Balbi540a4792012-09-12 16:27:59 +0530795 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
796 OMAP_I2C_STAT_RDR |
797 OMAP_I2C_STAT_XRDY |
798 OMAP_I2C_STAT_XDR |
799 OMAP_I2C_STAT_ARDY));
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800800 omap_i2c_complete_cmd(dev, err);
Sonasath, Moiz04c688d2009-07-21 10:14:40 -0500801 return IRQ_HANDLED;
802 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530803
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530804 if (stat & OMAP_I2C_STAT_RDR) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800805 u8 num_bytes = 1;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700806
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530807 if (dev->fifo_size)
808 num_bytes = dev->buf_len;
manjugk manjugkf3083d92010-05-11 11:35:20 -0700809
Felipe Balbibaf3d7b2012-09-12 16:27:56 +0530810 while (num_bytes--) {
Felipe Balbi2049b5b2012-09-12 16:27:57 +0530811 if (!dev->buf_len) {
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530812 dev_err(dev->dev,
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800813 "RDR IRQ while no data"
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530814 " requested\n");
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800815 break;
816 }
Felipe Balbi2049b5b2012-09-12 16:27:57 +0530817
818 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
819 *dev->buf++ = w;
820 dev->buf_len--;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530821
Felipe Balbi2049b5b2012-09-12 16:27:57 +0530822 /*
823 * Data reg in 2430, omap3 and
824 * omap4 is 8 bit wide
825 */
826 if (dev->flags &
827 OMAP_I2C_FLAG_16BIT_DATA_REG) {
828 if (dev->buf_len) {
829 *dev->buf++ = w >> 8;
830 dev->buf_len--;
831 }
832 }
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800833 }
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530834
835 if (dev->errata & I2C_OMAP_ERRATA_I207)
836 i2c_omap_errata_i207(dev, stat);
837
838 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
Komal Shah010d442c42006-08-13 23:44:09 +0200839 continue;
840 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530841
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530842 if (stat & OMAP_I2C_STAT_RRDY) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800843 u8 num_bytes = 1;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530844
845 if (dev->fifo_size)
846 num_bytes = dev->fifo_size;
847
Felipe Balbibaf3d7b2012-09-12 16:27:56 +0530848 while (num_bytes--) {
Felipe Balbi2049b5b2012-09-12 16:27:57 +0530849 if (!dev->buf_len) {
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530850 dev_err(dev->dev,
851 "RRDY IRQ while no data"
852 " requested\n");
853 break;
854 }
855
856 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
857 *dev->buf++ = w;
858 dev->buf_len--;
859
860 /*
861 * Data reg in 2430, omap3 and
862 * omap4 is 8 bit wide
863 */
864 if (dev->flags &
865 OMAP_I2C_FLAG_16BIT_DATA_REG) {
866 if (dev->buf_len) {
867 *dev->buf++ = w >> 8;
868 dev->buf_len--;
869 }
870 }
871 }
872
873 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
874 continue;
875 }
876
877 if (stat & OMAP_I2C_STAT_XDR) {
878 u8 num_bytes = 1;
879
880 if (dev->fifo_size)
881 num_bytes = dev->buf_len;
882
883 while (num_bytes--) {
884 if (!dev->buf_len) {
885 dev_err(dev->dev,
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800886 "XDR IRQ while no "
887 "data to send\n");
888 break;
Komal Shah010d442c42006-08-13 23:44:09 +0200889 }
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500890
Felipe Balbi2049b5b2012-09-12 16:27:57 +0530891 w = *dev->buf++;
892 dev->buf_len--;
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530893
Felipe Balbi2049b5b2012-09-12 16:27:57 +0530894 /*
895 * Data reg in 2430, omap3 and
896 * omap4 is 8 bit wide
897 */
898 if (dev->flags &
899 OMAP_I2C_FLAG_16BIT_DATA_REG) {
900 if (dev->buf_len) {
901 w |= *dev->buf++ << 8;
902 dev->buf_len--;
903 }
904 }
905
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +0530906 if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
907 errata_omap3_i462(dev, &stat, &err))
Alexander Shishkin2dd151a2010-05-11 11:35:14 -0700908 goto complete;
Sonasath, Moizcd086d32009-07-21 10:15:12 -0500909
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800910 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
911 }
Felipe Balbi6d9939f2012-09-12 16:28:00 +0530912
913 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
914 continue;
915 }
916
917 if (stat & OMAP_I2C_STAT_XRDY) {
918 u8 num_bytes = 1;
919
920 if (dev->fifo_size)
921 num_bytes = dev->fifo_size;
922
923 while (num_bytes--) {
924 if (!dev->buf_len) {
925 dev_err(dev->dev,
926 "XRDY IRQ while no "
927 "data to send\n");
928 break;
929 }
930
931 w = *dev->buf++;
932 dev->buf_len--;
933
934 /*
935 * Data reg in 2430, omap3 and
936 * omap4 is 8 bit wide
937 */
938 if (dev->flags &
939 OMAP_I2C_FLAG_16BIT_DATA_REG) {
940 if (dev->buf_len) {
941 w |= *dev->buf++ << 8;
942 dev->buf_len--;
943 }
944 }
945
946 if ((dev->errata & I2C_OMAP_ERRATA_I462) &&
947 errata_omap3_i462(dev, &stat, &err))
948 goto complete;
949
950 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
951 }
952
953 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
Komal Shah010d442c42006-08-13 23:44:09 +0200954 continue;
955 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530956
Komal Shah010d442c42006-08-13 23:44:09 +0200957 if (stat & OMAP_I2C_STAT_ROVR) {
958 dev_err(dev->dev, "Receive overrun\n");
959 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
960 }
Felipe Balbic55edb92012-09-12 16:27:58 +0530961
Komal Shah010d442c42006-08-13 23:44:09 +0200962 if (stat & OMAP_I2C_STAT_XUDF) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -0800963 dev_err(dev->dev, "Transmit underflow\n");
Komal Shah010d442c42006-08-13 23:44:09 +0200964 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
965 }
Komal Shah010d442c42006-08-13 23:44:09 +0200966 }
967
968 return count ? IRQ_HANDLED : IRQ_NONE;
969}
970
Jean Delvare8f9082c2006-09-03 22:39:46 +0200971static const struct i2c_algorithm omap_i2c_algo = {
Komal Shah010d442c42006-08-13 23:44:09 +0200972 .master_xfer = omap_i2c_xfer,
973 .functionality = omap_i2c_func,
974};
975
Benoit Cousson61451972011-12-22 15:56:36 +0100976#ifdef CONFIG_OF
977static struct omap_i2c_bus_platform_data omap3_pdata = {
978 .rev = OMAP_I2C_IP_VERSION_1,
979 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
980 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
981 OMAP_I2C_FLAG_BUS_SHIFT_2,
982};
983
984static struct omap_i2c_bus_platform_data omap4_pdata = {
985 .rev = OMAP_I2C_IP_VERSION_2,
986};
987
988static const struct of_device_id omap_i2c_of_match[] = {
989 {
990 .compatible = "ti,omap4-i2c",
991 .data = &omap4_pdata,
992 },
993 {
994 .compatible = "ti,omap3-i2c",
995 .data = &omap3_pdata,
996 },
997 { },
998};
999MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1000#endif
1001
Uwe Kleine-König1139aea2010-02-04 20:56:53 +01001002static int __devinit
Komal Shah010d442c42006-08-13 23:44:09 +02001003omap_i2c_probe(struct platform_device *pdev)
1004{
1005 struct omap_i2c_dev *dev;
1006 struct i2c_adapter *adap;
Felipe Balbid9ebd042012-09-12 16:27:55 +05301007 struct resource *mem, *irq;
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001008 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
Benoit Cousson61451972011-12-22 15:56:36 +01001009 struct device_node *node = pdev->dev.of_node;
1010 const struct of_device_id *match;
Ben Dookse3552042008-12-16 22:08:08 +00001011 irq_handler_t isr;
Komal Shah010d442c42006-08-13 23:44:09 +02001012 int r;
1013
1014 /* NOTE: driver uses the static register mapping */
1015 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1016 if (!mem) {
1017 dev_err(&pdev->dev, "no mem resource?\n");
1018 return -ENODEV;
1019 }
1020 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1021 if (!irq) {
1022 dev_err(&pdev->dev, "no irq resource?\n");
1023 return -ENODEV;
1024 }
1025
Felipe Balbid9ebd042012-09-12 16:27:55 +05301026 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1027 if (!dev) {
1028 dev_err(&pdev->dev, "Menory allocation failed\n");
1029 return -ENOMEM;
Komal Shah010d442c42006-08-13 23:44:09 +02001030 }
1031
Felipe Balbid9ebd042012-09-12 16:27:55 +05301032 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
1033 if (!dev->base) {
1034 dev_err(&pdev->dev, "I2C region already claimed\n");
1035 return -ENOMEM;
Komal Shah010d442c42006-08-13 23:44:09 +02001036 }
1037
Cousson, Benoit6c5aa402012-01-20 16:55:04 +01001038 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
Benoit Cousson61451972011-12-22 15:56:36 +01001039 if (match) {
1040 u32 freq = 100000; /* default to 100000 Hz */
1041
1042 pdata = match->data;
1043 dev->dtrev = pdata->rev;
1044 dev->flags = pdata->flags;
1045
1046 of_property_read_u32(node, "clock-frequency", &freq);
1047 /* convert DT freq value in Hz into kHz for speed */
1048 dev->speed = freq / 1000;
1049 } else if (pdata != NULL) {
1050 dev->speed = pdata->clkrate;
1051 dev->flags = pdata->flags;
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001052 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
Benoit Cousson61451972011-12-22 15:56:36 +01001053 dev->dtrev = pdata->rev;
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001054 }
Syed Mohammed Khasim4574eb62008-11-21 13:39:45 -08001055
Komal Shah010d442c42006-08-13 23:44:09 +02001056 dev->dev = &pdev->dev;
1057 dev->irq = irq->start;
Russell King55c381e2008-09-04 14:07:22 +01001058
Komal Shah010d442c42006-08-13 23:44:09 +02001059 platform_set_drvdata(pdev, dev);
Shubhrajyoti D0e33bbb2012-06-28 20:41:29 +05301060 init_completion(&dev->cmd_complete);
Komal Shah010d442c42006-08-13 23:44:09 +02001061
Benoit Cousson61451972011-12-22 15:56:36 +01001062 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
Mika Westerberg7c6bd202010-03-23 12:12:56 +02001063
Benoit Cousson61451972011-12-22 15:56:36 +01001064 if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
Andy Greena1295572011-05-30 07:43:06 -07001065 dev->regs = (u8 *)reg_map_ip_v2;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001066 else
Andy Greena1295572011-05-30 07:43:06 -07001067 dev->regs = (u8 *)reg_map_ip_v1;
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001068
Kevin Hilman7f4b08e2011-05-17 16:31:37 +02001069 pm_runtime_enable(dev->dev);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301070 r = pm_runtime_get_sync(dev->dev);
1071 if (IS_ERR_VALUE(r))
1072 goto err_free_mem;
Komal Shah010d442c42006-08-13 23:44:09 +02001073
Paul Walmsley9c76b872008-11-21 13:39:55 -08001074 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
Komal Shah010d442c42006-08-13 23:44:09 +02001075
Tasslehoff Kjappfot9aa8ec62012-05-29 16:26:20 +05301076 dev->errata = 0;
1077
1078 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207)
1079 dev->errata |= I2C_OMAP_ERRATA_I207;
1080
Jon Hunterf518b482012-06-28 20:41:31 +05301081 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
Shubhrajyoti Dc8db38f2012-05-29 16:26:22 +05301082 dev->errata |= I2C_OMAP_ERRATA_I462;
manjugk manjugk8a9d97d2010-05-11 11:35:23 -07001083
Benoit Cousson61451972011-12-22 15:56:36 +01001084 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001085 u16 s;
1086
1087 /* Set up the fifo size - Get total size */
1088 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1089 dev->fifo_size = 0x8 << s;
1090
1091 /*
1092 * Set up notification threshold as half the total available
1093 * size. This is to ensure that we can handle the status on int
1094 * call back latencies.
1095 */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001096
1097 dev->fifo_size = (dev->fifo_size / 2);
1098
Jon Hunterf518b482012-06-28 20:41:31 +05301099 if (dev->rev >= OMAP_I2C_REV_ON_3630_4430)
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001100 dev->b_hw = 0; /* Disable hardware fixes */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001101 else
Santosh Shilimkarf38e66e2010-05-11 11:35:04 -07001102 dev->b_hw = 1; /* Enable hardware fixes */
Shubhrajyoti D1d5a34f2011-12-06 10:25:58 -08001103
Kalle Jokiniemi20c9d2c2010-05-11 11:35:08 -07001104 /* calculate wakeup latency constraint for MPU */
1105 if (dev->set_mpu_wkup_lat != NULL)
1106 dev->latency = (1000000 * dev->fifo_size) /
Benoit Cousson61451972011-12-22 15:56:36 +01001107 (1000 * dev->speed / 8);
Nishanth Menonb6ee52c2008-11-21 13:39:46 -08001108 }
1109
Komal Shah010d442c42006-08-13 23:44:09 +02001110 /* reset ASAP, clearing any IRQs */
1111 omap_i2c_init(dev);
1112
Andy Green4e80f722011-05-30 07:43:07 -07001113 isr = (dev->rev < OMAP_I2C_OMAP1_REV_2) ? omap_i2c_omap1_isr :
1114 omap_i2c_isr;
Felipe Balbid9ebd042012-09-12 16:27:55 +05301115 r = devm_request_irq(&pdev->dev, dev->irq, isr, IRQF_NO_SUSPEND,
1116 pdev->name, dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001117
1118 if (r) {
1119 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1120 goto err_unuse_clocks;
1121 }
Paul Walmsley9c76b872008-11-21 13:39:55 -08001122
Andy Green9550d4d2011-05-30 07:43:10 -07001123 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", pdev->id,
Benoit Cousson61451972011-12-22 15:56:36 +01001124 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed);
Komal Shah010d442c42006-08-13 23:44:09 +02001125
1126 adap = &dev->adapter;
1127 i2c_set_adapdata(adap, dev);
1128 adap->owner = THIS_MODULE;
1129 adap->class = I2C_CLASS_HWMON;
Roel Kluin783fd6f2009-07-17 15:24:00 +02001130 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
Komal Shah010d442c42006-08-13 23:44:09 +02001131 adap->algo = &omap_i2c_algo;
1132 adap->dev.parent = &pdev->dev;
Benoit Cousson61451972011-12-22 15:56:36 +01001133 adap->dev.of_node = pdev->dev.of_node;
Komal Shah010d442c42006-08-13 23:44:09 +02001134
1135 /* i2c device drivers may be active on return from add_adapter() */
David Brownell7c175492007-05-01 23:26:32 +02001136 adap->nr = pdev->id;
1137 r = i2c_add_numbered_adapter(adap);
Komal Shah010d442c42006-08-13 23:44:09 +02001138 if (r) {
1139 dev_err(dev->dev, "failure adding adapter\n");
Felipe Balbid9ebd042012-09-12 16:27:55 +05301140 goto err_unuse_clocks;
Komal Shah010d442c42006-08-13 23:44:09 +02001141 }
1142
Benoit Cousson61451972011-12-22 15:56:36 +01001143 of_i2c_register_devices(adap);
1144
Shubhrajyoti D62ff2c22012-05-29 16:26:16 +05301145 pm_runtime_put(dev->dev);
1146
Komal Shah010d442c42006-08-13 23:44:09 +02001147 return 0;
1148
Komal Shah010d442c42006-08-13 23:44:09 +02001149err_unuse_clocks:
Tony Lindgren3e397522008-01-14 21:53:30 +01001150 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001151 pm_runtime_put(dev->dev);
Shubhrajyoti D24740512012-05-29 16:26:14 +05301152 pm_runtime_disable(&pdev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001153err_free_mem:
1154 platform_set_drvdata(pdev, NULL);
Komal Shah010d442c42006-08-13 23:44:09 +02001155
1156 return r;
1157}
1158
Shubhrajyoti Dd790aea2012-06-28 20:41:27 +05301159static int __devexit omap_i2c_remove(struct platform_device *pdev)
Komal Shah010d442c42006-08-13 23:44:09 +02001160{
1161 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301162 int ret;
Komal Shah010d442c42006-08-13 23:44:09 +02001163
1164 platform_set_drvdata(pdev, NULL);
1165
Komal Shah010d442c42006-08-13 23:44:09 +02001166 i2c_del_adapter(&dev->adapter);
Shubhrajyoti D3b0fb972012-05-29 16:26:19 +05301167 ret = pm_runtime_get_sync(&pdev->dev);
1168 if (IS_ERR_VALUE(ret))
1169 return ret;
1170
Komal Shah010d442c42006-08-13 23:44:09 +02001171 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
Shubhrajyoti D0861f432012-05-29 16:26:18 +05301172 pm_runtime_put(&pdev->dev);
Shubhrajyoti D24740512012-05-29 16:26:14 +05301173 pm_runtime_disable(&pdev->dev);
Komal Shah010d442c42006-08-13 23:44:09 +02001174 return 0;
1175}
1176
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301177#ifdef CONFIG_PM
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001178#ifdef CONFIG_PM_RUNTIME
1179static int omap_i2c_runtime_suspend(struct device *dev)
1180{
1181 struct platform_device *pdev = to_platform_device(dev);
1182 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301183 u16 iv;
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001184
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301185 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
Shubhrajyoti Dbd16c822012-05-29 16:26:15 +05301186
1187 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301188
1189 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1190 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1191 } else {
1192 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1193
1194 /* Flush posted write */
1195 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1196 }
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001197
1198 return 0;
1199}
1200
1201static int omap_i2c_runtime_resume(struct device *dev)
1202{
1203 struct platform_device *pdev = to_platform_device(dev);
1204 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1205
Shubhrajyoti D3dae3ef2012-05-29 16:26:13 +05301206 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) {
1207 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0);
1208 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1209 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1210 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1211 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1212 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1213 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1214 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1215 }
1216
1217 /*
1218 * Don't write to this register if the IE state is 0 as it can
1219 * cause deadlock.
1220 */
1221 if (_dev->iestate)
1222 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001223
1224 return 0;
1225}
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301226#endif /* CONFIG_PM_RUNTIME */
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001227
1228static struct dev_pm_ops omap_i2c_pm_ops = {
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301229 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1230 omap_i2c_runtime_resume, NULL)
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001231};
1232#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1233#else
1234#define OMAP_I2C_PM_OPS NULL
Shubhrajyoti D5692d2a2012-06-28 20:41:28 +05301235#endif /* CONFIG_PM */
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001236
Komal Shah010d442c42006-08-13 23:44:09 +02001237static struct platform_driver omap_i2c_driver = {
1238 .probe = omap_i2c_probe,
Shubhrajyoti Dd790aea2012-06-28 20:41:27 +05301239 .remove = __devexit_p(omap_i2c_remove),
Komal Shah010d442c42006-08-13 23:44:09 +02001240 .driver = {
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001241 .name = "omap_i2c",
Komal Shah010d442c42006-08-13 23:44:09 +02001242 .owner = THIS_MODULE,
Kevin Hilmanfab67af2011-05-17 16:31:38 +02001243 .pm = OMAP_I2C_PM_OPS,
Benoit Cousson61451972011-12-22 15:56:36 +01001244 .of_match_table = of_match_ptr(omap_i2c_of_match),
Komal Shah010d442c42006-08-13 23:44:09 +02001245 },
1246};
1247
1248/* I2C may be needed to bring up other drivers */
1249static int __init
1250omap_i2c_init_driver(void)
1251{
1252 return platform_driver_register(&omap_i2c_driver);
1253}
1254subsys_initcall(omap_i2c_init_driver);
1255
1256static void __exit omap_i2c_exit_driver(void)
1257{
1258 platform_driver_unregister(&omap_i2c_driver);
1259}
1260module_exit(omap_i2c_exit_driver);
1261
1262MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1263MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1264MODULE_LICENSE("GPL");
Benoit Coussonf7bb0d92010-12-09 14:24:16 +00001265MODULE_ALIAS("platform:omap_i2c");