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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * Copyright (c) 2001-2002 by David Brownell
David Brownell53bd6a62006-08-30 14:50:06 -07003 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 */
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22/* definitions used for the EHCI driver */
23
24/* statistics can be kept for for tuning/monitoring */
25struct ehci_stats {
26 /* irq usage */
27 unsigned long normal;
28 unsigned long error;
29 unsigned long reclaim;
30 unsigned long lost_iaa;
31
32 /* termination of urbs from core */
33 unsigned long complete;
34 unsigned long unlink;
35};
36
37/* ehci_hcd->lock guards shared data against other CPUs:
38 * ehci_hcd: async, reclaim, periodic (and shadow), ...
39 * usb_host_endpoint: hcpriv
40 * ehci_qh: qh_next, qtd_list
41 * ehci_qtd: qtd_list
42 *
43 * Also, hold this lock when talking to HC registers or
44 * when updating hw_* fields in shared qh/qtd/... structures.
45 */
46
47#define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
48
49struct ehci_hcd { /* one per controller */
David Brownell56c1e262005-04-09 09:00:29 -070050 /* glue to PCI and HCD framework */
51 struct ehci_caps __iomem *caps;
52 struct ehci_regs __iomem *regs;
53 struct ehci_dbg_port __iomem *debug;
54
55 __u32 hcs_params; /* cached register copy */
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 spinlock_t lock;
57
Stuart_Hayes@Dell.com196705c2007-05-03 08:58:49 -070058#ifdef CONFIG_CPU_FREQ
59 struct notifier_block cpufreq_transition;
60 int cpufreq_changing;
61 struct list_head split_intr_qhs;
62#endif
63
Linus Torvalds1da177e2005-04-16 15:20:36 -070064 /* async schedule support */
65 struct ehci_qh *async;
66 struct ehci_qh *reclaim;
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -070067 unsigned reclaim_ready : 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 unsigned scanning : 1;
69
70 /* periodic schedule support */
71#define DEFAULT_I_TDPS 1024 /* some HCs can do less */
72 unsigned periodic_size;
73 __le32 *periodic; /* hw periodic table */
74 dma_addr_t periodic_dma;
75 unsigned i_thresh; /* uframes HC might cache */
76
77 union ehci_shadow *pshadow; /* mirror hw periodic table */
78 int next_uframe; /* scan periodic, start here */
79 unsigned periodic_sched; /* periodic activity count */
80
81 /* per root hub port */
82 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
Alan Stern57e06c12007-01-16 11:59:45 -050083 /* bit vectors (one bit per port) */
84 unsigned long bus_suspended; /* which ports were
85 already suspended at the start of a bus suspend */
86 unsigned long companion_ports; /* which ports are
87 dedicated to the companion controller */
Linus Torvalds1da177e2005-04-16 15:20:36 -070088
89 /* per-HC memory pools (could be per-bus, but ...) */
90 struct dma_pool *qh_pool; /* qh per active urb */
91 struct dma_pool *qtd_pool; /* one or more per qh */
92 struct dma_pool *itd_pool; /* itd per iso urb */
93 struct dma_pool *sitd_pool; /* sitd per split iso urb */
94
95 struct timer_list watchdog;
Linus Torvalds1da177e2005-04-16 15:20:36 -070096 unsigned long actions;
97 unsigned stamp;
98 unsigned long next_statechange;
99 u32 command;
100
Kumar Gala8cd42e92006-01-20 13:57:52 -0800101 /* SILICON QUIRKS */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */
David Brownellf8aeb3b2006-01-20 13:55:14 -0800103 unsigned no_selective_suspend:1;
Kumar Gala8cd42e92006-01-20 13:57:52 -0800104 unsigned has_fsl_port_bug:1; /* FreeScale */
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100105 unsigned big_endian_mmio:1;
Kumar Gala8cd42e92006-01-20 13:57:52 -0800106
David Brownellf8aeb3b2006-01-20 13:55:14 -0800107 u8 sbrn; /* packed release number */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108
Linus Torvalds1da177e2005-04-16 15:20:36 -0700109 /* irq statistics */
110#ifdef EHCI_STATS
111 struct ehci_stats stats;
112# define COUNT(x) do { (x)++; } while (0)
113#else
114# define COUNT(x) do {} while (0)
115#endif
116};
117
David Brownell53bd6a62006-08-30 14:50:06 -0700118/* convert between an HCD pointer and the corresponding EHCI_HCD */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
120{
121 return (struct ehci_hcd *) (hcd->hcd_priv);
122}
123static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
124{
125 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
126}
127
128
129enum ehci_timer_action {
130 TIMER_IO_WATCHDOG,
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -0700131 TIMER_IAA_WATCHDOG,
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 TIMER_ASYNC_SHRINK,
133 TIMER_ASYNC_OFF,
134};
135
136static inline void
137timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
138{
139 clear_bit (action, &ehci->actions);
140}
141
142static inline void
143timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
144{
145 if (!test_and_set_bit (action, &ehci->actions)) {
146 unsigned long t;
147
148 switch (action) {
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -0700149 case TIMER_IAA_WATCHDOG:
150 t = EHCI_IAA_JIFFIES;
151 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 case TIMER_IO_WATCHDOG:
153 t = EHCI_IO_JIFFIES;
154 break;
155 case TIMER_ASYNC_OFF:
156 t = EHCI_ASYNC_JIFFIES;
157 break;
158 // case TIMER_ASYNC_SHRINK:
159 default:
160 t = EHCI_SHRINK_JIFFIES;
161 break;
162 }
163 t += jiffies;
164 // all timings except IAA watchdog can be overridden.
165 // async queue SHRINK often precedes IAA. while it's ready
166 // to go OFF neither can matter, and afterwards the IO
167 // watchdog stops unless there's still periodic traffic.
Greg Kroah-Hartman64f89792006-10-17 13:57:18 -0700168 if (action != TIMER_IAA_WATCHDOG
169 && t > ehci->watchdog.expires
Linus Torvalds1da177e2005-04-16 15:20:36 -0700170 && timer_pending (&ehci->watchdog))
171 return;
172 mod_timer (&ehci->watchdog, t);
173 }
174}
175
176/*-------------------------------------------------------------------------*/
177
178/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
179
180/* Section 2.2 Host Controller Capability Registers */
181struct ehci_caps {
182 /* these fields are specified as 8 and 16 bit registers,
183 * but some hosts can't perform 8 or 16 bit PCI accesses.
184 */
David Brownell56c1e262005-04-09 09:00:29 -0700185 u32 hc_capbase;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700186#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
187#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
188 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
189#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
190#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
191#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
192#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
David Brownell53bd6a62006-08-30 14:50:06 -0700193#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
194#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700195#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
196
197 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
198#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
199#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
200#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
201#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
202#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
203#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
204 u8 portroute [8]; /* nibbles for routing - offset 0xC */
205} __attribute__ ((packed));
206
207
208/* Section 2.3 Host Controller Operational Registers */
209struct ehci_regs {
210
211 /* USBCMD: offset 0x00 */
212 u32 command;
213/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
214#define CMD_PARK (1<<11) /* enable "park" on async qh */
215#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
216#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
217#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
218#define CMD_ASE (1<<5) /* async schedule enable */
David Brownell53bd6a62006-08-30 14:50:06 -0700219#define CMD_PSE (1<<4) /* periodic schedule enable */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700220/* 3:2 is periodic frame list size */
221#define CMD_RESET (1<<1) /* reset HC not bus */
222#define CMD_RUN (1<<0) /* start/stop HC */
223
224 /* USBSTS: offset 0x04 */
225 u32 status;
226#define STS_ASS (1<<15) /* Async Schedule Status */
227#define STS_PSS (1<<14) /* Periodic Schedule Status */
228#define STS_RECL (1<<13) /* Reclamation */
229#define STS_HALT (1<<12) /* Not running (any reason) */
230/* some bits reserved */
231 /* these STS_* flags are also intr_enable bits (USBINTR) */
232#define STS_IAA (1<<5) /* Interrupted on async advance */
233#define STS_FATAL (1<<4) /* such as some PCI access errors */
234#define STS_FLR (1<<3) /* frame list rolled over */
235#define STS_PCD (1<<2) /* port change detect */
236#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
237#define STS_INT (1<<0) /* "normal" completion (short, ...) */
238
239 /* USBINTR: offset 0x08 */
240 u32 intr_enable;
241
242 /* FRINDEX: offset 0x0C */
243 u32 frame_index; /* current microframe number */
244 /* CTRLDSSEGMENT: offset 0x10 */
David Brownell53bd6a62006-08-30 14:50:06 -0700245 u32 segment; /* address bits 63:32 if needed */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 /* PERIODICLISTBASE: offset 0x14 */
David Brownell53bd6a62006-08-30 14:50:06 -0700247 u32 frame_list; /* points to periodic list */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700248 /* ASYNCLISTADDR: offset 0x18 */
249 u32 async_next; /* address of next async queue head */
250
251 u32 reserved [9];
252
253 /* CONFIGFLAG: offset 0x40 */
254 u32 configured_flag;
255#define FLAG_CF (1<<0) /* true: we'll support "high speed" */
256
257 /* PORTSC: offset 0x44 */
258 u32 port_status [0]; /* up to N_PORTS */
259/* 31:23 reserved */
260#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
261#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
262#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
263/* 19:16 for port testing */
264#define PORT_LED_OFF (0<<14)
265#define PORT_LED_AMBER (1<<14)
266#define PORT_LED_GREEN (2<<14)
267#define PORT_LED_MASK (3<<14)
268#define PORT_OWNER (1<<13) /* true: companion hc owns this port */
269#define PORT_POWER (1<<12) /* true: has power (see PPC) */
270#define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
271/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
272/* 9 reserved */
273#define PORT_RESET (1<<8) /* reset port */
274#define PORT_SUSPEND (1<<7) /* suspend port */
275#define PORT_RESUME (1<<6) /* resume it */
276#define PORT_OCC (1<<5) /* over current change */
277#define PORT_OC (1<<4) /* over current active */
278#define PORT_PEC (1<<3) /* port enable change */
279#define PORT_PE (1<<2) /* port enable */
280#define PORT_CSC (1<<1) /* connect status change */
281#define PORT_CONNECT (1<<0) /* device connected */
David Brownell10f65242005-08-31 10:55:38 -0700282#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700283} __attribute__ ((packed));
284
285/* Appendix C, Debug port ... intended for use with special "debug devices"
286 * that can help if there's no serial console. (nonstandard enumeration.)
287 */
288struct ehci_dbg_port {
289 u32 control;
290#define DBGP_OWNER (1<<30)
291#define DBGP_ENABLED (1<<28)
292#define DBGP_DONE (1<<16)
293#define DBGP_INUSE (1<<10)
David Brownell56c1e262005-04-09 09:00:29 -0700294#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295# define DBGP_ERR_BAD 1
296# define DBGP_ERR_SIGNAL 2
297#define DBGP_ERROR (1<<6)
298#define DBGP_GO (1<<5)
299#define DBGP_OUT (1<<4)
300#define DBGP_LEN(x) (((x)>>0)&0x0f)
301 u32 pids;
302#define DBGP_PID_GET(x) (((x)>>16)&0xff)
David Brownell56c1e262005-04-09 09:00:29 -0700303#define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700304 u32 data03;
305 u32 data47;
306 u32 address;
David Brownell56c1e262005-04-09 09:00:29 -0700307#define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
Linus Torvalds1da177e2005-04-16 15:20:36 -0700308} __attribute__ ((packed));
309
310/*-------------------------------------------------------------------------*/
311
312#define QTD_NEXT(dma) cpu_to_le32((u32)dma)
313
314/*
315 * EHCI Specification 0.95 Section 3.5
David Brownell53bd6a62006-08-30 14:50:06 -0700316 * QTD: describe data transfer components (buffer, direction, ...)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700317 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
318 *
319 * These are associated only with "QH" (Queue Head) structures,
320 * used with control, bulk, and interrupt transfers.
321 */
322struct ehci_qtd {
323 /* first part defined by EHCI spec */
324 __le32 hw_next; /* see EHCI 3.5.1 */
325 __le32 hw_alt_next; /* see EHCI 3.5.2 */
David Brownell53bd6a62006-08-30 14:50:06 -0700326 __le32 hw_token; /* see EHCI 3.5.3 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327#define QTD_TOGGLE (1 << 31) /* data toggle */
328#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
329#define QTD_IOC (1 << 15) /* interrupt on complete */
330#define QTD_CERR(tok) (((tok)>>10) & 0x3)
331#define QTD_PID(tok) (((tok)>>8) & 0x3)
332#define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
333#define QTD_STS_HALT (1 << 6) /* halted on error */
334#define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
335#define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
336#define QTD_STS_XACT (1 << 3) /* device gave illegal response */
337#define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
338#define QTD_STS_STS (1 << 1) /* split transaction state */
339#define QTD_STS_PING (1 << 0) /* issue PING? */
340 __le32 hw_buf [5]; /* see EHCI 3.5.4 */
341 __le32 hw_buf_hi [5]; /* Appendix B */
342
343 /* the rest is HCD-private */
344 dma_addr_t qtd_dma; /* qtd address */
345 struct list_head qtd_list; /* sw qtd list */
346 struct urb *urb; /* qtd's urb */
347 size_t length; /* length of buffer */
348} __attribute__ ((aligned (32)));
349
350/* mask NakCnt+T in qh->hw_alt_next */
351#define QTD_MASK __constant_cpu_to_le32 (~0x1f)
352
353#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
354
355/*-------------------------------------------------------------------------*/
356
357/* type tag from {qh,itd,sitd,fstn}->hw_next */
358#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
359
360/* values for that type tag */
361#define Q_TYPE_ITD __constant_cpu_to_le32 (0 << 1)
362#define Q_TYPE_QH __constant_cpu_to_le32 (1 << 1)
David Brownell53bd6a62006-08-30 14:50:06 -0700363#define Q_TYPE_SITD __constant_cpu_to_le32 (2 << 1)
364#define Q_TYPE_FSTN __constant_cpu_to_le32 (3 << 1)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700365
366/* next async queue entry, or pointer to interrupt/periodic QH */
367#define QH_NEXT(dma) (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
368
369/* for periodic/async schedules and qtd lists, mark end of list */
370#define EHCI_LIST_END __constant_cpu_to_le32(1) /* "null pointer" to hw */
371
372/*
373 * Entries in periodic shadow table are pointers to one of four kinds
374 * of data structure. That's dictated by the hardware; a type tag is
375 * encoded in the low bits of the hardware's periodic schedule. Use
376 * Q_NEXT_TYPE to get the tag.
377 *
378 * For entries in the async schedule, the type tag always says "qh".
379 */
380union ehci_shadow {
David Brownell53bd6a62006-08-30 14:50:06 -0700381 struct ehci_qh *qh; /* Q_TYPE_QH */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700382 struct ehci_itd *itd; /* Q_TYPE_ITD */
383 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
384 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
David Brownell9a5d3e92005-04-18 17:39:23 -0700385 __le32 *hw_next; /* (all types) */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700386 void *ptr;
387};
388
389/*-------------------------------------------------------------------------*/
390
391/*
392 * EHCI Specification 0.95 Section 3.6
393 * QH: describes control/bulk/interrupt endpoints
394 * See Fig 3-7 "Queue Head Structure Layout".
395 *
396 * These appear in both the async and (for interrupt) periodic schedules.
397 */
398
399struct ehci_qh {
400 /* first part defined by EHCI spec */
401 __le32 hw_next; /* see EHCI 3.6.1 */
402 __le32 hw_info1; /* see EHCI 3.6.2 */
403#define QH_HEAD 0x00008000
Stuart_Hayes@Dell.com196705c2007-05-03 08:58:49 -0700404#define QH_INACTIVATE 0x00000080
Linus Torvalds1da177e2005-04-16 15:20:36 -0700405 __le32 hw_info2; /* see EHCI 3.6.2 */
David Brownell7dedacf2005-08-04 18:06:41 -0700406#define QH_SMASK 0x000000ff
407#define QH_CMASK 0x0000ff00
408#define QH_HUBADDR 0x007f0000
409#define QH_HUBPORT 0x3f800000
410#define QH_MULT 0xc0000000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700411 __le32 hw_current; /* qtd list - see EHCI 3.6.4 */
David Brownell53bd6a62006-08-30 14:50:06 -0700412
Linus Torvalds1da177e2005-04-16 15:20:36 -0700413 /* qtd overlay (hardware parts of a struct ehci_qtd) */
414 __le32 hw_qtd_next;
415 __le32 hw_alt_next;
416 __le32 hw_token;
417 __le32 hw_buf [5];
418 __le32 hw_buf_hi [5];
419
420 /* the rest is HCD-private */
421 dma_addr_t qh_dma; /* address of qh */
422 union ehci_shadow qh_next; /* ptr to qh; or periodic */
423 struct list_head qtd_list; /* sw qtd list */
424 struct ehci_qtd *dummy;
425 struct ehci_qh *reclaim; /* next to reclaim */
426
427 struct ehci_hcd *ehci;
428 struct kref kref;
429 unsigned stamp;
430
431 u8 qh_state;
432#define QH_STATE_LINKED 1 /* HC sees this */
433#define QH_STATE_UNLINK 2 /* HC may still see this */
434#define QH_STATE_IDLE 3 /* HC doesn't see this */
435#define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
436#define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
437
438 /* periodic schedule info */
439 u8 usecs; /* intr bandwidth */
440 u8 gap_uf; /* uframes split/csplit gap */
441 u8 c_usecs; /* ... split completion bw */
david-b@pacbell.netd0384202005-08-13 18:44:58 -0700442 u16 tt_usecs; /* tt downstream bandwidth */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700443 unsigned short period; /* polling interval */
444 unsigned short start; /* where polling starts */
445#define NO_FRAME ((unsigned short)~0) /* pick new start */
446 struct usb_device *dev; /* access to TT */
Stuart_Hayes@Dell.com196705c2007-05-03 08:58:49 -0700447#ifdef CONFIG_CPU_FREQ
448 struct list_head split_intr_qhs; /* list of split qhs */
449 __le32 was_active; /* active bit before "i" set */
450#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700451} __attribute__ ((aligned (32)));
452
453/*-------------------------------------------------------------------------*/
454
455/* description of one iso transaction (up to 3 KB data if highspeed) */
456struct ehci_iso_packet {
457 /* These will be copied to iTD when scheduling */
458 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
459 __le32 transaction; /* itd->hw_transaction[i] |= */
460 u8 cross; /* buf crosses pages */
461 /* for full speed OUT splits */
462 u32 buf1;
463};
464
465/* temporary schedule data for packets from iso urbs (both speeds)
466 * each packet is one logical usb transaction to the device (not TT),
467 * beginning at stream->next_uframe
468 */
469struct ehci_iso_sched {
470 struct list_head td_list;
471 unsigned span;
472 struct ehci_iso_packet packet [0];
473};
474
475/*
476 * ehci_iso_stream - groups all (s)itds for this endpoint.
477 * acts like a qh would, if EHCI had them for ISO.
478 */
479struct ehci_iso_stream {
480 /* first two fields match QH, but info1 == 0 */
481 __le32 hw_next;
482 __le32 hw_info1;
483
484 u32 refcount;
485 u8 bEndpointAddress;
486 u8 highspeed;
487 u16 depth; /* depth in uframes */
488 struct list_head td_list; /* queued itds/sitds */
489 struct list_head free_list; /* list of unused itds/sitds */
490 struct usb_device *udev;
David Brownell53bd6a62006-08-30 14:50:06 -0700491 struct usb_host_endpoint *ep;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700492
493 /* output of (re)scheduling */
494 unsigned long start; /* jiffies */
495 unsigned long rescheduled;
496 int next_uframe;
497 __le32 splits;
498
499 /* the rest is derived from the endpoint descriptor,
500 * trusting urb->interval == f(epdesc->bInterval) and
501 * including the extra info for hw_bufp[0..2]
502 */
503 u8 interval;
504 u8 usecs, c_usecs;
david-b@pacbell.netd0384202005-08-13 18:44:58 -0700505 u16 tt_usecs;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700506 u16 maxp;
507 u16 raw_mask;
508 unsigned bandwidth;
509
510 /* This is used to initialize iTD's hw_bufp fields */
David Brownell53bd6a62006-08-30 14:50:06 -0700511 __le32 buf0;
512 __le32 buf1;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700513 __le32 buf2;
514
515 /* this is used to initialize sITD's tt info */
516 __le32 address;
517};
518
519/*-------------------------------------------------------------------------*/
520
521/*
522 * EHCI Specification 0.95 Section 3.3
523 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
524 *
525 * Schedule records for high speed iso xfers
526 */
527struct ehci_itd {
528 /* first part defined by EHCI spec */
529 __le32 hw_next; /* see EHCI 3.3.1 */
530 __le32 hw_transaction [8]; /* see EHCI 3.3.2 */
531#define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
532#define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
533#define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
534#define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
535#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
536#define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
537
538#define ITD_ACTIVE __constant_cpu_to_le32(EHCI_ISOC_ACTIVE)
539
David Brownell53bd6a62006-08-30 14:50:06 -0700540 __le32 hw_bufp [7]; /* see EHCI 3.3.3 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700541 __le32 hw_bufp_hi [7]; /* Appendix B */
542
543 /* the rest is HCD-private */
544 dma_addr_t itd_dma; /* for this itd */
545 union ehci_shadow itd_next; /* ptr to periodic q entry */
546
547 struct urb *urb;
548 struct ehci_iso_stream *stream; /* endpoint's queue */
549 struct list_head itd_list; /* list of stream's itds */
550
551 /* any/all hw_transactions here may be used by that urb */
552 unsigned frame; /* where scheduled */
553 unsigned pg;
554 unsigned index[8]; /* in urb->iso_frame_desc */
555 u8 usecs[8];
556} __attribute__ ((aligned (32)));
557
558/*-------------------------------------------------------------------------*/
559
560/*
David Brownell53bd6a62006-08-30 14:50:06 -0700561 * EHCI Specification 0.95 Section 3.4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700562 * siTD, aka split-transaction isochronous Transfer Descriptor
563 * ... describe full speed iso xfers through TT in hubs
564 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
565 */
566struct ehci_sitd {
567 /* first part defined by EHCI spec */
568 __le32 hw_next;
569/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
570 __le32 hw_fullspeed_ep; /* EHCI table 3-9 */
571 __le32 hw_uframe; /* EHCI table 3-10 */
572 __le32 hw_results; /* EHCI table 3-11 */
573#define SITD_IOC (1 << 31) /* interrupt on completion */
574#define SITD_PAGE (1 << 30) /* buffer 0/1 */
575#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
576#define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
577#define SITD_STS_ERR (1 << 6) /* error from TT */
578#define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
579#define SITD_STS_BABBLE (1 << 4) /* device was babbling */
580#define SITD_STS_XACT (1 << 3) /* illegal IN response */
581#define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
582#define SITD_STS_STS (1 << 1) /* split transaction state */
583
584#define SITD_ACTIVE __constant_cpu_to_le32(SITD_STS_ACTIVE)
585
586 __le32 hw_buf [2]; /* EHCI table 3-12 */
587 __le32 hw_backpointer; /* EHCI table 3-13 */
588 __le32 hw_buf_hi [2]; /* Appendix B */
589
590 /* the rest is HCD-private */
591 dma_addr_t sitd_dma;
592 union ehci_shadow sitd_next; /* ptr to periodic q entry */
593
594 struct urb *urb;
595 struct ehci_iso_stream *stream; /* endpoint's queue */
596 struct list_head sitd_list; /* list of stream's sitds */
597 unsigned frame;
598 unsigned index;
599} __attribute__ ((aligned (32)));
600
601/*-------------------------------------------------------------------------*/
602
603/*
604 * EHCI Specification 0.96 Section 3.7
605 * Periodic Frame Span Traversal Node (FSTN)
606 *
607 * Manages split interrupt transactions (using TT) that span frame boundaries
608 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
609 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
610 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
611 */
612struct ehci_fstn {
613 __le32 hw_next; /* any periodic q entry */
614 __le32 hw_prev; /* qh or EHCI_LIST_END */
615
616 /* the rest is HCD-private */
617 dma_addr_t fstn_dma;
618 union ehci_shadow fstn_next; /* ptr to periodic q entry */
619} __attribute__ ((aligned (32)));
620
621/*-------------------------------------------------------------------------*/
622
623#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
624
625/*
626 * Some EHCI controllers have a Transaction Translator built into the
627 * root hub. This is a non-standard feature. Each controller will need
628 * to add code to the following inline functions, and call them as
629 * needed (mostly in root hub code).
630 */
631
632#define ehci_is_TDI(e) ((e)->is_tdi_rh_tt)
633
634/* Returns the speed of a device attached to a port on the root hub. */
635static inline unsigned int
636ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
637{
638 if (ehci_is_TDI(ehci)) {
639 switch ((portsc>>26)&3) {
640 case 0:
641 return 0;
642 case 1:
643 return (1<<USB_PORT_FEAT_LOWSPEED);
644 case 2:
645 default:
646 return (1<<USB_PORT_FEAT_HIGHSPEED);
647 }
648 }
649 return (1<<USB_PORT_FEAT_HIGHSPEED);
650}
651
652#else
653
654#define ehci_is_TDI(e) (0)
655
656#define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
657#endif
658
659/*-------------------------------------------------------------------------*/
660
Kumar Gala8cd42e92006-01-20 13:57:52 -0800661#ifdef CONFIG_PPC_83xx
662/* Some Freescale processors have an erratum in which the TT
663 * port number in the queue head was 0..N-1 instead of 1..N.
664 */
665#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
666#else
667#define ehci_has_fsl_portno_bug(e) (0)
668#endif
669
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100670/*
671 * While most USB host controllers implement their registers in
672 * little-endian format, a minority (celleb companion chip) implement
673 * them in big endian format.
674 *
675 * This attempts to support either format at compile time without a
676 * runtime penalty, or both formats with the additional overhead
677 * of checking a flag bit.
678 */
679
680#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
681#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
682#else
683#define ehci_big_endian_mmio(e) 0
684#endif
685
686static inline unsigned int ehci_readl (const struct ehci_hcd *ehci,
687 __u32 __iomem * regs)
688{
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100689#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100690 return ehci_big_endian_mmio(ehci) ?
Al Viro68f50e52007-02-09 16:40:00 +0000691 readl_be(regs) :
692 readl(regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100693#else
Al Viro68f50e52007-02-09 16:40:00 +0000694 return readl(regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100695#endif
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100696}
697
698static inline void ehci_writel (const struct ehci_hcd *ehci,
699 const unsigned int val, __u32 __iomem *regs)
700{
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100701#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100702 ehci_big_endian_mmio(ehci) ?
Al Viro68f50e52007-02-09 16:40:00 +0000703 writel_be(val, regs) :
704 writel(val, regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100705#else
Al Viro68f50e52007-02-09 16:40:00 +0000706 writel(val, regs);
Benjamin Herrenschmidtd728e322006-12-28 15:27:27 +1100707#endif
Benjamin Herrenschmidt083522d2006-12-15 06:54:08 +1100708}
Kumar Gala8cd42e92006-01-20 13:57:52 -0800709
710/*-------------------------------------------------------------------------*/
711
Linus Torvalds1da177e2005-04-16 15:20:36 -0700712#ifndef DEBUG
713#define STUB_DEBUG_FILES
714#endif /* DEBUG */
715
716/*-------------------------------------------------------------------------*/
717
718#endif /* __LINUX_EHCI_HCD_H */