Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1 | /* |
| 2 | * OMAP DMAengine support |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | */ |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 8 | #include <linux/delay.h> |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 9 | #include <linux/dmaengine.h> |
| 10 | #include <linux/dma-mapping.h> |
| 11 | #include <linux/err.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/interrupt.h> |
| 14 | #include <linux/list.h> |
| 15 | #include <linux/module.h> |
| 16 | #include <linux/omap-dma.h> |
| 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/slab.h> |
| 19 | #include <linux/spinlock.h> |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 20 | #include <linux/of_dma.h> |
| 21 | #include <linux/of_device.h> |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 22 | |
| 23 | #include "virt-dma.h" |
Tony Lindgren | 7d7e1eb | 2012-08-27 17:43:01 -0700 | [diff] [blame] | 24 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 25 | struct omap_dmadev { |
| 26 | struct dma_device ddev; |
| 27 | spinlock_t lock; |
| 28 | struct tasklet_struct task; |
| 29 | struct list_head pending; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 30 | void __iomem *base; |
| 31 | const struct omap_dma_reg *reg_map; |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 32 | struct omap_system_dma_plat_info *plat; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 33 | bool legacy; |
| 34 | spinlock_t irq_lock; |
| 35 | uint32_t irq_enable_mask; |
| 36 | struct omap_chan *lch_map[32]; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 37 | }; |
| 38 | |
| 39 | struct omap_chan { |
| 40 | struct virt_dma_chan vc; |
| 41 | struct list_head node; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 42 | void __iomem *channel_base; |
| 43 | const struct omap_dma_reg *reg_map; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 44 | |
| 45 | struct dma_slave_config cfg; |
| 46 | unsigned dma_sig; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 47 | bool cyclic; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 48 | bool paused; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 49 | |
| 50 | int dma_ch; |
| 51 | struct omap_desc *desc; |
| 52 | unsigned sgidx; |
| 53 | }; |
| 54 | |
| 55 | struct omap_sg { |
| 56 | dma_addr_t addr; |
| 57 | uint32_t en; /* number of elements (24-bit) */ |
| 58 | uint32_t fn; /* number of frames (16-bit) */ |
| 59 | }; |
| 60 | |
| 61 | struct omap_desc { |
| 62 | struct virt_dma_desc vd; |
| 63 | enum dma_transfer_direction dir; |
| 64 | dma_addr_t dev_addr; |
| 65 | |
Russell King | 7c836bc | 2012-06-18 16:45:19 +0100 | [diff] [blame] | 66 | int16_t fi; /* for OMAP_DMA_SYNC_PACKET */ |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 67 | uint8_t es; /* CSDP_DATA_TYPE_xxx */ |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 68 | uint32_t ccr; /* CCR value */ |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame] | 69 | uint16_t clnk_ctrl; /* CLNK_CTRL value */ |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 70 | uint16_t cicr; /* CICR value */ |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 71 | uint32_t csdp; /* CSDP value */ |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 72 | |
| 73 | unsigned sglen; |
| 74 | struct omap_sg sg[0]; |
| 75 | }; |
| 76 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 77 | enum { |
| 78 | CCR_FS = BIT(5), |
| 79 | CCR_READ_PRIORITY = BIT(6), |
| 80 | CCR_ENABLE = BIT(7), |
| 81 | CCR_AUTO_INIT = BIT(8), /* OMAP1 only */ |
| 82 | CCR_REPEAT = BIT(9), /* OMAP1 only */ |
| 83 | CCR_OMAP31_DISABLE = BIT(10), /* OMAP1 only */ |
| 84 | CCR_SUSPEND_SENSITIVE = BIT(8), /* OMAP2+ only */ |
| 85 | CCR_RD_ACTIVE = BIT(9), /* OMAP2+ only */ |
| 86 | CCR_WR_ACTIVE = BIT(10), /* OMAP2+ only */ |
| 87 | CCR_SRC_AMODE_CONSTANT = 0 << 12, |
| 88 | CCR_SRC_AMODE_POSTINC = 1 << 12, |
| 89 | CCR_SRC_AMODE_SGLIDX = 2 << 12, |
| 90 | CCR_SRC_AMODE_DBLIDX = 3 << 12, |
| 91 | CCR_DST_AMODE_CONSTANT = 0 << 14, |
| 92 | CCR_DST_AMODE_POSTINC = 1 << 14, |
| 93 | CCR_DST_AMODE_SGLIDX = 2 << 14, |
| 94 | CCR_DST_AMODE_DBLIDX = 3 << 14, |
| 95 | CCR_CONSTANT_FILL = BIT(16), |
| 96 | CCR_TRANSPARENT_COPY = BIT(17), |
| 97 | CCR_BS = BIT(18), |
| 98 | CCR_SUPERVISOR = BIT(22), |
| 99 | CCR_PREFETCH = BIT(23), |
| 100 | CCR_TRIGGER_SRC = BIT(24), |
| 101 | CCR_BUFFERING_DISABLE = BIT(25), |
| 102 | CCR_WRITE_PRIORITY = BIT(26), |
| 103 | CCR_SYNC_ELEMENT = 0, |
| 104 | CCR_SYNC_FRAME = CCR_FS, |
| 105 | CCR_SYNC_BLOCK = CCR_BS, |
| 106 | CCR_SYNC_PACKET = CCR_BS | CCR_FS, |
| 107 | |
| 108 | CSDP_DATA_TYPE_8 = 0, |
| 109 | CSDP_DATA_TYPE_16 = 1, |
| 110 | CSDP_DATA_TYPE_32 = 2, |
| 111 | CSDP_SRC_PORT_EMIFF = 0 << 2, /* OMAP1 only */ |
| 112 | CSDP_SRC_PORT_EMIFS = 1 << 2, /* OMAP1 only */ |
| 113 | CSDP_SRC_PORT_OCP_T1 = 2 << 2, /* OMAP1 only */ |
| 114 | CSDP_SRC_PORT_TIPB = 3 << 2, /* OMAP1 only */ |
| 115 | CSDP_SRC_PORT_OCP_T2 = 4 << 2, /* OMAP1 only */ |
| 116 | CSDP_SRC_PORT_MPUI = 5 << 2, /* OMAP1 only */ |
| 117 | CSDP_SRC_PACKED = BIT(6), |
| 118 | CSDP_SRC_BURST_1 = 0 << 7, |
| 119 | CSDP_SRC_BURST_16 = 1 << 7, |
| 120 | CSDP_SRC_BURST_32 = 2 << 7, |
| 121 | CSDP_SRC_BURST_64 = 3 << 7, |
| 122 | CSDP_DST_PORT_EMIFF = 0 << 9, /* OMAP1 only */ |
| 123 | CSDP_DST_PORT_EMIFS = 1 << 9, /* OMAP1 only */ |
| 124 | CSDP_DST_PORT_OCP_T1 = 2 << 9, /* OMAP1 only */ |
| 125 | CSDP_DST_PORT_TIPB = 3 << 9, /* OMAP1 only */ |
| 126 | CSDP_DST_PORT_OCP_T2 = 4 << 9, /* OMAP1 only */ |
| 127 | CSDP_DST_PORT_MPUI = 5 << 9, /* OMAP1 only */ |
| 128 | CSDP_DST_PACKED = BIT(13), |
| 129 | CSDP_DST_BURST_1 = 0 << 14, |
| 130 | CSDP_DST_BURST_16 = 1 << 14, |
| 131 | CSDP_DST_BURST_32 = 2 << 14, |
| 132 | CSDP_DST_BURST_64 = 3 << 14, |
| 133 | |
| 134 | CICR_TOUT_IE = BIT(0), /* OMAP1 only */ |
| 135 | CICR_DROP_IE = BIT(1), |
| 136 | CICR_HALF_IE = BIT(2), |
| 137 | CICR_FRAME_IE = BIT(3), |
| 138 | CICR_LAST_IE = BIT(4), |
| 139 | CICR_BLOCK_IE = BIT(5), |
| 140 | CICR_PKT_IE = BIT(7), /* OMAP2+ only */ |
| 141 | CICR_TRANS_ERR_IE = BIT(8), /* OMAP2+ only */ |
| 142 | CICR_SUPERVISOR_ERR_IE = BIT(10), /* OMAP2+ only */ |
| 143 | CICR_MISALIGNED_ERR_IE = BIT(11), /* OMAP2+ only */ |
| 144 | CICR_DRAIN_IE = BIT(12), /* OMAP2+ only */ |
| 145 | CICR_SUPER_BLOCK_IE = BIT(14), /* OMAP2+ only */ |
| 146 | |
| 147 | CLNK_CTRL_ENABLE_LNK = BIT(15), |
| 148 | }; |
| 149 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 150 | static const unsigned es_bytes[] = { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 151 | [CSDP_DATA_TYPE_8] = 1, |
| 152 | [CSDP_DATA_TYPE_16] = 2, |
| 153 | [CSDP_DATA_TYPE_32] = 4, |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 154 | }; |
| 155 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 156 | static struct of_dma_filter_info omap_dma_info = { |
| 157 | .filter_fn = omap_dma_filter_fn, |
| 158 | }; |
| 159 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 160 | static inline struct omap_dmadev *to_omap_dma_dev(struct dma_device *d) |
| 161 | { |
| 162 | return container_of(d, struct omap_dmadev, ddev); |
| 163 | } |
| 164 | |
| 165 | static inline struct omap_chan *to_omap_dma_chan(struct dma_chan *c) |
| 166 | { |
| 167 | return container_of(c, struct omap_chan, vc.chan); |
| 168 | } |
| 169 | |
| 170 | static inline struct omap_desc *to_omap_dma_desc(struct dma_async_tx_descriptor *t) |
| 171 | { |
| 172 | return container_of(t, struct omap_desc, vd.tx); |
| 173 | } |
| 174 | |
| 175 | static void omap_dma_desc_free(struct virt_dma_desc *vd) |
| 176 | { |
| 177 | kfree(container_of(vd, struct omap_desc, vd)); |
| 178 | } |
| 179 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 180 | static void omap_dma_write(uint32_t val, unsigned type, void __iomem *addr) |
| 181 | { |
| 182 | switch (type) { |
| 183 | case OMAP_DMA_REG_16BIT: |
| 184 | writew_relaxed(val, addr); |
| 185 | break; |
| 186 | case OMAP_DMA_REG_2X16BIT: |
| 187 | writew_relaxed(val, addr); |
| 188 | writew_relaxed(val >> 16, addr + 2); |
| 189 | break; |
| 190 | case OMAP_DMA_REG_32BIT: |
| 191 | writel_relaxed(val, addr); |
| 192 | break; |
| 193 | default: |
| 194 | WARN_ON(1); |
| 195 | } |
| 196 | } |
| 197 | |
| 198 | static unsigned omap_dma_read(unsigned type, void __iomem *addr) |
| 199 | { |
| 200 | unsigned val; |
| 201 | |
| 202 | switch (type) { |
| 203 | case OMAP_DMA_REG_16BIT: |
| 204 | val = readw_relaxed(addr); |
| 205 | break; |
| 206 | case OMAP_DMA_REG_2X16BIT: |
| 207 | val = readw_relaxed(addr); |
| 208 | val |= readw_relaxed(addr + 2) << 16; |
| 209 | break; |
| 210 | case OMAP_DMA_REG_32BIT: |
| 211 | val = readl_relaxed(addr); |
| 212 | break; |
| 213 | default: |
| 214 | WARN_ON(1); |
| 215 | val = 0; |
| 216 | } |
| 217 | |
| 218 | return val; |
| 219 | } |
| 220 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 221 | static void omap_dma_glbl_write(struct omap_dmadev *od, unsigned reg, unsigned val) |
| 222 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 223 | const struct omap_dma_reg *r = od->reg_map + reg; |
| 224 | |
| 225 | WARN_ON(r->stride); |
| 226 | |
| 227 | omap_dma_write(val, r->type, od->base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 228 | } |
| 229 | |
| 230 | static unsigned omap_dma_glbl_read(struct omap_dmadev *od, unsigned reg) |
| 231 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 232 | const struct omap_dma_reg *r = od->reg_map + reg; |
| 233 | |
| 234 | WARN_ON(r->stride); |
| 235 | |
| 236 | return omap_dma_read(r->type, od->base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | static void omap_dma_chan_write(struct omap_chan *c, unsigned reg, unsigned val) |
| 240 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 241 | const struct omap_dma_reg *r = c->reg_map + reg; |
| 242 | |
| 243 | omap_dma_write(val, r->type, c->channel_base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 244 | } |
| 245 | |
| 246 | static unsigned omap_dma_chan_read(struct omap_chan *c, unsigned reg) |
| 247 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 248 | const struct omap_dma_reg *r = c->reg_map + reg; |
| 249 | |
| 250 | return omap_dma_read(r->type, c->channel_base + r->offset); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 251 | } |
| 252 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 253 | static void omap_dma_clear_csr(struct omap_chan *c) |
| 254 | { |
| 255 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 256 | omap_dma_chan_read(c, CSR); |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 257 | else |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 258 | omap_dma_chan_write(c, CSR, ~0); |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 259 | } |
| 260 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 261 | static unsigned omap_dma_get_csr(struct omap_chan *c) |
| 262 | { |
| 263 | unsigned val = omap_dma_chan_read(c, CSR); |
| 264 | |
| 265 | if (!dma_omap1()) |
| 266 | omap_dma_chan_write(c, CSR, val); |
| 267 | |
| 268 | return val; |
| 269 | } |
| 270 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 271 | static void omap_dma_assign(struct omap_dmadev *od, struct omap_chan *c, |
| 272 | unsigned lch) |
| 273 | { |
| 274 | c->channel_base = od->base + od->plat->channel_stride * lch; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 275 | |
| 276 | od->lch_map[lch] = c; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 277 | } |
| 278 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 279 | static void omap_dma_start(struct omap_chan *c, struct omap_desc *d) |
| 280 | { |
| 281 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 282 | |
| 283 | if (__dma_omap15xx(od->plat->dma_attr)) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 284 | omap_dma_chan_write(c, CPC, 0); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 285 | else |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 286 | omap_dma_chan_write(c, CDAC, 0); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 287 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 288 | omap_dma_clear_csr(c); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 289 | |
| 290 | /* Enable interrupts */ |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 291 | omap_dma_chan_write(c, CICR, d->cicr); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 292 | |
Russell King | 45da7b0 | 2013-11-06 17:18:42 +0000 | [diff] [blame] | 293 | /* Enable channel */ |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 294 | omap_dma_chan_write(c, CCR, d->ccr | CCR_ENABLE); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 295 | } |
| 296 | |
| 297 | static void omap_dma_stop(struct omap_chan *c) |
| 298 | { |
| 299 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 300 | uint32_t val; |
| 301 | |
| 302 | /* disable irq */ |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 303 | omap_dma_chan_write(c, CICR, 0); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 304 | |
Russell King | 470b23f | 2013-11-02 21:23:06 +0000 | [diff] [blame] | 305 | omap_dma_clear_csr(c); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 306 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 307 | val = omap_dma_chan_read(c, CCR); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 308 | if (od->plat->errata & DMA_ERRATA_i541 && val & CCR_TRIGGER_SRC) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 309 | uint32_t sysconfig; |
| 310 | unsigned i; |
| 311 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 312 | sysconfig = omap_dma_glbl_read(od, OCP_SYSCONFIG); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 313 | val = sysconfig & ~DMA_SYSCONFIG_MIDLEMODE_MASK; |
| 314 | val |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE); |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 315 | omap_dma_glbl_write(od, OCP_SYSCONFIG, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 316 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 317 | val = omap_dma_chan_read(c, CCR); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 318 | val &= ~CCR_ENABLE; |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 319 | omap_dma_chan_write(c, CCR, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 320 | |
| 321 | /* Wait for sDMA FIFO to drain */ |
| 322 | for (i = 0; ; i++) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 323 | val = omap_dma_chan_read(c, CCR); |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 324 | if (!(val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE))) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 325 | break; |
| 326 | |
| 327 | if (i > 100) |
| 328 | break; |
| 329 | |
| 330 | udelay(5); |
| 331 | } |
| 332 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 333 | if (val & (CCR_RD_ACTIVE | CCR_WR_ACTIVE)) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 334 | dev_err(c->vc.chan.device->dev, |
| 335 | "DMA drain did not complete on lch %d\n", |
| 336 | c->dma_ch); |
| 337 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 338 | omap_dma_glbl_write(od, OCP_SYSCONFIG, sysconfig); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 339 | } else { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 340 | val &= ~CCR_ENABLE; |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 341 | omap_dma_chan_write(c, CCR, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | mb(); |
| 345 | |
| 346 | if (!__dma_omap15xx(od->plat->dma_attr) && c->cyclic) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 347 | val = omap_dma_chan_read(c, CLNK_CTRL); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 348 | |
| 349 | if (dma_omap1()) |
| 350 | val |= 1 << 14; /* set the STOP_LNK bit */ |
| 351 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 352 | val &= ~CLNK_CTRL_ENABLE_LNK; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 353 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 354 | omap_dma_chan_write(c, CLNK_CTRL, val); |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 355 | } |
| 356 | } |
| 357 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 358 | static void omap_dma_start_sg(struct omap_chan *c, struct omap_desc *d, |
| 359 | unsigned idx) |
| 360 | { |
| 361 | struct omap_sg *sg = d->sg + idx; |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 362 | unsigned cxsa, cxei, cxfi; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 363 | |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 364 | if (d->dir == DMA_DEV_TO_MEM) { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 365 | cxsa = CDSA; |
| 366 | cxei = CDEI; |
| 367 | cxfi = CDFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 368 | } else { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 369 | cxsa = CSSA; |
| 370 | cxei = CSEI; |
| 371 | cxfi = CSFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 372 | } |
| 373 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 374 | omap_dma_chan_write(c, cxsa, sg->addr); |
| 375 | omap_dma_chan_write(c, cxei, 0); |
| 376 | omap_dma_chan_write(c, cxfi, 0); |
| 377 | omap_dma_chan_write(c, CEN, sg->en); |
| 378 | omap_dma_chan_write(c, CFN, sg->fn); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 379 | |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 380 | omap_dma_start(c, d); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 381 | } |
| 382 | |
| 383 | static void omap_dma_start_desc(struct omap_chan *c) |
| 384 | { |
| 385 | struct virt_dma_desc *vd = vchan_next_desc(&c->vc); |
| 386 | struct omap_desc *d; |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 387 | unsigned cxsa, cxei, cxfi; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 388 | |
| 389 | if (!vd) { |
| 390 | c->desc = NULL; |
| 391 | return; |
| 392 | } |
| 393 | |
| 394 | list_del(&vd->node); |
| 395 | |
| 396 | c->desc = d = to_omap_dma_desc(&vd->tx); |
| 397 | c->sgidx = 0; |
| 398 | |
Russell King | 5987190 | 2013-11-06 17:15:16 +0000 | [diff] [blame] | 399 | /* |
| 400 | * This provides the necessary barrier to ensure data held in |
| 401 | * DMA coherent memory is visible to the DMA engine prior to |
| 402 | * the transfer starting. |
| 403 | */ |
| 404 | mb(); |
| 405 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 406 | omap_dma_chan_write(c, CCR, d->ccr); |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 407 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 408 | omap_dma_chan_write(c, CCR2, d->ccr >> 16); |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 409 | |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 410 | if (d->dir == DMA_DEV_TO_MEM) { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 411 | cxsa = CSSA; |
| 412 | cxei = CSEI; |
| 413 | cxfi = CSFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 414 | } else { |
Russell King | 893e63e | 2013-11-03 11:17:11 +0000 | [diff] [blame] | 415 | cxsa = CDSA; |
| 416 | cxei = CDEI; |
| 417 | cxfi = CDFI; |
Russell King | b9e9782 | 2013-11-02 13:26:57 +0000 | [diff] [blame] | 418 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 419 | |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 420 | omap_dma_chan_write(c, cxsa, d->dev_addr); |
| 421 | omap_dma_chan_write(c, cxei, 0); |
| 422 | omap_dma_chan_write(c, cxfi, d->fi); |
| 423 | omap_dma_chan_write(c, CSDP, d->csdp); |
| 424 | omap_dma_chan_write(c, CLNK_CTRL, d->clnk_ctrl); |
Russell King | 913a2d0 | 2013-11-02 14:41:42 +0000 | [diff] [blame] | 425 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 426 | omap_dma_start_sg(c, d, 0); |
| 427 | } |
| 428 | |
| 429 | static void omap_dma_callback(int ch, u16 status, void *data) |
| 430 | { |
| 431 | struct omap_chan *c = data; |
| 432 | struct omap_desc *d; |
| 433 | unsigned long flags; |
| 434 | |
| 435 | spin_lock_irqsave(&c->vc.lock, flags); |
| 436 | d = c->desc; |
| 437 | if (d) { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 438 | if (!c->cyclic) { |
| 439 | if (++c->sgidx < d->sglen) { |
| 440 | omap_dma_start_sg(c, d, c->sgidx); |
| 441 | } else { |
| 442 | omap_dma_start_desc(c); |
| 443 | vchan_cookie_complete(&d->vd); |
| 444 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 445 | } else { |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 446 | vchan_cyclic_callback(&d->vd); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 447 | } |
| 448 | } |
| 449 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 450 | } |
| 451 | |
| 452 | /* |
| 453 | * This callback schedules all pending channels. We could be more |
| 454 | * clever here by postponing allocation of the real DMA channels to |
| 455 | * this point, and freeing them when our virtual channel becomes idle. |
| 456 | * |
| 457 | * We would then need to deal with 'all channels in-use' |
| 458 | */ |
| 459 | static void omap_dma_sched(unsigned long data) |
| 460 | { |
| 461 | struct omap_dmadev *d = (struct omap_dmadev *)data; |
| 462 | LIST_HEAD(head); |
| 463 | |
| 464 | spin_lock_irq(&d->lock); |
| 465 | list_splice_tail_init(&d->pending, &head); |
| 466 | spin_unlock_irq(&d->lock); |
| 467 | |
| 468 | while (!list_empty(&head)) { |
| 469 | struct omap_chan *c = list_first_entry(&head, |
| 470 | struct omap_chan, node); |
| 471 | |
| 472 | spin_lock_irq(&c->vc.lock); |
| 473 | list_del_init(&c->node); |
| 474 | omap_dma_start_desc(c); |
| 475 | spin_unlock_irq(&c->vc.lock); |
| 476 | } |
| 477 | } |
| 478 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 479 | static irqreturn_t omap_dma_irq(int irq, void *devid) |
| 480 | { |
| 481 | struct omap_dmadev *od = devid; |
| 482 | unsigned status, channel; |
| 483 | |
| 484 | spin_lock(&od->irq_lock); |
| 485 | |
| 486 | status = omap_dma_glbl_read(od, IRQSTATUS_L1); |
| 487 | status &= od->irq_enable_mask; |
| 488 | if (status == 0) { |
| 489 | spin_unlock(&od->irq_lock); |
| 490 | return IRQ_NONE; |
| 491 | } |
| 492 | |
| 493 | while ((channel = ffs(status)) != 0) { |
| 494 | unsigned mask, csr; |
| 495 | struct omap_chan *c; |
| 496 | |
| 497 | channel -= 1; |
| 498 | mask = BIT(channel); |
| 499 | status &= ~mask; |
| 500 | |
| 501 | c = od->lch_map[channel]; |
| 502 | if (c == NULL) { |
| 503 | /* This should never happen */ |
| 504 | dev_err(od->ddev.dev, "invalid channel %u\n", channel); |
| 505 | continue; |
| 506 | } |
| 507 | |
| 508 | csr = omap_dma_get_csr(c); |
| 509 | omap_dma_glbl_write(od, IRQSTATUS_L1, mask); |
| 510 | |
| 511 | omap_dma_callback(channel, csr, c); |
| 512 | } |
| 513 | |
| 514 | spin_unlock(&od->irq_lock); |
| 515 | |
| 516 | return IRQ_HANDLED; |
| 517 | } |
| 518 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 519 | static int omap_dma_alloc_chan_resources(struct dma_chan *chan) |
| 520 | { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 521 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 522 | struct omap_chan *c = to_omap_dma_chan(chan); |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 523 | int ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 524 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 525 | if (od->legacy) { |
| 526 | ret = omap_request_dma(c->dma_sig, "DMA engine", |
| 527 | omap_dma_callback, c, &c->dma_ch); |
| 528 | } else { |
| 529 | ret = omap_request_dma(c->dma_sig, "DMA engine", NULL, NULL, |
| 530 | &c->dma_ch); |
| 531 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 532 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 533 | dev_dbg(od->ddev.dev, "allocating channel %u for %u\n", |
| 534 | c->dma_ch, c->dma_sig); |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 535 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 536 | if (ret >= 0) { |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 537 | omap_dma_assign(od, c, c->dma_ch); |
| 538 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 539 | if (!od->legacy) { |
| 540 | unsigned val; |
| 541 | |
| 542 | spin_lock_irq(&od->irq_lock); |
| 543 | val = BIT(c->dma_ch); |
| 544 | omap_dma_glbl_write(od, IRQSTATUS_L1, val); |
| 545 | od->irq_enable_mask |= val; |
| 546 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); |
| 547 | |
| 548 | val = omap_dma_glbl_read(od, IRQENABLE_L0); |
| 549 | val &= ~BIT(c->dma_ch); |
| 550 | omap_dma_glbl_write(od, IRQENABLE_L0, val); |
| 551 | spin_unlock_irq(&od->irq_lock); |
| 552 | } |
| 553 | } |
| 554 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 555 | return ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 556 | } |
| 557 | |
| 558 | static void omap_dma_free_chan_resources(struct dma_chan *chan) |
| 559 | { |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 560 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 561 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 562 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 563 | if (!od->legacy) { |
| 564 | spin_lock_irq(&od->irq_lock); |
| 565 | od->irq_enable_mask &= ~BIT(c->dma_ch); |
| 566 | omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); |
| 567 | spin_unlock_irq(&od->irq_lock); |
| 568 | } |
| 569 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 570 | c->channel_base = NULL; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 571 | od->lch_map[c->dma_ch] = NULL; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 572 | vchan_free_chan_resources(&c->vc); |
| 573 | omap_free_dma(c->dma_ch); |
| 574 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 575 | dev_dbg(od->ddev.dev, "freeing channel for %u\n", c->dma_sig); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 576 | } |
| 577 | |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 578 | static size_t omap_dma_sg_size(struct omap_sg *sg) |
| 579 | { |
| 580 | return sg->en * sg->fn; |
| 581 | } |
| 582 | |
| 583 | static size_t omap_dma_desc_size(struct omap_desc *d) |
| 584 | { |
| 585 | unsigned i; |
| 586 | size_t size; |
| 587 | |
| 588 | for (size = i = 0; i < d->sglen; i++) |
| 589 | size += omap_dma_sg_size(&d->sg[i]); |
| 590 | |
| 591 | return size * es_bytes[d->es]; |
| 592 | } |
| 593 | |
| 594 | static size_t omap_dma_desc_size_pos(struct omap_desc *d, dma_addr_t addr) |
| 595 | { |
| 596 | unsigned i; |
| 597 | size_t size, es_size = es_bytes[d->es]; |
| 598 | |
| 599 | for (size = i = 0; i < d->sglen; i++) { |
| 600 | size_t this_size = omap_dma_sg_size(&d->sg[i]) * es_size; |
| 601 | |
| 602 | if (size) |
| 603 | size += this_size; |
| 604 | else if (addr >= d->sg[i].addr && |
| 605 | addr < d->sg[i].addr + this_size) |
| 606 | size += d->sg[i].addr + this_size - addr; |
| 607 | } |
| 608 | return size; |
| 609 | } |
| 610 | |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 611 | /* |
| 612 | * OMAP 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is |
| 613 | * read before the DMA controller finished disabling the channel. |
| 614 | */ |
| 615 | static uint32_t omap_dma_chan_read_3_3(struct omap_chan *c, unsigned reg) |
| 616 | { |
| 617 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 618 | uint32_t val; |
| 619 | |
| 620 | val = omap_dma_chan_read(c, reg); |
| 621 | if (val == 0 && od->plat->errata & DMA_ERRATA_3_3) |
| 622 | val = omap_dma_chan_read(c, reg); |
| 623 | |
| 624 | return val; |
| 625 | } |
| 626 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 627 | static dma_addr_t omap_dma_get_src_pos(struct omap_chan *c) |
| 628 | { |
| 629 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 630 | dma_addr_t addr, cdac; |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 631 | |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 632 | if (__dma_omap15xx(od->plat->dma_attr)) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 633 | addr = omap_dma_chan_read(c, CPC); |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 634 | } else { |
| 635 | addr = omap_dma_chan_read_3_3(c, CSAC); |
| 636 | cdac = omap_dma_chan_read_3_3(c, CDAC); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 637 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 638 | /* |
| 639 | * CDAC == 0 indicates that the DMA transfer on the channel has |
| 640 | * not been started (no data has been transferred so far). |
| 641 | * Return the programmed source start address in this case. |
| 642 | */ |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 643 | if (cdac == 0) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 644 | addr = omap_dma_chan_read(c, CSSA); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 645 | } |
| 646 | |
| 647 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 648 | addr |= omap_dma_chan_read(c, CSSA) & 0xffff0000; |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 649 | |
| 650 | return addr; |
| 651 | } |
| 652 | |
| 653 | static dma_addr_t omap_dma_get_dst_pos(struct omap_chan *c) |
| 654 | { |
| 655 | struct omap_dmadev *od = to_omap_dma_dev(c->vc.chan.device); |
| 656 | dma_addr_t addr; |
| 657 | |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 658 | if (__dma_omap15xx(od->plat->dma_attr)) { |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 659 | addr = omap_dma_chan_read(c, CPC); |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 660 | } else { |
| 661 | addr = omap_dma_chan_read_3_3(c, CDAC); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 662 | |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 663 | /* |
Russell King | b07fd62 | 2013-11-06 19:26:45 +0000 | [diff] [blame] | 664 | * CDAC == 0 indicates that the DMA transfer on the channel |
| 665 | * has not been started (no data has been transferred so |
| 666 | * far). Return the programmed destination start address in |
| 667 | * this case. |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 668 | */ |
| 669 | if (addr == 0) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 670 | addr = omap_dma_chan_read(c, CDSA); |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 671 | } |
| 672 | |
| 673 | if (dma_omap1()) |
Russell King | c5ed98b | 2013-11-06 17:33:09 +0000 | [diff] [blame] | 674 | addr |= omap_dma_chan_read(c, CDSA) & 0xffff0000; |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 675 | |
| 676 | return addr; |
| 677 | } |
| 678 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 679 | static enum dma_status omap_dma_tx_status(struct dma_chan *chan, |
| 680 | dma_cookie_t cookie, struct dma_tx_state *txstate) |
| 681 | { |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 682 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 683 | struct virt_dma_desc *vd; |
| 684 | enum dma_status ret; |
| 685 | unsigned long flags; |
| 686 | |
| 687 | ret = dma_cookie_status(chan, cookie, txstate); |
Vinod Koul | 7cce508 | 2013-10-16 20:51:54 +0530 | [diff] [blame] | 688 | if (ret == DMA_COMPLETE || !txstate) |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 689 | return ret; |
| 690 | |
| 691 | spin_lock_irqsave(&c->vc.lock, flags); |
| 692 | vd = vchan_find_desc(&c->vc, cookie); |
| 693 | if (vd) { |
| 694 | txstate->residue = omap_dma_desc_size(to_omap_dma_desc(&vd->tx)); |
| 695 | } else if (c->desc && c->desc->vd.tx.cookie == cookie) { |
| 696 | struct omap_desc *d = c->desc; |
| 697 | dma_addr_t pos; |
| 698 | |
| 699 | if (d->dir == DMA_MEM_TO_DEV) |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 700 | pos = omap_dma_get_src_pos(c); |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 701 | else if (d->dir == DMA_DEV_TO_MEM) |
Russell King | 3997cab | 2013-11-02 18:04:17 +0000 | [diff] [blame] | 702 | pos = omap_dma_get_dst_pos(c); |
Russell King | 3850e22 | 2012-06-21 10:37:35 +0100 | [diff] [blame] | 703 | else |
| 704 | pos = 0; |
| 705 | |
| 706 | txstate->residue = omap_dma_desc_size_pos(d, pos); |
| 707 | } else { |
| 708 | txstate->residue = 0; |
| 709 | } |
| 710 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 711 | |
| 712 | return ret; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 713 | } |
| 714 | |
| 715 | static void omap_dma_issue_pending(struct dma_chan *chan) |
| 716 | { |
| 717 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 718 | unsigned long flags; |
| 719 | |
| 720 | spin_lock_irqsave(&c->vc.lock, flags); |
| 721 | if (vchan_issue_pending(&c->vc) && !c->desc) { |
Peter Ujfalusi | 7650246 | 2013-04-09 16:33:06 +0200 | [diff] [blame] | 722 | /* |
| 723 | * c->cyclic is used only by audio and in this case the DMA need |
| 724 | * to be started without delay. |
| 725 | */ |
| 726 | if (!c->cyclic) { |
| 727 | struct omap_dmadev *d = to_omap_dma_dev(chan->device); |
| 728 | spin_lock(&d->lock); |
| 729 | if (list_empty(&c->node)) |
| 730 | list_add_tail(&c->node, &d->pending); |
| 731 | spin_unlock(&d->lock); |
| 732 | tasklet_schedule(&d->task); |
| 733 | } else { |
| 734 | omap_dma_start_desc(c); |
| 735 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 736 | } |
| 737 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 738 | } |
| 739 | |
| 740 | static struct dma_async_tx_descriptor *omap_dma_prep_slave_sg( |
| 741 | struct dma_chan *chan, struct scatterlist *sgl, unsigned sglen, |
| 742 | enum dma_transfer_direction dir, unsigned long tx_flags, void *context) |
| 743 | { |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 744 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 745 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 746 | enum dma_slave_buswidth dev_width; |
| 747 | struct scatterlist *sgent; |
| 748 | struct omap_desc *d; |
| 749 | dma_addr_t dev_addr; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 750 | unsigned i, j = 0, es, en, frame_bytes; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 751 | u32 burst; |
| 752 | |
| 753 | if (dir == DMA_DEV_TO_MEM) { |
| 754 | dev_addr = c->cfg.src_addr; |
| 755 | dev_width = c->cfg.src_addr_width; |
| 756 | burst = c->cfg.src_maxburst; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 757 | } else if (dir == DMA_MEM_TO_DEV) { |
| 758 | dev_addr = c->cfg.dst_addr; |
| 759 | dev_width = c->cfg.dst_addr_width; |
| 760 | burst = c->cfg.dst_maxburst; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 761 | } else { |
| 762 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 763 | return NULL; |
| 764 | } |
| 765 | |
| 766 | /* Bus width translates to the element size (ES) */ |
| 767 | switch (dev_width) { |
| 768 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 769 | es = CSDP_DATA_TYPE_8; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 770 | break; |
| 771 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 772 | es = CSDP_DATA_TYPE_16; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 773 | break; |
| 774 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 775 | es = CSDP_DATA_TYPE_32; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 776 | break; |
| 777 | default: /* not reached */ |
| 778 | return NULL; |
| 779 | } |
| 780 | |
| 781 | /* Now allocate and setup the descriptor. */ |
| 782 | d = kzalloc(sizeof(*d) + sglen * sizeof(d->sg[0]), GFP_ATOMIC); |
| 783 | if (!d) |
| 784 | return NULL; |
| 785 | |
| 786 | d->dir = dir; |
| 787 | d->dev_addr = dev_addr; |
| 788 | d->es = es; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 789 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 790 | d->ccr = CCR_SYNC_FRAME; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 791 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 792 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 793 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 794 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 795 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 796 | d->cicr = CICR_DROP_IE | CICR_BLOCK_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 797 | d->csdp = es; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 798 | |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 799 | if (dma_omap1()) { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 800 | if (__dma_omap16xx(od->plat->dma_attr)) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 801 | d->ccr |= CCR_OMAP31_DISABLE; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 802 | /* Duplicate what plat-omap/dma.c does */ |
| 803 | d->ccr |= c->dma_ch + 1; |
| 804 | } else { |
| 805 | d->ccr |= c->dma_sig & 0x1f; |
| 806 | } |
| 807 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 808 | d->cicr |= CICR_TOUT_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 809 | |
| 810 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 811 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_TIPB; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 812 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 813 | d->csdp |= CSDP_DST_PORT_TIPB | CSDP_SRC_PORT_EMIFF; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 814 | } else { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 815 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
| 816 | d->ccr |= c->dma_sig & 0x1f; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 817 | |
| 818 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 819 | d->ccr |= CCR_TRIGGER_SRC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 820 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 821 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 822 | } |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 823 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
| 824 | d->ccr |= CCR_BUFFERING_DISABLE; |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame] | 825 | if (od->plat->errata & DMA_ERRATA_PARALLEL_CHANNELS) |
| 826 | d->clnk_ctrl = c->dma_ch; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 827 | |
| 828 | /* |
| 829 | * Build our scatterlist entries: each contains the address, |
| 830 | * the number of elements (EN) in each frame, and the number of |
| 831 | * frames (FN). Number of bytes for this entry = ES * EN * FN. |
| 832 | * |
| 833 | * Burst size translates to number of elements with frame sync. |
| 834 | * Note: DMA engine defines burst to be the number of dev-width |
| 835 | * transfers. |
| 836 | */ |
| 837 | en = burst; |
| 838 | frame_bytes = es_bytes[es] * en; |
| 839 | for_each_sg(sgl, sgent, sglen, i) { |
| 840 | d->sg[j].addr = sg_dma_address(sgent); |
| 841 | d->sg[j].en = en; |
| 842 | d->sg[j].fn = sg_dma_len(sgent) / frame_bytes; |
| 843 | j++; |
| 844 | } |
| 845 | |
| 846 | d->sglen = j; |
| 847 | |
| 848 | return vchan_tx_prep(&c->vc, &d->vd, tx_flags); |
| 849 | } |
| 850 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 851 | static struct dma_async_tx_descriptor *omap_dma_prep_dma_cyclic( |
| 852 | struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, |
Peter Ujfalusi | ec8b5e4 | 2012-09-14 15:05:47 +0300 | [diff] [blame] | 853 | size_t period_len, enum dma_transfer_direction dir, unsigned long flags, |
| 854 | void *context) |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 855 | { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 856 | struct omap_dmadev *od = to_omap_dma_dev(chan->device); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 857 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 858 | enum dma_slave_buswidth dev_width; |
| 859 | struct omap_desc *d; |
| 860 | dma_addr_t dev_addr; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 861 | unsigned es; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 862 | u32 burst; |
| 863 | |
| 864 | if (dir == DMA_DEV_TO_MEM) { |
| 865 | dev_addr = c->cfg.src_addr; |
| 866 | dev_width = c->cfg.src_addr_width; |
| 867 | burst = c->cfg.src_maxburst; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 868 | } else if (dir == DMA_MEM_TO_DEV) { |
| 869 | dev_addr = c->cfg.dst_addr; |
| 870 | dev_width = c->cfg.dst_addr_width; |
| 871 | burst = c->cfg.dst_maxburst; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 872 | } else { |
| 873 | dev_err(chan->device->dev, "%s: bad direction?\n", __func__); |
| 874 | return NULL; |
| 875 | } |
| 876 | |
| 877 | /* Bus width translates to the element size (ES) */ |
| 878 | switch (dev_width) { |
| 879 | case DMA_SLAVE_BUSWIDTH_1_BYTE: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 880 | es = CSDP_DATA_TYPE_8; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 881 | break; |
| 882 | case DMA_SLAVE_BUSWIDTH_2_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 883 | es = CSDP_DATA_TYPE_16; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 884 | break; |
| 885 | case DMA_SLAVE_BUSWIDTH_4_BYTES: |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 886 | es = CSDP_DATA_TYPE_32; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 887 | break; |
| 888 | default: /* not reached */ |
| 889 | return NULL; |
| 890 | } |
| 891 | |
| 892 | /* Now allocate and setup the descriptor. */ |
| 893 | d = kzalloc(sizeof(*d) + sizeof(d->sg[0]), GFP_ATOMIC); |
| 894 | if (!d) |
| 895 | return NULL; |
| 896 | |
| 897 | d->dir = dir; |
| 898 | d->dev_addr = dev_addr; |
| 899 | d->fi = burst; |
| 900 | d->es = es; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 901 | d->sg[0].addr = buf_addr; |
| 902 | d->sg[0].en = period_len / es_bytes[es]; |
| 903 | d->sg[0].fn = buf_len / period_len; |
| 904 | d->sglen = 1; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 905 | |
| 906 | d->ccr = 0; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 907 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 908 | d->ccr |= CCR_DST_AMODE_POSTINC | CCR_SRC_AMODE_CONSTANT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 909 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 910 | d->ccr |= CCR_DST_AMODE_CONSTANT | CCR_SRC_AMODE_POSTINC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 911 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 912 | d->cicr = CICR_DROP_IE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 913 | if (flags & DMA_PREP_INTERRUPT) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 914 | d->cicr |= CICR_FRAME_IE; |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 915 | |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 916 | d->csdp = es; |
| 917 | |
| 918 | if (dma_omap1()) { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 919 | if (__dma_omap16xx(od->plat->dma_attr)) { |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 920 | d->ccr |= CCR_OMAP31_DISABLE; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 921 | /* Duplicate what plat-omap/dma.c does */ |
| 922 | d->ccr |= c->dma_ch + 1; |
| 923 | } else { |
| 924 | d->ccr |= c->dma_sig & 0x1f; |
| 925 | } |
| 926 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 927 | d->cicr |= CICR_TOUT_IE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 928 | |
| 929 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 930 | d->csdp |= CSDP_DST_PORT_EMIFF | CSDP_SRC_PORT_MPUI; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 931 | else |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 932 | d->csdp |= CSDP_DST_PORT_MPUI | CSDP_SRC_PORT_EMIFF; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 933 | } else { |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 934 | d->ccr |= (c->dma_sig & ~0x1f) << 14; |
| 935 | d->ccr |= c->dma_sig & 0x1f; |
| 936 | |
| 937 | if (burst) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 938 | d->ccr |= CCR_SYNC_PACKET; |
| 939 | else |
| 940 | d->ccr |= CCR_SYNC_ELEMENT; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 941 | |
| 942 | if (dir == DMA_DEV_TO_MEM) |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 943 | d->ccr |= CCR_TRIGGER_SRC; |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 944 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 945 | d->cicr |= CICR_MISALIGNED_ERR_IE | CICR_TRANS_ERR_IE; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 946 | |
Russell King | 9043826 | 2013-11-02 19:57:06 +0000 | [diff] [blame] | 947 | d->csdp |= CSDP_DST_BURST_64 | CSDP_SRC_BURST_64; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 948 | } |
Russell King | 49ae0b2 | 2013-11-02 21:09:18 +0000 | [diff] [blame] | 949 | if (od->plat->errata & DMA_ERRATA_IFRAME_BUFFERING) |
| 950 | d->ccr |= CCR_BUFFERING_DISABLE; |
Russell King | 2f0d13b | 2013-11-02 18:51:53 +0000 | [diff] [blame] | 951 | |
Russell King | 965aeb4d | 2013-11-06 17:12:30 +0000 | [diff] [blame] | 952 | if (__dma_omap15xx(od->plat->dma_attr)) |
| 953 | d->ccr |= CCR_AUTO_INIT | CCR_REPEAT; |
| 954 | else |
| 955 | d->clnk_ctrl = c->dma_ch | CLNK_CTRL_ENABLE_LNK; |
| 956 | |
Russell King | 3ed4d18 | 2013-11-02 19:16:09 +0000 | [diff] [blame] | 957 | c->cyclic = true; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 958 | |
Peter Ujfalusi | 2dde5b9 | 2012-09-14 15:05:48 +0300 | [diff] [blame] | 959 | return vchan_tx_prep(&c->vc, &d->vd, flags); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 960 | } |
| 961 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 962 | static int omap_dma_slave_config(struct omap_chan *c, struct dma_slave_config *cfg) |
| 963 | { |
| 964 | if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || |
| 965 | cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) |
| 966 | return -EINVAL; |
| 967 | |
| 968 | memcpy(&c->cfg, cfg, sizeof(c->cfg)); |
| 969 | |
| 970 | return 0; |
| 971 | } |
| 972 | |
| 973 | static int omap_dma_terminate_all(struct omap_chan *c) |
| 974 | { |
| 975 | struct omap_dmadev *d = to_omap_dma_dev(c->vc.chan.device); |
| 976 | unsigned long flags; |
| 977 | LIST_HEAD(head); |
| 978 | |
| 979 | spin_lock_irqsave(&c->vc.lock, flags); |
| 980 | |
| 981 | /* Prevent this channel being scheduled */ |
| 982 | spin_lock(&d->lock); |
| 983 | list_del_init(&c->node); |
| 984 | spin_unlock(&d->lock); |
| 985 | |
| 986 | /* |
| 987 | * Stop DMA activity: we assume the callback will not be called |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 988 | * after omap_dma_stop() returns (even if it does, it will see |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 989 | * c->desc is NULL and exit.) |
| 990 | */ |
| 991 | if (c->desc) { |
| 992 | c->desc = NULL; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 993 | /* Avoid stopping the dma twice */ |
| 994 | if (!c->paused) |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 995 | omap_dma_stop(c); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 996 | } |
| 997 | |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 998 | if (c->cyclic) { |
| 999 | c->cyclic = false; |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1000 | c->paused = false; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1001 | } |
| 1002 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1003 | vchan_get_all_descriptors(&c->vc, &head); |
| 1004 | spin_unlock_irqrestore(&c->vc.lock, flags); |
| 1005 | vchan_dma_desc_free_list(&c->vc, &head); |
| 1006 | |
| 1007 | return 0; |
| 1008 | } |
| 1009 | |
| 1010 | static int omap_dma_pause(struct omap_chan *c) |
| 1011 | { |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1012 | /* Pause/Resume only allowed with cyclic mode */ |
| 1013 | if (!c->cyclic) |
| 1014 | return -EINVAL; |
| 1015 | |
| 1016 | if (!c->paused) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 1017 | omap_dma_stop(c); |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1018 | c->paused = true; |
| 1019 | } |
| 1020 | |
| 1021 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1022 | } |
| 1023 | |
| 1024 | static int omap_dma_resume(struct omap_chan *c) |
| 1025 | { |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1026 | /* Pause/Resume only allowed with cyclic mode */ |
| 1027 | if (!c->cyclic) |
| 1028 | return -EINVAL; |
| 1029 | |
| 1030 | if (c->paused) { |
Russell King | fa3ad86 | 2013-11-02 17:07:09 +0000 | [diff] [blame] | 1031 | omap_dma_start(c, c->desc); |
Peter Ujfalusi | 2dcdf57 | 2012-09-14 15:05:45 +0300 | [diff] [blame] | 1032 | c->paused = false; |
| 1033 | } |
| 1034 | |
| 1035 | return 0; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1036 | } |
| 1037 | |
| 1038 | static int omap_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, |
| 1039 | unsigned long arg) |
| 1040 | { |
| 1041 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1042 | int ret; |
| 1043 | |
| 1044 | switch (cmd) { |
| 1045 | case DMA_SLAVE_CONFIG: |
| 1046 | ret = omap_dma_slave_config(c, (struct dma_slave_config *)arg); |
| 1047 | break; |
| 1048 | |
| 1049 | case DMA_TERMINATE_ALL: |
| 1050 | ret = omap_dma_terminate_all(c); |
| 1051 | break; |
| 1052 | |
| 1053 | case DMA_PAUSE: |
| 1054 | ret = omap_dma_pause(c); |
| 1055 | break; |
| 1056 | |
| 1057 | case DMA_RESUME: |
| 1058 | ret = omap_dma_resume(c); |
| 1059 | break; |
| 1060 | |
| 1061 | default: |
| 1062 | ret = -ENXIO; |
| 1063 | break; |
| 1064 | } |
| 1065 | |
| 1066 | return ret; |
| 1067 | } |
| 1068 | |
| 1069 | static int omap_dma_chan_init(struct omap_dmadev *od, int dma_sig) |
| 1070 | { |
| 1071 | struct omap_chan *c; |
| 1072 | |
| 1073 | c = kzalloc(sizeof(*c), GFP_KERNEL); |
| 1074 | if (!c) |
| 1075 | return -ENOMEM; |
| 1076 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1077 | c->reg_map = od->reg_map; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1078 | c->dma_sig = dma_sig; |
| 1079 | c->vc.desc_free = omap_dma_desc_free; |
| 1080 | vchan_init(&c->vc, &od->ddev); |
| 1081 | INIT_LIST_HEAD(&c->node); |
| 1082 | |
| 1083 | od->ddev.chancnt++; |
| 1084 | |
| 1085 | return 0; |
| 1086 | } |
| 1087 | |
| 1088 | static void omap_dma_free(struct omap_dmadev *od) |
| 1089 | { |
| 1090 | tasklet_kill(&od->task); |
| 1091 | while (!list_empty(&od->ddev.channels)) { |
| 1092 | struct omap_chan *c = list_first_entry(&od->ddev.channels, |
| 1093 | struct omap_chan, vc.chan.device_node); |
| 1094 | |
| 1095 | list_del(&c->vc.chan.device_node); |
| 1096 | tasklet_kill(&c->vc.task); |
| 1097 | kfree(c); |
| 1098 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | static int omap_dma_probe(struct platform_device *pdev) |
| 1102 | { |
| 1103 | struct omap_dmadev *od; |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1104 | struct resource *res; |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 1105 | int rc, i, irq; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1106 | |
Russell King | 104fce7 | 2013-11-02 12:58:29 +0000 | [diff] [blame] | 1107 | od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1108 | if (!od) |
| 1109 | return -ENOMEM; |
| 1110 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1111 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1112 | od->base = devm_ioremap_resource(&pdev->dev, res); |
| 1113 | if (IS_ERR(od->base)) |
| 1114 | return PTR_ERR(od->base); |
| 1115 | |
Russell King | 1b416c4 | 2013-11-02 13:00:03 +0000 | [diff] [blame] | 1116 | od->plat = omap_get_plat_info(); |
| 1117 | if (!od->plat) |
| 1118 | return -EPROBE_DEFER; |
| 1119 | |
Russell King | 596c471 | 2013-12-10 11:08:01 +0000 | [diff] [blame] | 1120 | od->reg_map = od->plat->reg_map; |
| 1121 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1122 | dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1123 | dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1124 | od->ddev.device_alloc_chan_resources = omap_dma_alloc_chan_resources; |
| 1125 | od->ddev.device_free_chan_resources = omap_dma_free_chan_resources; |
| 1126 | od->ddev.device_tx_status = omap_dma_tx_status; |
| 1127 | od->ddev.device_issue_pending = omap_dma_issue_pending; |
| 1128 | od->ddev.device_prep_slave_sg = omap_dma_prep_slave_sg; |
Russell King | 3a774ea | 2012-06-21 10:40:15 +0100 | [diff] [blame] | 1129 | od->ddev.device_prep_dma_cyclic = omap_dma_prep_dma_cyclic; |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1130 | od->ddev.device_control = omap_dma_control; |
| 1131 | od->ddev.dev = &pdev->dev; |
| 1132 | INIT_LIST_HEAD(&od->ddev.channels); |
| 1133 | INIT_LIST_HEAD(&od->pending); |
| 1134 | spin_lock_init(&od->lock); |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 1135 | spin_lock_init(&od->irq_lock); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1136 | |
| 1137 | tasklet_init(&od->task, omap_dma_sched, (unsigned long)od); |
| 1138 | |
| 1139 | for (i = 0; i < 127; i++) { |
| 1140 | rc = omap_dma_chan_init(od, i); |
| 1141 | if (rc) { |
| 1142 | omap_dma_free(od); |
| 1143 | return rc; |
| 1144 | } |
| 1145 | } |
| 1146 | |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 1147 | irq = platform_get_irq(pdev, 1); |
| 1148 | if (irq <= 0) { |
| 1149 | dev_info(&pdev->dev, "failed to get L1 IRQ: %d\n", irq); |
| 1150 | od->legacy = true; |
| 1151 | } else { |
| 1152 | /* Disable all interrupts */ |
| 1153 | od->irq_enable_mask = 0; |
| 1154 | omap_dma_glbl_write(od, IRQENABLE_L1, 0); |
| 1155 | |
| 1156 | rc = devm_request_irq(&pdev->dev, irq, omap_dma_irq, |
| 1157 | IRQF_SHARED, "omap-dma-engine", od); |
| 1158 | if (rc) |
| 1159 | return rc; |
| 1160 | } |
| 1161 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1162 | rc = dma_async_device_register(&od->ddev); |
| 1163 | if (rc) { |
| 1164 | pr_warn("OMAP-DMA: failed to register slave DMA engine device: %d\n", |
| 1165 | rc); |
| 1166 | omap_dma_free(od); |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1167 | return rc; |
| 1168 | } |
| 1169 | |
| 1170 | platform_set_drvdata(pdev, od); |
| 1171 | |
| 1172 | if (pdev->dev.of_node) { |
| 1173 | omap_dma_info.dma_cap = od->ddev.cap_mask; |
| 1174 | |
| 1175 | /* Device-tree DMA controller registration */ |
| 1176 | rc = of_dma_controller_register(pdev->dev.of_node, |
| 1177 | of_dma_simple_xlate, &omap_dma_info); |
| 1178 | if (rc) { |
| 1179 | pr_warn("OMAP-DMA: failed to register DMA controller\n"); |
| 1180 | dma_async_device_unregister(&od->ddev); |
| 1181 | omap_dma_free(od); |
| 1182 | } |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1183 | } |
| 1184 | |
| 1185 | dev_info(&pdev->dev, "OMAP DMA engine driver\n"); |
| 1186 | |
| 1187 | return rc; |
| 1188 | } |
| 1189 | |
| 1190 | static int omap_dma_remove(struct platform_device *pdev) |
| 1191 | { |
| 1192 | struct omap_dmadev *od = platform_get_drvdata(pdev); |
| 1193 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1194 | if (pdev->dev.of_node) |
| 1195 | of_dma_controller_free(pdev->dev.of_node); |
| 1196 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1197 | dma_async_device_unregister(&od->ddev); |
Russell King | 6ddeb6d | 2013-12-10 19:05:50 +0000 | [diff] [blame^] | 1198 | |
| 1199 | if (!od->legacy) { |
| 1200 | /* Disable all interrupts */ |
| 1201 | omap_dma_glbl_write(od, IRQENABLE_L0, 0); |
| 1202 | } |
| 1203 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1204 | omap_dma_free(od); |
| 1205 | |
| 1206 | return 0; |
| 1207 | } |
| 1208 | |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1209 | static const struct of_device_id omap_dma_match[] = { |
| 1210 | { .compatible = "ti,omap2420-sdma", }, |
| 1211 | { .compatible = "ti,omap2430-sdma", }, |
| 1212 | { .compatible = "ti,omap3430-sdma", }, |
| 1213 | { .compatible = "ti,omap3630-sdma", }, |
| 1214 | { .compatible = "ti,omap4430-sdma", }, |
| 1215 | {}, |
| 1216 | }; |
| 1217 | MODULE_DEVICE_TABLE(of, omap_dma_match); |
| 1218 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1219 | static struct platform_driver omap_dma_driver = { |
| 1220 | .probe = omap_dma_probe, |
| 1221 | .remove = omap_dma_remove, |
| 1222 | .driver = { |
| 1223 | .name = "omap-dma-engine", |
| 1224 | .owner = THIS_MODULE, |
Jon Hunter | 8d30662 | 2013-02-26 12:27:24 -0600 | [diff] [blame] | 1225 | .of_match_table = of_match_ptr(omap_dma_match), |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1226 | }, |
| 1227 | }; |
| 1228 | |
| 1229 | bool omap_dma_filter_fn(struct dma_chan *chan, void *param) |
| 1230 | { |
| 1231 | if (chan->device->dev->driver == &omap_dma_driver.driver) { |
| 1232 | struct omap_chan *c = to_omap_dma_chan(chan); |
| 1233 | unsigned req = *(unsigned *)param; |
| 1234 | |
| 1235 | return req == c->dma_sig; |
| 1236 | } |
| 1237 | return false; |
| 1238 | } |
| 1239 | EXPORT_SYMBOL_GPL(omap_dma_filter_fn); |
| 1240 | |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1241 | static int omap_dma_init(void) |
| 1242 | { |
Tony Lindgren | be1f948 | 2013-01-11 11:24:19 -0800 | [diff] [blame] | 1243 | return platform_driver_register(&omap_dma_driver); |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1244 | } |
| 1245 | subsys_initcall(omap_dma_init); |
| 1246 | |
| 1247 | static void __exit omap_dma_exit(void) |
| 1248 | { |
Russell King | 7bedaa5 | 2012-04-13 12:10:24 +0100 | [diff] [blame] | 1249 | platform_driver_unregister(&omap_dma_driver); |
| 1250 | } |
| 1251 | module_exit(omap_dma_exit); |
| 1252 | |
| 1253 | MODULE_AUTHOR("Russell King"); |
| 1254 | MODULE_LICENSE("GPL"); |