Linus Walleij | 4a31bd2 | 2012-01-11 13:52:34 +0100 | [diff] [blame] | 1 | #include <linux/clk.h> |
| 2 | #include <linux/clkdev.h> |
| 3 | #include <linux/err.h> |
| 4 | #include <linux/io.h> |
| 5 | #include <linux/clk-provider.h> |
Linus Walleij | 6e2b07a | 2013-04-16 21:38:29 +0200 | [diff] [blame^] | 6 | #include <linux/of.h> |
Linus Walleij | 4a31bd2 | 2012-01-11 13:52:34 +0100 | [diff] [blame] | 7 | |
| 8 | /* |
| 9 | * The Nomadik clock tree is described in the STN8815A12 DB V4.2 |
| 10 | * reference manual for the chip, page 94 ff. |
| 11 | */ |
| 12 | |
Linus Walleij | 6e2b07a | 2013-04-16 21:38:29 +0200 | [diff] [blame^] | 13 | static const __initconst struct of_device_id cpu8815_clk_match[] = { |
| 14 | { .compatible = "fixed-clock", .data = of_fixed_clk_setup, }, |
| 15 | { /* sentinel */ } |
| 16 | }; |
| 17 | |
Linus Walleij | 4a31bd2 | 2012-01-11 13:52:34 +0100 | [diff] [blame] | 18 | void __init nomadik_clk_init(void) |
| 19 | { |
| 20 | struct clk *clk; |
| 21 | |
| 22 | clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); |
| 23 | clk_register_clkdev(clk, "apb_pclk", NULL); |
Linus Walleij | 4a31bd2 | 2012-01-11 13:52:34 +0100 | [diff] [blame] | 24 | |
| 25 | /* |
| 26 | * The 2.4 MHz TIMCLK reference clock is active at boot time, this is |
| 27 | * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used |
| 28 | * by the timers and watchdog. See page 105 ff. |
| 29 | */ |
| 30 | clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT, |
| 31 | 2400000); |
| 32 | clk_register_clkdev(clk, NULL, "mtu0"); |
| 33 | clk_register_clkdev(clk, NULL, "mtu1"); |
| 34 | |
Linus Walleij | 6e2b07a | 2013-04-16 21:38:29 +0200 | [diff] [blame^] | 35 | of_clk_init(cpu8815_clk_match); |
Linus Walleij | 4a31bd2 | 2012-01-11 13:52:34 +0100 | [diff] [blame] | 36 | } |