Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 1 | /* |
| 2 | * AMD64 class Memory Controller kernel module |
| 3 | * |
| 4 | * Copyright (c) 2009 SoftwareBitMaker. |
| 5 | * Copyright (c) 2009 Advanced Micro Devices, Inc. |
| 6 | * |
| 7 | * This file may be distributed under the terms of the |
| 8 | * GNU General Public License. |
| 9 | * |
| 10 | * Originally Written by Thayne Harbaugh |
| 11 | * |
| 12 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: |
| 13 | * - K8 CPU Revision D and greater support |
| 14 | * |
| 15 | * Changes by Dave Peterson <dsp@llnl.gov> <dave_peterson@pobox.com>: |
| 16 | * - Module largely rewritten, with new (and hopefully correct) |
| 17 | * code for dealing with node and chip select interleaving, |
| 18 | * various code cleanup, and bug fixes |
| 19 | * - Added support for memory hoisting using DRAM hole address |
| 20 | * register |
| 21 | * |
| 22 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: |
| 23 | * -K8 Rev (1207) revision support added, required Revision |
| 24 | * specific mini-driver code to support Rev F as well as |
| 25 | * prior revisions |
| 26 | * |
| 27 | * Changes by Douglas "norsk" Thompson <dougthompson@xmission.com>: |
| 28 | * -Family 10h revision support added. New PCI Device IDs, |
| 29 | * indicating new changes. Actual registers modified |
| 30 | * were slight, less than the Rev E to Rev F transition |
| 31 | * but changing the PCI Device ID was the proper thing to |
| 32 | * do, as it provides for almost automactic family |
| 33 | * detection. The mods to Rev F required more family |
| 34 | * information detection. |
| 35 | * |
Borislav Petkov | 43aff26 | 2012-10-29 18:40:09 +0100 | [diff] [blame] | 36 | * Changes/Fixes by Borislav Petkov <bp@alien8.de>: |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 37 | * - misc fixes and code cleanups |
| 38 | * |
| 39 | * This module is based on the following documents |
| 40 | * (available from http://www.amd.com/): |
| 41 | * |
| 42 | * Title: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD |
| 43 | * Opteron Processors |
| 44 | * AMD publication #: 26094 |
| 45 | *` Revision: 3.26 |
| 46 | * |
| 47 | * Title: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh |
| 48 | * Processors |
| 49 | * AMD publication #: 32559 |
| 50 | * Revision: 3.00 |
| 51 | * Issue Date: May 2006 |
| 52 | * |
| 53 | * Title: BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h |
| 54 | * Processors |
| 55 | * AMD publication #: 31116 |
| 56 | * Revision: 3.00 |
| 57 | * Issue Date: September 07, 2007 |
| 58 | * |
| 59 | * Sections in the first 2 documents are no longer in sync with each other. |
| 60 | * The Family 10h BKDG was totally re-written from scratch with a new |
| 61 | * presentation model. |
| 62 | * Therefore, comments that refer to a Document section might be off. |
| 63 | */ |
| 64 | |
| 65 | #include <linux/module.h> |
| 66 | #include <linux/ctype.h> |
| 67 | #include <linux/init.h> |
| 68 | #include <linux/pci.h> |
| 69 | #include <linux/pci_ids.h> |
| 70 | #include <linux/slab.h> |
| 71 | #include <linux/mmzone.h> |
| 72 | #include <linux/edac.h> |
Doug Thompson | f943199 | 2009-04-27 19:46:08 +0200 | [diff] [blame] | 73 | #include <asm/msr.h> |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 74 | #include "edac_core.h" |
Borislav Petkov | 47ca08a | 2010-09-27 15:30:39 +0200 | [diff] [blame] | 75 | #include "mce_amd.h" |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 76 | |
Borislav Petkov | 24f9a7f | 2010-10-07 18:29:15 +0200 | [diff] [blame] | 77 | #define amd64_debug(fmt, arg...) \ |
| 78 | edac_printk(KERN_DEBUG, "amd64", fmt, ##arg) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 79 | |
Borislav Petkov | 24f9a7f | 2010-10-07 18:29:15 +0200 | [diff] [blame] | 80 | #define amd64_info(fmt, arg...) \ |
| 81 | edac_printk(KERN_INFO, "amd64", fmt, ##arg) |
| 82 | |
| 83 | #define amd64_notice(fmt, arg...) \ |
| 84 | edac_printk(KERN_NOTICE, "amd64", fmt, ##arg) |
| 85 | |
| 86 | #define amd64_warn(fmt, arg...) \ |
| 87 | edac_printk(KERN_WARNING, "amd64", fmt, ##arg) |
| 88 | |
| 89 | #define amd64_err(fmt, arg...) \ |
| 90 | edac_printk(KERN_ERR, "amd64", fmt, ##arg) |
| 91 | |
| 92 | #define amd64_mc_warn(mci, fmt, arg...) \ |
| 93 | edac_mc_chipset_printk(mci, KERN_WARNING, "amd64", fmt, ##arg) |
| 94 | |
| 95 | #define amd64_mc_err(mci, fmt, arg...) \ |
| 96 | edac_mc_chipset_printk(mci, KERN_ERR, "amd64", fmt, ##arg) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 97 | |
| 98 | /* |
| 99 | * Throughout the comments in this code, the following terms are used: |
| 100 | * |
| 101 | * SysAddr, DramAddr, and InputAddr |
| 102 | * |
| 103 | * These terms come directly from the amd64 documentation |
| 104 | * (AMD publication #26094). They are defined as follows: |
| 105 | * |
| 106 | * SysAddr: |
| 107 | * This is a physical address generated by a CPU core or a device |
| 108 | * doing DMA. If generated by a CPU core, a SysAddr is the result of |
| 109 | * a virtual to physical address translation by the CPU core's address |
| 110 | * translation mechanism (MMU). |
| 111 | * |
| 112 | * DramAddr: |
| 113 | * A DramAddr is derived from a SysAddr by subtracting an offset that |
| 114 | * depends on which node the SysAddr maps to and whether the SysAddr |
| 115 | * is within a range affected by memory hoisting. The DRAM Base |
| 116 | * (section 3.4.4.1) and DRAM Limit (section 3.4.4.2) registers |
| 117 | * determine which node a SysAddr maps to. |
| 118 | * |
| 119 | * If the DRAM Hole Address Register (DHAR) is enabled and the SysAddr |
| 120 | * is within the range of addresses specified by this register, then |
| 121 | * a value x from the DHAR is subtracted from the SysAddr to produce a |
| 122 | * DramAddr. Here, x represents the base address for the node that |
| 123 | * the SysAddr maps to plus an offset due to memory hoisting. See |
| 124 | * section 3.4.8 and the comments in amd64_get_dram_hole_info() and |
| 125 | * sys_addr_to_dram_addr() below for more information. |
| 126 | * |
| 127 | * If the SysAddr is not affected by the DHAR then a value y is |
| 128 | * subtracted from the SysAddr to produce a DramAddr. Here, y is the |
| 129 | * base address for the node that the SysAddr maps to. See section |
| 130 | * 3.4.4 and the comments in sys_addr_to_dram_addr() below for more |
| 131 | * information. |
| 132 | * |
| 133 | * InputAddr: |
| 134 | * A DramAddr is translated to an InputAddr before being passed to the |
| 135 | * memory controller for the node that the DramAddr is associated |
| 136 | * with. The memory controller then maps the InputAddr to a csrow. |
| 137 | * If node interleaving is not in use, then the InputAddr has the same |
| 138 | * value as the DramAddr. Otherwise, the InputAddr is produced by |
| 139 | * discarding the bits used for node interleaving from the DramAddr. |
| 140 | * See section 3.4.4 for more information. |
| 141 | * |
| 142 | * The memory controller for a given node uses its DRAM CS Base and |
| 143 | * DRAM CS Mask registers to map an InputAddr to a csrow. See |
| 144 | * sections 3.5.4 and 3.5.5 for more information. |
| 145 | */ |
| 146 | |
Borislav Petkov | df71a05 | 2011-01-19 18:15:10 +0100 | [diff] [blame] | 147 | #define EDAC_AMD64_VERSION "3.4.0" |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 148 | #define EDAC_MOD_STR "amd64_edac" |
| 149 | |
| 150 | /* Extended Model from CPUID, for CPU Revision numbers */ |
Borislav Petkov | 1433eb9 | 2009-10-21 13:44:36 +0200 | [diff] [blame] | 151 | #define K8_REV_D 1 |
| 152 | #define K8_REV_E 2 |
| 153 | #define K8_REV_F 4 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 154 | |
| 155 | /* Hardware limit on ChipSelect rows per MC and processors per system */ |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 156 | #define NUM_CHIPSELECTS 8 |
| 157 | #define DRAM_RANGES 8 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 158 | |
Borislav Petkov | f6d6ae9 | 2009-11-03 15:29:26 +0100 | [diff] [blame] | 159 | #define ON true |
| 160 | #define OFF false |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 161 | |
| 162 | /* |
Borislav Petkov | 11c75ea | 2010-11-29 19:49:02 +0100 | [diff] [blame] | 163 | * Create a contiguous bitmask starting at bit position @lo and ending at |
| 164 | * position @hi. For example |
| 165 | * |
| 166 | * GENMASK(21, 39) gives us the 64bit vector 0x000000ffffe00000. |
| 167 | */ |
| 168 | #define GENMASK(lo, hi) (((1ULL << ((hi) - (lo) + 1)) - 1) << (lo)) |
| 169 | |
| 170 | /* |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 171 | * PCI-defined configuration space registers |
| 172 | */ |
Borislav Petkov | df71a05 | 2011-01-19 18:15:10 +0100 | [diff] [blame] | 173 | #define PCI_DEVICE_ID_AMD_15H_NB_F1 0x1601 |
| 174 | #define PCI_DEVICE_ID_AMD_15H_NB_F2 0x1602 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 175 | |
| 176 | |
| 177 | /* |
| 178 | * Function 1 - Address Map |
| 179 | */ |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 180 | #define DRAM_BASE_LO 0x40 |
| 181 | #define DRAM_LIMIT_LO 0x44 |
| 182 | |
Borislav Petkov | 151fa71 | 2011-02-21 19:33:10 +0100 | [diff] [blame] | 183 | #define dram_intlv_en(pvt, i) ((u8)((pvt->ranges[i].base.lo >> 8) & 0x7)) |
| 184 | #define dram_rw(pvt, i) ((u8)(pvt->ranges[i].base.lo & 0x3)) |
| 185 | #define dram_intlv_sel(pvt, i) ((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7)) |
| 186 | #define dram_dst_node(pvt, i) ((u8)(pvt->ranges[i].lim.lo & 0x7)) |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 187 | |
Borislav Petkov | bc21fa5 | 2010-11-11 17:29:13 +0100 | [diff] [blame] | 188 | #define DHAR 0xf0 |
Borislav Petkov | c8e518d | 2010-12-10 19:49:19 +0100 | [diff] [blame] | 189 | #define dhar_valid(pvt) ((pvt)->dhar & BIT(0)) |
| 190 | #define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1)) |
| 191 | #define dhar_base(pvt) ((pvt)->dhar & 0xff000000) |
| 192 | #define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 193 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 194 | /* NOTE: Extra mask bit vs K8 */ |
Borislav Petkov | c8e518d | 2010-12-10 19:49:19 +0100 | [diff] [blame] | 195 | #define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 196 | |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 197 | #define DCT_CFG_SEL 0x10C |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 198 | |
Borislav Petkov | c1ae683 | 2011-03-30 15:42:10 +0200 | [diff] [blame] | 199 | #define DRAM_LOCAL_NODE_BASE 0x120 |
Borislav Petkov | f08e457 | 2011-03-21 20:45:06 +0100 | [diff] [blame] | 200 | #define DRAM_LOCAL_NODE_LIM 0x124 |
| 201 | |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 202 | #define DRAM_BASE_HI 0x140 |
| 203 | #define DRAM_LIMIT_HI 0x144 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 204 | |
| 205 | |
| 206 | /* |
| 207 | * Function 2 - DRAM controller |
| 208 | */ |
Borislav Petkov | 11c75ea | 2010-11-29 19:49:02 +0100 | [diff] [blame] | 209 | #define DCSB0 0x40 |
| 210 | #define DCSB1 0x140 |
| 211 | #define DCSB_CS_ENABLE BIT(0) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 212 | |
Borislav Petkov | 11c75ea | 2010-11-29 19:49:02 +0100 | [diff] [blame] | 213 | #define DCSM0 0x60 |
| 214 | #define DCSM1 0x160 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 215 | |
Borislav Petkov | 11c75ea | 2010-11-29 19:49:02 +0100 | [diff] [blame] | 216 | #define csrow_enabled(i, dct, pvt) ((pvt)->csels[(dct)].csbases[(i)] & DCSB_CS_ENABLE) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 217 | |
| 218 | #define DBAM0 0x80 |
| 219 | #define DBAM1 0x180 |
| 220 | |
| 221 | /* Extract the DIMM 'type' on the i'th DIMM from the DBAM reg value passed */ |
| 222 | #define DBAM_DIMM(i, reg) ((((reg) >> (4*i))) & 0xF) |
| 223 | |
| 224 | #define DBAM_MAX_VALUE 11 |
| 225 | |
Borislav Petkov | cb32850 | 2010-12-22 14:28:24 +0100 | [diff] [blame] | 226 | #define DCLR0 0x90 |
| 227 | #define DCLR1 0x190 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 228 | #define REVE_WIDTH_128 BIT(16) |
Borislav Petkov | 41d8bfa | 2011-01-18 19:16:08 +0100 | [diff] [blame] | 229 | #define WIDTH_128 BIT(11) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 230 | |
Borislav Petkov | cb32850 | 2010-12-22 14:28:24 +0100 | [diff] [blame] | 231 | #define DCHR0 0x94 |
| 232 | #define DCHR1 0x194 |
Borislav Petkov | 1433eb9 | 2009-10-21 13:44:36 +0200 | [diff] [blame] | 233 | #define DDR3_MODE BIT(8) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 234 | |
Borislav Petkov | 78da121 | 2010-12-22 19:31:45 +0100 | [diff] [blame] | 235 | #define DCT_SEL_LO 0x110 |
| 236 | #define dct_sel_baseaddr(pvt) ((pvt)->dct_sel_lo & 0xFFFFF800) |
| 237 | #define dct_sel_interleave_addr(pvt) (((pvt)->dct_sel_lo >> 6) & 0x3) |
| 238 | #define dct_high_range_enabled(pvt) ((pvt)->dct_sel_lo & BIT(0)) |
| 239 | #define dct_interleave_enabled(pvt) ((pvt)->dct_sel_lo & BIT(2)) |
Borislav Petkov | cb32850 | 2010-12-22 14:28:24 +0100 | [diff] [blame] | 240 | |
Borislav Petkov | 78da121 | 2010-12-22 19:31:45 +0100 | [diff] [blame] | 241 | #define dct_ganging_enabled(pvt) ((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4))) |
Borislav Petkov | cb32850 | 2010-12-22 14:28:24 +0100 | [diff] [blame] | 242 | |
Borislav Petkov | 78da121 | 2010-12-22 19:31:45 +0100 | [diff] [blame] | 243 | #define dct_data_intlv_enabled(pvt) ((pvt)->dct_sel_lo & BIT(5)) |
Borislav Petkov | 78da121 | 2010-12-22 19:31:45 +0100 | [diff] [blame] | 244 | #define dct_memory_cleared(pvt) ((pvt)->dct_sel_lo & BIT(10)) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 245 | |
Borislav Petkov | 95b0ef5 | 2011-01-11 22:08:07 +0100 | [diff] [blame] | 246 | #define SWAP_INTLV_REG 0x10c |
| 247 | |
Borislav Petkov | 78da121 | 2010-12-22 19:31:45 +0100 | [diff] [blame] | 248 | #define DCT_SEL_HI 0x114 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 249 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 250 | /* |
| 251 | * Function 3 - Misc Control |
| 252 | */ |
Borislav Petkov | c9f4f26 | 2010-12-22 19:48:20 +0100 | [diff] [blame] | 253 | #define NBCTL 0x40 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 254 | |
Borislav Petkov | a97fa68 | 2010-12-23 14:07:18 +0100 | [diff] [blame] | 255 | #define NBCFG 0x44 |
| 256 | #define NBCFG_CHIPKILL BIT(23) |
| 257 | #define NBCFG_ECC_ENABLE BIT(22) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 258 | |
Borislav Petkov | 5980bb9 | 2011-01-07 16:26:49 +0100 | [diff] [blame] | 259 | /* F3x48: NBSL */ |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 260 | #define F10_NBSL_EXT_ERR_ECC 0x8 |
Borislav Petkov | 5980bb9 | 2011-01-07 16:26:49 +0100 | [diff] [blame] | 261 | #define NBSL_PP_OBS 0x2 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 262 | |
Borislav Petkov | 5980bb9 | 2011-01-07 16:26:49 +0100 | [diff] [blame] | 263 | #define SCRCTRL 0x58 |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 264 | |
| 265 | #define F10_ONLINE_SPARE 0xB0 |
Borislav Petkov | 614ec9d | 2011-01-13 18:02:22 +0100 | [diff] [blame] | 266 | #define online_spare_swap_done(pvt, c) (((pvt)->online_spare >> (1 + 2 * (c))) & 0x1) |
| 267 | #define online_spare_bad_dramcs(pvt, c) (((pvt)->online_spare >> (4 + 4 * (c))) & 0x7) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 268 | |
| 269 | #define F10_NB_ARRAY_ADDR 0xB8 |
Borislav Petkov | 5980bb9 | 2011-01-07 16:26:49 +0100 | [diff] [blame] | 270 | #define F10_NB_ARRAY_DRAM_ECC BIT(31) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 271 | |
| 272 | /* Bits [2:1] are used to select 16-byte section within a 64-byte cacheline */ |
| 273 | #define SET_NB_ARRAY_ADDRESS(section) (((section) & 0x3) << 1) |
| 274 | |
| 275 | #define F10_NB_ARRAY_DATA 0xBC |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 276 | #define SET_NB_DRAM_INJECTION_WRITE(word, bits) \ |
| 277 | (BIT(((word) & 0xF) + 20) | \ |
Borislav Petkov | 94baaee | 2009-09-24 11:05:30 +0200 | [diff] [blame] | 278 | BIT(17) | bits) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 279 | #define SET_NB_DRAM_INJECTION_READ(word, bits) \ |
| 280 | (BIT(((word) & 0xF) + 20) | \ |
Borislav Petkov | 94baaee | 2009-09-24 11:05:30 +0200 | [diff] [blame] | 281 | BIT(16) | bits) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 282 | |
Borislav Petkov | 5980bb9 | 2011-01-07 16:26:49 +0100 | [diff] [blame] | 283 | #define NBCAP 0xE8 |
| 284 | #define NBCAP_CHIPKILL BIT(4) |
| 285 | #define NBCAP_SECDED BIT(3) |
| 286 | #define NBCAP_DCT_DUAL BIT(0) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 287 | |
Borislav Petkov | ad6a32e | 2010-03-09 12:46:00 +0100 | [diff] [blame] | 288 | #define EXT_NB_MCA_CFG 0x180 |
| 289 | |
Borislav Petkov | f6d6ae9 | 2009-11-03 15:29:26 +0100 | [diff] [blame] | 290 | /* MSRs */ |
Borislav Petkov | 5980bb9 | 2011-01-07 16:26:49 +0100 | [diff] [blame] | 291 | #define MSR_MCGCTL_NBE BIT(4) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 292 | |
| 293 | /* AMD sets the first MC device at device ID 0x18. */ |
Borislav Petkov | b487c33 | 2011-02-21 18:55:00 +0100 | [diff] [blame] | 294 | static inline u8 get_node_id(struct pci_dev *pdev) |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 295 | { |
| 296 | return PCI_SLOT(pdev->devfn) - 0x18; |
| 297 | } |
| 298 | |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 299 | enum amd_families { |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 300 | K8_CPUS = 0, |
| 301 | F10_CPUS, |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 302 | F15_CPUS, |
| 303 | NUM_FAMILIES, |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 304 | }; |
| 305 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 306 | /* Error injection control structure */ |
| 307 | struct error_injection { |
| 308 | u32 section; |
| 309 | u32 word; |
| 310 | u32 bit_map; |
| 311 | }; |
| 312 | |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 313 | /* low and high part of PCI config space regs */ |
| 314 | struct reg_pair { |
| 315 | u32 lo, hi; |
| 316 | }; |
| 317 | |
| 318 | /* |
| 319 | * See F1x[1, 0][7C:40] DRAM Base/Limit Registers |
| 320 | */ |
| 321 | struct dram_range { |
| 322 | struct reg_pair base; |
| 323 | struct reg_pair lim; |
| 324 | }; |
| 325 | |
Borislav Petkov | 11c75ea | 2010-11-29 19:49:02 +0100 | [diff] [blame] | 326 | /* A DCT chip selects collection */ |
| 327 | struct chip_select { |
| 328 | u32 csbases[NUM_CHIPSELECTS]; |
| 329 | u8 b_cnt; |
| 330 | |
| 331 | u32 csmasks[NUM_CHIPSELECTS]; |
| 332 | u8 m_cnt; |
| 333 | }; |
| 334 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 335 | struct amd64_pvt { |
Borislav Petkov | b8cfa02 | 2010-10-01 19:35:38 +0200 | [diff] [blame] | 336 | struct low_ops *ops; |
| 337 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 338 | /* pci_device handles which we utilize */ |
Borislav Petkov | 8d5b5d9 | 2010-10-01 20:11:07 +0200 | [diff] [blame] | 339 | struct pci_dev *F1, *F2, *F3; |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 340 | |
Borislav Petkov | b487c33 | 2011-02-21 18:55:00 +0100 | [diff] [blame] | 341 | unsigned mc_node_id; /* MC index of this MC node */ |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 342 | int ext_model; /* extended model value of this node */ |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 343 | int channel_count; |
| 344 | |
| 345 | /* Raw registers */ |
| 346 | u32 dclr0; /* DRAM Configuration Low DCT0 reg */ |
| 347 | u32 dclr1; /* DRAM Configuration Low DCT1 reg */ |
| 348 | u32 dchr0; /* DRAM Configuration High DCT0 reg */ |
| 349 | u32 dchr1; /* DRAM Configuration High DCT1 reg */ |
| 350 | u32 nbcap; /* North Bridge Capabilities */ |
| 351 | u32 nbcfg; /* F10 North Bridge Configuration */ |
| 352 | u32 ext_nbcfg; /* Extended F10 North Bridge Configuration */ |
| 353 | u32 dhar; /* DRAM Hoist reg */ |
| 354 | u32 dbam0; /* DRAM Base Address Mapping reg for DCT0 */ |
| 355 | u32 dbam1; /* DRAM Base Address Mapping reg for DCT1 */ |
| 356 | |
Borislav Petkov | 11c75ea | 2010-11-29 19:49:02 +0100 | [diff] [blame] | 357 | /* one for each DCT */ |
| 358 | struct chip_select csels[2]; |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 359 | |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 360 | /* DRAM base and limit pairs F1x[78,70,68,60,58,50,48,40] */ |
| 361 | struct dram_range ranges[DRAM_RANGES]; |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 362 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 363 | u64 top_mem; /* top of memory below 4GB */ |
| 364 | u64 top_mem2; /* top of memory above 4GB */ |
| 365 | |
Borislav Petkov | 78da121 | 2010-12-22 19:31:45 +0100 | [diff] [blame] | 366 | u32 dct_sel_lo; /* DRAM Controller Select Low */ |
| 367 | u32 dct_sel_hi; /* DRAM Controller Select High */ |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 368 | u32 online_spare; /* On-Line spare Reg */ |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 369 | |
Borislav Petkov | ad6a32e | 2010-03-09 12:46:00 +0100 | [diff] [blame] | 370 | /* x4 or x8 syndromes in use */ |
Borislav Petkov | a3b7db0 | 2011-01-19 20:35:12 +0100 | [diff] [blame] | 371 | u8 ecc_sym_sz; |
Borislav Petkov | ad6a32e | 2010-03-09 12:46:00 +0100 | [diff] [blame] | 372 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 373 | /* place to store error injection parameters prior to issue */ |
| 374 | struct error_injection injection; |
Borislav Petkov | ae7bb7c | 2010-10-14 16:01:30 +0200 | [diff] [blame] | 375 | }; |
| 376 | |
Borislav Petkov | 7f19bf7 | 2010-10-21 18:52:53 +0200 | [diff] [blame] | 377 | static inline u64 get_dram_base(struct amd64_pvt *pvt, unsigned i) |
| 378 | { |
| 379 | u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8; |
| 380 | |
| 381 | if (boot_cpu_data.x86 == 0xf) |
| 382 | return addr; |
| 383 | |
| 384 | return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr; |
| 385 | } |
| 386 | |
| 387 | static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i) |
| 388 | { |
| 389 | u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff; |
| 390 | |
| 391 | if (boot_cpu_data.x86 == 0xf) |
| 392 | return lim; |
| 393 | |
| 394 | return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim; |
| 395 | } |
| 396 | |
Borislav Petkov | f192c7b | 2011-01-10 14:24:32 +0100 | [diff] [blame] | 397 | static inline u16 extract_syndrome(u64 status) |
| 398 | { |
| 399 | return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00); |
| 400 | } |
| 401 | |
Borislav Petkov | ae7bb7c | 2010-10-14 16:01:30 +0200 | [diff] [blame] | 402 | /* |
| 403 | * per-node ECC settings descriptor |
| 404 | */ |
| 405 | struct ecc_settings { |
| 406 | u32 old_nbctl; |
| 407 | bool nbctl_valid; |
| 408 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 409 | struct flags { |
Borislav Petkov | d95cf4d | 2010-02-24 14:49:47 +0100 | [diff] [blame] | 410 | unsigned long nb_mce_enable:1; |
| 411 | unsigned long nb_ecc_prev:1; |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 412 | } flags; |
| 413 | }; |
| 414 | |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 415 | #ifdef CONFIG_EDAC_DEBUG |
Mauro Carvalho Chehab | c560875 | 2012-03-21 14:00:44 -0300 | [diff] [blame] | 416 | int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci); |
| 417 | void amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci); |
| 418 | |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 419 | #else |
Mauro Carvalho Chehab | c560875 | 2012-03-21 14:00:44 -0300 | [diff] [blame] | 420 | static inline int amd64_create_sysfs_dbg_files(struct mem_ctl_info *mci) |
| 421 | { |
| 422 | return 0; |
| 423 | } |
| 424 | static void inline amd64_remove_sysfs_dbg_files(struct mem_ctl_info *mci) |
| 425 | { |
| 426 | } |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 427 | #endif |
| 428 | |
| 429 | #ifdef CONFIG_EDAC_AMD64_ERROR_INJECTION |
Mauro Carvalho Chehab | c560875 | 2012-03-21 14:00:44 -0300 | [diff] [blame] | 430 | int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci); |
| 431 | void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci); |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 432 | |
Mauro Carvalho Chehab | c560875 | 2012-03-21 14:00:44 -0300 | [diff] [blame] | 433 | #else |
| 434 | static inline int amd64_create_sysfs_inject_files(struct mem_ctl_info *mci) |
| 435 | { |
| 436 | return 0; |
| 437 | } |
| 438 | static inline void amd64_remove_sysfs_inject_files(struct mem_ctl_info *mci) |
| 439 | { |
| 440 | } |
| 441 | #endif |
Doug Thompson | 7d6034d | 2009-04-27 20:01:01 +0200 | [diff] [blame] | 442 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 443 | /* |
| 444 | * Each of the PCI Device IDs types have their own set of hardware accessor |
| 445 | * functions and per device encoding/decoding logic. |
| 446 | */ |
| 447 | struct low_ops { |
Borislav Petkov | 1433eb9 | 2009-10-21 13:44:36 +0200 | [diff] [blame] | 448 | int (*early_channel_count) (struct amd64_pvt *pvt); |
Borislav Petkov | f192c7b | 2011-01-10 14:24:32 +0100 | [diff] [blame] | 449 | void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr, |
| 450 | u16 syndrome); |
Borislav Petkov | 41d8bfa | 2011-01-18 19:16:08 +0100 | [diff] [blame] | 451 | int (*dbam_to_cs) (struct amd64_pvt *pvt, u8 dct, unsigned cs_mode); |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 452 | int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset, |
| 453 | u32 *val, const char *func); |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 454 | }; |
| 455 | |
| 456 | struct amd64_family_type { |
| 457 | const char *ctl_name; |
Borislav Petkov | 8d5b5d9 | 2010-10-01 20:11:07 +0200 | [diff] [blame] | 458 | u16 f1_id, f3_id; |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 459 | struct low_ops ops; |
| 460 | }; |
| 461 | |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 462 | int __amd64_write_pci_cfg_dword(struct pci_dev *pdev, int offset, |
| 463 | u32 val, const char *func); |
Borislav Petkov | 6ba5dcd | 2009-10-13 19:26:55 +0200 | [diff] [blame] | 464 | |
| 465 | #define amd64_read_pci_cfg(pdev, offset, val) \ |
Borislav Petkov | b2b0c60 | 2010-10-08 18:32:29 +0200 | [diff] [blame] | 466 | __amd64_read_pci_cfg_dword(pdev, offset, val, __func__) |
| 467 | |
| 468 | #define amd64_write_pci_cfg(pdev, offset, val) \ |
| 469 | __amd64_write_pci_cfg_dword(pdev, offset, val, __func__) |
| 470 | |
| 471 | #define amd64_read_dct_pci_cfg(pvt, offset, val) \ |
| 472 | pvt->ops->read_dct_pci_cfg(pvt, offset, val, __func__) |
Borislav Petkov | 6ba5dcd | 2009-10-13 19:26:55 +0200 | [diff] [blame] | 473 | |
Doug Thompson | cfe40fd | 2009-05-04 19:25:34 +0200 | [diff] [blame] | 474 | int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base, |
| 475 | u64 *hole_offset, u64 *hole_size); |
Mauro Carvalho Chehab | c560875 | 2012-03-21 14:00:44 -0300 | [diff] [blame] | 476 | |
| 477 | #define to_mci(k) container_of(k, struct mem_ctl_info, dev) |