Liu Gang | 6ec4bed | 2011-11-12 20:02:28 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Freescale MPC85xx/MPC86xx RapidIO RMU support |
| 3 | * |
| 4 | * Copyright 2009 Sysgo AG |
| 5 | * Thomas Moll <thomas.moll@sysgo.com> |
| 6 | * - fixed maintenance access routines, check for aligned access |
| 7 | * |
| 8 | * Copyright 2009 Integrated Device Technology, Inc. |
| 9 | * Alex Bounine <alexandre.bounine@idt.com> |
| 10 | * - Added Port-Write message handling |
| 11 | * - Added Machine Check exception handling |
| 12 | * |
| 13 | * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc. |
| 14 | * Zhang Wei <wei.zhang@freescale.com> |
| 15 | * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com> |
| 16 | * Liu Gang <Gang.Liu@freescale.com> |
| 17 | * |
| 18 | * Copyright 2005 MontaVista Software, Inc. |
| 19 | * Matt Porter <mporter@kernel.crashing.org> |
| 20 | * |
| 21 | * This program is free software; you can redistribute it and/or modify it |
| 22 | * under the terms of the GNU General Public License as published by the |
| 23 | * Free Software Foundation; either version 2 of the License, or (at your |
| 24 | * option) any later version. |
| 25 | */ |
| 26 | |
| 27 | #include <linux/types.h> |
| 28 | #include <linux/dma-mapping.h> |
| 29 | #include <linux/interrupt.h> |
| 30 | #include <linux/of_platform.h> |
| 31 | #include <linux/slab.h> |
| 32 | |
| 33 | #include "fsl_rio.h" |
| 34 | |
| 35 | #define GET_RMM_HANDLE(mport) \ |
| 36 | (((struct rio_priv *)(mport->priv))->rmm_handle) |
| 37 | |
| 38 | /* RapidIO definition irq, which read from OF-tree */ |
| 39 | #define IRQ_RIO_PW(m) (((struct rio_priv *)(m->priv))->pwirq) |
| 40 | #define IRQ_RIO_BELL(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->bellirq) |
| 41 | #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq) |
| 42 | #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq) |
| 43 | |
| 44 | #define RIO_MIN_TX_RING_SIZE 2 |
| 45 | #define RIO_MAX_TX_RING_SIZE 2048 |
| 46 | #define RIO_MIN_RX_RING_SIZE 2 |
| 47 | #define RIO_MAX_RX_RING_SIZE 2048 |
| 48 | |
| 49 | #define RIO_IPWMR_SEN 0x00100000 |
| 50 | #define RIO_IPWMR_QFIE 0x00000100 |
| 51 | #define RIO_IPWMR_EIE 0x00000020 |
| 52 | #define RIO_IPWMR_CQ 0x00000002 |
| 53 | #define RIO_IPWMR_PWE 0x00000001 |
| 54 | |
| 55 | #define RIO_IPWSR_QF 0x00100000 |
| 56 | #define RIO_IPWSR_TE 0x00000080 |
| 57 | #define RIO_IPWSR_QFI 0x00000010 |
| 58 | #define RIO_IPWSR_PWD 0x00000008 |
| 59 | #define RIO_IPWSR_PWB 0x00000004 |
| 60 | |
| 61 | #define RIO_EPWISR 0x10010 |
| 62 | /* EPWISR Error match value */ |
| 63 | #define RIO_EPWISR_PINT1 0x80000000 |
| 64 | #define RIO_EPWISR_PINT2 0x40000000 |
| 65 | #define RIO_EPWISR_MU 0x00000002 |
| 66 | #define RIO_EPWISR_PW 0x00000001 |
| 67 | |
| 68 | #define IPWSR_CLEAR 0x98 |
| 69 | #define OMSR_CLEAR 0x1cb3 |
| 70 | #define IMSR_CLEAR 0x491 |
| 71 | #define IDSR_CLEAR 0x91 |
| 72 | #define ODSR_CLEAR 0x1c00 |
| 73 | #define LTLEECSR_ENABLE_ALL 0xFFC000FC |
| 74 | #define RIO_LTLEECSR 0x060c |
| 75 | |
| 76 | #define RIO_IM0SR 0x13064 |
| 77 | #define RIO_IM1SR 0x13164 |
| 78 | #define RIO_OM0SR 0x13004 |
| 79 | #define RIO_OM1SR 0x13104 |
| 80 | |
| 81 | #define RIO_P_MSG_REGS_OFFSET 0x11000 |
| 82 | #define RIO_S_MSG_REGS_OFFSET 0x13000 |
| 83 | |
| 84 | #define RIO_DBELL_WIN_SIZE 0x1000 |
| 85 | |
| 86 | #define RIO_MSG_OMR_MUI 0x00000002 |
| 87 | #define RIO_MSG_OSR_TE 0x00000080 |
| 88 | #define RIO_MSG_OSR_QOI 0x00000020 |
| 89 | #define RIO_MSG_OSR_QFI 0x00000010 |
| 90 | #define RIO_MSG_OSR_MUB 0x00000004 |
| 91 | #define RIO_MSG_OSR_EOMI 0x00000002 |
| 92 | #define RIO_MSG_OSR_QEI 0x00000001 |
| 93 | |
| 94 | #define RIO_MSG_IMR_MI 0x00000002 |
| 95 | #define RIO_MSG_ISR_TE 0x00000080 |
| 96 | #define RIO_MSG_ISR_QFI 0x00000010 |
| 97 | #define RIO_MSG_ISR_DIQI 0x00000001 |
| 98 | |
| 99 | #define RIO_MSG_DESC_SIZE 32 |
| 100 | #define RIO_MSG_BUFFER_SIZE 4096 |
| 101 | |
| 102 | #define DOORBELL_DMR_DI 0x00000002 |
| 103 | #define DOORBELL_DSR_TE 0x00000080 |
| 104 | #define DOORBELL_DSR_QFI 0x00000010 |
| 105 | #define DOORBELL_DSR_DIQI 0x00000001 |
| 106 | #define DOORBELL_TID_OFFSET 0x02 |
| 107 | #define DOORBELL_SID_OFFSET 0x04 |
| 108 | #define DOORBELL_INFO_OFFSET 0x06 |
| 109 | |
| 110 | #define DOORBELL_MESSAGE_SIZE 0x08 |
| 111 | #define DBELL_SID(x) (*(u16 *)(x + DOORBELL_SID_OFFSET)) |
| 112 | #define DBELL_TID(x) (*(u16 *)(x + DOORBELL_TID_OFFSET)) |
| 113 | #define DBELL_INF(x) (*(u16 *)(x + DOORBELL_INFO_OFFSET)) |
| 114 | |
| 115 | struct rio_msg_regs { |
| 116 | u32 omr; /* 0xD_3000 - Outbound message 0 mode register */ |
| 117 | u32 osr; /* 0xD_3004 - Outbound message 0 status register */ |
| 118 | u32 pad1; |
| 119 | u32 odqdpar; /* 0xD_300C - Outbound message 0 descriptor queue |
| 120 | dequeue pointer address register */ |
| 121 | u32 pad2; |
| 122 | u32 osar; /* 0xD_3014 - Outbound message 0 source address |
| 123 | register */ |
| 124 | u32 odpr; /* 0xD_3018 - Outbound message 0 destination port |
| 125 | register */ |
| 126 | u32 odatr; /* 0xD_301C - Outbound message 0 destination attributes |
| 127 | Register*/ |
| 128 | u32 odcr; /* 0xD_3020 - Outbound message 0 double-word count |
| 129 | register */ |
| 130 | u32 pad3; |
| 131 | u32 odqepar; /* 0xD_3028 - Outbound message 0 descriptor queue |
| 132 | enqueue pointer address register */ |
| 133 | u32 pad4[13]; |
| 134 | u32 imr; /* 0xD_3060 - Inbound message 0 mode register */ |
| 135 | u32 isr; /* 0xD_3064 - Inbound message 0 status register */ |
| 136 | u32 pad5; |
| 137 | u32 ifqdpar; /* 0xD_306C - Inbound message 0 frame queue dequeue |
| 138 | pointer address register*/ |
| 139 | u32 pad6; |
| 140 | u32 ifqepar; /* 0xD_3074 - Inbound message 0 frame queue enqueue |
| 141 | pointer address register */ |
| 142 | u32 pad7[226]; |
| 143 | u32 odmr; /* 0xD_3400 - Outbound doorbell mode register */ |
| 144 | u32 odsr; /* 0xD_3404 - Outbound doorbell status register */ |
| 145 | u32 res0[4]; |
| 146 | u32 oddpr; /* 0xD_3418 - Outbound doorbell destination port |
| 147 | register */ |
| 148 | u32 oddatr; /* 0xD_341c - Outbound doorbell destination attributes |
| 149 | register */ |
| 150 | u32 res1[3]; |
| 151 | u32 odretcr; /* 0xD_342C - Outbound doorbell retry error threshold |
| 152 | configuration register */ |
| 153 | u32 res2[12]; |
| 154 | u32 dmr; /* 0xD_3460 - Inbound doorbell mode register */ |
| 155 | u32 dsr; /* 0xD_3464 - Inbound doorbell status register */ |
| 156 | u32 pad8; |
| 157 | u32 dqdpar; /* 0xD_346C - Inbound doorbell queue dequeue Pointer |
| 158 | address register */ |
| 159 | u32 pad9; |
| 160 | u32 dqepar; /* 0xD_3474 - Inbound doorbell Queue enqueue pointer |
| 161 | address register */ |
| 162 | u32 pad10[26]; |
| 163 | u32 pwmr; /* 0xD_34E0 - Inbound port-write mode register */ |
| 164 | u32 pwsr; /* 0xD_34E4 - Inbound port-write status register */ |
| 165 | u32 epwqbar; /* 0xD_34E8 - Extended Port-Write Queue Base Address |
| 166 | register */ |
| 167 | u32 pwqbar; /* 0xD_34EC - Inbound port-write queue base address |
| 168 | register */ |
| 169 | }; |
| 170 | |
| 171 | struct rio_tx_desc { |
| 172 | u32 res1; |
| 173 | u32 saddr; |
| 174 | u32 dport; |
| 175 | u32 dattr; |
| 176 | u32 res2; |
| 177 | u32 res3; |
| 178 | u32 dwcnt; |
| 179 | u32 res4; |
| 180 | }; |
| 181 | |
| 182 | struct rio_dbell_ring { |
| 183 | void *virt; |
| 184 | dma_addr_t phys; |
| 185 | }; |
| 186 | |
| 187 | struct rio_msg_tx_ring { |
| 188 | void *virt; |
| 189 | dma_addr_t phys; |
| 190 | void *virt_buffer[RIO_MAX_TX_RING_SIZE]; |
| 191 | dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE]; |
| 192 | int tx_slot; |
| 193 | int size; |
| 194 | void *dev_id; |
| 195 | }; |
| 196 | |
| 197 | struct rio_msg_rx_ring { |
| 198 | void *virt; |
| 199 | dma_addr_t phys; |
| 200 | void *virt_buffer[RIO_MAX_RX_RING_SIZE]; |
| 201 | int rx_slot; |
| 202 | int size; |
| 203 | void *dev_id; |
| 204 | }; |
| 205 | |
| 206 | struct fsl_rmu { |
| 207 | struct rio_atmu_regs __iomem *dbell_atmu_regs; |
| 208 | void __iomem *dbell_win; |
| 209 | struct rio_msg_regs __iomem *msg_regs; |
| 210 | struct rio_dbell_ring dbell_ring; |
| 211 | struct rio_msg_tx_ring msg_tx_ring; |
| 212 | struct rio_msg_rx_ring msg_rx_ring; |
| 213 | int bellirq; |
| 214 | int txirq; |
| 215 | int rxirq; |
| 216 | }; |
| 217 | |
| 218 | /** |
| 219 | * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler |
| 220 | * @irq: Linux interrupt number |
| 221 | * @dev_instance: Pointer to interrupt-specific data |
| 222 | * |
| 223 | * Handles outbound message interrupts. Executes a register outbound |
| 224 | * mailbox event handler and acks the interrupt occurrence. |
| 225 | */ |
| 226 | static irqreturn_t |
| 227 | fsl_rio_tx_handler(int irq, void *dev_instance) |
| 228 | { |
| 229 | int osr; |
| 230 | struct rio_mport *port = (struct rio_mport *)dev_instance; |
| 231 | struct fsl_rmu *rmu = GET_RMM_HANDLE(port); |
| 232 | |
| 233 | osr = in_be32(&rmu->msg_regs->osr); |
| 234 | |
| 235 | if (osr & RIO_MSG_OSR_TE) { |
| 236 | pr_info("RIO: outbound message transmission error\n"); |
| 237 | out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE); |
| 238 | goto out; |
| 239 | } |
| 240 | |
| 241 | if (osr & RIO_MSG_OSR_QOI) { |
| 242 | pr_info("RIO: outbound message queue overflow\n"); |
| 243 | out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI); |
| 244 | goto out; |
| 245 | } |
| 246 | |
| 247 | if (osr & RIO_MSG_OSR_EOMI) { |
| 248 | u32 dqp = in_be32(&rmu->msg_regs->odqdpar); |
| 249 | int slot = (dqp - rmu->msg_tx_ring.phys) >> 5; |
| 250 | port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id, -1, |
| 251 | slot); |
| 252 | |
| 253 | /* Ack the end-of-message interrupt */ |
| 254 | out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI); |
| 255 | } |
| 256 | |
| 257 | out: |
| 258 | return IRQ_HANDLED; |
| 259 | } |
| 260 | |
| 261 | /** |
| 262 | * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler |
| 263 | * @irq: Linux interrupt number |
| 264 | * @dev_instance: Pointer to interrupt-specific data |
| 265 | * |
| 266 | * Handles inbound message interrupts. Executes a registered inbound |
| 267 | * mailbox event handler and acks the interrupt occurrence. |
| 268 | */ |
| 269 | static irqreturn_t |
| 270 | fsl_rio_rx_handler(int irq, void *dev_instance) |
| 271 | { |
| 272 | int isr; |
| 273 | struct rio_mport *port = (struct rio_mport *)dev_instance; |
| 274 | struct fsl_rmu *rmu = GET_RMM_HANDLE(port); |
| 275 | |
| 276 | isr = in_be32(&rmu->msg_regs->isr); |
| 277 | |
| 278 | if (isr & RIO_MSG_ISR_TE) { |
| 279 | pr_info("RIO: inbound message reception error\n"); |
| 280 | out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE); |
| 281 | goto out; |
| 282 | } |
| 283 | |
| 284 | /* XXX Need to check/dispatch until queue empty */ |
| 285 | if (isr & RIO_MSG_ISR_DIQI) { |
| 286 | /* |
| 287 | * We implement *only* mailbox 0, but can receive messages |
| 288 | * for any mailbox/letter to that mailbox destination. So, |
| 289 | * make the callback with an unknown/invalid mailbox number |
| 290 | * argument. |
| 291 | */ |
| 292 | port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id, -1, -1); |
| 293 | |
| 294 | /* Ack the queueing interrupt */ |
| 295 | out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI); |
| 296 | } |
| 297 | |
| 298 | out: |
| 299 | return IRQ_HANDLED; |
| 300 | } |
| 301 | |
| 302 | /** |
| 303 | * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler |
| 304 | * @irq: Linux interrupt number |
| 305 | * @dev_instance: Pointer to interrupt-specific data |
| 306 | * |
| 307 | * Handles doorbell interrupts. Parses a list of registered |
| 308 | * doorbell event handlers and executes a matching event handler. |
| 309 | */ |
| 310 | static irqreturn_t |
| 311 | fsl_rio_dbell_handler(int irq, void *dev_instance) |
| 312 | { |
| 313 | int dsr; |
| 314 | struct rio_mport *port = (struct rio_mport *)dev_instance; |
| 315 | struct fsl_rmu *rmu = GET_RMM_HANDLE(port); |
| 316 | |
| 317 | dsr = in_be32(&rmu->msg_regs->dsr); |
| 318 | |
| 319 | if (dsr & DOORBELL_DSR_TE) { |
| 320 | pr_info("RIO: doorbell reception error\n"); |
| 321 | out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_TE); |
| 322 | goto out; |
| 323 | } |
| 324 | |
| 325 | if (dsr & DOORBELL_DSR_QFI) { |
| 326 | pr_info("RIO: doorbell queue full\n"); |
| 327 | out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_QFI); |
| 328 | } |
| 329 | |
| 330 | /* XXX Need to check/dispatch until queue empty */ |
| 331 | if (dsr & DOORBELL_DSR_DIQI) { |
| 332 | u32 dmsg = |
| 333 | (u32) rmu->dbell_ring.virt + |
| 334 | (in_be32(&rmu->msg_regs->dqdpar) & 0xfff); |
| 335 | struct rio_dbell *dbell; |
| 336 | int found = 0; |
| 337 | |
| 338 | pr_debug |
| 339 | ("RIO: processing doorbell," |
| 340 | " sid %2.2x tid %2.2x info %4.4x\n", |
| 341 | DBELL_SID(dmsg), DBELL_TID(dmsg), DBELL_INF(dmsg)); |
| 342 | |
| 343 | list_for_each_entry(dbell, &port->dbells, node) { |
| 344 | if ((dbell->res->start <= DBELL_INF(dmsg)) && |
| 345 | (dbell->res->end >= DBELL_INF(dmsg))) { |
| 346 | found = 1; |
| 347 | break; |
| 348 | } |
| 349 | } |
| 350 | if (found) { |
| 351 | dbell->dinb(port, dbell->dev_id, |
| 352 | DBELL_SID(dmsg), |
| 353 | DBELL_TID(dmsg), DBELL_INF(dmsg)); |
| 354 | } else { |
| 355 | pr_debug |
| 356 | ("RIO: spurious doorbell," |
| 357 | " sid %2.2x tid %2.2x info %4.4x\n", |
| 358 | DBELL_SID(dmsg), DBELL_TID(dmsg), |
| 359 | DBELL_INF(dmsg)); |
| 360 | } |
| 361 | setbits32(&rmu->msg_regs->dmr, DOORBELL_DMR_DI); |
| 362 | out_be32(&rmu->msg_regs->dsr, DOORBELL_DSR_DIQI); |
| 363 | } |
| 364 | |
| 365 | out: |
| 366 | return IRQ_HANDLED; |
| 367 | } |
| 368 | |
| 369 | void msg_unit_error_handler(struct rio_mport *port) |
| 370 | { |
| 371 | struct fsl_rmu *rmu = GET_RMM_HANDLE(port); |
| 372 | |
| 373 | /*XXX: Error recovery is not implemented, we just clear errors */ |
| 374 | out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0); |
| 375 | |
| 376 | out_be32((u32 *)(rio_regs_win + RIO_IM0SR), IMSR_CLEAR); |
| 377 | out_be32((u32 *)(rio_regs_win + RIO_IM1SR), IMSR_CLEAR); |
| 378 | out_be32((u32 *)(rio_regs_win + RIO_OM0SR), OMSR_CLEAR); |
| 379 | out_be32((u32 *)(rio_regs_win + RIO_OM1SR), OMSR_CLEAR); |
| 380 | |
| 381 | out_be32(&rmu->msg_regs->odsr, ODSR_CLEAR); |
| 382 | out_be32(&rmu->msg_regs->dsr, IDSR_CLEAR); |
| 383 | |
| 384 | out_be32(&rmu->msg_regs->pwsr, IPWSR_CLEAR); |
| 385 | } |
| 386 | |
| 387 | /** |
| 388 | * fsl_rio_port_write_handler - MPC85xx port write interrupt handler |
| 389 | * @irq: Linux interrupt number |
| 390 | * @dev_instance: Pointer to interrupt-specific data |
| 391 | * |
| 392 | * Handles port write interrupts. Parses a list of registered |
| 393 | * port write event handlers and executes a matching event handler. |
| 394 | */ |
| 395 | static irqreturn_t |
| 396 | fsl_rio_port_write_handler(int irq, void *dev_instance) |
| 397 | { |
| 398 | u32 ipwmr, ipwsr; |
| 399 | struct rio_mport *port = (struct rio_mport *)dev_instance; |
| 400 | struct rio_priv *priv = port->priv; |
| 401 | struct fsl_rmu *rmu; |
| 402 | u32 epwisr, tmp; |
| 403 | |
| 404 | rmu = GET_RMM_HANDLE(port); |
| 405 | epwisr = in_be32(priv->regs_win + RIO_EPWISR); |
| 406 | if (!(epwisr & RIO_EPWISR_PW)) |
| 407 | goto pw_done; |
| 408 | |
| 409 | ipwmr = in_be32(&rmu->msg_regs->pwmr); |
| 410 | ipwsr = in_be32(&rmu->msg_regs->pwsr); |
| 411 | |
| 412 | #ifdef DEBUG_PW |
| 413 | pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr); |
| 414 | if (ipwsr & RIO_IPWSR_QF) |
| 415 | pr_debug(" QF"); |
| 416 | if (ipwsr & RIO_IPWSR_TE) |
| 417 | pr_debug(" TE"); |
| 418 | if (ipwsr & RIO_IPWSR_QFI) |
| 419 | pr_debug(" QFI"); |
| 420 | if (ipwsr & RIO_IPWSR_PWD) |
| 421 | pr_debug(" PWD"); |
| 422 | if (ipwsr & RIO_IPWSR_PWB) |
| 423 | pr_debug(" PWB"); |
| 424 | pr_debug(" )\n"); |
| 425 | #endif |
| 426 | /* Schedule deferred processing if PW was received */ |
| 427 | if (ipwsr & RIO_IPWSR_QFI) { |
| 428 | /* Save PW message (if there is room in FIFO), |
| 429 | * otherwise discard it. |
| 430 | */ |
| 431 | if (kfifo_avail(&priv->pw_fifo) >= RIO_PW_MSG_SIZE) { |
| 432 | priv->port_write_msg.msg_count++; |
| 433 | kfifo_in(&priv->pw_fifo, priv->port_write_msg.virt, |
| 434 | RIO_PW_MSG_SIZE); |
| 435 | } else { |
| 436 | priv->port_write_msg.discard_count++; |
| 437 | pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n", |
| 438 | priv->port_write_msg.discard_count); |
| 439 | } |
| 440 | /* Clear interrupt and issue Clear Queue command. This allows |
| 441 | * another port-write to be received. |
| 442 | */ |
| 443 | out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_QFI); |
| 444 | out_be32(&rmu->msg_regs->pwmr, ipwmr | RIO_IPWMR_CQ); |
| 445 | |
| 446 | schedule_work(&priv->pw_work); |
| 447 | } |
| 448 | |
| 449 | if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) { |
| 450 | priv->port_write_msg.err_count++; |
| 451 | pr_debug("RIO: Port-Write Transaction Err (%d)\n", |
| 452 | priv->port_write_msg.err_count); |
| 453 | /* Clear Transaction Error: port-write controller should be |
| 454 | * disabled when clearing this error |
| 455 | */ |
| 456 | out_be32(&rmu->msg_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE); |
| 457 | out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_TE); |
| 458 | out_be32(&rmu->msg_regs->pwmr, ipwmr); |
| 459 | } |
| 460 | |
| 461 | if (ipwsr & RIO_IPWSR_PWD) { |
| 462 | priv->port_write_msg.discard_count++; |
| 463 | pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n", |
| 464 | priv->port_write_msg.discard_count); |
| 465 | out_be32(&rmu->msg_regs->pwsr, RIO_IPWSR_PWD); |
| 466 | } |
| 467 | |
| 468 | pw_done: |
| 469 | if (epwisr & RIO_EPWISR_PINT1) { |
| 470 | tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); |
| 471 | pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); |
| 472 | fsl_rio_port_error_handler(port, 0); |
| 473 | } |
| 474 | |
| 475 | if (epwisr & RIO_EPWISR_PINT2) { |
| 476 | tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); |
| 477 | pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); |
| 478 | fsl_rio_port_error_handler(port, 1); |
| 479 | } |
| 480 | |
| 481 | if (epwisr & RIO_EPWISR_MU) { |
| 482 | tmp = in_be32(priv->regs_win + RIO_LTLEDCSR); |
| 483 | pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp); |
| 484 | msg_unit_error_handler(port); |
| 485 | } |
| 486 | |
| 487 | return IRQ_HANDLED; |
| 488 | } |
| 489 | |
| 490 | static void fsl_pw_dpc(struct work_struct *work) |
| 491 | { |
| 492 | struct rio_priv *priv = container_of(work, struct rio_priv, pw_work); |
| 493 | unsigned long flags; |
| 494 | u32 msg_buffer[RIO_PW_MSG_SIZE/sizeof(u32)]; |
| 495 | |
| 496 | /* |
| 497 | * Process port-write messages |
| 498 | */ |
| 499 | spin_lock_irqsave(&priv->pw_fifo_lock, flags); |
| 500 | while (kfifo_out(&priv->pw_fifo, (unsigned char *)msg_buffer, |
| 501 | RIO_PW_MSG_SIZE)) { |
| 502 | /* Process one message */ |
| 503 | spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); |
| 504 | #ifdef DEBUG_PW |
| 505 | { |
| 506 | u32 i; |
| 507 | pr_debug("%s : Port-Write Message:", __func__); |
| 508 | for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) { |
| 509 | if ((i%4) == 0) |
| 510 | pr_debug("\n0x%02x: 0x%08x", i*4, |
| 511 | msg_buffer[i]); |
| 512 | else |
| 513 | pr_debug(" 0x%08x", msg_buffer[i]); |
| 514 | } |
| 515 | pr_debug("\n"); |
| 516 | } |
| 517 | #endif |
| 518 | /* Pass the port-write message to RIO core for processing */ |
| 519 | rio_inb_pwrite_handler((union rio_pw_msg *)msg_buffer); |
| 520 | spin_lock_irqsave(&priv->pw_fifo_lock, flags); |
| 521 | } |
| 522 | spin_unlock_irqrestore(&priv->pw_fifo_lock, flags); |
| 523 | } |
| 524 | |
| 525 | /** |
| 526 | * fsl_rio_pw_enable - enable/disable port-write interface init |
| 527 | * @mport: Master port implementing the port write unit |
| 528 | * @enable: 1=enable; 0=disable port-write message handling |
| 529 | */ |
| 530 | int fsl_rio_pw_enable(struct rio_mport *mport, int enable) |
| 531 | { |
| 532 | struct fsl_rmu *rmu; |
| 533 | u32 rval; |
| 534 | |
| 535 | rmu = GET_RMM_HANDLE(mport); |
| 536 | |
| 537 | rval = in_be32(&rmu->msg_regs->pwmr); |
| 538 | |
| 539 | if (enable) |
| 540 | rval |= RIO_IPWMR_PWE; |
| 541 | else |
| 542 | rval &= ~RIO_IPWMR_PWE; |
| 543 | |
| 544 | out_be32(&rmu->msg_regs->pwmr, rval); |
| 545 | |
| 546 | return 0; |
| 547 | } |
| 548 | |
| 549 | /** |
| 550 | * fsl_rio_port_write_init - MPC85xx port write interface init |
| 551 | * @mport: Master port implementing the port write unit |
| 552 | * |
| 553 | * Initializes port write unit hardware and DMA buffer |
| 554 | * ring. Called from fsl_rio_setup(). Returns %0 on success |
| 555 | * or %-ENOMEM on failure. |
| 556 | */ |
| 557 | |
| 558 | int fsl_rio_port_write_init(struct rio_mport *mport) |
| 559 | { |
| 560 | struct rio_priv *priv = mport->priv; |
| 561 | struct fsl_rmu *rmu; |
| 562 | int rc = 0; |
| 563 | |
| 564 | rmu = GET_RMM_HANDLE(mport); |
| 565 | |
| 566 | /* Following configurations require a disabled port write controller */ |
| 567 | out_be32(&rmu->msg_regs->pwmr, |
| 568 | in_be32(&rmu->msg_regs->pwmr) & ~RIO_IPWMR_PWE); |
| 569 | |
| 570 | /* Initialize port write */ |
| 571 | priv->port_write_msg.virt = dma_alloc_coherent(priv->dev, |
| 572 | RIO_PW_MSG_SIZE, |
| 573 | &priv->port_write_msg.phys, GFP_KERNEL); |
| 574 | if (!priv->port_write_msg.virt) { |
| 575 | pr_err("RIO: unable allocate port write queue\n"); |
| 576 | return -ENOMEM; |
| 577 | } |
| 578 | |
| 579 | priv->port_write_msg.err_count = 0; |
| 580 | priv->port_write_msg.discard_count = 0; |
| 581 | |
| 582 | /* Point dequeue/enqueue pointers at first entry */ |
| 583 | out_be32(&rmu->msg_regs->epwqbar, 0); |
| 584 | out_be32(&rmu->msg_regs->pwqbar, (u32) priv->port_write_msg.phys); |
| 585 | |
| 586 | pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n", |
| 587 | in_be32(&rmu->msg_regs->epwqbar), |
| 588 | in_be32(&rmu->msg_regs->pwqbar)); |
| 589 | |
| 590 | /* Clear interrupt status IPWSR */ |
| 591 | out_be32(&rmu->msg_regs->pwsr, |
| 592 | (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD)); |
| 593 | |
| 594 | /* Configure port write contoller for snooping enable all reporting, |
| 595 | clear queue full */ |
| 596 | out_be32(&rmu->msg_regs->pwmr, |
| 597 | RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ); |
| 598 | |
| 599 | |
| 600 | /* Hook up port-write handler */ |
| 601 | rc = request_irq(IRQ_RIO_PW(mport), fsl_rio_port_write_handler, |
| 602 | IRQF_SHARED, "port-write", (void *)mport); |
| 603 | if (rc < 0) { |
| 604 | pr_err("MPC85xx RIO: unable to request inbound doorbell irq"); |
| 605 | goto err_out; |
| 606 | } |
| 607 | /* Enable Error Interrupt */ |
| 608 | out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL); |
| 609 | |
| 610 | INIT_WORK(&priv->pw_work, fsl_pw_dpc); |
| 611 | spin_lock_init(&priv->pw_fifo_lock); |
| 612 | if (kfifo_alloc(&priv->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) { |
| 613 | pr_err("FIFO allocation failed\n"); |
| 614 | rc = -ENOMEM; |
| 615 | goto err_out_irq; |
| 616 | } |
| 617 | |
| 618 | pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n", |
| 619 | in_be32(&rmu->msg_regs->pwmr), |
| 620 | in_be32(&rmu->msg_regs->pwsr)); |
| 621 | |
| 622 | return rc; |
| 623 | |
| 624 | err_out_irq: |
| 625 | free_irq(IRQ_RIO_PW(mport), (void *)mport); |
| 626 | err_out: |
| 627 | dma_free_coherent(priv->dev, RIO_PW_MSG_SIZE, |
| 628 | priv->port_write_msg.virt, |
| 629 | priv->port_write_msg.phys); |
| 630 | return rc; |
| 631 | } |
| 632 | |
| 633 | /** |
| 634 | * fsl_rio_doorbell_send - Send a MPC85xx doorbell message |
| 635 | * @mport: RapidIO master port info |
| 636 | * @index: ID of RapidIO interface |
| 637 | * @destid: Destination ID of target device |
| 638 | * @data: 16-bit info field of RapidIO doorbell message |
| 639 | * |
| 640 | * Sends a MPC85xx doorbell message. Returns %0 on success or |
| 641 | * %-EINVAL on failure. |
| 642 | */ |
| 643 | static int fsl_rio_doorbell_send(struct rio_mport *mport, |
| 644 | int index, u16 destid, u16 data) |
| 645 | { |
| 646 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 647 | |
| 648 | pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n", |
| 649 | index, destid, data); |
| 650 | switch (mport->phy_type) { |
| 651 | case RIO_PHY_PARALLEL: |
| 652 | out_be32(&rmu->dbell_atmu_regs->rowtar, destid << 22); |
| 653 | out_be16(rmu->dbell_win, data); |
| 654 | break; |
| 655 | case RIO_PHY_SERIAL: |
| 656 | /* In the serial version silicons, such as MPC8548, MPC8641, |
| 657 | * below operations is must be. |
| 658 | */ |
| 659 | out_be32(&rmu->msg_regs->odmr, 0x00000000); |
| 660 | out_be32(&rmu->msg_regs->odretcr, 0x00000004); |
| 661 | out_be32(&rmu->msg_regs->oddpr, destid << 16); |
| 662 | out_be32(&rmu->msg_regs->oddatr, data); |
| 663 | out_be32(&rmu->msg_regs->odmr, 0x00000001); |
| 664 | break; |
| 665 | } |
| 666 | |
| 667 | return 0; |
| 668 | } |
| 669 | |
| 670 | /** |
| 671 | * fsl_add_outb_message - Add message to the MPC85xx outbound message queue |
| 672 | * @mport: Master port with outbound message queue |
| 673 | * @rdev: Target of outbound message |
| 674 | * @mbox: Outbound mailbox |
| 675 | * @buffer: Message to add to outbound queue |
| 676 | * @len: Length of message |
| 677 | * |
| 678 | * Adds the @buffer message to the MPC85xx outbound message queue. Returns |
| 679 | * %0 on success or %-EINVAL on failure. |
| 680 | */ |
| 681 | static int |
| 682 | fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox, |
| 683 | void *buffer, size_t len) |
| 684 | { |
| 685 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 686 | u32 omr; |
| 687 | struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt |
| 688 | + rmu->msg_tx_ring.tx_slot; |
| 689 | int ret = 0; |
| 690 | |
| 691 | pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \ |
| 692 | "%8.8x len %8.8x\n", rdev->destid, mbox, (int)buffer, len); |
| 693 | |
| 694 | if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) { |
| 695 | ret = -EINVAL; |
| 696 | goto out; |
| 697 | } |
| 698 | |
| 699 | /* Copy and clear rest of buffer */ |
| 700 | memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer, |
| 701 | len); |
| 702 | if (len < (RIO_MAX_MSG_SIZE - 4)) |
| 703 | memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot] |
| 704 | + len, 0, RIO_MAX_MSG_SIZE - len); |
| 705 | |
| 706 | switch (mport->phy_type) { |
| 707 | case RIO_PHY_PARALLEL: |
| 708 | /* Set mbox field for message */ |
| 709 | desc->dport = mbox & 0x3; |
| 710 | |
| 711 | /* Enable EOMI interrupt, set priority, and set destid */ |
| 712 | desc->dattr = 0x28000000 | (rdev->destid << 2); |
| 713 | break; |
| 714 | case RIO_PHY_SERIAL: |
| 715 | /* Set mbox field for message, and set destid */ |
| 716 | desc->dport = (rdev->destid << 16) | (mbox & 0x3); |
| 717 | |
| 718 | /* Enable EOMI interrupt and priority */ |
| 719 | desc->dattr = 0x28000000; |
| 720 | break; |
| 721 | } |
| 722 | |
| 723 | /* Set transfer size aligned to next power of 2 (in double words) */ |
| 724 | desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len); |
| 725 | |
| 726 | /* Set snooping and source buffer address */ |
| 727 | desc->saddr = 0x00000004 |
| 728 | | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot]; |
| 729 | |
| 730 | /* Increment enqueue pointer */ |
| 731 | omr = in_be32(&rmu->msg_regs->omr); |
| 732 | out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI); |
| 733 | |
| 734 | /* Go to next descriptor */ |
| 735 | if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size) |
| 736 | rmu->msg_tx_ring.tx_slot = 0; |
| 737 | |
| 738 | out: |
| 739 | return ret; |
| 740 | } |
| 741 | |
| 742 | /** |
| 743 | * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox |
| 744 | * @mport: Master port implementing the outbound message unit |
| 745 | * @dev_id: Device specific pointer to pass on event |
| 746 | * @mbox: Mailbox to open |
| 747 | * @entries: Number of entries in the outbound mailbox ring |
| 748 | * |
| 749 | * Initializes buffer ring, request the outbound message interrupt, |
| 750 | * and enables the outbound message unit. Returns %0 on success and |
| 751 | * %-EINVAL or %-ENOMEM on failure. |
| 752 | */ |
| 753 | static int |
| 754 | fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) |
| 755 | { |
| 756 | int i, j, rc = 0; |
| 757 | struct rio_priv *priv = mport->priv; |
| 758 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 759 | |
| 760 | if ((entries < RIO_MIN_TX_RING_SIZE) || |
| 761 | (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) { |
| 762 | rc = -EINVAL; |
| 763 | goto out; |
| 764 | } |
| 765 | |
| 766 | /* Initialize shadow copy ring */ |
| 767 | rmu->msg_tx_ring.dev_id = dev_id; |
| 768 | rmu->msg_tx_ring.size = entries; |
| 769 | |
| 770 | for (i = 0; i < rmu->msg_tx_ring.size; i++) { |
| 771 | rmu->msg_tx_ring.virt_buffer[i] = |
| 772 | dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, |
| 773 | &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL); |
| 774 | if (!rmu->msg_tx_ring.virt_buffer[i]) { |
| 775 | rc = -ENOMEM; |
| 776 | for (j = 0; j < rmu->msg_tx_ring.size; j++) |
| 777 | if (rmu->msg_tx_ring.virt_buffer[j]) |
| 778 | dma_free_coherent(priv->dev, |
| 779 | RIO_MSG_BUFFER_SIZE, |
| 780 | rmu->msg_tx_ring. |
| 781 | virt_buffer[j], |
| 782 | rmu->msg_tx_ring. |
| 783 | phys_buffer[j]); |
| 784 | goto out; |
| 785 | } |
| 786 | } |
| 787 | |
| 788 | /* Initialize outbound message descriptor ring */ |
| 789 | rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev, |
| 790 | rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, |
| 791 | &rmu->msg_tx_ring.phys, GFP_KERNEL); |
| 792 | if (!rmu->msg_tx_ring.virt) { |
| 793 | rc = -ENOMEM; |
| 794 | goto out_dma; |
| 795 | } |
| 796 | memset(rmu->msg_tx_ring.virt, 0, |
| 797 | rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE); |
| 798 | rmu->msg_tx_ring.tx_slot = 0; |
| 799 | |
| 800 | /* Point dequeue/enqueue pointers at first entry in ring */ |
| 801 | out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys); |
| 802 | out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys); |
| 803 | |
| 804 | /* Configure for snooping */ |
| 805 | out_be32(&rmu->msg_regs->osar, 0x00000004); |
| 806 | |
| 807 | /* Clear interrupt status */ |
| 808 | out_be32(&rmu->msg_regs->osr, 0x000000b3); |
| 809 | |
| 810 | /* Hook up outbound message handler */ |
| 811 | rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0, |
| 812 | "msg_tx", (void *)mport); |
| 813 | if (rc < 0) |
| 814 | goto out_irq; |
| 815 | |
| 816 | /* |
| 817 | * Configure outbound message unit |
| 818 | * Snooping |
| 819 | * Interrupts (all enabled, except QEIE) |
| 820 | * Chaining mode |
| 821 | * Disable |
| 822 | */ |
| 823 | out_be32(&rmu->msg_regs->omr, 0x00100220); |
| 824 | |
| 825 | /* Set number of entries */ |
| 826 | out_be32(&rmu->msg_regs->omr, |
| 827 | in_be32(&rmu->msg_regs->omr) | |
| 828 | ((get_bitmask_order(entries) - 2) << 12)); |
| 829 | |
| 830 | /* Now enable the unit */ |
| 831 | out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1); |
| 832 | |
| 833 | out: |
| 834 | return rc; |
| 835 | |
| 836 | out_irq: |
| 837 | dma_free_coherent(priv->dev, |
| 838 | rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, |
| 839 | rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); |
| 840 | |
| 841 | out_dma: |
| 842 | for (i = 0; i < rmu->msg_tx_ring.size; i++) |
| 843 | dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, |
| 844 | rmu->msg_tx_ring.virt_buffer[i], |
| 845 | rmu->msg_tx_ring.phys_buffer[i]); |
| 846 | |
| 847 | return rc; |
| 848 | } |
| 849 | |
| 850 | /** |
| 851 | * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox |
| 852 | * @mport: Master port implementing the outbound message unit |
| 853 | * @mbox: Mailbox to close |
| 854 | * |
| 855 | * Disables the outbound message unit, free all buffers, and |
| 856 | * frees the outbound message interrupt. |
| 857 | */ |
| 858 | static void fsl_close_outb_mbox(struct rio_mport *mport, int mbox) |
| 859 | { |
| 860 | struct rio_priv *priv = mport->priv; |
| 861 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 862 | |
| 863 | /* Disable inbound message unit */ |
| 864 | out_be32(&rmu->msg_regs->omr, 0); |
| 865 | |
| 866 | /* Free ring */ |
| 867 | dma_free_coherent(priv->dev, |
| 868 | rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE, |
| 869 | rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys); |
| 870 | |
| 871 | /* Free interrupt */ |
| 872 | free_irq(IRQ_RIO_TX(mport), (void *)mport); |
| 873 | } |
| 874 | |
| 875 | /** |
| 876 | * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox |
| 877 | * @mport: Master port implementing the inbound message unit |
| 878 | * @dev_id: Device specific pointer to pass on event |
| 879 | * @mbox: Mailbox to open |
| 880 | * @entries: Number of entries in the inbound mailbox ring |
| 881 | * |
| 882 | * Initializes buffer ring, request the inbound message interrupt, |
| 883 | * and enables the inbound message unit. Returns %0 on success |
| 884 | * and %-EINVAL or %-ENOMEM on failure. |
| 885 | */ |
| 886 | static int |
| 887 | fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries) |
| 888 | { |
| 889 | int i, rc = 0; |
| 890 | struct rio_priv *priv = mport->priv; |
| 891 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 892 | |
| 893 | if ((entries < RIO_MIN_RX_RING_SIZE) || |
| 894 | (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) { |
| 895 | rc = -EINVAL; |
| 896 | goto out; |
| 897 | } |
| 898 | |
| 899 | /* Initialize client buffer ring */ |
| 900 | rmu->msg_rx_ring.dev_id = dev_id; |
| 901 | rmu->msg_rx_ring.size = entries; |
| 902 | rmu->msg_rx_ring.rx_slot = 0; |
| 903 | for (i = 0; i < rmu->msg_rx_ring.size; i++) |
| 904 | rmu->msg_rx_ring.virt_buffer[i] = NULL; |
| 905 | |
| 906 | /* Initialize inbound message ring */ |
| 907 | rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev, |
| 908 | rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, |
| 909 | &rmu->msg_rx_ring.phys, GFP_KERNEL); |
| 910 | if (!rmu->msg_rx_ring.virt) { |
| 911 | rc = -ENOMEM; |
| 912 | goto out; |
| 913 | } |
| 914 | |
| 915 | /* Point dequeue/enqueue pointers at first entry in ring */ |
| 916 | out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys); |
| 917 | out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys); |
| 918 | |
| 919 | /* Clear interrupt status */ |
| 920 | out_be32(&rmu->msg_regs->isr, 0x00000091); |
| 921 | |
| 922 | /* Hook up inbound message handler */ |
| 923 | rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0, |
| 924 | "msg_rx", (void *)mport); |
| 925 | if (rc < 0) { |
| 926 | dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE, |
| 927 | rmu->msg_tx_ring.virt_buffer[i], |
| 928 | rmu->msg_tx_ring.phys_buffer[i]); |
| 929 | goto out; |
| 930 | } |
| 931 | |
| 932 | /* |
| 933 | * Configure inbound message unit: |
| 934 | * Snooping |
| 935 | * 4KB max message size |
| 936 | * Unmask all interrupt sources |
| 937 | * Disable |
| 938 | */ |
| 939 | out_be32(&rmu->msg_regs->imr, 0x001b0060); |
| 940 | |
| 941 | /* Set number of queue entries */ |
| 942 | setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12); |
| 943 | |
| 944 | /* Now enable the unit */ |
| 945 | setbits32(&rmu->msg_regs->imr, 0x1); |
| 946 | |
| 947 | out: |
| 948 | return rc; |
| 949 | } |
| 950 | |
| 951 | /** |
| 952 | * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox |
| 953 | * @mport: Master port implementing the inbound message unit |
| 954 | * @mbox: Mailbox to close |
| 955 | * |
| 956 | * Disables the inbound message unit, free all buffers, and |
| 957 | * frees the inbound message interrupt. |
| 958 | */ |
| 959 | static void fsl_close_inb_mbox(struct rio_mport *mport, int mbox) |
| 960 | { |
| 961 | struct rio_priv *priv = mport->priv; |
| 962 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 963 | |
| 964 | /* Disable inbound message unit */ |
| 965 | out_be32(&rmu->msg_regs->imr, 0); |
| 966 | |
| 967 | /* Free ring */ |
| 968 | dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE, |
| 969 | rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys); |
| 970 | |
| 971 | /* Free interrupt */ |
| 972 | free_irq(IRQ_RIO_RX(mport), (void *)mport); |
| 973 | } |
| 974 | |
| 975 | /** |
| 976 | * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue |
| 977 | * @mport: Master port implementing the inbound message unit |
| 978 | * @mbox: Inbound mailbox number |
| 979 | * @buf: Buffer to add to inbound queue |
| 980 | * |
| 981 | * Adds the @buf buffer to the MPC85xx inbound message queue. Returns |
| 982 | * %0 on success or %-EINVAL on failure. |
| 983 | */ |
| 984 | static int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf) |
| 985 | { |
| 986 | int rc = 0; |
| 987 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 988 | |
| 989 | pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n", |
| 990 | rmu->msg_rx_ring.rx_slot); |
| 991 | |
| 992 | if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) { |
| 993 | printk(KERN_ERR |
| 994 | "RIO: error adding inbound buffer %d, buffer exists\n", |
| 995 | rmu->msg_rx_ring.rx_slot); |
| 996 | rc = -EINVAL; |
| 997 | goto out; |
| 998 | } |
| 999 | |
| 1000 | rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf; |
| 1001 | if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size) |
| 1002 | rmu->msg_rx_ring.rx_slot = 0; |
| 1003 | |
| 1004 | out: |
| 1005 | return rc; |
| 1006 | } |
| 1007 | |
| 1008 | /** |
| 1009 | * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit |
| 1010 | * @mport: Master port implementing the inbound message unit |
| 1011 | * @mbox: Inbound mailbox number |
| 1012 | * |
| 1013 | * Gets the next available inbound message from the inbound message queue. |
| 1014 | * A pointer to the message is returned on success or NULL on failure. |
| 1015 | */ |
| 1016 | static void *fsl_get_inb_message(struct rio_mport *mport, int mbox) |
| 1017 | { |
| 1018 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 1019 | u32 phys_buf, virt_buf; |
| 1020 | void *buf = NULL; |
| 1021 | int buf_idx; |
| 1022 | |
| 1023 | phys_buf = in_be32(&rmu->msg_regs->ifqdpar); |
| 1024 | |
| 1025 | /* If no more messages, then bail out */ |
| 1026 | if (phys_buf == in_be32(&rmu->msg_regs->ifqepar)) |
| 1027 | goto out2; |
| 1028 | |
| 1029 | virt_buf = (u32) rmu->msg_rx_ring.virt + (phys_buf |
| 1030 | - rmu->msg_rx_ring.phys); |
| 1031 | buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE; |
| 1032 | buf = rmu->msg_rx_ring.virt_buffer[buf_idx]; |
| 1033 | |
| 1034 | if (!buf) { |
| 1035 | printk(KERN_ERR |
| 1036 | "RIO: inbound message copy failed, no buffers\n"); |
| 1037 | goto out1; |
| 1038 | } |
| 1039 | |
| 1040 | /* Copy max message size, caller is expected to allocate that big */ |
| 1041 | memcpy(buf, (void *)virt_buf, RIO_MAX_MSG_SIZE); |
| 1042 | |
| 1043 | /* Clear the available buffer */ |
| 1044 | rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL; |
| 1045 | |
| 1046 | out1: |
| 1047 | setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI); |
| 1048 | |
| 1049 | out2: |
| 1050 | return buf; |
| 1051 | } |
| 1052 | |
| 1053 | /** |
| 1054 | * fsl_rio_doorbell_init - MPC85xx doorbell interface init |
| 1055 | * @mport: Master port implementing the inbound doorbell unit |
| 1056 | * |
| 1057 | * Initializes doorbell unit hardware and inbound DMA buffer |
| 1058 | * ring. Called from fsl_rio_setup(). Returns %0 on success |
| 1059 | * or %-ENOMEM on failure. |
| 1060 | */ |
| 1061 | static int fsl_rio_doorbell_init(struct rio_mport *mport) |
| 1062 | { |
| 1063 | struct rio_priv *priv = mport->priv; |
| 1064 | struct fsl_rmu *rmu = GET_RMM_HANDLE(mport); |
| 1065 | int rc = 0; |
| 1066 | |
| 1067 | /* Map outbound doorbell window immediately after maintenance window */ |
| 1068 | rmu->dbell_win = ioremap(mport->iores.start + RIO_MAINT_WIN_SIZE, |
| 1069 | RIO_DBELL_WIN_SIZE); |
| 1070 | if (!rmu->dbell_win) { |
| 1071 | printk(KERN_ERR |
| 1072 | "RIO: unable to map outbound doorbell window\n"); |
| 1073 | rc = -ENOMEM; |
| 1074 | goto out; |
| 1075 | } |
| 1076 | |
| 1077 | /* Initialize inbound doorbells */ |
| 1078 | rmu->dbell_ring.virt = dma_alloc_coherent(priv->dev, 512 * |
| 1079 | DOORBELL_MESSAGE_SIZE, &rmu->dbell_ring.phys, GFP_KERNEL); |
| 1080 | if (!rmu->dbell_ring.virt) { |
| 1081 | printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n"); |
| 1082 | rc = -ENOMEM; |
| 1083 | iounmap(rmu->dbell_win); |
| 1084 | goto out; |
| 1085 | } |
| 1086 | |
| 1087 | /* Point dequeue/enqueue pointers at first entry in ring */ |
| 1088 | out_be32(&rmu->msg_regs->dqdpar, (u32) rmu->dbell_ring.phys); |
| 1089 | out_be32(&rmu->msg_regs->dqepar, (u32) rmu->dbell_ring.phys); |
| 1090 | |
| 1091 | /* Clear interrupt status */ |
| 1092 | out_be32(&rmu->msg_regs->dsr, 0x00000091); |
| 1093 | |
| 1094 | /* Hook up doorbell handler */ |
| 1095 | rc = request_irq(IRQ_RIO_BELL(mport), fsl_rio_dbell_handler, 0, |
| 1096 | "dbell_rx", (void *)mport); |
| 1097 | if (rc < 0) { |
| 1098 | iounmap(rmu->dbell_win); |
| 1099 | dma_free_coherent(priv->dev, 512 * DOORBELL_MESSAGE_SIZE, |
| 1100 | rmu->dbell_ring.virt, rmu->dbell_ring.phys); |
| 1101 | printk(KERN_ERR |
| 1102 | "MPC85xx RIO: unable to request inbound doorbell irq"); |
| 1103 | goto out; |
| 1104 | } |
| 1105 | |
| 1106 | /* Configure doorbells for snooping, 512 entries, and enable */ |
| 1107 | out_be32(&rmu->msg_regs->dmr, 0x00108161); |
| 1108 | |
| 1109 | out: |
| 1110 | return rc; |
| 1111 | } |
| 1112 | |
| 1113 | int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node) |
| 1114 | { |
| 1115 | struct rio_priv *priv; |
| 1116 | struct fsl_rmu *rmu; |
| 1117 | struct rio_ops *ops; |
| 1118 | |
| 1119 | if (!mport || !mport->priv || !node) |
| 1120 | return -1; |
| 1121 | |
| 1122 | rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL); |
| 1123 | if (!rmu) |
| 1124 | return -ENOMEM; |
| 1125 | |
| 1126 | priv = mport->priv; |
| 1127 | priv->rmm_handle = rmu; |
| 1128 | rmu->dbell_atmu_regs = priv->atmu_regs + 2; |
| 1129 | rmu->msg_regs = (struct rio_msg_regs *)(priv->regs_win + |
| 1130 | ((mport->phy_type == RIO_PHY_SERIAL) ? |
| 1131 | RIO_S_MSG_REGS_OFFSET : RIO_P_MSG_REGS_OFFSET)); |
| 1132 | |
| 1133 | rmu->bellirq = irq_of_parse_and_map(node, 2); |
| 1134 | rmu->txirq = irq_of_parse_and_map(node, 3); |
| 1135 | rmu->rxirq = irq_of_parse_and_map(node, 4); |
| 1136 | dev_info(priv->dev, "bellirq: %d, txirq: %d, rxirq %d\n", |
| 1137 | rmu->bellirq, rmu->txirq, rmu->rxirq); |
| 1138 | |
| 1139 | ops = mport->ops; |
| 1140 | |
| 1141 | ops->dsend = fsl_rio_doorbell_send; |
| 1142 | ops->open_outb_mbox = fsl_open_outb_mbox; |
| 1143 | ops->open_inb_mbox = fsl_open_inb_mbox; |
| 1144 | ops->close_outb_mbox = fsl_close_outb_mbox; |
| 1145 | ops->close_inb_mbox = fsl_close_inb_mbox; |
| 1146 | ops->add_outb_message = fsl_add_outb_message; |
| 1147 | ops->add_inb_buffer = fsl_add_inb_buffer; |
| 1148 | ops->get_inb_message = fsl_get_inb_message; |
| 1149 | |
| 1150 | rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); |
| 1151 | rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0); |
| 1152 | rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0); |
| 1153 | |
| 1154 | /* Configure outbound doorbell window */ |
| 1155 | out_be32(&rmu->dbell_atmu_regs->rowbar, |
| 1156 | (mport->iores.start + RIO_MAINT_WIN_SIZE) >> 12); |
| 1157 | /* 4k window size */ |
| 1158 | out_be32(&rmu->dbell_atmu_regs->rowar, 0x8004200b); |
| 1159 | |
| 1160 | fsl_rio_doorbell_init(mport); |
| 1161 | |
| 1162 | return 0; |
| 1163 | } |