Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | #ifndef __MV643XX_ETH_H__ |
| 2 | #define __MV643XX_ETH_H__ |
| 3 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | #include <linux/module.h> |
| 5 | #include <linux/kernel.h> |
| 6 | #include <linux/spinlock.h> |
| 7 | #include <linux/workqueue.h> |
James Chapman | c28a4f8 | 2006-01-27 01:13:15 -0700 | [diff] [blame] | 8 | #include <linux/mii.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | |
| 10 | #include <linux/mv643xx.h> |
| 11 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 12 | /* Checksum offload for Tx works for most packets, but |
| 13 | * fails if previous packet sent did not use hw csum |
| 14 | */ |
Dale Farnsworth | 2600636 | 2005-08-22 15:53:29 -0700 | [diff] [blame] | 15 | #define MV643XX_CHECKSUM_OFFLOAD_TX |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | #define MV643XX_NAPI |
| 17 | #define MV643XX_TX_FAST_REFILL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #undef MV643XX_COAL |
| 19 | |
| 20 | /* |
| 21 | * Number of RX / TX descriptors on RX / TX rings. |
| 22 | * Note that allocating RX descriptors is done by allocating the RX |
| 23 | * ring AND a preallocated RX buffers (skb's) for each descriptor. |
| 24 | * The TX descriptors only allocates the TX descriptors ring, |
| 25 | * with no pre allocated TX buffers (skb's are allocated by higher layers. |
| 26 | */ |
| 27 | |
| 28 | /* Default TX ring size is 1000 descriptors */ |
| 29 | #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000 |
| 30 | |
| 31 | /* Default RX ring size is 400 descriptors */ |
| 32 | #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400 |
| 33 | |
| 34 | #define MV643XX_TX_COAL 100 |
| 35 | #ifdef MV643XX_COAL |
| 36 | #define MV643XX_RX_COAL 100 |
| 37 | #endif |
| 38 | |
Dale Farnsworth | 7303fde | 2006-03-03 10:03:36 -0700 | [diff] [blame] | 39 | #ifdef MV643XX_CHECKSUM_OFFLOAD_TX |
| 40 | #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1) |
| 41 | #else |
| 42 | #define MAX_DESCS_PER_SKB 1 |
| 43 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 44 | |
Dale Farnsworth | 7303fde | 2006-03-03 10:03:36 -0700 | [diff] [blame] | 45 | #define ETH_VLAN_HLEN 4 |
| 46 | #define ETH_FCS_LEN 4 |
| 47 | #define ETH_DMA_ALIGN 8 /* hw requires 8-byte alignment */ |
| 48 | #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */ |
| 49 | #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \ |
| 50 | ETH_VLAN_HLEN + ETH_FCS_LEN) |
| 51 | #define ETH_RX_SKB_SIZE ((dev->mtu + ETH_WRAPPER_LEN + 7) & ~0x7) |
| 52 | |
| 53 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ |
| 54 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ |
| 55 | |
| 56 | #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2) |
| 57 | #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9) |
| 58 | #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR) |
| 59 | #define ETH_INT_CAUSE_EXT 0x00000002 |
| 60 | #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT) |
| 61 | |
| 62 | #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0) |
| 63 | #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8) |
| 64 | #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR) |
| 65 | #define ETH_INT_CAUSE_PHY 0x00010000 |
| 66 | #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY) |
| 67 | |
| 68 | #define ETH_INT_MASK_ALL 0x00000000 |
| 69 | #define ETH_INT_MASK_ALL_EXT 0x00000000 |
| 70 | |
| 71 | #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */ |
| 72 | #define PHY_WAIT_MICRO_SECONDS 10 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | /* Buffer offset from buffer pointer */ |
| 75 | #define RX_BUF_OFFSET 0x2 |
| 76 | |
| 77 | /* Gigabit Ethernet Unit Global Registers */ |
| 78 | |
| 79 | /* MIB Counters register definitions */ |
| 80 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0 |
| 81 | #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4 |
| 82 | #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8 |
| 83 | #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc |
| 84 | #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10 |
| 85 | #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14 |
| 86 | #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18 |
| 87 | #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c |
| 88 | #define ETH_MIB_FRAMES_64_OCTETS 0x20 |
| 89 | #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24 |
| 90 | #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28 |
| 91 | #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c |
| 92 | #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30 |
| 93 | #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34 |
| 94 | #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38 |
| 95 | #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c |
| 96 | #define ETH_MIB_GOOD_FRAMES_SENT 0x40 |
| 97 | #define ETH_MIB_EXCESSIVE_COLLISION 0x44 |
| 98 | #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48 |
| 99 | #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c |
| 100 | #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50 |
| 101 | #define ETH_MIB_FC_SENT 0x54 |
| 102 | #define ETH_MIB_GOOD_FC_RECEIVED 0x58 |
| 103 | #define ETH_MIB_BAD_FC_RECEIVED 0x5c |
| 104 | #define ETH_MIB_UNDERSIZE_RECEIVED 0x60 |
| 105 | #define ETH_MIB_FRAGMENTS_RECEIVED 0x64 |
| 106 | #define ETH_MIB_OVERSIZE_RECEIVED 0x68 |
| 107 | #define ETH_MIB_JABBER_RECEIVED 0x6c |
| 108 | #define ETH_MIB_MAC_RECEIVE_ERROR 0x70 |
| 109 | #define ETH_MIB_BAD_CRC_EVENT 0x74 |
| 110 | #define ETH_MIB_COLLISION 0x78 |
| 111 | #define ETH_MIB_LATE_COLLISION 0x7c |
| 112 | |
| 113 | /* Port serial status reg (PSR) */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 114 | #define ETH_INTERFACE_PCM 0x00000001 |
| 115 | #define ETH_LINK_IS_UP 0x00000002 |
| 116 | #define ETH_PORT_AT_FULL_DUPLEX 0x00000004 |
| 117 | #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008 |
| 118 | #define ETH_GMII_SPEED_1000 0x00000010 |
| 119 | #define ETH_MII_SPEED_100 0x00000020 |
| 120 | #define ETH_TX_IN_PROGRESS 0x00000080 |
| 121 | #define ETH_BYPASS_ACTIVE 0x00000100 |
| 122 | #define ETH_PORT_AT_PARTITION_STATE 0x00000200 |
| 123 | #define ETH_PORT_TX_FIFO_EMPTY 0x00000400 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | |
| 125 | /* SMI reg */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 126 | #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */ |
| 127 | #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */ |
| 128 | #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */ |
| 129 | #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */ |
| 130 | |
| 131 | /* Interrupt Cause Register Bit Definitions */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | /* SDMA command status fields macros */ |
| 134 | |
| 135 | /* Tx & Rx descriptors status */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 136 | #define ETH_ERROR_SUMMARY 0x00000001 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 137 | |
| 138 | /* Tx & Rx descriptors command */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 139 | #define ETH_BUFFER_OWNED_BY_DMA 0x80000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 140 | |
| 141 | /* Tx descriptors status */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 142 | #define ETH_LC_ERROR 0 |
| 143 | #define ETH_UR_ERROR 0x00000002 |
| 144 | #define ETH_RL_ERROR 0x00000004 |
| 145 | #define ETH_LLC_SNAP_FORMAT 0x00000200 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 146 | |
| 147 | /* Rx descriptors status */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 148 | #define ETH_OVERRUN_ERROR 0x00000002 |
| 149 | #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004 |
| 150 | #define ETH_RESOURCE_ERROR 0x00000006 |
| 151 | #define ETH_VLAN_TAGGED 0x00080000 |
| 152 | #define ETH_BPDU_FRAME 0x00100000 |
| 153 | #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000 |
| 154 | #define ETH_OTHER_FRAME_TYPE 0x00400000 |
| 155 | #define ETH_LAYER_2_IS_ETH_V_2 0x00800000 |
| 156 | #define ETH_FRAME_TYPE_IP_V_4 0x01000000 |
| 157 | #define ETH_FRAME_HEADER_OK 0x02000000 |
| 158 | #define ETH_RX_LAST_DESC 0x04000000 |
| 159 | #define ETH_RX_FIRST_DESC 0x08000000 |
| 160 | #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000 |
| 161 | #define ETH_RX_ENABLE_INTERRUPT 0x20000000 |
| 162 | #define ETH_LAYER_4_CHECKSUM_OK 0x40000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | |
| 164 | /* Rx descriptors byte count */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 165 | #define ETH_FRAME_FRAGMENTED 0x00000004 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | |
| 167 | /* Tx descriptors command */ |
Dale Farnsworth | ebe19a4 | 2006-03-03 10:06:20 -0700 | [diff] [blame] | 168 | #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400 |
| 169 | #define ETH_FRAME_SET_TO_VLAN 0x00008000 |
| 170 | #define ETH_UDP_FRAME 0x00010000 |
| 171 | #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000 |
| 172 | #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000 |
| 173 | #define ETH_ZERO_PADDING 0x00080000 |
| 174 | #define ETH_TX_LAST_DESC 0x00100000 |
| 175 | #define ETH_TX_FIRST_DESC 0x00200000 |
| 176 | #define ETH_GEN_CRC 0x00400000 |
| 177 | #define ETH_TX_ENABLE_INTERRUPT 0x00800000 |
| 178 | #define ETH_AUTO_MODE 0x40000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | |
Dale Farnsworth | 2600636 | 2005-08-22 15:53:29 -0700 | [diff] [blame] | 180 | #define ETH_TX_IHL_SHIFT 11 |
| 181 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | /* typedefs */ |
| 183 | |
| 184 | typedef enum _eth_func_ret_status { |
| 185 | ETH_OK, /* Returned as expected. */ |
| 186 | ETH_ERROR, /* Fundamental error. */ |
| 187 | ETH_RETRY, /* Could not process request. Try later.*/ |
| 188 | ETH_END_OF_JOB, /* Ring has nothing to process. */ |
| 189 | ETH_QUEUE_FULL, /* Ring resource error. */ |
| 190 | ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */ |
| 191 | } ETH_FUNC_RET_STATUS; |
| 192 | |
| 193 | typedef enum _eth_target { |
| 194 | ETH_TARGET_DRAM, |
| 195 | ETH_TARGET_DEVICE, |
| 196 | ETH_TARGET_CBS, |
| 197 | ETH_TARGET_PCI0, |
| 198 | ETH_TARGET_PCI1 |
| 199 | } ETH_TARGET; |
| 200 | |
| 201 | /* These are for big-endian machines. Little endian needs different |
| 202 | * definitions. |
| 203 | */ |
| 204 | #if defined(__BIG_ENDIAN) |
| 205 | struct eth_rx_desc { |
| 206 | u16 byte_cnt; /* Descriptor buffer byte count */ |
| 207 | u16 buf_size; /* Buffer size */ |
| 208 | u32 cmd_sts; /* Descriptor command status */ |
| 209 | u32 next_desc_ptr; /* Next descriptor pointer */ |
| 210 | u32 buf_ptr; /* Descriptor buffer pointer */ |
| 211 | }; |
| 212 | |
| 213 | struct eth_tx_desc { |
| 214 | u16 byte_cnt; /* buffer byte count */ |
| 215 | u16 l4i_chk; /* CPU provided TCP checksum */ |
| 216 | u32 cmd_sts; /* Command/status field */ |
| 217 | u32 next_desc_ptr; /* Pointer to next descriptor */ |
| 218 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ |
| 219 | }; |
| 220 | |
| 221 | #elif defined(__LITTLE_ENDIAN) |
| 222 | struct eth_rx_desc { |
| 223 | u32 cmd_sts; /* Descriptor command status */ |
| 224 | u16 buf_size; /* Buffer size */ |
| 225 | u16 byte_cnt; /* Descriptor buffer byte count */ |
| 226 | u32 buf_ptr; /* Descriptor buffer pointer */ |
| 227 | u32 next_desc_ptr; /* Next descriptor pointer */ |
| 228 | }; |
| 229 | |
| 230 | struct eth_tx_desc { |
| 231 | u32 cmd_sts; /* Command/status field */ |
| 232 | u16 l4i_chk; /* CPU provided TCP checksum */ |
| 233 | u16 byte_cnt; /* buffer byte count */ |
| 234 | u32 buf_ptr; /* pointer to buffer for this descriptor*/ |
| 235 | u32 next_desc_ptr; /* Pointer to next descriptor */ |
| 236 | }; |
| 237 | #else |
| 238 | #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined |
| 239 | #endif |
| 240 | |
| 241 | /* Unified struct for Rx and Tx operations. The user is not required to */ |
| 242 | /* be familier with neither Tx nor Rx descriptors. */ |
| 243 | struct pkt_info { |
| 244 | unsigned short byte_cnt; /* Descriptor buffer byte count */ |
| 245 | unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */ |
| 246 | unsigned int cmd_sts; /* Descriptor command status */ |
| 247 | dma_addr_t buf_ptr; /* Descriptor buffer pointer */ |
| 248 | struct sk_buff *return_info; /* User resource return information */ |
| 249 | }; |
| 250 | |
| 251 | /* Ethernet port specific infomation */ |
| 252 | |
| 253 | struct mv643xx_mib_counters { |
| 254 | u64 good_octets_received; |
| 255 | u32 bad_octets_received; |
| 256 | u32 internal_mac_transmit_err; |
| 257 | u32 good_frames_received; |
| 258 | u32 bad_frames_received; |
| 259 | u32 broadcast_frames_received; |
| 260 | u32 multicast_frames_received; |
| 261 | u32 frames_64_octets; |
| 262 | u32 frames_65_to_127_octets; |
| 263 | u32 frames_128_to_255_octets; |
| 264 | u32 frames_256_to_511_octets; |
| 265 | u32 frames_512_to_1023_octets; |
| 266 | u32 frames_1024_to_max_octets; |
| 267 | u64 good_octets_sent; |
| 268 | u32 good_frames_sent; |
| 269 | u32 excessive_collision; |
| 270 | u32 multicast_frames_sent; |
| 271 | u32 broadcast_frames_sent; |
| 272 | u32 unrec_mac_control_received; |
| 273 | u32 fc_sent; |
| 274 | u32 good_fc_received; |
| 275 | u32 bad_fc_received; |
| 276 | u32 undersize_received; |
| 277 | u32 fragments_received; |
| 278 | u32 oversize_received; |
| 279 | u32 jabber_received; |
| 280 | u32 mac_receive_error; |
| 281 | u32 bad_crc_event; |
| 282 | u32 collision; |
| 283 | u32 late_collision; |
| 284 | }; |
| 285 | |
| 286 | struct mv643xx_private { |
| 287 | int port_num; /* User Ethernet port number */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | |
| 289 | u32 rx_sram_addr; /* Base address of rx sram area */ |
| 290 | u32 rx_sram_size; /* Size of rx sram area */ |
| 291 | u32 tx_sram_addr; /* Base address of tx sram area */ |
| 292 | u32 tx_sram_size; /* Size of tx sram area */ |
| 293 | |
| 294 | int rx_resource_err; /* Rx ring resource error flag */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | |
| 296 | /* Tx/Rx rings managment indexes fields. For driver use */ |
| 297 | |
| 298 | /* Next available and first returning Rx resource */ |
| 299 | int rx_curr_desc_q, rx_used_desc_q; |
| 300 | |
| 301 | /* Next available and first returning Tx resource */ |
| 302 | int tx_curr_desc_q, tx_used_desc_q; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 303 | |
| 304 | #ifdef MV643XX_TX_FAST_REFILL |
| 305 | u32 tx_clean_threshold; |
| 306 | #endif |
| 307 | |
| 308 | struct eth_rx_desc *p_rx_desc_area; |
| 309 | dma_addr_t rx_desc_dma; |
Dale Farnsworth | c8aaea2 | 2006-03-03 10:02:05 -0700 | [diff] [blame] | 310 | int rx_desc_area_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | struct sk_buff **rx_skb; |
| 312 | |
| 313 | struct eth_tx_desc *p_tx_desc_area; |
| 314 | dma_addr_t tx_desc_dma; |
Dale Farnsworth | c8aaea2 | 2006-03-03 10:02:05 -0700 | [diff] [blame] | 315 | int tx_desc_area_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | struct sk_buff **tx_skb; |
| 317 | |
| 318 | struct work_struct tx_timeout_task; |
| 319 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 320 | struct net_device_stats stats; |
| 321 | struct mv643xx_mib_counters mib_counters; |
| 322 | spinlock_t lock; |
| 323 | /* Size of Tx Ring per queue */ |
Dale Farnsworth | c8aaea2 | 2006-03-03 10:02:05 -0700 | [diff] [blame] | 324 | int tx_ring_size; |
Dale Farnsworth | f98e36f1 | 2006-01-27 01:09:18 -0700 | [diff] [blame] | 325 | /* Number of tx descriptors in use */ |
Dale Farnsworth | c8aaea2 | 2006-03-03 10:02:05 -0700 | [diff] [blame] | 326 | int tx_desc_count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 327 | /* Size of Rx Ring per queue */ |
Dale Farnsworth | c8aaea2 | 2006-03-03 10:02:05 -0700 | [diff] [blame] | 328 | int rx_ring_size; |
Dale Farnsworth | f98e36f1 | 2006-01-27 01:09:18 -0700 | [diff] [blame] | 329 | /* Number of rx descriptors in use */ |
Dale Farnsworth | c8aaea2 | 2006-03-03 10:02:05 -0700 | [diff] [blame] | 330 | int rx_desc_count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | |
| 332 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 333 | * Used in case RX Ring is empty, which can be caused when |
| 334 | * system does not have resources (skb's) |
| 335 | */ |
| 336 | struct timer_list timeout; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | |
| 338 | u32 rx_int_coal; |
| 339 | u32 tx_int_coal; |
James Chapman | c28a4f8 | 2006-01-27 01:13:15 -0700 | [diff] [blame] | 340 | struct mii_if_info mii; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 341 | }; |
| 342 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 343 | /* Port operation control routines */ |
| 344 | static void eth_port_init(struct mv643xx_private *mp); |
| 345 | static void eth_port_reset(unsigned int eth_port_num); |
Dale Farnsworth | ed9b5d4 | 2006-01-27 01:06:38 -0700 | [diff] [blame] | 346 | static void eth_port_start(struct net_device *dev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 347 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | /* Port MAC address routines */ |
| 349 | static void eth_port_uc_addr_set(unsigned int eth_port_num, |
| 350 | unsigned char *p_addr); |
| 351 | |
| 352 | /* PHY and MIB routines */ |
| 353 | static void ethernet_phy_reset(unsigned int eth_port_num); |
| 354 | |
| 355 | static void eth_port_write_smi_reg(unsigned int eth_port_num, |
| 356 | unsigned int phy_reg, unsigned int value); |
| 357 | |
| 358 | static void eth_port_read_smi_reg(unsigned int eth_port_num, |
| 359 | unsigned int phy_reg, unsigned int *value); |
| 360 | |
| 361 | static void eth_clear_mib_counters(unsigned int eth_port_num); |
| 362 | |
| 363 | /* Port data flow control routines */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 364 | static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp, |
| 365 | struct pkt_info *p_pkt_info); |
| 366 | static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp, |
| 367 | struct pkt_info *p_pkt_info); |
| 368 | |
| 369 | #endif /* __MV643XX_ETH_H__ */ |